From 7fb99409eaa232346621aa5811912aeaf511baec Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 02:28:25 +0200 Subject: [PATCH 01/10] evidence: add independent ULX3S reproduction receipt --- .../reproduction-receipt.json | 84 ++++++++++++++ test/test_lsc1_ulx3s_reproduction.py | 51 +++++++++ tools/verify_lsc1_ulx3s_reproduction.py | 104 ++++++++++++++++++ 3 files changed, 239 insertions(+) create mode 100644 evidence/lsc1-09-cleanroom/reproduction-receipt.json create mode 100644 test/test_lsc1_ulx3s_reproduction.py create mode 100644 tools/verify_lsc1_ulx3s_reproduction.py diff --git a/evidence/lsc1-09-cleanroom/reproduction-receipt.json b/evidence/lsc1-09-cleanroom/reproduction-receipt.json new file mode 100644 index 00000000..52c911e8 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/reproduction-receipt.json @@ -0,0 +1,84 @@ +{ + "schema": "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v1", + "scoper": "99f65947-0cdb-4d83-a569-d3bf3d1458ae", + "base_commit": "5610ea221dd82b5749690043e8c3665b2be9ced8", + "build_source": { + "commit": "fde1b885a56b98391833f4632676f14d1e3e2f9c", + "tree": "87462c2c698c43318df8b9a4db78c0c6ca9de251", + "inputs_match_revision": true + }, + "scope": { + "design": "full LSC-1 host-prepared packet UART endpoint", + "host_fetch": false, + "memory_expansion": false, + "physical_hardware": false, + "end_to_end": false, + "universal_or_unbounded": false, + "later_roadmap_work": false + }, + "evidence_layers": { + "executable_model": "not exercised by the reproduction builds", + "lean": "validated separately; does not prove the bitstream", + "authored_rtl": "build input only", + "netlist": "generated intermediate only", + "place_and_route": "two host executions with archived timing receipts", + "physical_hardware": "no board attached, programmed, or observed" + }, + "toolchain": { + "yosys": "Yosys 0.33 (git sha1 2584903a060)", + "nextpnr-ecp5": "\"nextpnr-ecp5\" -- Next Generation Place and Route (Version nextpnr-0.11.1)", + "ecppack": "Project Trellis ecppack Version 1.4-2build4" + }, + "command": ["./fpga/ulx3s/build_packet_uart.sh"], + "nextpnr_options": ["--85k", "--package", "CABGA381", "--seed", "2", "--placer", "static", "--no-tmdriv", "--router", "router1"], + "required_core_clock_mhz": 10.0, + "runs": [ + { + "id": "clean-build-1", + "checkout": "independent detached worktree", + "pre_build_tracked_clean": true, + "exit_code": 0, + "source_manifest_sha256": "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", + "artifact_manifest_complete": true, + "program_finished_normally": true, + "core_clock_pass": true, + "achieved_core_clock_mhz": 15.32, + "raw_receipt_sha256": { + "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", + "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", + "yosys.log": "54813f13acb695472ce71450f9f94d5a6118274c47332866cea1ed9b4271149f", + "nextpnr.log": "8a161adaf61e8d97c25a7bacadcbcb82144ed8c0392e31445c0d8cec754c8fb0", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba" + }, + "artifacts": { + "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", + "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", + "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee" + } + }, + { + "id": "clean-build-2", + "checkout": "independent detached worktree", + "pre_build_tracked_clean": true, + "exit_code": 0, + "source_manifest_sha256": "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", + "artifact_manifest_complete": true, + "program_finished_normally": true, + "core_clock_pass": true, + "achieved_core_clock_mhz": 15.32, + "raw_receipt_sha256": { + "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", + "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", + "yosys.log": "a6ad59bf36b5acd48fe7448132d687730118a33c5181ff9185d7358d8e840028", + "nextpnr.log": "2d01813e70101a4dfc7a376f8234c4a3d92007e6c97e0ea1b428fbaf579f65c2", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba" + }, + "artifacts": { + "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", + "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", + "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee" + } + } + ], + "conclusion": "two clean host builds reproduced the archived packet bitstream artifacts byte-for-byte" +} diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py new file mode 100644 index 00000000..f61c3690 --- /dev/null +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -0,0 +1,51 @@ +from __future__ import annotations + +import copy +import json +import tempfile +import unittest +from pathlib import Path + +from tools.verify_lsc1_ulx3s_reproduction import RECEIPT, verify + + +class ReproductionReceiptTest(unittest.TestCase): + def receipt(self) -> dict: + return json.loads(RECEIPT.read_text()) + + def rejected(self, mutate, message: str) -> None: + receipt = copy.deepcopy(self.receipt()) + mutate(receipt) + with tempfile.TemporaryDirectory() as td: + path = Path(td) / "receipt.json" + path.write_text(json.dumps(receipt)) + with self.assertRaisesRegex(ValueError, message): + verify(path) + + def test_receipt_accepts(self): + verify() + + def test_missing_second_run_rejected(self): + self.rejected(lambda r: r["runs"].pop(), "exactly two runs") + + def test_nonzero_exit_rejected(self): + self.rejected(lambda r: r["runs"][1].update(exit_code=1), "normal exit") + + def test_timing_failure_rejected(self): + self.rejected(lambda r: r["runs"][0].update(core_clock_pass=False), "10 MHz timing") + + def test_artifact_divergence_rejected(self): + self.rejected(lambda r: r["runs"][1]["artifacts"].update(ulx3s_lsc1_packet={}), "run artifact hashes") + + def test_raw_log_digest_mutation_rejected(self): + self.rejected(lambda r: r["runs"][0]["raw_receipt_sha256"].update({"nextpnr.log": "0" * 64}), "raw receipt hashes") + + def test_scope_expansion_rejected(self): + self.rejected(lambda r: r["scope"].update(physical_hardware=True), "scope boundary physical_hardware") + + def test_unpinned_option_rejected(self): + self.rejected(lambda r: r["nextpnr_options"].remove("--no-tmdriv"), "nextpnr options") + + +if __name__ == "__main__": + unittest.main() diff --git a/tools/verify_lsc1_ulx3s_reproduction.py b/tools/verify_lsc1_ulx3s_reproduction.py new file mode 100644 index 00000000..7cddfbe5 --- /dev/null +++ b/tools/verify_lsc1_ulx3s_reproduction.py @@ -0,0 +1,104 @@ +#!/usr/bin/env python3 +"""Fail-closed verification of the two-run host-build reproduction receipt.""" +from __future__ import annotations + +import hashlib +import json +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +RECEIPT = ROOT / "evidence/lsc1-09-cleanroom/reproduction-receipt.json" +ARCHIVE = ROOT / "results/ulx3s-lsc1-packet-20260726" +SOURCE = "fde1b885a56b98391833f4632676f14d1e3e2f9c" +BASE = "5610ea221dd82b5749690043e8c3665b2be9ced8" +ARTIFACTS = { + "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", + "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", + "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee", +} +TOOLS = { + "yosys": "Yosys 0.33 (git sha1 2584903a060)", + "nextpnr-ecp5": '"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.11.1)', + "ecppack": "Project Trellis ecppack Version 1.4-2build4", +} +OPTIONS = ["--85k", "--package", "CABGA381", "--seed", "2", "--placer", "static", "--no-tmdriv", "--router", "router1"] +RAW_RECEIPTS = { + "clean-build-1": { + "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", + "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", + "yosys.log": "54813f13acb695472ce71450f9f94d5a6118274c47332866cea1ed9b4271149f", + "nextpnr.log": "8a161adaf61e8d97c25a7bacadcbcb82144ed8c0392e31445c0d8cec754c8fb0", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", + }, + "clean-build-2": { + "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", + "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", + "yosys.log": "a6ad59bf36b5acd48fe7448132d687730118a33c5181ff9185d7358d8e840028", + "nextpnr.log": "2d01813e70101a4dfc7a376f8234c4a3d92007e6c97e0ea1b428fbaf579f65c2", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", + }, +} + + +def require(value: bool, message: str) -> None: + if not value: + raise ValueError(message) + + +def sha(path: Path) -> str: + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def verify(path: Path = RECEIPT) -> None: + r = json.loads(path.read_text(encoding="utf-8")) + require(r.get("schema") == "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v1", "schema") + require(r.get("scoper") == "99f65947-0cdb-4d83-a569-d3bf3d1458ae", "scoper") + require(r.get("base_commit") == BASE, "base commit") + source = r.get("build_source", {}) + require(source == {"commit": SOURCE, "tree": "87462c2c698c43318df8b9a4db78c0c6ca9de251", "inputs_match_revision": True}, "source identity") + tree = subprocess.check_output(["git", "rev-parse", f"{SOURCE}^{{tree}}"], cwd=ROOT, text=True).strip() + require(tree == source["tree"], "source tree object") + scope = r.get("scope", {}) + require(scope.get("design") == "full LSC-1 host-prepared packet UART endpoint", "full LSC-1 scope") + for key in ("host_fetch", "memory_expansion", "physical_hardware", "end_to_end", "universal_or_unbounded", "later_roadmap_work"): + require(scope.get(key) is False, f"scope boundary {key}") + layers = r.get("evidence_layers", {}) + require(set(layers) == {"executable_model", "lean", "authored_rtl", "netlist", "place_and_route", "physical_hardware"}, "evidence layer separation") + require(r.get("toolchain") == TOOLS, "toolchain") + require(r.get("command") == ["./fpga/ulx3s/build_packet_uart.sh"], "command") + require(r.get("nextpnr_options") == OPTIONS, "nextpnr options") + require(r.get("required_core_clock_mhz") == 10.0, "clock requirement") + manifest = {line.split()[1]: line.split()[0] for line in (ARCHIVE / "SHA256SUMS").read_text().splitlines()} + require(manifest == ARTIFACTS, "archived artifact manifest") + for name, expected in ARTIFACTS.items(): + require(sha(ARCHIVE / name) == expected, f"archived hash {name}") + runs = r.get("runs") + require(isinstance(runs, list) and len(runs) == 2, "exactly two runs") + require({x.get("id") for x in runs} == {"clean-build-1", "clean-build-2"}, "independent run identities") + for run in runs: + require(run.get("checkout") == "independent detached worktree", "isolated checkout") + require(run.get("pre_build_tracked_clean") is True, "clean checkout") + require(run.get("exit_code") == 0, "normal exit") + require(run.get("source_manifest_sha256") == "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", "complete source manifest") + require(run.get("artifact_manifest_complete") is True, "complete artifact manifest") + require(run.get("program_finished_normally") is True, "nextpnr completion") + require(run.get("core_clock_pass") is True and run.get("achieved_core_clock_mhz", 0) >= 10.0, "10 MHz timing") + require(run.get("raw_receipt_sha256") == RAW_RECEIPTS[run["id"]], "raw receipt hashes") + require(run.get("artifacts") == ARTIFACTS, "run artifact hashes") + require(r.get("conclusion") == "two clean host builds reproduced the archived packet bitstream artifacts byte-for-byte", "conclusion") + + +def main() -> int: + try: + verify() + except (ValueError, KeyError, json.JSONDecodeError, OSError, subprocess.CalledProcessError) as error: + print(f"FAIL reproduction receipt: {error}", file=sys.stderr) + return 1 + print("PASS two-run clean-room ULX3S LSC-1 host-build reproduction") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) From adc3e2c5b86fb08e1b0225573486ae08af4ac194 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 02:30:31 +0200 Subject: [PATCH 02/10] checksums: index ULX3S reproduction receipt --- SHA256SUMS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/SHA256SUMS b/SHA256SUMS index cd01eba2..24dc7369 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -124,6 +124,7 @@ ec7683d9bc6ce928175024df6c7c33dd23bcddd4cf57d7f93596cbd513c194f2 ./evidence/lsc 61d7c90b7ce7cd3a602b33ba9ae4b220d398caa3fc13ba2b09fa9197047258e5 ./evidence/lsc1-08-s9/receipt.json 9e62743a486d333d23e958d5a19612a9df0ac1ebf35a876e3b07144e82b6ae46 ./evidence/lsc1-08-s9/receipt.json.sha256 39f80a1f105ab1a1031fa74a1c232a1e4c8f196e2329f20947768b199c86b4b6 ./evidence/lsc1-08-s9/request_validator_equiv_miter.sv +6ec36fa28296cbc09b10916978c8e3f446ec30bfb70f6d9c8cb83e4613dc5297 ./evidence/lsc1-09-cleanroom/reproduction-receipt.json 386956c565ea8a78d5ad39ed988dab49aeeff7c7f901f7ec166c89b4d039455d ./formal/LSC1U_COMPOSITIONAL_REFINEMENT.md ff660d3e6022c71f3dad4ad9f61565f137a9130c7c48d45fed892bd572beafc2 ./formal/LSC1U_XOR_REFINEMENT.md 05401a99f2d5ec82dba92a60a54c11a697174566aff9aa9a19bd8092d059615d ./formal/README.md @@ -561,6 +562,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls 739d601ff16a130bbe53d758dd3bbfd9c57a2edfa87c9fd25d215cbc43f0919d ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py +69ef2d5a2c4c2a69081040d1bc47115ba4bf37eb8485d2d7ae3f3cd7f426b6bb ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py @@ -602,6 +604,7 @@ a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py 6f6d2f97d96aeddd39e3bae8c4ea9193bec8a5a4237d5a17a93057e1d2c38f26 ./tools/verify_fabrication_bundle.py c8043064d4d9ef0e6f9b2d5035a1a569c88d6f56bb16abef58cccef96c1617cc ./tools/verify_lsc1_fpga_packet_evidence.py +304d7850c0e59f3789b4d475d7eb68c0f3707189b92b474a65d61b5ef2197f2f ./tools/verify_lsc1_ulx3s_reproduction.py 650919f4b3f0d2a94022d4de230f16afca36fc5c3eee45b77571cb0ec5c52994 ./tools/verify_lsc1u_release_equivalence.py 4af566c345d8108c6b409f0c622fe132bdfc3b3a2b3eddee28f778e378d71254 ./tools/workload_validation.py d930b3a00795450bad3cfa1941fcc3028e03b5cf9724dab32c7f07d0678f38b4 ./workloads/blake3_stack.program.json From a9ce903a2c38901b839c92b51aa48b6e2815ec44 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 03:14:11 +0200 Subject: [PATCH 03/10] evidence: preserve and bind clean ULX3S builds --- Makefile | 2 + SHA256SUMS | 36 +- .../clean-build-1/SHA256SUMS | 3 + .../clean-build-1/SOURCE_MANIFEST.txt | 28 + .../clean-build-1/build.stderr | 0 .../clean-build-1/build.stdout | 44 + .../clean-build-1/ecppack.log | 0 .../clean-build-1/nextpnr.log | 3442 + .../clean-build-1/timing.txt | 6 + .../clean-build-1/tool_versions.txt | 5 + .../clean-build-1/ulx3s_lsc1_packet.bit | Bin 0 -> 1927725 bytes .../clean-build-1/ulx3s_lsc1_packet.config | 496803 +++++++++++++++ .../clean-build-1/ulx3s_lsc1_packet.svf | 48249 ++ .../lsc1-09-cleanroom/clean-build-1/yosys.log | 32855 + .../clean-build-2/SHA256SUMS | 3 + .../clean-build-2/SOURCE_MANIFEST.txt | 28 + .../clean-build-2/build.stderr | 0 .../clean-build-2/build.stdout | 44 + .../clean-build-2/ecppack.log | 0 .../clean-build-2/nextpnr.log | 3442 + .../clean-build-2/timing.txt | 6 + .../clean-build-2/tool_versions.txt | 5 + .../clean-build-2/ulx3s_lsc1_packet.bit | Bin 0 -> 1927725 bytes .../clean-build-2/ulx3s_lsc1_packet.config | 496803 +++++++++++++++ .../clean-build-2/ulx3s_lsc1_packet.svf | 48249 ++ .../lsc1-09-cleanroom/clean-build-2/yosys.log | 32855 + .../reproduction-receipt.json | 62 +- test/test_lsc1_fpga_packet_evidence.py | 7 +- test/test_lsc1_ulx3s_reproduction.py | 82 +- tools/verify_lsc1_fpga_packet_evidence.py | 16 +- tools/verify_lsc1_ulx3s_reproduction.py | 136 +- 31 files changed, 1163112 insertions(+), 99 deletions(-) create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/SHA256SUMS create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/SOURCE_MANIFEST.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/build.stderr create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/build.stdout create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/ecppack.log create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/nextpnr.log create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/timing.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/tool_versions.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.bit create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.config create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.svf create mode 100644 evidence/lsc1-09-cleanroom/clean-build-1/yosys.log create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/SHA256SUMS create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/SOURCE_MANIFEST.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/build.stderr create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/build.stdout create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/ecppack.log create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/nextpnr.log create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/timing.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/tool_versions.txt create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.bit create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.config create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.svf create mode 100644 evidence/lsc1-09-cleanroom/clean-build-2/yosys.log diff --git a/Makefile b/Makefile index d09faa66..a120028f 100644 --- a/Makefile +++ b/Makefile @@ -16,6 +16,8 @@ workflow-check: PYTHONDONTWRITEBYTECODE=1 $(PYTHON) test/test_lsc1_scalar_status_workflow.py -v PYTHONDONTWRITEBYTECODE=1 $(PYTHON) test/test_oss_cad_suite_workflow.py -v PYTHONDONTWRITEBYTECODE=1 PYTHONPATH=. $(PYTHON) test/test_lsc1_fpga_packet_evidence.py -v + PYTHONDONTWRITEBYTECODE=1 $(PYTHON) tools/verify_lsc1_ulx3s_reproduction.py + PYTHONDONTWRITEBYTECODE=1 PYTHONPATH=. $(PYTHON) test/test_lsc1_ulx3s_reproduction.py -v fabrication-bundle: PYTHONDONTWRITEBYTECODE=1 $(PYTHON) tools/verify_fabrication_bundle.py diff --git a/SHA256SUMS b/SHA256SUMS index 24dc7369..590fd199 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -10,7 +10,7 @@ dc4fd27671dc6184c8106cac4193bada03706186206784f4cd872ca183592494 ./.github/work dab1b175b7de029e4bc85180f261d26d4c63850f0bc1f28477bb3e91a5e3d4f0 ./.gitignore cfc7749b96f63bd31c3c42b5c471bf756814053e847c10f3eb003417bc523d30 ./LICENSE 6e3ce8bd9c03e8a089c469de50450f30806ccec946f47e383ad335efca7d6192 ./MANIFEST.md -93d5e04cad47ee11b1c70bcb2402f0d5de7aeb9293d7da327fdaef41d2465e7f ./Makefile +1c2f541cbf84c338848b0c8de068191bc513670e15a673a7dd1f3ef9ce5c4b98 ./Makefile 80e228fef99ac1908d50b416073df9f555fa693ad4e3ee59fa88c76028fc2232 ./README.md de4c0f6adf6ff1356bf9d7599ab52aef93a00b50c5a77c727ec0ce036ff2d1a2 ./RESULTS.md baa38ad5792511470f4cc9d2344d46f0c7af8a365d5b5e178dca88634b288bff ./VALIDATION.txt @@ -124,7 +124,31 @@ ec7683d9bc6ce928175024df6c7c33dd23bcddd4cf57d7f93596cbd513c194f2 ./evidence/lsc 61d7c90b7ce7cd3a602b33ba9ae4b220d398caa3fc13ba2b09fa9197047258e5 ./evidence/lsc1-08-s9/receipt.json 9e62743a486d333d23e958d5a19612a9df0ac1ebf35a876e3b07144e82b6ae46 ./evidence/lsc1-08-s9/receipt.json.sha256 39f80a1f105ab1a1031fa74a1c232a1e4c8f196e2329f20947768b199c86b4b6 ./evidence/lsc1-08-s9/request_validator_equiv_miter.sv -6ec36fa28296cbc09b10916978c8e3f446ec30bfb70f6d9c8cb83e4613dc5297 ./evidence/lsc1-09-cleanroom/reproduction-receipt.json +cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf ./evidence/lsc1-09-cleanroom/clean-build-1/SHA256SUMS +0bc16e2f0a9ac2898397b294ee8598bab14d2e3e365b639ed14e3a2d3406dab8 ./evidence/lsc1-09-cleanroom/clean-build-1/SOURCE_MANIFEST.txt +e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./evidence/lsc1-09-cleanroom/clean-build-1/build.stderr +6f7d74f3be9705e033495da9fb32f471f94f96dea3aba12186e9439840155e18 ./evidence/lsc1-09-cleanroom/clean-build-1/build.stdout +e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./evidence/lsc1-09-cleanroom/clean-build-1/ecppack.log +07b91105557953e74ad07c1abcd79b644580301eddb470bbfa1a9c2f3a9fcf17 ./evidence/lsc1-09-cleanroom/clean-build-1/nextpnr.log +47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba ./evidence/lsc1-09-cleanroom/clean-build-1/timing.txt +e026fa9460991757e1d8f6a077ae81a6e36607c93887d8b17979b3e0edf38f26 ./evidence/lsc1-09-cleanroom/clean-build-1/tool_versions.txt +226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e ./evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.bit +0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b ./evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.config +0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee ./evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.svf +bbfbb242f6bc0f3b02f1b105c1b3f7c981cab7be08deb71a995e69fe09acfdd7 ./evidence/lsc1-09-cleanroom/clean-build-1/yosys.log +cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf ./evidence/lsc1-09-cleanroom/clean-build-2/SHA256SUMS +0bc16e2f0a9ac2898397b294ee8598bab14d2e3e365b639ed14e3a2d3406dab8 ./evidence/lsc1-09-cleanroom/clean-build-2/SOURCE_MANIFEST.txt +e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./evidence/lsc1-09-cleanroom/clean-build-2/build.stderr +667c264f5ceb3a207c1e0b8deda6020d700963c2d60f7f50385acb8c2d5db38b ./evidence/lsc1-09-cleanroom/clean-build-2/build.stdout +e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./evidence/lsc1-09-cleanroom/clean-build-2/ecppack.log +3dc26a9f8dca3b968e034728fd453eb5234b148b8f039792f844d0395d4f6139 ./evidence/lsc1-09-cleanroom/clean-build-2/nextpnr.log +47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba ./evidence/lsc1-09-cleanroom/clean-build-2/timing.txt +e026fa9460991757e1d8f6a077ae81a6e36607c93887d8b17979b3e0edf38f26 ./evidence/lsc1-09-cleanroom/clean-build-2/tool_versions.txt +226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e ./evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.bit +0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b ./evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.config +0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee ./evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.svf +189e5d6c46bacdc04b208684042a95ce8f4f8887daece94e58bfdf7f71148b10 ./evidence/lsc1-09-cleanroom/clean-build-2/yosys.log +9c3c153138a30efdee397ddca8c50991fd30e960f626ecd242c9d61e6aa776a3 ./evidence/lsc1-09-cleanroom/reproduction-receipt.json 386956c565ea8a78d5ad39ed988dab49aeeff7c7f901f7ec166c89b4d039455d ./formal/LSC1U_COMPOSITIONAL_REFINEMENT.md ff660d3e6022c71f3dad4ad9f61565f137a9130c7c48d45fed892bd572beafc2 ./formal/LSC1U_XOR_REFINEMENT.md 05401a99f2d5ec82dba92a60a54c11a697174566aff9aa9a19bd8092d059615d ./formal/README.md @@ -559,10 +583,10 @@ b78b938f396ae20d1fdccde99281430778a879808e60a35788b6fe044151329c ./test/tb_stre 35973f5dec33bee955394cc0e7d4d3ca6d28b972bccdca968ec4152ecb6c99fb ./test/test_lsc1_05_v2_adversarial_regressions.py e9e334081265e38bcb8112537430c0f479725d93ef8add7aa21fc272a1ff6be0 ./test/test_lsc1_authored_rtl_contract.py d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_lsc1_blake3_status_workflow.py -739d601ff16a130bbe53d758dd3bbfd9c57a2edfa87c9fd25d215cbc43f0919d ./test/test_lsc1_fpga_packet_evidence.py +d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -69ef2d5a2c4c2a69081040d1bc47115ba4bf37eb8485d2d7ae3f3cd7f426b6bb ./test/test_lsc1_ulx3s_reproduction.py +2fa8f3fb0eb7bd1a9c6ae69b6aecac7c6a5978e5ca22bfacbc1d2586ff1e93ef ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py @@ -603,8 +627,8 @@ d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b ./tools/rtl_st a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py 6f6d2f97d96aeddd39e3bae8c4ea9193bec8a5a4237d5a17a93057e1d2c38f26 ./tools/verify_fabrication_bundle.py -c8043064d4d9ef0e6f9b2d5035a1a569c88d6f56bb16abef58cccef96c1617cc ./tools/verify_lsc1_fpga_packet_evidence.py -304d7850c0e59f3789b4d475d7eb68c0f3707189b92b474a65d61b5ef2197f2f ./tools/verify_lsc1_ulx3s_reproduction.py +39798bd016682b3ab57644a8eca7fedf46d5369d3c54230fdf8c4645c673536f ./tools/verify_lsc1_fpga_packet_evidence.py +e914ee72891c4a49a50e698a425e1d822501c0ad8408f31faf25e7a265d821ea ./tools/verify_lsc1_ulx3s_reproduction.py 650919f4b3f0d2a94022d4de230f16afca36fc5c3eee45b77571cb0ec5c52994 ./tools/verify_lsc1u_release_equivalence.py 4af566c345d8108c6b409f0c622fe132bdfc3b3a2b3eddee28f778e378d71254 ./tools/workload_validation.py d930b3a00795450bad3cfa1941fcc3028e03b5cf9724dab32c7f07d0678f38b4 ./workloads/blake3_stack.program.json diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/SHA256SUMS b/evidence/lsc1-09-cleanroom/clean-build-1/SHA256SUMS new file mode 100644 index 00000000..96118384 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/SHA256SUMS @@ -0,0 +1,3 @@ +226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e ulx3s_lsc1_packet.bit +0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b ulx3s_lsc1_packet.config +0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee ulx3s_lsc1_packet.svf diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/SOURCE_MANIFEST.txt b/evidence/lsc1-09-cleanroom/clean-build-1/SOURCE_MANIFEST.txt new file mode 100644 index 00000000..2bda79c1 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/SOURCE_MANIFEST.txt @@ -0,0 +1,28 @@ +=== SOURCE PROVENANCE === +revision: adc3e2c5b86fb08e1b0225573486ae08af4ac194 +inputs-match-revision: yes +d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 asic_core/rtl/gf128_mul_bitstream.sv +4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 asic_core/rtl/gf2n_mul_bitstream.sv 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asic_core/rtl/lsc1_packet_tx.sv +0d0cee24aea05b1a2ae2691a1cc46518af79b79e6228b8bb41031394c15b8d4f asic_core/rtl/lsc1_request_validator.sv +8adab68bd187db1d8fee337e6c4487304d4ad61f57d62d63ce1173bbe9ae1a2a asic_core/rtl/lsc1_response_payload_mux.sv +41b68a8068f417ff8f0d33f0408405f4fae5a7b5e2fd60b482d11148e541e6c7 asic_core/rtl/lsc1_stream_adapter.sv +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +5a4a26710548d8bc7908cbfc33d611fad6de8f825cf5585bc94aed9ae6cfb804 fpga/ulx3s/build_packet_uart.sh +31f67a30da28cd68594e3e84ee9b44af08759a57990312c20a09d7a950569c97 fpga/ulx3s/uart_bridge.sv +042f81e94f1e7e45ca810b85ca90e3d8f11fd5d670718ccd0ae65db33cfccaf1 fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 fpga/ulx3s/uart_tx.sv +0d0d1e9821163e7289883bca7b9e16e81fa454079e1942f198ed9688d30576f3 fpga/ulx3s/ulx3s_core_pll.sv +89cbe328d101570ec2c8e874f61134d6cd293c5b39c47e53f34cef0e56d9089a fpga/ulx3s/ulx3s_packet_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/build.stderr b/evidence/lsc1-09-cleanroom/clean-build-1/build.stderr new file mode 100644 index 00000000..e69de29b diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/build.stdout b/evidence/lsc1-09-cleanroom/clean-build-1/build.stdout new file mode 100644 index 00000000..d086e561 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/build.stdout @@ -0,0 +1,44 @@ +=== TOOL VERSIONS (LSC-1 PACKET UART) === +Yosys 0.33 (git sha1 2584903a060) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.11.1) +Project Trellis ecppack Version 1.4-2build4 +date: 2026-09-06T00:58:29Z +=== SOURCE PROVENANCE === +revision: adc3e2c5b86fb08e1b0225573486ae08af4ac194 +inputs-match-revision: yes +d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 asic_core/rtl/gf128_mul_bitstream.sv +4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 asic_core/rtl/gf2n_mul_bitstream.sv +192eddc1727d8976ea48db9a532f44893d06bdec7651c65a1b1b99502b5e70c5 asic_core/rtl/lean_silicon_lsc1.sv +774b239a6221619559c57f0e00aad4000b507fd7c941dc9da204c1e357d6ad90 asic_core/rtl/lean_silicon_lsc1_mincore.sv +bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b asic_core/rtl/leanvm_b_stream_alu.sv +37a01a30bfa5dd52e05854ec4f9c0cb11c0959d95d610d0fb383e5fdd08af4f9 asic_core/rtl/lsc1_blake3_alias_check.sv +af51a2f56073aee7ef95c183e06d0e7c0e0613a0c7193d9f883ed26b026986a8 asic_core/rtl/lsc1_blake3_lifecycle.sv +d89d5cef0c529810a8a456892aaf13134e3b7ce34894f4c45da43ba81c7e066d asic_core/rtl/lsc1_cell_alias_check.sv +5fafb0f5fe81ac5aaf32d0d9974d7d7d2e2b66dde05cdb707e2067ab516f5e05 asic_core/rtl/lsc1_field_encoder.sv +bbf7b0d27ccfb371b45a5b9627f1eb10257056ac7c4b1ba3ca1be1bdbeadac4d asic_core/rtl/lsc1_packet_frontend.sv +311d30b3bfb4603c6b722183fd289a62cc48ccad72adb792100cfd435397cff3 asic_core/rtl/lsc1_packet_rx.sv +8a9a1c80b85fbeb253f955e618dc1521aff6fb432698c8bb5eef743e1eefcb2e asic_core/rtl/lsc1_packet_tx.sv +0d0cee24aea05b1a2ae2691a1cc46518af79b79e6228b8bb41031394c15b8d4f asic_core/rtl/lsc1_request_validator.sv +8adab68bd187db1d8fee337e6c4487304d4ad61f57d62d63ce1173bbe9ae1a2a asic_core/rtl/lsc1_response_payload_mux.sv +41b68a8068f417ff8f0d33f0408405f4fae5a7b5e2fd60b482d11148e541e6c7 asic_core/rtl/lsc1_stream_adapter.sv +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +5a4a26710548d8bc7908cbfc33d611fad6de8f825cf5585bc94aed9ae6cfb804 fpga/ulx3s/build_packet_uart.sh +31f67a30da28cd68594e3e84ee9b44af08759a57990312c20a09d7a950569c97 fpga/ulx3s/uart_bridge.sv +042f81e94f1e7e45ca810b85ca90e3d8f11fd5d670718ccd0ae65db33cfccaf1 fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 fpga/ulx3s/uart_tx.sv +0d0d1e9821163e7289883bca7b9e16e81fa454079e1942f198ed9688d30576f3 fpga/ulx3s/ulx3s_core_pll.sv +89cbe328d101570ec2c8e874f61134d6cd293c5b39c47e53f34cef0e56d9089a fpga/ulx3s/ulx3s_packet_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf +ulx3s_lsc1_packet.bit: OK +ulx3s_lsc1_packet.config: OK +ulx3s_lsc1_packet.svf: OK +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +bitstream: /tmp/lean-silicon-lsc1-repair.qocLpF/run-1/results/ulx3s-lsc1-packet-20260726/ulx3s_lsc1_packet.bit +sha256: 226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/ecppack.log b/evidence/lsc1-09-cleanroom/clean-build-1/ecppack.log new file mode 100644 index 00000000..e69de29b diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/nextpnr.log b/evidence/lsc1-09-cleanroom/clean-build-1/nextpnr.log new file mode 100644 index 00000000..6caffda3 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/nextpnr.log @@ -0,0 +1,3442 @@ +Info: constraining clock net 'clk' to 25.00 MHz + +Info: Logic utilisation before packing: +Info: Total LUT4s: 28745/83640 34% +Info: logic LUTs: 27175/83640 32% +Info: carry LUTs: 1570/83640 1% +Info: RAM LUTs: 0/10455 0% +Info: RAMW LUTs: 0/20910 0% + +Info: Total DFFs: 7221/83640 8% + +Info: Packing IOs.. +Info: pin 'uart_tx$tr_io' constrained to Bel 'X0/Y56/PIOC'. +Info: pin 'uart_rx$tr_io' constrained to Bel 'X0/Y89/PIOB'. +Info: pin 'led$tr_io' constrained to Bel 'X0/Y35/PIOC'. +Info: pin 'clk$tr_io' constrained to Bel 'X0/Y47/PIOA'. +Info: placed PLL 'core_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL' +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 5684 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Promoting globals... +Info: promoting clock net core_clk to global network +Info: Checksum: 0xa96ca5f1 + +Info: Device utilisation: +Info: TRELLIS_IO: 4/ 365 1% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 208 0% +Info: MULT18X18D: 1/ 156 0% +Info: ALU54B: 0/ 78 0% +Info: EHXPLLL: 1/ 4 25% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 224 0% +Info: SIOLOGIC: 0/ 141 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 14 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 7221/ 83640 8% +Info: TRELLIS_COMB: 29127/ 83640 34% +Info: TRELLIS_RAMW: 0/ 10455 0% + +Info: Running Static placer... +Info: ⌁ bel grid 127x96, placer grid 127x95... +Info: ⌁ initialising bels... +Info: ⌁ initialising cells... +Info: ⌁ inserting spacers... +Info: ⌁ group COMB pre-spacer utilisation 34.82% (target 70.00%) +Info: ⌁ group COMB inserted a total of 29420 spacers +Info: ⌁ group FF pre-spacer utilisation 8.63% (target 70.00%) +Info: ⌁ group FF inserted a total of 51326 spacers +Info: ⌁ group RAM pre-spacer utilisation 0.00% (target 70.00%) +Info: ⌁ group RAM inserted a total of 145 spacers +Info: ⌁ group MUL pre-spacer utilisation 0.64% (target 70.00%) +Info: ⌁ group MUL inserted a total of 108 spacers +Info: initial density penalty: 0.000025 +Info: coord_dist: 0.000621 grad_dist: 0.000244 +Info: initial steplen=0.010000 next steplen = 2.542392 +Info: coord_dist: 0.000621 grad_dist: 0.000244 +Info: iter=0 steplen=2.542392 a=1.000000 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.00 +Info: system potential: 8514805.000000 hpwl: 20096.478516 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: Strict legalising 7 cells... +Info: HPWL after legalise: 20224.486328 (delta: 128.007812) +Info: coord_dist: 0.157905 grad_dist: 0.066841 +Info: iter=1 steplen=2.362397 a=1.618034 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.40 +Info: system potential: 8582809.000000 hpwl: 13807.583984 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.075696 grad_dist: 0.039319 +Info: iter=2 steplen=1.925172 a=2.193527 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.60 +Info: system potential: 8598067.000000 hpwl: 10372.306641 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.054848 grad_dist: 0.034262 +Info: iter=3 steplen=1.600815 a=2.749791 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.79 +Info: system potential: 8605408.000000 hpwl: 8136.815430 +Info: overlap: COMB=99.7%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035386 grad_dist: 0.022816 +Info: iter=4 steplen=1.550963 a=3.294880 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.94 +Info: system potential: 8609257.000000 hpwl: 6795.866699 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021060 grad_dist: 0.012018 +Info: iter=5 steplen=1.752297 a=3.832601 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.07 +Info: system potential: 8606709.000000 hpwl: 5815.658203 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016144 grad_dist: 0.007474 +Info: iter=6 steplen=2.159947 a=4.365079 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.17 +Info: system potential: 8597473.000000 hpwl: 5038.107422 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016653 grad_dist: 0.008327 +Info: iter=7 steplen=1.999925 a=4.893622 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.27 +Info: system potential: 8589082.000000 hpwl: 4389.816406 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018115 grad_dist: 0.011364 +Info: iter=8 steplen=1.594051 a=5.419099 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.38 +Info: system potential: 8582088.000000 hpwl: 3739.517578 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016821 grad_dist: 0.011320 +Info: iter=9 steplen=1.485981 a=5.942117 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.48 +Info: system potential: 8577730.000000 hpwl: 3270.938721 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012070 grad_dist: 0.007600 +Info: iter=10 steplen=1.588207 a=6.463116 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.59 +Info: system potential: 8571819.000000 hpwl: 2953.775391 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008682 grad_dist: 0.004639 +Info: iter=11 steplen=1.871586 a=6.982428 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.70 +Info: system potential: 8567021.000000 hpwl: 2721.067383 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007932 grad_dist: 0.004161 +Info: iter=12 steplen=1.906472 a=7.500307 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.83 +Info: system potential: 8563001.000000 hpwl: 2531.046875 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008403 grad_dist: 0.005095 +Info: iter=13 steplen=1.649297 a=8.016954 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.95 +Info: system potential: 8561013.000000 hpwl: 2338.870605 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008331 grad_dist: 0.005430 +Info: iter=14 steplen=1.534174 a=8.532532 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.08 +Info: system potential: 8558900.000000 hpwl: 2181.093506 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006953 grad_dist: 0.004373 +Info: iter=15 steplen=1.589933 a=9.047169 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.20 +Info: system potential: 8556616.000000 hpwl: 2067.925293 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005590 grad_dist: 0.003171 +Info: iter=16 steplen=1.762770 a=9.560975 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.32 +Info: system potential: 8552007.000000 hpwl: 1983.437378 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005148 grad_dist: 0.002826 +Info: iter=17 steplen=1.821740 a=10.074040 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.43 +Info: system potential: 8549572.000000 hpwl: 1910.777222 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005337 grad_dist: 0.003162 +Info: iter=18 steplen=1.687788 a=10.586441 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.54 +Info: system potential: 8549344.000000 hpwl: 1835.611328 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005431 grad_dist: 0.003400 +Info: iter=19 steplen=1.597300 a=11.098242 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.65 +Info: system potential: 8546717.000000 hpwl: 1767.199219 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005018 grad_dist: 0.003089 +Info: iter=20 steplen=1.624351 a=11.609499 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.76 +Info: system potential: 8544092.000000 hpwl: 1716.198486 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004486 grad_dist: 0.002603 +Info: iter=21 steplen=1.723353 a=12.120261 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.88 +Info: system potential: 8544484.000000 hpwl: 1680.581421 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004293 grad_dist: 0.002436 +Info: iter=22 steplen=1.762445 a=12.630569 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.98 +Info: system potential: 8543948.000000 hpwl: 1653.231567 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004402 grad_dist: 0.002599 +Info: iter=23 steplen=1.693478 a=13.140462 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.10 +Info: system potential: 8541987.000000 hpwl: 1626.857300 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004483 grad_dist: 0.002743 +Info: iter=24 steplen=1.634380 a=13.649971 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.22 +Info: system potential: 8540601.000000 hpwl: 1602.899780 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004320 grad_dist: 0.002626 +Info: iter=25 steplen=1.645450 a=14.159125 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.34 +Info: system potential: 8536555.000000 hpwl: 1586.517334 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004065 grad_dist: 0.002393 +Info: iter=26 steplen=1.698927 a=14.667951 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.47 +Info: system potential: 8535830.000000 hpwl: 1575.769775 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003949 grad_dist: 0.002297 +Info: iter=27 steplen=1.719671 a=15.176470 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.58 +Info: system potential: 8535099.000000 hpwl: 1568.298950 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003982 grad_dist: 0.002365 +Info: iter=28 steplen=1.683457 a=15.684704 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.70 +Info: system potential: 8533242.000000 hpwl: 1559.154297 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004000 grad_dist: 0.002426 +Info: iter=29 steplen=1.648507 a=16.192673 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.82 +Info: system potential: 8532322.000000 hpwl: 1550.568970 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003890 grad_dist: 0.002355 +Info: iter=30 steplen=1.652200 a=16.700390 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.93 +Info: system potential: 8531519.000000 hpwl: 1543.876099 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003722 grad_dist: 0.002217 +Info: iter=31 steplen=1.679111 a=17.207872 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.05 +Info: system potential: 8529541.000000 hpwl: 1540.543945 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003612 grad_dist: 0.002139 +Info: iter=32 steplen=1.688514 a=17.715136 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.17 +Info: system potential: 8529077.000000 hpwl: 1538.243408 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003571 grad_dist: 0.002139 +Info: iter=33 steplen=1.669522 a=18.222191 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.28 +Info: system potential: 8529539.000000 hpwl: 1536.187500 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003521 grad_dist: 0.002133 +Info: iter=34 steplen=1.650666 a=18.729050 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.40 +Info: system potential: 8527445.000000 hpwl: 1534.105103 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003412 grad_dist: 0.002065 +Info: iter=35 steplen=1.652514 a=19.235723 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.51 +Info: system potential: 8526462.000000 hpwl: 1533.675049 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003276 grad_dist: 0.001966 +Info: iter=36 steplen=1.666453 a=19.742220 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.63 +Info: system potential: 8525433.000000 hpwl: 1534.347412 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003171 grad_dist: 0.001897 +Info: iter=37 steplen=1.671391 a=20.248550 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.76 +Info: system potential: 8526380.000000 hpwl: 1535.843140 +Info: overlap: COMB=99.7%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003102 grad_dist: 0.001866 +Info: iter=38 steplen=1.662205 a=20.754723 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.87 +Info: system potential: 8526406.000000 hpwl: 1537.221680 +Info: overlap: COMB=99.7%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003035 grad_dist: 0.001835 +Info: iter=39 steplen=1.653676 a=21.260744 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.99 +Info: system potential: 8526979.000000 hpwl: 1539.255981 +Info: overlap: COMB=99.7%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002948 grad_dist: 0.001780 +Info: iter=40 steplen=1.656143 a=21.766623 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.11 +Info: system potential: 8525591.000000 hpwl: 1542.428101 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002857 grad_dist: 0.001717 +Info: iter=41 steplen=1.664403 a=22.272364 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.23 +Info: system potential: 8525118.000000 hpwl: 1546.994385 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002788 grad_dist: 0.001672 +Info: iter=42 steplen=1.667891 a=22.777975 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.35 +Info: system potential: 8523290.000000 hpwl: 1552.597778 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002744 grad_dist: 0.001648 +Info: iter=43 steplen=1.665321 a=23.283461 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.47 +Info: system potential: 8522112.000000 hpwl: 1559.111572 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002709 grad_dist: 0.001628 +Info: iter=44 steplen=1.663431 a=23.788830 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.59 +Info: system potential: 8519849.000000 hpwl: 1566.114624 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002676 grad_dist: 0.001605 +Info: iter=45 steplen=1.667239 a=24.294085 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.72 +Info: system potential: 8518502.000000 hpwl: 1573.757080 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002653 grad_dist: 0.001585 +Info: iter=46 steplen=1.673540 a=24.799229 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.84 +Info: system potential: 8517161.000000 hpwl: 1581.522461 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002650 grad_dist: 0.001580 +Info: iter=47 steplen=1.677325 a=25.304270 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.96 +Info: system potential: 8515713.000000 hpwl: 1589.523926 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002668 grad_dist: 0.001590 +Info: iter=48 steplen=1.677365 a=25.809210 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.07 +Info: system potential: 8515972.000000 hpwl: 1597.237549 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002698 grad_dist: 0.001608 +Info: iter=49 steplen=1.677481 a=26.314053 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.20 +Info: system potential: 8513372.000000 hpwl: 1604.944458 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002735 grad_dist: 0.001628 +Info: iter=50 steplen=1.679927 a=26.818802 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.32 +Info: system potential: 8511293.000000 hpwl: 1612.398926 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002781 grad_dist: 0.001652 +Info: iter=51 steplen=1.683222 a=27.323462 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.44 +Info: system potential: 8509669.000000 hpwl: 1620.124268 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002840 grad_dist: 0.001686 +Info: iter=52 steplen=1.684606 a=27.828035 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.57 +Info: system potential: 8511234.000000 hpwl: 1627.488037 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002910 grad_dist: 0.001728 +Info: iter=53 steplen=1.684033 a=28.332527 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.69 +Info: system potential: 8512777.000000 hpwl: 1635.078369 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002986 grad_dist: 0.001774 +Info: iter=54 steplen=1.683441 a=28.836939 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.81 +Info: system potential: 8514427.000000 hpwl: 1642.497925 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003064 grad_dist: 0.001820 +Info: iter=55 steplen=1.683243 a=29.341272 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.92 +Info: system potential: 8512579.000000 hpwl: 1650.272949 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003145 grad_dist: 0.001867 +Info: iter=56 steplen=1.684613 a=29.845533 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.04 +Info: system potential: 8509419.000000 hpwl: 1657.951294 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003232 grad_dist: 0.001918 +Info: iter=57 steplen=1.685404 a=30.349722 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.16 +Info: system potential: 8507435.000000 hpwl: 1665.997192 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003325 grad_dist: 0.001974 +Info: iter=58 steplen=1.684822 a=30.853840 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.29 +Info: system potential: 8507813.000000 hpwl: 1673.851807 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003423 grad_dist: 0.002033 +Info: iter=59 steplen=1.683768 a=31.357891 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.40 +Info: system potential: 8505955.000000 hpwl: 1681.950195 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003521 grad_dist: 0.002092 +Info: iter=60 steplen=1.683519 a=31.861877 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.52 +Info: system potential: 8502002.000000 hpwl: 1689.939331 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003620 grad_dist: 0.002150 +Info: iter=61 steplen=1.684048 a=32.365799 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.65 +Info: system potential: 8500115.000000 hpwl: 1698.280029 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003723 grad_dist: 0.002211 +Info: iter=62 steplen=1.684241 a=32.869659 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.76 +Info: system potential: 8498147.000000 hpwl: 1706.541870 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003830 grad_dist: 0.002275 +Info: iter=63 steplen=1.683796 a=33.373463 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.88 +Info: system potential: 8496199.000000 hpwl: 1715.107666 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003940 grad_dist: 0.002341 +Info: iter=64 steplen=1.683232 a=33.877209 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.01 +Info: system potential: 8494107.000000 hpwl: 1723.658203 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004051 grad_dist: 0.002407 +Info: iter=65 steplen=1.683157 a=34.380898 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.11 +Info: system potential: 8492958.000000 hpwl: 1732.588257 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004165 grad_dist: 0.002474 +Info: iter=66 steplen=1.683469 a=34.884533 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.23 +Info: system potential: 8492325.000000 hpwl: 1741.576660 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004281 grad_dist: 0.002543 +Info: iter=67 steplen=1.683365 a=35.388115 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.36 +Info: system potential: 8486891.000000 hpwl: 1750.923218 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004401 grad_dist: 0.002615 +Info: iter=68 steplen=1.683104 a=35.891647 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.46 +Info: system potential: 8482260.000000 hpwl: 1760.320557 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004524 grad_dist: 0.002688 +Info: iter=69 steplen=1.683297 a=36.395130 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.58 +Info: system potential: 8479875.000000 hpwl: 1770.121704 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004651 grad_dist: 0.002762 +Info: iter=70 steplen=1.683671 a=36.898563 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.70 +Info: system potential: 8478173.000000 hpwl: 1780.125366 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004782 grad_dist: 0.002840 +Info: iter=71 steplen=1.683787 a=37.401951 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.81 +Info: system potential: 8472433.000000 hpwl: 1790.523926 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004917 grad_dist: 0.002921 +Info: iter=72 steplen=1.683692 a=37.905293 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.93 +Info: system potential: 8467401.000000 hpwl: 1801.082397 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005057 grad_dist: 0.003003 +Info: iter=73 steplen=1.683696 a=38.408588 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.05 +Info: system potential: 8464948.000000 hpwl: 1812.117432 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005200 grad_dist: 0.003088 +Info: iter=74 steplen=1.683964 a=38.911842 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.16 +Info: system potential: 8463548.000000 hpwl: 1823.383911 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005347 grad_dist: 0.003174 +Info: iter=75 steplen=1.684380 a=39.415054 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.27 +Info: system potential: 8461371.000000 hpwl: 1835.103516 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005500 grad_dist: 0.003265 +Info: iter=76 steplen=1.684658 a=39.918224 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.38 +Info: system potential: 8461066.000000 hpwl: 1847.145142 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005658 grad_dist: 0.003358 +Info: iter=77 steplen=1.684687 a=40.421356 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.50 +Info: system potential: 8458474.000000 hpwl: 1859.591431 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005821 grad_dist: 0.003455 +Info: iter=78 steplen=1.684895 a=40.924446 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.61 +Info: system potential: 8456665.000000 hpwl: 1872.411865 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005988 grad_dist: 0.003553 +Info: iter=79 steplen=1.685361 a=41.427502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.72 +Info: system potential: 8459255.000000 hpwl: 1885.696899 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006160 grad_dist: 0.003655 +Info: iter=80 steplen=1.685378 a=41.930519 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.83 +Info: system potential: 8456068.000000 hpwl: 1899.391968 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006340 grad_dist: 0.003760 +Info: iter=81 steplen=1.686169 a=42.433502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.95 +Info: system potential: 8454533.000000 hpwl: 1913.641479 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006526 grad_dist: 0.003868 +Info: iter=82 steplen=1.686917 a=42.936447 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.06 +Info: system potential: 8461490.000000 hpwl: 1928.404541 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006720 grad_dist: 0.003983 +Info: iter=83 steplen=1.687244 a=43.439358 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.17 +Info: system potential: 8463342.000000 hpwl: 1943.686646 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006924 grad_dist: 0.004103 +Info: iter=84 steplen=1.687602 a=43.942234 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.28 +Info: system potential: 8471180.000000 hpwl: 1959.590698 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007133 grad_dist: 0.004226 +Info: iter=85 steplen=1.688087 a=44.445080 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.40 +Info: system potential: 8467627.000000 hpwl: 1976.066406 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007351 grad_dist: 0.004353 +Info: iter=86 steplen=1.688851 a=44.947891 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.51 +Info: system potential: 8464463.000000 hpwl: 1993.311646 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007578 grad_dist: 0.004485 +Info: iter=87 steplen=1.689589 a=45.450672 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.62 +Info: system potential: 8463951.000000 hpwl: 2011.174194 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007815 grad_dist: 0.004624 +Info: iter=88 steplen=1.690159 a=45.953423 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.73 +Info: system potential: 8459463.000000 hpwl: 2029.907959 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008062 grad_dist: 0.004768 +Info: iter=89 steplen=1.690795 a=46.456142 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.85 +Info: system potential: 8454278.000000 hpwl: 2049.376465 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008318 grad_dist: 0.004918 +Info: iter=90 steplen=1.691517 a=46.958832 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.97 +Info: system potential: 8451459.000000 hpwl: 2069.900146 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008584 grad_dist: 0.005073 +Info: iter=91 steplen=1.692062 a=47.461494 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.08 +Info: system potential: 8448445.000000 hpwl: 2091.127441 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008860 grad_dist: 0.005234 +Info: iter=92 steplen=1.692882 a=47.964130 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.20 +Info: system potential: 8445511.000000 hpwl: 2113.532227 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009148 grad_dist: 0.005400 +Info: iter=93 steplen=1.694047 a=48.466736 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.32 +Info: system potential: 8435234.000000 hpwl: 2136.761230 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009449 grad_dist: 0.005575 +Info: iter=94 steplen=1.694966 a=48.969315 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.43 +Info: system potential: 8430420.000000 hpwl: 2161.344971 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009764 grad_dist: 0.005759 +Info: iter=95 steplen=1.695576 a=49.471867 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.56 +Info: system potential: 8420643.000000 hpwl: 2186.796875 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010091 grad_dist: 0.005949 +Info: iter=96 steplen=1.696301 a=49.974392 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.68 +Info: system potential: 8414419.000000 hpwl: 2213.828369 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010430 grad_dist: 0.006145 +Info: iter=97 steplen=1.697423 a=50.476894 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.80 +Info: system potential: 8395722.000000 hpwl: 2241.787842 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010782 grad_dist: 0.006348 +Info: iter=98 steplen=1.698540 a=50.979370 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.93 +Info: system potential: 8379563.500000 hpwl: 2271.525635 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011149 grad_dist: 0.006560 +Info: iter=99 steplen=1.699444 a=51.481823 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.05 +Info: system potential: 8368260.500000 hpwl: 2302.227783 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011530 grad_dist: 0.006782 +Info: iter=100 steplen=1.700242 a=51.984253 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.17 +Info: system potential: 8352019.000000 hpwl: 2334.883545 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011925 grad_dist: 0.007009 +Info: iter=101 steplen=1.701323 a=52.486656 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.30 +Info: system potential: 8343772.500000 hpwl: 2368.516357 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012328 grad_dist: 0.007244 +Info: iter=102 steplen=1.701805 a=52.989037 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.43 +Info: system potential: 8329875.000000 hpwl: 2404.383545 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012748 grad_dist: 0.007484 +Info: iter=103 steplen=1.703336 a=53.491394 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.56 +Info: system potential: 8316487.000000 hpwl: 2441.320068 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.013181 grad_dist: 0.007731 +Info: iter=104 steplen=1.704924 a=53.993732 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.69 +Info: system potential: 8301330.500000 hpwl: 2480.910645 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.013634 grad_dist: 0.007992 +Info: iter=105 steplen=1.705991 a=54.496048 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.84 +Info: system potential: 8281380.000000 hpwl: 2521.450195 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.014106 grad_dist: 0.008265 +Info: iter=106 steplen=1.706677 a=54.998341 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.97 +Info: system potential: 8260743.000000 hpwl: 2564.805420 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.014588 grad_dist: 0.008543 +Info: iter=107 steplen=1.707478 a=55.500614 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.11 +Info: system potential: 8239633.500000 hpwl: 2608.909180 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.015077 grad_dist: 0.008825 +Info: iter=108 steplen=1.708554 a=56.002865 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.26 +Info: system potential: 8210766.000000 hpwl: 2656.306885 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.015578 grad_dist: 0.009111 +Info: iter=109 steplen=1.709830 a=56.505096 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.41 +Info: system potential: 8188782.000000 hpwl: 2704.452637 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016091 grad_dist: 0.009406 +Info: iter=110 steplen=1.710742 a=57.007309 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.56 +Info: system potential: 8165506.000000 hpwl: 2756.184570 +Info: overlap: COMB=99.4%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016617 grad_dist: 0.009708 +Info: iter=111 steplen=1.711671 a=57.509502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.71 +Info: system potential: 8138830.500000 hpwl: 2808.476807 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.017146 grad_dist: 0.010015 +Info: iter=112 steplen=1.712127 a=58.011677 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.88 +Info: system potential: 8107955.000000 hpwl: 2864.552490 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.017684 grad_dist: 0.010322 +Info: iter=113 steplen=1.713264 a=58.513832 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.05 +Info: system potential: 8077053.500000 hpwl: 2920.982178 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018228 grad_dist: 0.010630 +Info: iter=114 steplen=1.714753 a=59.015968 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.21 +Info: system potential: 8044288.000000 hpwl: 2981.765137 +Info: overlap: COMB=99.5%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018786 grad_dist: 0.010948 +Info: iter=115 steplen=1.715950 a=59.518085 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.39 +Info: system potential: 8009852.500000 hpwl: 3042.644531 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.019357 grad_dist: 0.011276 +Info: iter=116 steplen=1.716622 a=60.020187 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.56 +Info: system potential: 7973161.000000 hpwl: 3107.905273 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.019937 grad_dist: 0.011608 +Info: iter=117 steplen=1.717462 a=60.522270 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.75 +Info: system potential: 7947153.000000 hpwl: 3173.127686 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.020518 grad_dist: 0.011939 +Info: iter=118 steplen=1.718579 a=61.024338 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.94 +Info: system potential: 7918307.500000 hpwl: 3243.307617 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021108 grad_dist: 0.012272 +Info: iter=119 steplen=1.720080 a=61.526386 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.15 +Info: system potential: 7881625.500000 hpwl: 3313.404297 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021711 grad_dist: 0.012613 +Info: iter=120 steplen=1.721361 a=62.028416 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.35 +Info: system potential: 7848025.000000 hpwl: 3388.735596 +Info: overlap: COMB=99.4%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.022331 grad_dist: 0.012964 +Info: iter=121 steplen=1.722475 a=62.530430 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.56 +Info: system potential: 7819774.500000 hpwl: 3463.793213 +Info: overlap: COMB=99.4%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.022962 grad_dist: 0.013321 +Info: iter=122 steplen=1.723732 a=63.032429 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.77 +Info: system potential: 7803936.000000 hpwl: 3544.241943 +Info: overlap: COMB=99.4%, FF=98.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.023604 grad_dist: 0.013682 +Info: iter=123 steplen=1.725162 a=63.534412 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.00 +Info: system potential: 7772771.500000 hpwl: 3624.341553 +Info: overlap: COMB=99.4%, FF=98.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.024249 grad_dist: 0.014051 +Info: iter=124 steplen=1.725753 a=64.036377 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.23 +Info: system potential: 7734660.500000 hpwl: 3709.754883 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.024898 grad_dist: 0.014421 +Info: iter=125 steplen=1.726456 a=64.538330 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.47 +Info: system potential: 7683216.500000 hpwl: 3794.507812 +Info: overlap: COMB=99.4%, FF=98.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.025540 grad_dist: 0.014787 +Info: iter=126 steplen=1.727227 a=65.040268 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.71 +Info: system potential: 7622771.000000 hpwl: 3884.712158 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.026176 grad_dist: 0.015150 +Info: iter=127 steplen=1.727807 a=65.542191 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.95 +Info: system potential: 7560831.500000 hpwl: 3973.969727 +Info: overlap: COMB=99.3%, FF=98.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.026805 grad_dist: 0.015513 +Info: iter=128 steplen=1.727903 a=66.044098 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.20 +Info: system potential: 7504115.500000 hpwl: 4068.275879 +Info: overlap: COMB=99.4%, FF=98.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.027419 grad_dist: 0.015869 +Info: iter=129 steplen=1.727766 a=66.545990 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.46 +Info: system potential: 7448961.500000 hpwl: 4161.238770 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.028011 grad_dist: 0.016213 +Info: iter=130 steplen=1.727689 a=67.047867 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.73 +Info: system potential: 7388779.000000 hpwl: 4259.378906 +Info: overlap: COMB=99.3%, FF=98.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.028584 grad_dist: 0.016544 +Info: iter=131 steplen=1.727765 a=67.549728 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.02 +Info: system potential: 7322618.500000 hpwl: 4356.195801 +Info: overlap: COMB=99.3%, FF=98.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.029145 grad_dist: 0.016868 +Info: iter=132 steplen=1.727790 a=68.051582 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.31 +Info: system potential: 7250014.500000 hpwl: 4458.327148 +Info: overlap: COMB=99.3%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.029699 grad_dist: 0.017189 +Info: iter=133 steplen=1.727787 a=68.553421 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.62 +Info: system potential: 7182640.500000 hpwl: 4558.850098 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.030246 grad_dist: 0.017507 +Info: iter=134 steplen=1.727680 a=69.055244 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.94 +Info: system potential: 7119545.500000 hpwl: 4664.079590 +Info: overlap: COMB=99.3%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.030790 grad_dist: 0.017821 +Info: iter=135 steplen=1.727712 a=69.557053 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.27 +Info: system potential: 7064553.000000 hpwl: 4767.367676 +Info: overlap: COMB=99.3%, FF=98.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.031330 grad_dist: 0.018132 +Info: iter=136 steplen=1.727878 a=70.058853 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.62 +Info: system potential: 7001991.500000 hpwl: 4875.217285 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.031872 grad_dist: 0.018444 +Info: iter=137 steplen=1.728110 a=70.560638 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.97 +Info: system potential: 6946372.000000 hpwl: 4980.763184 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.032417 grad_dist: 0.018757 +Info: iter=138 steplen=1.728230 a=71.062408 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 20.33 +Info: system potential: 6880503.500000 hpwl: 5090.250977 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.032961 grad_dist: 0.019072 +Info: iter=139 steplen=1.728226 a=71.564163 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 20.70 +Info: system potential: 6823283.500000 hpwl: 5197.462402 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.033502 grad_dist: 0.019384 +Info: iter=140 steplen=1.728340 a=72.065910 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.10 +Info: system potential: 6767464.000000 hpwl: 5308.474121 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.034035 grad_dist: 0.019691 +Info: iter=141 steplen=1.728468 a=72.567650 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.49 +Info: system potential: 6714823.500000 hpwl: 5417.166504 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.034566 grad_dist: 0.019995 +Info: iter=142 steplen=1.728731 a=73.069374 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.89 +Info: system potential: 6667323.000000 hpwl: 5529.572266 +Info: overlap: COMB=99.1%, FF=97.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035097 grad_dist: 0.020297 +Info: iter=143 steplen=1.729220 a=73.571083 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 22.30 +Info: system potential: 6621768.500000 hpwl: 5640.035156 +Info: overlap: COMB=99.1%, FF=97.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035635 grad_dist: 0.020601 +Info: iter=144 steplen=1.729806 a=74.072784 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 22.73 +Info: system potential: 6580090.000000 hpwl: 5754.417480 +Info: overlap: COMB=99.1%, FF=97.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.036181 grad_dist: 0.020911 +Info: iter=145 steplen=1.730254 a=74.574471 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 23.15 +Info: system potential: 6537505.000000 hpwl: 5866.941895 +Info: overlap: COMB=99.1%, FF=97.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.036738 grad_dist: 0.021226 +Info: iter=146 steplen=1.730841 a=75.076149 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 23.58 +Info: system potential: 6489350.500000 hpwl: 5983.432129 +Info: overlap: COMB=99.1%, FF=97.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.037302 grad_dist: 0.021543 +Info: iter=147 steplen=1.731514 a=75.577812 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.03 +Info: system potential: 6446750.000000 hpwl: 6098.070312 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.037880 grad_dist: 0.021866 +Info: iter=148 steplen=1.732381 a=76.079468 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.49 +Info: system potential: 6407622.500000 hpwl: 6216.986328 +Info: overlap: COMB=99.0%, FF=97.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.038470 grad_dist: 0.022197 +Info: iter=149 steplen=1.733097 a=76.581108 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.96 +Info: system potential: 6374991.000000 hpwl: 6333.979004 +Info: overlap: COMB=99.0%, FF=97.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.039079 grad_dist: 0.022538 +Info: iter=150 steplen=1.733952 a=77.082741 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 25.44 +Info: system potential: 6334709.500000 hpwl: 6455.270508 +Info: overlap: COMB=99.0%, FF=97.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.039702 grad_dist: 0.022886 +Info: iter=151 steplen=1.734775 a=77.584366 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 25.93 +Info: system potential: 6294619.000000 hpwl: 6574.238770 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.040343 grad_dist: 0.023243 +Info: iter=152 steplen=1.735721 a=78.085976 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 26.44 +Info: system potential: 6256852.500000 hpwl: 6698.014160 +Info: overlap: COMB=98.9%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.041001 grad_dist: 0.023611 +Info: iter=153 steplen=1.736511 a=78.587578 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 26.94 +Info: system potential: 6222937.500000 hpwl: 6819.216797 +Info: overlap: COMB=98.9%, FF=96.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.041680 grad_dist: 0.023989 +Info: iter=154 steplen=1.737449 a=79.089165 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 27.45 +Info: system potential: 6179733.000000 hpwl: 6945.390625 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.042376 grad_dist: 0.024378 +Info: iter=155 steplen=1.738280 a=79.590744 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 27.96 +Info: system potential: 6143025.000000 hpwl: 7068.854492 +Info: overlap: COMB=98.9%, FF=96.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.043095 grad_dist: 0.024779 +Info: iter=156 steplen=1.739177 a=80.092316 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 28.45 +Info: system potential: 6104339.000000 hpwl: 7197.405762 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.043833 grad_dist: 0.025193 +Info: iter=157 steplen=1.739931 a=80.593872 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 28.95 +Info: system potential: 6063214.000000 hpwl: 7322.881836 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.044597 grad_dist: 0.025618 +Info: iter=158 steplen=1.740822 a=81.095421 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 29.42 +Info: system potential: 6025433.500000 hpwl: 7453.872559 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.045379 grad_dist: 0.026057 +Info: iter=159 steplen=1.741497 a=81.596962 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 29.89 +Info: system potential: 5979945.500000 hpwl: 7581.052246 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.046188 grad_dist: 0.026509 +Info: iter=160 steplen=1.742310 a=82.098495 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 30.35 +Info: system potential: 5933397.000000 hpwl: 7714.185547 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.047012 grad_dist: 0.026974 +Info: iter=161 steplen=1.742875 a=82.600021 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 30.80 +Info: system potential: 5891555.000000 hpwl: 7842.596191 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.047859 grad_dist: 0.027448 +Info: iter=162 steplen=1.743618 a=83.101532 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 31.26 +Info: system potential: 5838790.500000 hpwl: 7977.649414 +Info: overlap: COMB=98.8%, FF=96.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.048721 grad_dist: 0.027931 +Info: iter=163 steplen=1.744336 a=83.603035 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 31.70 +Info: system potential: 5796730.000000 hpwl: 8107.588379 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.049605 grad_dist: 0.028424 +Info: iter=164 steplen=1.745140 a=84.104530 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 32.14 +Info: system potential: 5759914.000000 hpwl: 8244.602539 +Info: overlap: COMB=98.8%, FF=96.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.050506 grad_dist: 0.028930 +Info: iter=165 steplen=1.745823 a=84.606018 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 32.58 +Info: system potential: 5727264.000000 hpwl: 8376.832031 +Info: overlap: COMB=98.7%, FF=96.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.051435 grad_dist: 0.029444 +Info: iter=166 steplen=1.746841 a=85.107498 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.00 +Info: system potential: 5694033.000000 hpwl: 8517.190430 +Info: overlap: COMB=98.7%, FF=95.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.052384 grad_dist: 0.029971 +Info: iter=167 steplen=1.747802 a=85.608963 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.43 +Info: system potential: 5656227.000000 hpwl: 8653.161133 +Info: overlap: COMB=98.6%, FF=95.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.053368 grad_dist: 0.030515 +Info: iter=168 steplen=1.748915 a=86.110420 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.85 +Info: system potential: 5610102.000000 hpwl: 8798.030273 +Info: overlap: COMB=98.7%, FF=96.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.054376 grad_dist: 0.031075 +Info: iter=169 steplen=1.749844 a=86.611870 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 34.27 +Info: system potential: 5566582.500000 hpwl: 8939.132812 +Info: overlap: COMB=98.6%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.055417 grad_dist: 0.031648 +Info: iter=170 steplen=1.751015 a=87.113312 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 34.67 +Info: system potential: 5528910.500000 hpwl: 9089.878906 +Info: overlap: COMB=98.5%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.056475 grad_dist: 0.032234 +Info: iter=171 steplen=1.752036 a=87.614746 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.08 +Info: system potential: 5487287.500000 hpwl: 9238.583008 +Info: overlap: COMB=98.6%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.057571 grad_dist: 0.032833 +Info: iter=172 steplen=1.753436 a=88.116173 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.49 +Info: system potential: 5452114.000000 hpwl: 9397.672852 +Info: overlap: COMB=98.5%, FF=95.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.058690 grad_dist: 0.033450 +Info: iter=173 steplen=1.754552 a=88.617592 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.90 +Info: system potential: 5417467.000000 hpwl: 9555.486328 +Info: overlap: COMB=98.5%, FF=95.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.059850 grad_dist: 0.034090 +Info: iter=174 steplen=1.755666 a=89.119003 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 36.29 +Info: system potential: 5372263.000000 hpwl: 9722.668945 +Info: overlap: COMB=98.5%, FF=95.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.061029 grad_dist: 0.034747 +Info: iter=175 steplen=1.756348 a=89.620407 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 36.67 +Info: system potential: 5330796.500000 hpwl: 9888.072266 +Info: overlap: COMB=98.4%, FF=95.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.062227 grad_dist: 0.035414 +Info: iter=176 steplen=1.757111 a=90.121803 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.05 +Info: system potential: 5294574.500000 hpwl: 10061.114258 +Info: overlap: COMB=98.4%, FF=95.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.063421 grad_dist: 0.036081 +Info: iter=177 steplen=1.757726 a=90.623192 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.41 +Info: system potential: 5255217.000000 hpwl: 10233.398438 +Info: overlap: COMB=98.4%, FF=95.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.064624 grad_dist: 0.036747 +Info: iter=178 steplen=1.758630 a=91.124573 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.78 +Info: system potential: 5216764.500000 hpwl: 10411.831055 +Info: overlap: COMB=98.3%, FF=94.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.065823 grad_dist: 0.037414 +Info: iter=179 steplen=1.759302 a=91.625946 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.16 +Info: system potential: 5174847.000000 hpwl: 10589.868164 +Info: overlap: COMB=98.3%, FF=94.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.067031 grad_dist: 0.038084 +Info: iter=180 steplen=1.760081 a=92.127312 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.57 +Info: system potential: 5124769.000000 hpwl: 10772.805664 +Info: overlap: COMB=98.4%, FF=94.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.068225 grad_dist: 0.038751 +Info: iter=181 steplen=1.760603 a=92.628670 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.99 +Info: system potential: 5072445.500000 hpwl: 10955.675781 +Info: overlap: COMB=98.3%, FF=94.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.069412 grad_dist: 0.039409 +Info: iter=182 steplen=1.761324 a=93.130020 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 39.45 +Info: system potential: 5026487.000000 hpwl: 11142.213867 +Info: overlap: COMB=98.3%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.070575 grad_dist: 0.040055 +Info: iter=183 steplen=1.761982 a=93.631363 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 39.94 +Info: system potential: 4978157.000000 hpwl: 11328.912109 +Info: overlap: COMB=98.3%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.071738 grad_dist: 0.040692 +Info: iter=184 steplen=1.762969 a=94.132698 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 40.46 +Info: system potential: 4932299.500000 hpwl: 11518.359375 +Info: overlap: COMB=98.2%, FF=94.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.072892 grad_dist: 0.041327 +Info: iter=185 steplen=1.763776 a=94.634026 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 41.01 +Info: system potential: 4892566.000000 hpwl: 11708.231445 +Info: overlap: COMB=98.2%, FF=94.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.074055 grad_dist: 0.041963 +Info: iter=186 steplen=1.764766 a=95.135345 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 41.60 +Info: system potential: 4852654.000000 hpwl: 11900.305664 +Info: overlap: COMB=98.2%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.075215 grad_dist: 0.042597 +Info: iter=187 steplen=1.765712 a=95.636665 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 42.21 +Info: system potential: 4817535.000000 hpwl: 12092.366211 +Info: overlap: COMB=98.1%, FF=94.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.076383 grad_dist: 0.043230 +Info: iter=188 steplen=1.766891 a=96.137978 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 42.87 +Info: system potential: 4783562.500000 hpwl: 12286.185547 +Info: overlap: COMB=98.1%, FF=94.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.077553 grad_dist: 0.043864 +Info: iter=189 steplen=1.768039 a=96.639275 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 43.55 +Info: system potential: 4749353.000000 hpwl: 12479.855469 +Info: overlap: COMB=98.1%, FF=94.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.078742 grad_dist: 0.044503 +Info: iter=190 steplen=1.769377 a=97.140572 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 44.26 +Info: system potential: 4715383.500000 hpwl: 12675.065430 +Info: overlap: COMB=98.0%, FF=93.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.079939 grad_dist: 0.045147 +Info: iter=191 steplen=1.770627 a=97.641861 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 45.00 +Info: system potential: 4679545.500000 hpwl: 12870.277344 +Info: overlap: COMB=98.0%, FF=93.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.081154 grad_dist: 0.045798 +Info: iter=192 steplen=1.771991 a=98.143143 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 45.76 +Info: system potential: 4647268.000000 hpwl: 13066.356445 +Info: overlap: COMB=97.9%, FF=93.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.082375 grad_dist: 0.046454 +Info: iter=193 steplen=1.773251 a=98.644417 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 46.53 +Info: system potential: 4612301.500000 hpwl: 13262.174805 +Info: overlap: COMB=97.9%, FF=93.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.083614 grad_dist: 0.047116 +Info: iter=194 steplen=1.774641 a=99.145683 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 47.34 +Info: system potential: 4580488.500000 hpwl: 13458.455078 +Info: overlap: COMB=97.9%, FF=93.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.084859 grad_dist: 0.047785 +Info: iter=195 steplen=1.775870 a=99.646942 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 48.14 +Info: system potential: 4545085.500000 hpwl: 13655.028320 +Info: overlap: COMB=97.8%, FF=93.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086123 grad_dist: 0.048462 +Info: iter=196 steplen=1.777140 a=100.148193 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 48.96 +Info: system potential: 4510969.000000 hpwl: 13851.360352 +Info: overlap: COMB=97.8%, FF=93.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.087392 grad_dist: 0.049143 +Info: iter=197 steplen=1.778311 a=100.649437 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 49.79 +Info: system potential: 4474014.000000 hpwl: 14047.770508 +Info: overlap: COMB=97.8%, FF=93.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088673 grad_dist: 0.049826 +Info: iter=198 steplen=1.779654 a=101.150681 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 50.63 +Info: system potential: 4442674.500000 hpwl: 14243.244141 +Info: overlap: COMB=97.8%, FF=93.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.089956 grad_dist: 0.050513 +Info: iter=199 steplen=1.780867 a=101.651917 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 51.45 +Info: system potential: 4409180.500000 hpwl: 14438.568359 +Info: overlap: COMB=97.7%, FF=92.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.091259 grad_dist: 0.051205 +Info: iter=200 steplen=1.782236 a=102.153145 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 52.29 +Info: system potential: 4376227.000000 hpwl: 14632.612305 +Info: overlap: COMB=97.7%, FF=92.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.092570 grad_dist: 0.051903 +Info: iter=201 steplen=1.783529 a=102.654366 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 53.11 +Info: system potential: 4341388.500000 hpwl: 14826.385742 +Info: overlap: COMB=97.7%, FF=92.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.093900 grad_dist: 0.052610 +Info: iter=202 steplen=1.784847 a=103.155586 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 53.92 +Info: system potential: 4301986.000000 hpwl: 15018.722656 +Info: overlap: COMB=97.6%, FF=92.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.095240 grad_dist: 0.053321 +Info: iter=203 steplen=1.786157 a=103.656799 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 54.73 +Info: system potential: 4263971.500000 hpwl: 15212.285156 +Info: overlap: COMB=97.6%, FF=92.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.096586 grad_dist: 0.054037 +Info: iter=204 steplen=1.787426 a=104.158005 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 55.55 +Info: system potential: 4224621.000000 hpwl: 15404.966797 +Info: overlap: COMB=97.6%, FF=92.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.097932 grad_dist: 0.054751 +Info: iter=205 steplen=1.788669 a=104.659203 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 56.35 +Info: system potential: 4191258.000000 hpwl: 15599.207031 +Info: overlap: COMB=97.6%, FF=92.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099280 grad_dist: 0.055460 +Info: iter=206 steplen=1.790098 a=105.160400 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 57.16 +Info: system potential: 4161082.000000 hpwl: 15793.301758 +Info: overlap: COMB=97.5%, FF=92.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.100630 grad_dist: 0.056167 +Info: iter=207 steplen=1.791609 a=105.661591 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 57.95 +Info: system potential: 4130626.250000 hpwl: 15989.558594 +Info: overlap: COMB=97.4%, FF=91.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.101993 grad_dist: 0.056880 +Info: iter=208 steplen=1.793143 a=106.162773 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 58.75 +Info: system potential: 4095690.750000 hpwl: 16186.119141 +Info: overlap: COMB=97.4%, FF=91.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.103365 grad_dist: 0.057598 +Info: iter=209 steplen=1.794572 a=106.663948 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 59.53 +Info: system potential: 4064890.750000 hpwl: 16385.292969 +Info: overlap: COMB=97.4%, FF=92.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.104738 grad_dist: 0.058316 +Info: iter=210 steplen=1.796050 a=107.165123 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 60.32 +Info: system potential: 4028955.000000 hpwl: 16584.988281 +Info: overlap: COMB=97.3%, FF=91.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106103 grad_dist: 0.059026 +Info: iter=211 steplen=1.797568 a=107.666290 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 61.09 +Info: system potential: 3989928.000000 hpwl: 16788.468750 +Info: overlap: COMB=97.3%, FF=91.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.107463 grad_dist: 0.059731 +Info: iter=212 steplen=1.799129 a=108.167450 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 61.87 +Info: system potential: 3953746.500000 hpwl: 16992.027344 +Info: overlap: COMB=97.2%, FF=91.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.108816 grad_dist: 0.060432 +Info: iter=213 steplen=1.800616 a=108.668602 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 62.64 +Info: system potential: 3918786.750000 hpwl: 17199.271484 +Info: overlap: COMB=97.1%, FF=91.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110162 grad_dist: 0.061128 +Info: iter=214 steplen=1.802154 a=109.169754 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 63.44 +Info: system potential: 3884546.500000 hpwl: 17406.363281 +Info: overlap: COMB=97.0%, FF=91.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.111493 grad_dist: 0.061815 +Info: iter=215 steplen=1.803648 a=109.670898 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 64.22 +Info: system potential: 3852372.000000 hpwl: 17617.705078 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.112814 grad_dist: 0.062495 +Info: iter=216 steplen=1.805166 a=110.172035 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 65.03 +Info: system potential: 3820459.750000 hpwl: 17828.677734 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114119 grad_dist: 0.063168 +Info: iter=217 steplen=1.806606 a=110.673164 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 65.84 +Info: system potential: 3788681.500000 hpwl: 18043.574219 +Info: overlap: COMB=96.9%, FF=90.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.115413 grad_dist: 0.063833 +Info: iter=218 steplen=1.808050 a=111.174294 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 66.68 +Info: system potential: 3757345.500000 hpwl: 18258.994141 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.116685 grad_dist: 0.064490 +Info: iter=219 steplen=1.809337 a=111.675415 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 67.51 +Info: system potential: 3725131.500000 hpwl: 18477.525391 +Info: overlap: COMB=96.9%, FF=90.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.117941 grad_dist: 0.065139 +Info: iter=220 steplen=1.810611 a=112.176537 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 68.38 +Info: system potential: 3693135.500000 hpwl: 18697.146484 +Info: overlap: COMB=96.9%, FF=90.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.119168 grad_dist: 0.065776 +Info: iter=221 steplen=1.811729 a=112.677650 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 69.24 +Info: system potential: 3656854.750000 hpwl: 18918.423828 +Info: overlap: COMB=96.7%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.120374 grad_dist: 0.066400 +Info: iter=222 steplen=1.812859 a=113.178757 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 70.14 +Info: system potential: 3628093.250000 hpwl: 19142.156250 +Info: overlap: COMB=96.6%, FF=90.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.121543 grad_dist: 0.067009 +Info: iter=223 steplen=1.813817 a=113.679863 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 71.05 +Info: system potential: 3594067.250000 hpwl: 19366.810547 +Info: overlap: COMB=96.6%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.122686 grad_dist: 0.067601 +Info: iter=224 steplen=1.814853 a=114.180962 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 72.01 +Info: system potential: 3559474.750000 hpwl: 19594.535156 +Info: overlap: COMB=96.6%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.123788 grad_dist: 0.068174 +Info: iter=225 steplen=1.815769 a=114.682053 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 72.98 +Info: system potential: 3528440.500000 hpwl: 19822.343750 +Info: overlap: COMB=96.5%, FF=89.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.124856 grad_dist: 0.068728 +Info: iter=226 steplen=1.816655 a=115.183144 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 74.01 +Info: system potential: 3492570.250000 hpwl: 20053.828125 +Info: overlap: COMB=96.4%, FF=89.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.125878 grad_dist: 0.069258 +Info: iter=227 steplen=1.817527 a=115.684227 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 75.03 +Info: system potential: 3461786.750000 hpwl: 20284.755859 +Info: overlap: COMB=96.3%, FF=89.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126857 grad_dist: 0.069762 +Info: iter=228 steplen=1.818442 a=116.185310 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 76.11 +Info: system potential: 3429086.250000 hpwl: 20519.091797 +Info: overlap: COMB=96.3%, FF=89.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.127790 grad_dist: 0.070241 +Info: iter=229 steplen=1.819309 a=116.686386 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 77.16 +Info: system potential: 3398440.000000 hpwl: 20752.310547 +Info: overlap: COMB=96.4%, FF=88.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.128683 grad_dist: 0.070695 +Info: iter=230 steplen=1.820247 a=117.187462 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 78.28 +Info: system potential: 3364164.500000 hpwl: 20988.890625 +Info: overlap: COMB=96.3%, FF=88.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.129525 grad_dist: 0.071124 +Info: iter=231 steplen=1.821115 a=117.688530 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 79.38 +Info: system potential: 3334479.250000 hpwl: 21224.595703 +Info: overlap: COMB=96.3%, FF=88.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130321 grad_dist: 0.071526 +Info: iter=232 steplen=1.822006 a=118.189590 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 80.53 +Info: system potential: 3301195.250000 hpwl: 21463.806641 +Info: overlap: COMB=96.2%, FF=88.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131060 grad_dist: 0.071899 +Info: iter=233 steplen=1.822828 a=118.690651 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 81.66 +Info: system potential: 3268614.750000 hpwl: 21702.332031 +Info: overlap: COMB=96.1%, FF=87.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131747 grad_dist: 0.072243 +Info: iter=234 steplen=1.823666 a=119.191704 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 82.85 +Info: system potential: 3246746.250000 hpwl: 21944.130859 +Info: overlap: COMB=95.9%, FF=87.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132371 grad_dist: 0.072557 +Info: iter=235 steplen=1.824372 a=119.692749 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 84.01 +Info: system potential: 3216556.250000 hpwl: 22185.050781 +Info: overlap: COMB=95.9%, FF=87.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132947 grad_dist: 0.072840 +Info: iter=236 steplen=1.825202 a=120.193794 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 85.23 +Info: system potential: 3185128.500000 hpwl: 22430.900391 +Info: overlap: COMB=95.7%, FF=87.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133457 grad_dist: 0.073096 +Info: iter=237 steplen=1.825780 a=120.694832 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 86.40 +Info: system potential: 3153969.250000 hpwl: 22675.060547 +Info: overlap: COMB=95.6%, FF=87.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133913 grad_dist: 0.073325 +Info: iter=238 steplen=1.826284 a=121.195869 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 87.63 +Info: system potential: 3115736.750000 hpwl: 22925.292969 +Info: overlap: COMB=95.6%, FF=87.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134288 grad_dist: 0.073516 +Info: iter=239 steplen=1.826633 a=121.696899 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 88.81 +Info: system potential: 3086980.000000 hpwl: 23173.066406 +Info: overlap: COMB=95.6%, FF=87.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134584 grad_dist: 0.073667 +Info: iter=240 steplen=1.826935 a=122.197929 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 90.06 +Info: system potential: 3058013.750000 hpwl: 23427.605469 +Info: overlap: COMB=95.5%, FF=86.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134796 grad_dist: 0.073777 +Info: iter=241 steplen=1.827082 a=122.698952 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 91.27 +Info: system potential: 3030148.750000 hpwl: 23679.279297 +Info: overlap: COMB=95.6%, FF=86.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134935 grad_dist: 0.073847 +Info: iter=242 steplen=1.827222 a=123.199974 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 92.54 +Info: system potential: 3009162.250000 hpwl: 23939.556641 +Info: overlap: COMB=95.5%, FF=85.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134989 grad_dist: 0.073879 +Info: iter=243 steplen=1.827168 a=123.700989 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 93.77 +Info: system potential: 2981113.750000 hpwl: 24195.367188 +Info: overlap: COMB=95.4%, FF=85.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134974 grad_dist: 0.073870 +Info: iter=244 steplen=1.827181 a=124.201996 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 95.08 +Info: system potential: 2953028.500000 hpwl: 24461.812500 +Info: overlap: COMB=95.3%, FF=85.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134868 grad_dist: 0.073822 +Info: iter=245 steplen=1.826923 a=124.703003 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 96.35 +Info: system potential: 2927574.000000 hpwl: 24721.267578 +Info: overlap: COMB=95.0%, FF=85.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134684 grad_dist: 0.073733 +Info: iter=246 steplen=1.826634 a=125.204002 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 97.71 +Info: system potential: 2899663.000000 hpwl: 24993.507812 +Info: overlap: COMB=95.0%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134399 grad_dist: 0.073593 +Info: iter=247 steplen=1.826247 a=125.705002 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 99.04 +Info: system potential: 2867884.750000 hpwl: 25257.064453 +Info: overlap: COMB=94.9%, FF=85.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134023 grad_dist: 0.073402 +Info: iter=248 steplen=1.825880 a=126.205994 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 100.47 +Info: system potential: 2839718.250000 hpwl: 25536.142578 +Info: overlap: COMB=94.9%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133545 grad_dist: 0.073163 +Info: iter=249 steplen=1.825295 a=126.706985 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 101.87 +Info: system potential: 2813498.250000 hpwl: 25805.027344 +Info: overlap: COMB=94.9%, FF=85.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132975 grad_dist: 0.072874 +Info: iter=250 steplen=1.824735 a=127.207970 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 103.38 +Info: system potential: 2787680.250000 hpwl: 26091.232422 +Info: overlap: COMB=94.9%, FF=85.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132298 grad_dist: 0.072530 +Info: iter=251 steplen=1.824056 a=127.708954 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 104.85 +Info: system potential: 2757824.250000 hpwl: 26365.931641 +Info: overlap: COMB=94.8%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131533 grad_dist: 0.072135 +Info: iter=252 steplen=1.823427 a=128.209930 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 106.40 +Info: system potential: 2725088.500000 hpwl: 26660.105469 +Info: overlap: COMB=94.6%, FF=84.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130661 grad_dist: 0.071695 +Info: iter=253 steplen=1.822443 a=128.710907 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 107.88 +Info: system potential: 2697391.500000 hpwl: 26940.792969 +Info: overlap: COMB=94.4%, FF=84.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.129690 grad_dist: 0.071206 +Info: iter=254 steplen=1.821338 a=129.211884 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 109.44 +Info: system potential: 2675123.500000 hpwl: 27242.322266 +Info: overlap: COMB=94.4%, FF=83.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.128599 grad_dist: 0.070654 +Info: iter=255 steplen=1.820114 a=129.712845 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 110.93 +Info: system potential: 2653252.500000 hpwl: 27530.800781 +Info: overlap: COMB=94.3%, FF=82.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.127415 grad_dist: 0.070046 +Info: iter=256 steplen=1.819010 a=130.213806 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 112.50 +Info: system potential: 2625045.250000 hpwl: 27842.980469 +Info: overlap: COMB=94.2%, FF=83.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126139 grad_dist: 0.069400 +Info: iter=257 steplen=1.817559 a=130.714767 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 114.02 +Info: system potential: 2598766.250000 hpwl: 28140.531250 +Info: overlap: COMB=94.2%, FF=83.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.124786 grad_dist: 0.068720 +Info: iter=258 steplen=1.815862 a=131.215714 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 115.62 +Info: system potential: 2568909.250000 hpwl: 28463.080078 +Info: overlap: COMB=94.0%, FF=82.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.123325 grad_dist: 0.067986 +Info: iter=259 steplen=1.813973 a=131.716660 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 117.19 +Info: system potential: 2537531.000000 hpwl: 28769.453125 +Info: overlap: COMB=94.0%, FF=82.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.121755 grad_dist: 0.067190 +Info: iter=260 steplen=1.812117 a=132.217606 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 118.86 +Info: system potential: 2512710.500000 hpwl: 29102.195312 +Info: overlap: COMB=93.7%, FF=82.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.120073 grad_dist: 0.066335 +Info: iter=261 steplen=1.810103 a=132.718552 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 120.50 +Info: system potential: 2492911.000000 hpwl: 29416.316406 +Info: overlap: COMB=93.6%, FF=81.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.118310 grad_dist: 0.065429 +Info: iter=262 steplen=1.808219 a=133.219498 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 122.25 +Info: system potential: 2468728.250000 hpwl: 29756.978516 +Info: overlap: COMB=93.4%, FF=81.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.116471 grad_dist: 0.064478 +Info: iter=263 steplen=1.806364 a=133.720428 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 123.97 +Info: system potential: 2441460.500000 hpwl: 30078.949219 +Info: overlap: COMB=93.3%, FF=80.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114568 grad_dist: 0.063494 +Info: iter=264 steplen=1.804383 a=134.221359 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 125.78 +Info: system potential: 2413471.000000 hpwl: 30426.777344 +Info: overlap: COMB=93.3%, FF=80.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.112601 grad_dist: 0.062476 +Info: iter=265 steplen=1.802306 a=134.722290 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 127.53 +Info: system potential: 2386902.000000 hpwl: 30756.544922 +Info: overlap: COMB=93.3%, FF=80.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110568 grad_dist: 0.061418 +Info: iter=266 steplen=1.800251 a=135.223221 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 129.36 +Info: system potential: 2361020.500000 hpwl: 31109.386719 +Info: overlap: COMB=93.1%, FF=80.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.108474 grad_dist: 0.060322 +Info: iter=267 steplen=1.798242 a=135.724152 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 131.13 +Info: system potential: 2336535.500000 hpwl: 31447.740234 +Info: overlap: COMB=93.1%, FF=80.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106344 grad_dist: 0.059201 +Info: iter=268 steplen=1.796335 a=136.225067 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 132.96 +Info: system potential: 2313116.000000 hpwl: 31806.652344 +Info: overlap: COMB=92.8%, FF=79.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.104199 grad_dist: 0.058068 +Info: iter=269 steplen=1.794423 a=136.725983 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 134.74 +Info: system potential: 2288399.250000 hpwl: 32153.570312 +Info: overlap: COMB=92.6%, FF=79.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.102067 grad_dist: 0.056935 +Info: iter=270 steplen=1.792675 a=137.226898 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 136.59 +Info: system potential: 2262210.000000 hpwl: 32519.486328 +Info: overlap: COMB=92.5%, FF=79.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099951 grad_dist: 0.055810 +Info: iter=271 steplen=1.790908 a=137.727798 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 138.41 +Info: system potential: 2236369.500000 hpwl: 32875.203125 +Info: overlap: COMB=92.3%, FF=79.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.097881 grad_dist: 0.054700 +Info: iter=272 steplen=1.789409 a=138.228714 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 140.30 +Info: system potential: 2210155.500000 hpwl: 33248.867188 +Info: overlap: COMB=92.1%, FF=78.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.095867 grad_dist: 0.053612 +Info: iter=273 steplen=1.788166 a=138.729614 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 142.17 +Info: system potential: 2184050.750000 hpwl: 33613.546875 +Info: overlap: COMB=92.1%, FF=78.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.093942 grad_dist: 0.052559 +Info: iter=274 steplen=1.787376 a=139.230515 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 144.08 +Info: system potential: 2157209.500000 hpwl: 33995.226562 +Info: overlap: COMB=92.1%, FF=78.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.092127 grad_dist: 0.051558 +Info: iter=275 steplen=1.786858 a=139.731415 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 145.94 +Info: system potential: 2134231.500000 hpwl: 34369.488281 +Info: overlap: COMB=91.8%, FF=77.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.090470 grad_dist: 0.050626 +Info: iter=276 steplen=1.787026 a=140.232315 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 147.87 +Info: system potential: 2104992.750000 hpwl: 34760.445312 +Info: overlap: COMB=91.6%, FF=77.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088998 grad_dist: 0.049784 +Info: iter=277 steplen=1.787693 a=140.733200 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 149.74 +Info: system potential: 2079202.000000 hpwl: 35146.277344 +Info: overlap: COMB=91.4%, FF=76.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.087762 grad_dist: 0.049059 +Info: iter=278 steplen=1.788913 a=141.234085 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 151.65 +Info: system potential: 2053050.250000 hpwl: 35546.171875 +Info: overlap: COMB=91.2%, FF=76.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086790 grad_dist: 0.048471 +Info: iter=279 steplen=1.790570 a=141.734970 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 153.52 +Info: system potential: 2022814.000000 hpwl: 35944.484375 +Info: overlap: COMB=91.3%, FF=76.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086110 grad_dist: 0.048031 +Info: iter=280 steplen=1.792801 a=142.235855 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 155.47 +Info: system potential: 1995800.125000 hpwl: 36355.667969 +Info: overlap: COMB=91.1%, FF=76.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.085749 grad_dist: 0.047751 +Info: iter=281 steplen=1.795767 a=142.736740 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 157.42 +Info: system potential: 1969756.375000 hpwl: 36766.609375 +Info: overlap: COMB=90.8%, FF=75.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.085747 grad_dist: 0.047650 +Info: iter=282 steplen=1.799525 a=143.237610 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 159.47 +Info: system potential: 1945184.125000 hpwl: 37191.394531 +Info: overlap: COMB=90.7%, FF=75.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086138 grad_dist: 0.047751 +Info: iter=283 steplen=1.803885 a=143.738480 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 161.48 +Info: system potential: 1918799.375000 hpwl: 37616.925781 +Info: overlap: COMB=90.5%, FF=74.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086946 grad_dist: 0.048072 +Info: iter=284 steplen=1.808656 a=144.239349 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 163.55 +Info: system potential: 1892061.625000 hpwl: 38054.613281 +Info: overlap: COMB=90.4%, FF=74.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088169 grad_dist: 0.048615 +Info: iter=285 steplen=1.813634 a=144.740219 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 165.59 +Info: system potential: 1868252.250000 hpwl: 38493.636719 +Info: overlap: COMB=90.1%, FF=74.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.089799 grad_dist: 0.049368 +Info: iter=286 steplen=1.818966 a=145.241074 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 167.69 +Info: system potential: 1843982.000000 hpwl: 38945.535156 +Info: overlap: COMB=89.8%, FF=73.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.091814 grad_dist: 0.050321 +Info: iter=287 steplen=1.824549 a=145.741928 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 169.75 +Info: system potential: 1817313.375000 hpwl: 39398.785156 +Info: overlap: COMB=89.7%, FF=72.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.094205 grad_dist: 0.051469 +Info: iter=288 steplen=1.830331 a=146.242783 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 171.88 +Info: system potential: 1791054.000000 hpwl: 39866.933594 +Info: overlap: COMB=89.6%, FF=72.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.096932 grad_dist: 0.052800 +Info: iter=289 steplen=1.835839 a=146.743637 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 173.97 +Info: system potential: 1762001.750000 hpwl: 40333.933594 +Info: overlap: COMB=89.5%, FF=72.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099969 grad_dist: 0.054286 +Info: iter=290 steplen=1.841536 a=147.244492 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 176.15 +Info: system potential: 1738440.625000 hpwl: 40817.558594 +Info: overlap: COMB=89.5%, FF=73.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.103266 grad_dist: 0.055895 +Info: iter=291 steplen=1.847484 a=147.745331 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 178.32 +Info: system potential: 1714568.125000 hpwl: 41298.214844 +Info: overlap: COMB=89.3%, FF=73.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106795 grad_dist: 0.057626 +Info: iter=292 steplen=1.853223 a=148.246185 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 180.60 +Info: system potential: 1688180.875000 hpwl: 41799.242188 +Info: overlap: COMB=88.9%, FF=72.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110524 grad_dist: 0.059464 +Info: iter=293 steplen=1.858669 a=148.747025 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 182.81 +Info: system potential: 1661179.250000 hpwl: 42293.519531 +Info: overlap: COMB=88.6%, FF=71.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114387 grad_dist: 0.061367 +Info: iter=294 steplen=1.863985 a=149.247864 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 185.10 +Info: system potential: 1631940.375000 hpwl: 42811.039062 +Info: overlap: COMB=88.3%, FF=71.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.118327 grad_dist: 0.063305 +Info: iter=295 steplen=1.869168 a=149.748703 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 187.30 +Info: system potential: 1603837.375000 hpwl: 43318.074219 +Info: overlap: COMB=88.1%, FF=70.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.122296 grad_dist: 0.065255 +Info: iter=296 steplen=1.874123 a=150.249542 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 189.59 +Info: system potential: 1573837.000000 hpwl: 43851.621094 +Info: overlap: COMB=87.8%, FF=69.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126255 grad_dist: 0.067197 +Info: iter=297 steplen=1.878870 a=150.750381 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 191.80 +Info: system potential: 1547659.250000 hpwl: 44367.437500 +Info: overlap: COMB=87.6%, FF=69.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130176 grad_dist: 0.069107 +Info: iter=298 steplen=1.883693 a=151.251205 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 194.10 +Info: system potential: 1521394.375000 hpwl: 44915.273438 +Info: overlap: COMB=87.5%, FF=69.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134012 grad_dist: 0.070977 +Info: iter=299 steplen=1.888108 a=151.752029 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 196.35 +Info: system potential: 1493733.250000 hpwl: 45437.484375 +Info: overlap: COMB=87.5%, FF=69.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.137734 grad_dist: 0.072797 +Info: iter=300 steplen=1.892036 a=152.252853 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 198.73 +Info: system potential: 1467182.500000 hpwl: 45995.589844 +Info: overlap: COMB=87.2%, FF=68.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.141300 grad_dist: 0.074533 +Info: iter=301 steplen=1.895801 a=152.753677 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 200.96 +Info: system potential: 1443358.000000 hpwl: 46522.445312 +Info: overlap: COMB=86.9%, FF=67.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.144675 grad_dist: 0.076171 +Info: iter=302 steplen=1.899343 a=153.254501 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 203.30 +Info: system potential: 1418588.625000 hpwl: 47090.300781 +Info: overlap: COMB=86.8%, FF=67.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.147843 grad_dist: 0.077714 +Info: iter=303 steplen=1.902407 a=153.755310 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 205.58 +Info: system potential: 1394502.250000 hpwl: 47623.062500 +Info: overlap: COMB=86.6%, FF=66.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.150785 grad_dist: 0.079146 +Info: iter=304 steplen=1.905155 a=154.256119 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 207.98 +Info: system potential: 1365500.500000 hpwl: 48201.382812 +Info: overlap: COMB=86.3%, FF=66.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153450 grad_dist: 0.080447 +Info: iter=305 steplen=1.907472 a=154.756927 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 210.21 +Info: system potential: 1340192.125000 hpwl: 48738.648438 +Info: overlap: COMB=86.0%, FF=65.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.155833 grad_dist: 0.081600 +Info: iter=306 steplen=1.909713 a=155.257736 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 212.58 +Info: system potential: 1315067.000000 hpwl: 49325.710938 +Info: overlap: COMB=85.7%, FF=65.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157901 grad_dist: 0.082607 +Info: iter=307 steplen=1.911477 a=155.758545 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 214.85 +Info: system potential: 1288748.000000 hpwl: 49868.644531 +Info: overlap: COMB=85.5%, FF=64.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159681 grad_dist: 0.083474 +Info: iter=308 steplen=1.912943 a=156.259354 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 217.22 +Info: system potential: 1261813.000000 hpwl: 50462.695312 +Info: overlap: COMB=85.1%, FF=64.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161151 grad_dist: 0.084200 +Info: iter=309 steplen=1.913920 a=156.760162 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 219.41 +Info: system potential: 1236862.625000 hpwl: 51010.964844 +Info: overlap: COMB=84.7%, FF=63.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162316 grad_dist: 0.084781 +Info: iter=310 steplen=1.914537 a=157.260956 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 221.80 +Info: system potential: 1213856.500000 hpwl: 51613.265625 +Info: overlap: COMB=84.5%, FF=62.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163163 grad_dist: 0.085206 +Info: iter=311 steplen=1.914925 a=157.761749 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 224.07 +Info: system potential: 1189944.625000 hpwl: 52169.816406 +Info: overlap: COMB=84.2%, FF=61.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163717 grad_dist: 0.085473 +Info: iter=312 steplen=1.915428 a=158.262543 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 226.46 +Info: system potential: 1163608.125000 hpwl: 52781.156250 +Info: overlap: COMB=84.0%, FF=61.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163983 grad_dist: 0.085611 +Info: iter=313 steplen=1.915442 a=158.763336 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 228.64 +Info: system potential: 1138379.375000 hpwl: 53347.023438 +Info: overlap: COMB=83.9%, FF=61.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164035 grad_dist: 0.085645 +Info: iter=314 steplen=1.915284 a=159.264130 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 230.99 +Info: system potential: 1117846.500000 hpwl: 53966.812500 +Info: overlap: COMB=83.7%, FF=60.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163860 grad_dist: 0.085574 +Info: iter=315 steplen=1.914846 a=159.764908 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 233.17 +Info: system potential: 1096324.625000 hpwl: 54541.125000 +Info: overlap: COMB=83.5%, FF=60.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163491 grad_dist: 0.085401 +Info: iter=316 steplen=1.914405 a=160.265686 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 235.49 +Info: system potential: 1071944.375000 hpwl: 55172.156250 +Info: overlap: COMB=82.9%, FF=59.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162967 grad_dist: 0.085135 +Info: iter=317 steplen=1.914223 a=160.766464 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 237.64 +Info: system potential: 1050678.750000 hpwl: 55759.777344 +Info: overlap: COMB=82.6%, FF=59.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162345 grad_dist: 0.084807 +Info: iter=318 steplen=1.914290 a=161.267242 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 239.90 +Info: system potential: 1024486.625000 hpwl: 56405.390625 +Info: overlap: COMB=82.4%, FF=58.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161685 grad_dist: 0.084464 +Info: iter=319 steplen=1.914248 a=161.768021 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 241.98 +Info: system potential: 1000763.625000 hpwl: 57010.933594 +Info: overlap: COMB=82.1%, FF=57.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161070 grad_dist: 0.084133 +Info: iter=320 steplen=1.914476 a=162.268799 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 244.23 +Info: system potential: 977026.937500 hpwl: 57670.875000 +Info: overlap: COMB=81.6%, FF=56.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160506 grad_dist: 0.083819 +Info: iter=321 steplen=1.914912 a=162.769562 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 246.23 +Info: system potential: 954483.687500 hpwl: 58291.000000 +Info: overlap: COMB=81.4%, FF=56.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160041 grad_dist: 0.083535 +Info: iter=322 steplen=1.915852 a=163.270325 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 248.42 +Info: system potential: 933709.437500 hpwl: 58965.707031 +Info: overlap: COMB=81.1%, FF=55.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159742 grad_dist: 0.083303 +Info: iter=323 steplen=1.917602 a=163.771088 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 250.45 +Info: system potential: 911229.375000 hpwl: 59606.640625 +Info: overlap: COMB=80.4%, FF=54.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159685 grad_dist: 0.083178 +Info: iter=324 steplen=1.919800 a=164.271851 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 252.64 +Info: system potential: 890168.250000 hpwl: 60303.453125 +Info: overlap: COMB=80.5%, FF=54.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159927 grad_dist: 0.083205 +Info: iter=325 steplen=1.922080 a=164.772614 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 254.67 +Info: system potential: 866066.125000 hpwl: 60964.828125 +Info: overlap: COMB=79.9%, FF=54.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160491 grad_dist: 0.083365 +Info: iter=326 steplen=1.925157 a=165.273376 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 256.83 +Info: system potential: 844353.000000 hpwl: 61680.906250 +Info: overlap: COMB=79.6%, FF=53.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161331 grad_dist: 0.083650 +Info: iter=327 steplen=1.928654 a=165.774139 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 258.73 +Info: system potential: 823618.125000 hpwl: 62362.546875 +Info: overlap: COMB=79.0%, FF=52.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162508 grad_dist: 0.084083 +Info: iter=328 steplen=1.932702 a=166.274887 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 260.84 +Info: system potential: 803165.750000 hpwl: 63099.886719 +Info: overlap: COMB=78.8%, FF=51.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164044 grad_dist: 0.084677 +Info: iter=329 steplen=1.937300 a=166.775635 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 262.77 +Info: system potential: 780379.437500 hpwl: 63803.554688 +Info: overlap: COMB=78.8%, FF=51.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.165922 grad_dist: 0.085435 +Info: iter=330 steplen=1.942083 a=167.276382 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 264.82 +Info: system potential: 758608.062500 hpwl: 64562.277344 +Info: overlap: COMB=78.5%, FF=50.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168068 grad_dist: 0.086337 +Info: iter=331 steplen=1.946645 a=167.777130 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 266.60 +Info: system potential: 737945.375000 hpwl: 65285.960938 +Info: overlap: COMB=77.9%, FF=50.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.170422 grad_dist: 0.087333 +Info: iter=332 steplen=1.951404 a=168.277878 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 268.59 +Info: system potential: 715477.062500 hpwl: 66062.304688 +Info: overlap: COMB=77.6%, FF=49.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.172922 grad_dist: 0.088391 +Info: iter=333 steplen=1.956325 a=168.778625 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 270.32 +Info: system potential: 696568.062500 hpwl: 66806.648438 +Info: overlap: COMB=77.1%, FF=48.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175497 grad_dist: 0.089506 +Info: iter=334 steplen=1.960732 a=169.279373 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 272.26 +Info: system potential: 678429.250000 hpwl: 67597.468750 +Info: overlap: COMB=76.8%, FF=47.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178140 grad_dist: 0.090633 +Info: iter=335 steplen=1.965511 a=169.780106 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 273.95 +Info: system potential: 658875.437500 hpwl: 68358.882812 +Info: overlap: COMB=76.6%, FF=47.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.180775 grad_dist: 0.091754 +Info: iter=336 steplen=1.970220 a=170.280838 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 275.82 +Info: system potential: 638048.875000 hpwl: 69166.671875 +Info: overlap: COMB=76.1%, FF=46.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.183355 grad_dist: 0.092888 +Info: iter=337 steplen=1.973946 a=170.781570 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 277.36 +Info: system potential: 619693.562500 hpwl: 69940.960938 +Info: overlap: COMB=75.8%, FF=45.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185773 grad_dist: 0.093972 +Info: iter=338 steplen=1.976902 a=171.282303 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 279.21 +Info: system potential: 600167.687500 hpwl: 70754.695312 +Info: overlap: COMB=75.7%, FF=45.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.187938 grad_dist: 0.094910 +Info: iter=339 steplen=1.980159 a=171.783035 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 280.76 +Info: system potential: 580950.500000 hpwl: 71541.640625 +Info: overlap: COMB=75.2%, FF=45.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.189768 grad_dist: 0.095719 +Info: iter=340 steplen=1.982555 a=172.283768 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 282.54 +Info: system potential: 565097.000000 hpwl: 72362.726562 +Info: overlap: COMB=74.6%, FF=43.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.191311 grad_dist: 0.096419 +Info: iter=341 steplen=1.984170 a=172.784500 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 284.08 +Info: system potential: 547988.687500 hpwl: 73155.093750 +Info: overlap: COMB=74.3%, FF=42.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.192572 grad_dist: 0.096954 +Info: iter=342 steplen=1.986207 a=173.285233 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 285.94 +Info: system potential: 530487.437500 hpwl: 73984.023438 +Info: overlap: COMB=74.2%, FF=42.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193492 grad_dist: 0.097353 +Info: iter=343 steplen=1.987526 a=173.785950 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 287.36 +Info: system potential: 514400.875000 hpwl: 74784.843750 +Info: overlap: COMB=73.5%, FF=41.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194132 grad_dist: 0.097659 +Info: iter=344 steplen=1.987869 a=174.286667 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 289.09 +Info: system potential: 499281.937500 hpwl: 75617.148438 +Info: overlap: COMB=73.1%, FF=41.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194490 grad_dist: 0.097812 +Info: iter=345 steplen=1.988407 a=174.787384 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 290.56 +Info: system potential: 483101.250000 hpwl: 76424.062500 +Info: overlap: COMB=72.6%, FF=40.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194570 grad_dist: 0.097813 +Info: iter=346 steplen=1.989213 a=175.288101 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 292.31 +Info: system potential: 467811.843750 hpwl: 77264.601562 +Info: overlap: COMB=72.2%, FF=39.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194464 grad_dist: 0.097748 +Info: iter=347 steplen=1.989455 a=175.788818 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 293.61 +Info: system potential: 453081.750000 hpwl: 78078.945312 +Info: overlap: COMB=72.0%, FF=38.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194293 grad_dist: 0.097643 +Info: iter=348 steplen=1.989834 a=176.289536 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 295.32 +Info: system potential: 438590.937500 hpwl: 78924.242188 +Info: overlap: COMB=71.7%, FF=37.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194063 grad_dist: 0.097482 +Info: iter=349 steplen=1.990756 a=176.790237 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 296.66 +Info: system potential: 424514.187500 hpwl: 79746.804688 +Info: overlap: COMB=71.1%, FF=37.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193885 grad_dist: 0.097309 +Info: iter=350 steplen=1.992480 a=177.290939 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 298.23 +Info: system potential: 411689.593750 hpwl: 80600.539062 +Info: overlap: COMB=71.0%, FF=36.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193924 grad_dist: 0.097208 +Info: iter=351 steplen=1.994941 a=177.791641 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 299.54 +Info: system potential: 396681.593750 hpwl: 81434.023438 +Info: overlap: COMB=70.6%, FF=35.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194336 grad_dist: 0.097258 +Info: iter=352 steplen=1.998150 a=178.292343 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 301.16 +Info: system potential: 383841.937500 hpwl: 82298.328125 +Info: overlap: COMB=69.8%, FF=33.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.195134 grad_dist: 0.097486 +Info: iter=353 steplen=2.001652 a=178.793045 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 302.47 +Info: system potential: 372050.937500 hpwl: 83141.179688 +Info: overlap: COMB=69.2%, FF=33.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.196381 grad_dist: 0.097876 +Info: iter=354 steplen=2.006425 a=179.293747 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 304.13 +Info: system potential: 359683.625000 hpwl: 84015.070312 +Info: overlap: COMB=69.2%, FF=33.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.198135 grad_dist: 0.098462 +Info: iter=355 steplen=2.012306 a=179.794449 penalty=[0.16, 0.16, 0.16, 0.16] +Info: update_chains distance 305.48 +Info: system potential: 347710.968750 hpwl: 84872.898438 +Info: overlap: COMB=68.7%, FF=32.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.200480 grad_dist: 0.099322 +Info: iter=356 steplen=2.018480 a=180.295135 penalty=[0.16, 0.16, 0.16, 0.16] +Info: update_chains distance 307.18 +Info: system potential: 336445.093750 hpwl: 85756.796875 +Info: overlap: COMB=67.8%, FF=31.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.203356 grad_dist: 0.100436 +Info: iter=357 steplen=2.024739 a=180.795822 penalty=[0.17, 0.17, 0.17, 0.17] +Info: update_chains distance 308.51 +Info: system potential: 324542.343750 hpwl: 86623.015625 +Info: overlap: COMB=67.7%, FF=31.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.206619 grad_dist: 0.101723 +Info: iter=358 steplen=2.031179 a=181.296509 penalty=[0.17, 0.17, 0.17, 0.17] +Info: update_chains distance 310.14 +Info: system potential: 312635.031250 hpwl: 87510.164062 +Info: overlap: COMB=67.0%, FF=30.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.210204 grad_dist: 0.103137 +Info: iter=359 steplen=2.038094 a=181.797195 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 311.31 +Info: system potential: 301512.531250 hpwl: 88381.226562 +Info: overlap: COMB=66.5%, FF=30.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.214009 grad_dist: 0.104671 +Info: iter=360 steplen=2.044579 a=182.297882 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 312.78 +Info: system potential: 291503.687500 hpwl: 89267.609375 +Info: overlap: COMB=66.1%, FF=29.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.217943 grad_dist: 0.106290 +Info: iter=361 steplen=2.050451 a=182.798569 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 313.81 +Info: system potential: 281322.093750 hpwl: 90133.203125 +Info: overlap: COMB=65.8%, FF=29.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.221825 grad_dist: 0.107905 +Info: iter=362 steplen=2.055740 a=183.299255 penalty=[0.19, 0.19, 0.19, 0.19] +Info: update_chains distance 315.25 +Info: system potential: 270961.968750 hpwl: 91010.453125 +Info: overlap: COMB=65.5%, FF=28.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.225480 grad_dist: 0.109441 +Info: iter=363 steplen=2.060297 a=183.799942 penalty=[0.19, 0.19, 0.19, 0.19] +Info: update_chains distance 316.17 +Info: system potential: 261459.531250 hpwl: 91865.335938 +Info: overlap: COMB=65.0%, FF=27.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.228811 grad_dist: 0.110850 +Info: iter=364 steplen=2.064144 a=184.300613 penalty=[0.20, 0.20, 0.20, 0.20] +Info: update_chains distance 317.60 +Info: system potential: 252832.500000 hpwl: 92729.960938 +Info: overlap: COMB=64.5%, FF=27.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.231696 grad_dist: 0.112101 +Info: iter=365 steplen=2.066837 a=184.801285 penalty=[0.20, 0.20, 0.20, 0.20] +Info: update_chains distance 318.61 +Info: system potential: 243646.656250 hpwl: 93571.406250 +Info: overlap: COMB=63.9%, FF=26.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.233996 grad_dist: 0.113145 +Info: iter=366 steplen=2.068113 a=185.301956 penalty=[0.21, 0.21, 0.21, 0.21] +Info: update_chains distance 320.10 +Info: system potential: 235145.687500 hpwl: 94411.390625 +Info: overlap: COMB=63.6%, FF=25.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.235624 grad_dist: 0.113899 +Info: iter=367 steplen=2.068708 a=185.802628 penalty=[0.21, 0.21, 0.21, 0.21] +Info: update_chains distance 321.10 +Info: system potential: 227244.468750 hpwl: 95229.593750 +Info: overlap: COMB=63.1%, FF=25.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236511 grad_dist: 0.114346 +Info: iter=368 steplen=2.068381 a=186.303299 penalty=[0.22, 0.22, 0.22, 0.22] +Info: update_chains distance 322.76 +Info: system potential: 219732.125000 hpwl: 96048.367188 +Info: overlap: COMB=62.7%, FF=24.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236709 grad_dist: 0.114516 +Info: iter=369 steplen=2.067029 a=186.803970 penalty=[0.22, 0.22, 0.22, 0.22] +Info: update_chains distance 323.87 +Info: system potential: 212239.125000 hpwl: 96844.976562 +Info: overlap: COMB=62.1%, FF=23.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236205 grad_dist: 0.114398 +Info: iter=370 steplen=2.064773 a=187.304642 penalty=[0.23, 0.23, 0.23, 0.23] +Info: update_chains distance 325.69 +Info: system potential: 204744.640625 hpwl: 97643.000000 +Info: overlap: COMB=61.3%, FF=23.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.234998 grad_dist: 0.113984 +Info: iter=371 steplen=2.061675 a=187.805298 penalty=[0.24, 0.24, 0.24, 0.24] +Info: update_chains distance 326.90 +Info: system potential: 198011.515625 hpwl: 98423.070312 +Info: overlap: COMB=60.8%, FF=23.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.233191 grad_dist: 0.113292 +Info: iter=372 steplen=2.058322 a=188.305954 penalty=[0.24, 0.24, 0.24, 0.24] +Info: update_chains distance 328.73 +Info: system potential: 191483.531250 hpwl: 99198.187500 +Info: overlap: COMB=60.0%, FF=22.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.230912 grad_dist: 0.112360 +Info: iter=373 steplen=2.055102 a=188.806625 penalty=[0.25, 0.25, 0.25, 0.25] +Info: update_chains distance 330.08 +Info: system potential: 184948.656250 hpwl: 99965.906250 +Info: overlap: COMB=59.5%, FF=21.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.228308 grad_dist: 0.111277 +Info: iter=374 steplen=2.051703 a=189.307281 penalty=[0.25, 0.25, 0.25, 0.25] +Info: update_chains distance 332.06 +Info: system potential: 178557.078125 hpwl: 100726.929688 +Info: overlap: COMB=59.2%, FF=21.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.225539 grad_dist: 0.110108 +Info: iter=375 steplen=2.048338 a=189.807938 penalty=[0.26, 0.26, 0.26, 0.26] +Info: update_chains distance 333.53 +Info: system potential: 172487.750000 hpwl: 101479.609375 +Info: overlap: COMB=58.5%, FF=21.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.222671 grad_dist: 0.108872 +Info: iter=376 steplen=2.045260 a=190.308594 penalty=[0.27, 0.27, 0.27, 0.27] +Info: update_chains distance 335.60 +Info: system potential: 166894.953125 hpwl: 102226.578125 +Info: overlap: COMB=58.0%, FF=20.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.219845 grad_dist: 0.107597 +Info: iter=377 steplen=2.043225 a=190.809250 penalty=[0.27, 0.27, 0.27, 0.27] +Info: update_chains distance 337.19 +Info: system potential: 161279.000000 hpwl: 102970.515625 +Info: overlap: COMB=57.3%, FF=20.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.217169 grad_dist: 0.106368 +Info: iter=378 steplen=2.041681 a=191.309906 penalty=[0.28, 0.28, 0.28, 0.28] +Info: update_chains distance 339.44 +Info: system potential: 155802.593750 hpwl: 103711.406250 +Info: overlap: COMB=56.5%, FF=19.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.214793 grad_dist: 0.105267 +Info: iter=379 steplen=2.040449 a=191.810562 penalty=[0.29, 0.29, 0.29, 0.29] +Info: update_chains distance 341.20 +Info: system potential: 150498.265625 hpwl: 104446.226562 +Info: overlap: COMB=56.2%, FF=19.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.212696 grad_dist: 0.104296 +Info: iter=380 steplen=2.039359 a=192.311218 penalty=[0.29, 0.29, 0.29, 0.29] +Info: update_chains distance 343.51 +Info: system potential: 145335.875000 hpwl: 105173.234375 +Info: overlap: COMB=55.5%, FF=18.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.210897 grad_dist: 0.103417 +Info: iter=381 steplen=2.039293 a=192.811874 penalty=[0.30, 0.30, 0.30, 0.30] +Info: update_chains distance 345.37 +Info: system potential: 140392.140625 hpwl: 105894.343750 +Info: overlap: COMB=54.9%, FF=18.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.209296 grad_dist: 0.102653 +Info: iter=382 steplen=2.038863 a=193.312515 penalty=[0.31, 0.31, 0.31, 0.31] +Info: update_chains distance 347.73 +Info: system potential: 135629.656250 hpwl: 106607.250000 +Info: overlap: COMB=54.5%, FF=17.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.207949 grad_dist: 0.102002 +Info: iter=383 steplen=2.038689 a=193.813171 penalty=[0.32, 0.32, 0.32, 0.32] +Info: update_chains distance 349.60 +Info: system potential: 131015.070312 hpwl: 107311.093750 +Info: overlap: COMB=53.7%, FF=16.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.206685 grad_dist: 0.101407 +Info: iter=384 steplen=2.038161 a=194.313828 penalty=[0.33, 0.33, 0.33, 0.33] +Info: update_chains distance 352.01 +Info: system potential: 126618.726562 hpwl: 108003.328125 +Info: overlap: COMB=53.0%, FF=16.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.205471 grad_dist: 0.100842 +Info: iter=385 steplen=2.037562 a=194.814468 penalty=[0.33, 0.33, 0.33, 0.33] +Info: update_chains distance 353.98 +Info: system potential: 122386.031250 hpwl: 108682.906250 +Info: overlap: COMB=52.5%, FF=15.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.204164 grad_dist: 0.100271 +Info: iter=386 steplen=2.036124 a=195.315109 penalty=[0.34, 0.34, 0.34, 0.34] +Info: update_chains distance 356.38 +Info: system potential: 118249.070312 hpwl: 109350.492188 +Info: overlap: COMB=51.9%, FF=15.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.202711 grad_dist: 0.099638 +Info: iter=387 steplen=2.034483 a=195.815750 penalty=[0.35, 0.35, 0.35, 0.35] +Info: update_chains distance 358.33 +Info: system potential: 114335.875000 hpwl: 110005.562500 +Info: overlap: COMB=51.5%, FF=15.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.201074 grad_dist: 0.098903 +Info: iter=388 steplen=2.033053 a=196.316391 penalty=[0.36, 0.36, 0.36, 0.36] +Info: update_chains distance 360.75 +Info: system potential: 110647.929688 hpwl: 110651.945312 +Info: overlap: COMB=50.8%, FF=15.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.199362 grad_dist: 0.098100 +Info: iter=389 steplen=2.032222 a=196.817032 penalty=[0.37, 0.37, 0.37, 0.37] +Info: update_chains distance 362.74 +Info: system potential: 107072.109375 hpwl: 111284.757812 +Info: overlap: COMB=50.4%, FF=14.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.197669 grad_dist: 0.097306 +Info: iter=390 steplen=2.031423 a=197.317673 penalty=[0.38, 0.38, 0.38, 0.38] +Info: update_chains distance 365.12 +Info: system potential: 103568.851562 hpwl: 111911.562500 +Info: overlap: COMB=49.6%, FF=13.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.196034 grad_dist: 0.096556 +Info: iter=391 steplen=2.030267 a=197.818314 penalty=[0.39, 0.39, 0.39, 0.39] +Info: update_chains distance 367.01 +Info: system potential: 100274.101562 hpwl: 112519.062500 +Info: overlap: COMB=49.0%, FF=13.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194428 grad_dist: 0.095817 +Info: iter=392 steplen=2.029151 a=198.318954 penalty=[0.40, 0.40, 0.40, 0.40] +Info: update_chains distance 369.34 +Info: system potential: 97043.343750 hpwl: 113120.484375 +Info: overlap: COMB=48.6%, FF=12.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.192884 grad_dist: 0.095057 +Info: iter=393 steplen=2.029152 a=198.819580 penalty=[0.41, 0.41, 0.41, 0.41] +Info: update_chains distance 371.21 +Info: system potential: 93935.687500 hpwl: 113708.820312 +Info: overlap: COMB=47.8%, FF=12.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.191468 grad_dist: 0.094342 +Info: iter=394 steplen=2.029504 a=199.320206 penalty=[0.42, 0.42, 0.42, 0.42] +Info: update_chains distance 373.54 +Info: system potential: 90887.273438 hpwl: 114293.242188 +Info: overlap: COMB=46.7%, FF=12.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.190291 grad_dist: 0.093753 +Info: iter=395 steplen=2.029708 a=199.820831 penalty=[0.43, 0.43, 0.43, 0.43] +Info: update_chains distance 375.44 +Info: system potential: 87905.085938 hpwl: 114861.625000 +Info: overlap: COMB=46.2%, FF=12.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.189314 grad_dist: 0.093260 +Info: iter=396 steplen=2.029961 a=200.321457 penalty=[0.44, 0.44, 0.44, 0.44] +Info: update_chains distance 377.79 +Info: system potential: 85076.875000 hpwl: 115429.484375 +Info: overlap: COMB=45.4%, FF=11.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.188445 grad_dist: 0.092823 +Info: iter=397 steplen=2.030155 a=200.822083 penalty=[0.45, 0.45, 0.45, 0.45] +Info: update_chains distance 379.64 +Info: system potential: 82382.820312 hpwl: 115976.492188 +Info: overlap: COMB=44.9%, FF=11.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.187585 grad_dist: 0.092411 +Info: iter=398 steplen=2.029904 a=201.322708 penalty=[0.46, 0.46, 0.46, 0.46] +Info: update_chains distance 381.95 +Info: system potential: 79758.531250 hpwl: 116521.320312 +Info: overlap: COMB=44.3%, FF=10.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.186713 grad_dist: 0.091988 +Info: iter=399 steplen=2.029758 a=201.823334 penalty=[0.47, 0.47, 0.47, 0.47] +Info: update_chains distance 383.77 +Info: system potential: 77215.046875 hpwl: 117045.218750 +Info: overlap: COMB=43.6%, FF=10.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185847 grad_dist: 0.091541 +Info: iter=400 steplen=2.030207 a=202.323944 penalty=[0.48, 0.48, 0.48, 0.48] +Info: update_chains distance 386.08 +Info: system potential: 74683.414062 hpwl: 117565.601562 +Info: overlap: COMB=43.0%, FF=10.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185009 grad_dist: 0.091120 +Info: iter=401 steplen=2.030389 a=202.824554 penalty=[0.49, 0.49, 0.49, 0.49] +Info: update_chains distance 388.01 +Info: system potential: 72268.867188 hpwl: 118072.960938 +Info: overlap: COMB=42.6%, FF=9.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.184137 grad_dist: 0.090744 +Info: iter=402 steplen=2.029199 a=203.325180 penalty=[0.51, 0.51, 0.51, 0.51] +Info: update_chains distance 390.36 +Info: system potential: 69933.273438 hpwl: 118564.984375 +Info: overlap: COMB=41.8%, FF=9.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.183097 grad_dist: 0.090315 +Info: iter=403 steplen=2.027312 a=203.825790 penalty=[0.52, 0.52, 0.52, 0.52] +Info: update_chains distance 392.21 +Info: system potential: 67706.078125 hpwl: 119049.664062 +Info: overlap: COMB=41.4%, FF=8.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.181849 grad_dist: 0.089733 +Info: iter=404 steplen=2.026561 a=204.326401 penalty=[0.53, 0.53, 0.53, 0.53] +Info: update_chains distance 394.53 +Info: system potential: 65626.484375 hpwl: 119520.281250 +Info: overlap: COMB=40.7%, FF=8.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.180606 grad_dist: 0.089068 +Info: iter=405 steplen=2.027737 a=204.827011 penalty=[0.55, 0.55, 0.55, 0.55] +Info: update_chains distance 396.50 +Info: system potential: 63566.652344 hpwl: 119999.187500 +Info: overlap: COMB=40.2%, FF=7.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.179587 grad_dist: 0.088513 +Info: iter=406 steplen=2.028930 a=205.327621 penalty=[0.56, 0.56, 0.56, 0.56] +Info: update_chains distance 399.02 +Info: system potential: 61573.984375 hpwl: 120465.617188 +Info: overlap: COMB=39.8%, FF=7.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178953 grad_dist: 0.088148 +Info: iter=407 steplen=2.030138 a=205.828232 penalty=[0.57, 0.57, 0.57, 0.57] +Info: update_chains distance 401.10 +Info: system potential: 59590.441406 hpwl: 120939.812500 +Info: overlap: COMB=39.1%, FF=7.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178509 grad_dist: 0.087901 +Info: iter=408 steplen=2.030789 a=206.328842 penalty=[0.59, 0.59, 0.59, 0.59] +Info: update_chains distance 403.63 +Info: system potential: 57781.550781 hpwl: 121398.656250 +Info: overlap: COMB=38.6%, FF=7.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178145 grad_dist: 0.087696 +Info: iter=409 steplen=2.031390 a=206.829453 penalty=[0.60, 0.60, 0.60, 0.60] +Info: update_chains distance 405.65 +Info: system potential: 55933.847656 hpwl: 121872.906250 +Info: overlap: COMB=38.0%, FF=7.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177842 grad_dist: 0.087486 +Info: iter=410 steplen=2.032812 a=207.330063 penalty=[0.62, 0.62, 0.62, 0.62] +Info: update_chains distance 408.09 +Info: system potential: 54024.042969 hpwl: 122333.304688 +Info: overlap: COMB=37.1%, FF=6.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177518 grad_dist: 0.087309 +Info: iter=411 steplen=2.033214 a=207.830658 penalty=[0.63, 0.63, 0.63, 0.63] +Info: update_chains distance 410.16 +Info: system potential: 52195.578125 hpwl: 122812.617188 +Info: overlap: COMB=36.5%, FF=6.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177187 grad_dist: 0.087150 +Info: iter=412 steplen=2.033121 a=208.331253 penalty=[0.65, 0.65, 0.65, 0.65] +Info: update_chains distance 412.72 +Info: system potential: 50362.500000 hpwl: 123274.671875 +Info: overlap: COMB=35.9%, FF=6.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176810 grad_dist: 0.086920 +Info: iter=413 steplen=2.034171 a=208.831848 penalty=[0.67, 0.67, 0.67, 0.67] +Info: update_chains distance 414.80 +Info: system potential: 48573.363281 hpwl: 123760.976562 +Info: overlap: COMB=35.3%, FF=5.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176424 grad_dist: 0.086661 +Info: iter=414 steplen=2.035802 a=209.332443 penalty=[0.68, 0.68, 0.68, 0.68] +Info: update_chains distance 417.29 +Info: system potential: 46811.378906 hpwl: 124234.335938 +Info: overlap: COMB=34.8%, FF=6.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176070 grad_dist: 0.086467 +Info: iter=415 steplen=2.036277 a=209.833038 penalty=[0.70, 0.70, 0.70, 0.70] +Info: update_chains distance 419.35 +Info: system potential: 45118.382812 hpwl: 124728.085938 +Info: overlap: COMB=34.5%, FF=5.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175877 grad_dist: 0.086294 +Info: iter=416 steplen=2.038111 a=210.333633 penalty=[0.72, 0.72, 0.72, 0.72] +Info: update_chains distance 421.65 +Info: system potential: 43458.222656 hpwl: 125211.093750 +Info: overlap: COMB=34.1%, FF=5.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175830 grad_dist: 0.086128 +Info: iter=417 steplen=2.041507 a=210.834229 penalty=[0.73, 0.73, 0.73, 0.73] +Info: update_chains distance 423.78 +Info: system potential: 41741.523438 hpwl: 125719.406250 +Info: overlap: COMB=33.3%, FF=4.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175925 grad_dist: 0.086097 +Info: iter=418 steplen=2.043347 a=211.334824 penalty=[0.75, 0.75, 0.75, 0.75] +Info: update_chains distance 426.20 +Info: system potential: 40209.914062 hpwl: 126215.601562 +Info: overlap: COMB=32.9%, FF=4.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176030 grad_dist: 0.086169 +Info: iter=419 steplen=2.042847 a=211.835419 penalty=[0.77, 0.77, 0.77, 0.77] +Info: update_chains distance 428.19 +Info: system potential: 38723.980469 hpwl: 126720.539062 +Info: overlap: COMB=32.3%, FF=4.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175996 grad_dist: 0.086109 +Info: iter=420 steplen=2.043875 a=212.336014 penalty=[0.79, 0.79, 0.79, 0.79] +Info: update_chains distance 430.43 +Info: system potential: 37195.742188 hpwl: 127220.273438 +Info: overlap: COMB=31.9%, FF=4.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175745 grad_dist: 0.085886 +Info: iter=421 steplen=2.046263 a=212.836594 penalty=[0.81, 0.81, 0.81, 0.81] +Info: update_chains distance 432.36 +Info: system potential: 35735.921875 hpwl: 127739.312500 +Info: overlap: COMB=31.4%, FF=4.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175517 grad_dist: 0.085701 +Info: iter=422 steplen=2.048010 a=213.337173 penalty=[0.83, 0.83, 0.83, 0.83] +Info: update_chains distance 434.49 +Info: system potential: 34291.511719 hpwl: 128245.851562 +Info: overlap: COMB=30.9%, FF=4.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175404 grad_dist: 0.085582 +Info: iter=423 steplen=2.049542 a=213.837753 penalty=[0.85, 0.85, 0.85, 0.85] +Info: update_chains distance 436.25 +Info: system potential: 32834.160156 hpwl: 128767.234375 +Info: overlap: COMB=30.2%, FF=4.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175250 grad_dist: 0.085442 +Info: iter=424 steplen=2.051092 a=214.338333 penalty=[0.87, 0.87, 0.87, 0.87] +Info: update_chains distance 438.10 +Info: system potential: 31396.417969 hpwl: 129274.796875 +Info: overlap: COMB=29.8%, FF=4.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175059 grad_dist: 0.085265 +Info: iter=425 steplen=2.053112 a=214.838913 penalty=[0.89, 0.89, 0.89, 0.89] +Info: update_chains distance 439.38 +Info: system potential: 30121.751953 hpwl: 129795.484375 +Info: overlap: COMB=29.1%, FF=3.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174909 grad_dist: 0.085079 +Info: iter=426 steplen=2.055849 a=215.339493 penalty=[0.92, 0.92, 0.92, 0.92] +Info: update_chains distance 440.94 +Info: system potential: 28823.443359 hpwl: 130301.960938 +Info: overlap: COMB=28.5%, FF=3.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174824 grad_dist: 0.084937 +Info: iter=427 steplen=2.058291 a=215.840073 penalty=[0.94, 0.94, 0.94, 0.94] +Info: update_chains distance 442.14 +Info: system potential: 27537.847656 hpwl: 130823.562500 +Info: overlap: COMB=27.9%, FF=3.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174825 grad_dist: 0.084833 +Info: iter=428 steplen=2.060818 a=216.340652 penalty=[0.96, 0.96, 0.96, 0.96] +Info: update_chains distance 443.50 +Info: system potential: 26314.400391 hpwl: 131324.093750 +Info: overlap: COMB=27.9%, FF=3.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174813 grad_dist: 0.084746 +Info: iter=429 steplen=2.062794 a=216.841232 penalty=[0.99, 0.99, 0.99, 0.99] +Info: update_chains distance 444.61 +Info: system potential: 25083.455078 hpwl: 131837.171875 +Info: overlap: COMB=27.3%, FF=3.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174756 grad_dist: 0.084634 +Info: iter=430 steplen=2.064832 a=217.341812 penalty=[1.01, 1.01, 1.01, 1.01] +Info: update_chains distance 445.90 +Info: system potential: 23858.943359 hpwl: 132322.734375 +Info: overlap: COMB=26.8%, FF=3.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174600 grad_dist: 0.084484 +Info: iter=431 steplen=2.066663 a=217.842392 penalty=[1.04, 1.04, 1.04, 1.04] +Info: update_chains distance 446.61 +Info: system potential: 22709.591797 hpwl: 132817.859375 +Info: overlap: COMB=26.2%, FF=3.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174214 grad_dist: 0.084306 +Info: iter=432 steplen=2.066452 a=218.342972 penalty=[1.06, 1.06, 1.06, 1.06] +Info: update_chains distance 447.59 +Info: system potential: 21630.294922 hpwl: 133277.156250 +Info: overlap: COMB=25.6%, FF=2.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.173573 grad_dist: 0.083995 +Info: iter=433 steplen=2.066476 a=218.843536 penalty=[1.09, 1.09, 1.09, 1.09] +Info: update_chains distance 448.18 +Info: system potential: 20663.419922 hpwl: 133741.781250 +Info: overlap: COMB=25.0%, FF=2.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.172700 grad_dist: 0.083503 +Info: iter=434 steplen=2.068194 a=219.344101 penalty=[1.12, 1.12, 1.12, 1.12] +Info: update_chains distance 449.10 +Info: system potential: 19734.441406 hpwl: 134183.781250 +Info: overlap: COMB=24.4%, FF=2.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.171834 grad_dist: 0.082981 +Info: iter=435 steplen=2.070770 a=219.844681 penalty=[1.15, 1.15, 1.15, 1.15] +Info: update_chains distance 449.57 +Info: system potential: 18867.146484 hpwl: 134626.671875 +Info: overlap: COMB=24.0%, FF=2.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.171048 grad_dist: 0.082572 +Info: iter=436 steplen=2.071513 a=220.345245 penalty=[1.17, 1.17, 1.17, 1.17] +Info: update_chains distance 450.31 +Info: system potential: 18020.859375 hpwl: 135047.687500 +Info: overlap: COMB=23.8%, FF=2.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.170332 grad_dist: 0.082199 +Info: iter=437 steplen=2.072185 a=220.845810 penalty=[1.20, 1.20, 1.20, 1.20] +Info: update_chains distance 450.66 +Info: system potential: 17237.900391 hpwl: 135457.640625 +Info: overlap: COMB=23.2%, FF=2.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.169588 grad_dist: 0.081754 +Info: iter=438 steplen=2.074370 a=221.346375 penalty=[1.23, 1.23, 1.23, 1.23] +Info: update_chains distance 451.43 +Info: system potential: 16498.933594 hpwl: 135856.750000 +Info: overlap: COMB=22.7%, FF=2.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168909 grad_dist: 0.081321 +Info: iter=439 steplen=2.077060 a=221.846939 penalty=[1.26, 1.26, 1.26, 1.26] +Info: update_chains distance 452.04 +Info: system potential: 15816.792969 hpwl: 136243.890625 +Info: overlap: COMB=22.0%, FF=2.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168323 grad_dist: 0.081013 +Info: iter=440 steplen=2.077725 a=222.347504 penalty=[1.30, 1.30, 1.30, 1.30] +Info: update_chains distance 453.23 +Info: system potential: 15168.061523 hpwl: 136617.953125 +Info: overlap: COMB=21.8%, FF=2.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.167808 grad_dist: 0.080719 +Info: iter=441 steplen=2.078918 a=222.848068 penalty=[1.33, 1.33, 1.33, 1.33] +Info: update_chains distance 454.01 +Info: system potential: 14549.710938 hpwl: 136973.437500 +Info: overlap: COMB=21.2%, FF=2.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.167122 grad_dist: 0.080347 +Info: iter=442 steplen=2.079998 a=223.348633 penalty=[1.36, 1.36, 1.36, 1.36] +Info: update_chains distance 455.14 +Info: system potential: 14012.304688 hpwl: 137324.343750 +Info: overlap: COMB=20.8%, FF=2.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.166201 grad_dist: 0.079932 +Info: iter=443 steplen=2.079283 a=223.849197 penalty=[1.40, 1.40, 1.40, 1.40] +Info: update_chains distance 455.81 +Info: system potential: 13449.343750 hpwl: 137642.703125 +Info: overlap: COMB=20.7%, FF=1.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.165297 grad_dist: 0.079404 +Info: iter=444 steplen=2.081732 a=224.349762 penalty=[1.43, 1.43, 1.43, 1.43] +Info: update_chains distance 456.59 +Info: system potential: 12947.724609 hpwl: 137973.218750 +Info: overlap: COMB=20.4%, FF=1.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164392 grad_dist: 0.078838 +Info: iter=445 steplen=2.085188 a=224.850327 penalty=[1.47, 1.47, 1.47, 1.47] +Info: update_chains distance 456.93 +Info: system potential: 12423.333008 hpwl: 138273.875000 +Info: overlap: COMB=20.1%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163911 grad_dist: 0.078440 +Info: iter=446 steplen=2.089653 a=225.350876 penalty=[1.50, 1.50, 1.50, 1.50] +Info: update_chains distance 457.68 +Info: system potential: 11962.882812 hpwl: 138600.062500 +Info: overlap: COMB=20.1%, FF=2.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163669 grad_dist: 0.078250 +Info: iter=447 steplen=2.091615 a=225.851425 penalty=[1.54, 1.54, 1.54, 1.54] +Info: update_chains distance 458.10 +Info: system potential: 11523.691406 hpwl: 138878.593750 +Info: overlap: COMB=19.7%, FF=1.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163421 grad_dist: 0.078133 +Info: iter=448 steplen=2.091591 a=226.351974 penalty=[1.58, 1.58, 1.58, 1.58] +Info: update_chains distance 458.95 +Info: system potential: 11112.025391 hpwl: 139188.718750 +Info: overlap: COMB=19.3%, FF=1.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163086 grad_dist: 0.077852 +Info: iter=449 steplen=2.094835 a=226.852524 penalty=[1.62, 1.62, 1.62, 1.62] +Info: update_chains distance 459.56 +Info: system potential: 10695.295898 hpwl: 139448.859375 +Info: overlap: COMB=19.1%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162593 grad_dist: 0.077489 +Info: iter=450 steplen=2.098278 a=227.353073 penalty=[1.66, 1.66, 1.66, 1.66] +Info: update_chains distance 460.60 +Info: system potential: 10314.656250 hpwl: 139763.062500 +Info: overlap: COMB=18.8%, FF=1.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162129 grad_dist: 0.077241 +Info: iter=451 steplen=2.099002 a=227.853622 penalty=[1.70, 1.70, 1.70, 1.70] +Info: update_chains distance 461.25 +Info: system potential: 9902.566406 hpwl: 140011.531250 +Info: overlap: COMB=18.4%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161913 grad_dist: 0.076991 +Info: iter=452 steplen=2.103029 a=228.354172 penalty=[1.74, 1.74, 1.74, 1.74] +Info: update_chains distance 461.91 +Info: system potential: 9538.675781 hpwl: 140323.812500 +Info: overlap: COMB=18.1%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161786 grad_dist: 0.076729 +Info: iter=453 steplen=2.108548 a=228.854721 penalty=[1.79, 1.79, 1.79, 1.79] +Info: update_chains distance 462.48 +Info: system potential: 9133.239258 hpwl: 140578.937500 +Info: overlap: COMB=17.8%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161871 grad_dist: 0.076684 +Info: iter=454 steplen=2.110883 a=229.355270 penalty=[1.83, 1.83, 1.83, 1.83] +Info: update_chains distance 463.35 +Info: system potential: 8760.636719 hpwl: 140894.234375 +Info: overlap: COMB=17.4%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161743 grad_dist: 0.076727 +Info: iter=455 steplen=2.108043 a=229.855820 penalty=[1.88, 1.88, 1.88, 1.88] +Info: update_chains distance 463.91 +Info: system potential: 8430.484375 hpwl: 141135.718750 +Info: overlap: COMB=17.3%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161242 grad_dist: 0.076449 +Info: iter=456 steplen=2.109155 a=230.356369 penalty=[1.92, 1.92, 1.92, 1.92] +Info: update_chains distance 464.53 +Info: system potential: 8101.475098 hpwl: 141441.859375 +Info: overlap: COMB=17.0%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160544 grad_dist: 0.075857 +Info: iter=457 steplen=2.116397 a=230.856918 penalty=[1.97, 1.97, 1.97, 1.97] +Info: update_chains distance 465.08 +Info: system potential: 7765.088867 hpwl: 141703.937500 +Info: overlap: COMB=16.6%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159941 grad_dist: 0.075492 +Info: iter=458 steplen=2.118638 a=231.357468 penalty=[2.02, 2.02, 2.02, 2.02] +Info: update_chains distance 465.67 +Info: system potential: 7434.513672 hpwl: 142017.578125 +Info: overlap: COMB=16.3%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159570 grad_dist: 0.075390 +Info: iter=459 steplen=2.116598 a=231.858002 penalty=[2.07, 2.07, 2.07, 2.07] +Info: update_chains distance 466.33 +Info: system potential: 7129.029785 hpwl: 142272.234375 +Info: overlap: COMB=16.1%, FF=1.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.158951 grad_dist: 0.075050 +Info: iter=460 steplen=2.117938 a=232.358536 penalty=[2.12, 2.12, 2.12, 2.12] +Info: update_chains distance 467.25 +Info: system potential: 6845.776855 hpwl: 142581.718750 +Info: overlap: COMB=15.8%, FF=1.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157981 grad_dist: 0.074435 +Info: iter=461 steplen=2.122388 a=232.859070 penalty=[2.18, 2.18, 2.18, 2.18] +Info: update_chains distance 468.16 +Info: system potential: 6588.242676 hpwl: 142842.734375 +Info: overlap: COMB=15.4%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157232 grad_dist: 0.073915 +Info: iter=462 steplen=2.127196 a=233.359604 penalty=[2.23, 2.23, 2.23, 2.23] +Info: update_chains distance 469.41 +Info: system potential: 6301.302246 hpwl: 143155.875000 +Info: overlap: COMB=15.7%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156984 grad_dist: 0.073639 +Info: iter=463 steplen=2.131798 a=233.860138 penalty=[2.29, 2.29, 2.29, 2.29] +Info: update_chains distance 470.54 +Info: system potential: 6057.123535 hpwl: 143425.281250 +Info: overlap: COMB=15.4%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156727 grad_dist: 0.073522 +Info: iter=464 steplen=2.131715 a=234.360672 penalty=[2.34, 2.34, 2.34, 2.34] +Info: update_chains distance 471.61 +Info: system potential: 5776.902344 hpwl: 143725.671875 +Info: overlap: COMB=15.1%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156326 grad_dist: 0.073320 +Info: iter=465 steplen=2.132102 a=234.861206 penalty=[2.40, 2.40, 2.40, 2.40] +Info: update_chains distance 472.30 +Info: system potential: 5557.244141 hpwl: 143986.046875 +Info: overlap: COMB=14.8%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.155186 grad_dist: 0.072834 +Info: iter=466 steplen=2.130677 a=235.361740 penalty=[2.46, 2.46, 2.46, 2.46] +Info: update_chains distance 473.63 +Info: system potential: 5319.213379 hpwl: 144268.250000 +Info: overlap: COMB=14.0%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.154075 grad_dist: 0.072111 +Info: iter=467 steplen=2.136635 a=235.862274 penalty=[2.52, 2.52, 2.52, 2.52] +Info: update_chains distance 474.89 +Info: system potential: 5082.393066 hpwl: 144528.281250 +Info: overlap: COMB=13.8%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153111 grad_dist: 0.071433 +Info: iter=468 steplen=2.143432 a=236.362808 penalty=[2.59, 2.59, 2.59, 2.59] +Info: update_chains distance 476.11 +Info: system potential: 4869.984863 hpwl: 144809.843750 +Info: overlap: COMB=13.4%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152972 grad_dist: 0.071160 +Info: iter=469 steplen=2.149685 a=236.863342 penalty=[2.65, 2.65, 2.65, 2.65] +Info: update_chains distance 476.98 +Info: system potential: 4643.716309 hpwl: 145067.109375 +Info: overlap: COMB=13.2%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153304 grad_dist: 0.071225 +Info: iter=470 steplen=2.152397 a=237.363861 penalty=[2.72, 2.72, 2.72, 2.72] +Info: update_chains distance 477.85 +Info: system potential: 4461.454590 hpwl: 145326.531250 +Info: overlap: COMB=13.0%, FF=0.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153390 grad_dist: 0.071300 +Info: iter=471 steplen=2.151330 a=237.864380 penalty=[2.79, 2.79, 2.79, 2.79] +Info: update_chains distance 478.07 +Info: system potential: 4268.108398 hpwl: 145554.406250 +Info: overlap: COMB=12.7%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153334 grad_dist: 0.071096 +Info: iter=472 steplen=2.156715 a=238.364914 penalty=[2.86, 2.86, 2.86, 2.86] +Info: update_chains distance 478.78 +Info: system potential: 4078.253174 hpwl: 145787.968750 +Info: overlap: COMB=12.5%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153043 grad_dist: 0.070766 +Info: iter=473 steplen=2.162667 a=238.865433 penalty=[2.93, 2.93, 2.93, 2.93] +Info: update_chains distance 479.41 +Info: system potential: 3917.518799 hpwl: 146010.359375 +Info: overlap: COMB=12.3%, FF=0.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152932 grad_dist: 0.070660 +Info: iter=474 steplen=2.164347 a=239.365952 penalty=[3.00, 3.00, 3.00, 3.00] +Info: update_chains distance 480.25 +Info: system potential: 3758.513428 hpwl: 146219.406250 +Info: overlap: COMB=11.9%, FF=0.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153350 grad_dist: 0.070560 +Info: iter=475 steplen=2.173333 a=239.866470 penalty=[3.07, 3.07, 3.07, 3.07] +Info: update_chains distance 481.13 +Info: system potential: 3619.491699 hpwl: 146431.187500 +Info: overlap: COMB=11.8%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153576 grad_dist: 0.070573 +Info: iter=476 steplen=2.176136 a=240.366989 penalty=[3.15, 3.15, 3.15, 3.15] +Info: update_chains distance 482.62 +Info: system potential: 3508.918945 hpwl: 146631.578125 +Info: overlap: COMB=11.5%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153543 grad_dist: 0.070685 +Info: iter=477 steplen=2.172205 a=240.867508 penalty=[3.23, 3.23, 3.23, 3.23] +Info: update_chains distance 483.21 +Info: system potential: 3374.741211 hpwl: 146804.765625 +Info: overlap: COMB=11.2%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153227 grad_dist: 0.070396 +Info: iter=478 steplen=2.176660 a=241.368027 penalty=[3.31, 3.31, 3.31, 3.31] +Info: update_chains distance 484.26 +Info: system potential: 3255.671875 hpwl: 146994.984375 +Info: overlap: COMB=11.0%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152323 grad_dist: 0.069792 +Info: iter=479 steplen=2.182525 a=241.868546 penalty=[3.39, 3.39, 3.39, 3.39] +Info: update_chains distance 485.27 +Info: system potential: 3144.638672 hpwl: 147172.062500 +Info: overlap: COMB=10.9%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151657 grad_dist: 0.069385 +Info: iter=480 steplen=2.185716 a=242.369064 penalty=[3.48, 3.48, 3.48, 3.48] +Info: update_chains distance 486.61 +Info: system potential: 3011.866699 hpwl: 147366.593750 +Info: overlap: COMB=10.7%, FF=0.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151521 grad_dist: 0.069117 +Info: iter=481 steplen=2.192243 a=242.869583 penalty=[3.57, 3.57, 3.57, 3.57] +Info: update_chains distance 487.51 +Info: system potential: 2905.388428 hpwl: 147543.781250 +Info: overlap: COMB=10.4%, FF=0.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151530 grad_dist: 0.068924 +Info: iter=482 steplen=2.198524 a=243.370102 penalty=[3.65, 3.65, 3.65, 3.65] +Info: update_chains distance 489.26 +Info: system potential: 2802.557129 hpwl: 147748.046875 +Info: overlap: COMB=10.2%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151931 grad_dist: 0.068858 +Info: iter=483 steplen=2.206452 a=243.870621 penalty=[3.75, 3.75, 3.75, 3.75] +Info: update_chains distance 490.59 +Info: system potential: 2689.866699 hpwl: 147929.328125 +Info: overlap: COMB=10.0%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152483 grad_dist: 0.068981 +Info: iter=484 steplen=2.210502 a=244.371124 penalty=[3.84, 3.84, 3.84, 3.84] +Info: update_chains distance 492.25 +Info: system potential: 2593.473633 hpwl: 148131.437500 +Info: overlap: COMB=10.0%, FF=0.6%, RAM=0.0%, MUL=0.0% +Info: Strict legalising 24792 cells... +Info: HPWL after legalise: 159214.000000 (delta: 11082.562500) + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 159011 +Info: at iteration #5: temp = 0.000000, timing cost = 0, wirelen = 148373 +Info: at iteration #10: temp = 0.000000, timing cost = 0, wirelen = 146766 +Info: at iteration #15: temp = 0.000000, timing cost = 0, wirelen = 146348 +Info: at iteration #20: temp = 0.000000, timing cost = 0, wirelen = 146242 +Info: at iteration #23: temp = 0.000000, timing cost = 0, wirelen = 146233 +Info: SA placement time 43.57s + +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) + +Info: Max delay -> posedge $glbnet$core_clk: 3.52 ns +Info: Max delay posedge $glbnet$core_clk -> : 9.48 ns + +Info: Slack histogram: +Info: legend: * represents 36 endpoint(s) +Info: + represents [1,36) endpoint(s) +Info: [ 25523, 29209) |***+ +Info: [ 29209, 32895) |+ +Info: [ 32895, 36581) | +Info: [ 36581, 40267) | +Info: [ 40267, 43953) | +Info: [ 43953, 47639) | +Info: [ 47639, 51325) | +Info: [ 51325, 55011) |+ +Info: [ 55011, 58697) |*********+ +Info: [ 58697, 62383) |**************************************+ +Info: [ 62383, 66069) |******************************+ +Info: [ 66069, 69755) |*******+ +Info: [ 69755, 73441) |*+ +Info: [ 73441, 77127) |*************+ +Info: [ 77127, 80813) |***************************************************+ +Info: [ 80813, 84499) |************************************************************ +Info: [ 84499, 88185) |******************************************************+ +Info: [ 88185, 91871) |**********************************+ +Info: [ 91871, 95557) |*****************+ +Info: [ 95557, 99243) |**+ +Info: Checksum: 0xd4f9c64c +Info: Routing globals... +Info: routing clock net $glbnet$core_clk using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 111218 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 0 999 | 0 999 | 110219| 2.07 2.07| +Info: 2000 | 0 1999 | 0 1000 | 109219| 0.40 2.47| +Info: 3000 | 0 2999 | 0 1000 | 108219| 0.37 2.84| +Info: 4000 | 3 3996 | 3 997 | 107224| 0.44 3.28| +Info: 5000 | 4 4995 | 1 999 | 106225| 0.43 3.71| +Info: 6000 | 16 5983 | 12 988 | 105277| 0.46 4.17| +Info: 7000 | 32 6967 | 16 984 | 104294| 0.45 4.63| +Info: 8000 | 53 7946 | 21 979 | 103333| 0.44 5.06| +Info: 9000 | 56 8943 | 3 997 | 102349| 0.39 5.46| +Info: 10000 | 66 9933 | 10 990 | 101382| 0.46 5.92| +Info: 11000 | 69 10930 | 3 997 | 100392| 0.44 6.36| +Info: 12000 | 78 11921 | 9 991 | 99410| 0.62 6.97| +Info: 13000 | 82 12917 | 4 996 | 98418| 0.47 7.44| +Info: 14000 | 93 13906 | 11 989 | 97435| 0.45 7.90| +Info: 15000 | 112 14887 | 19 981 | 96475| 0.60 8.50| +Info: 16000 | 125 15874 | 13 987 | 95495| 0.59 9.09| +Info: 17000 | 149 16850 | 24 976 | 94537| 0.59 9.68| +Info: 18000 | 173 17826 | 24 976 | 93583| 0.49 10.18| +Info: 19000 | 187 18812 | 14 986 | 92609| 0.52 10.70| +Info: 20000 | 217 19782 | 30 970 | 91682| 0.57 11.27| +Info: 21000 | 251 20748 | 34 966 | 90736| 0.53 11.80| +Info: 22000 | 308 21691 | 57 943 | 89903| 0.61 12.42| +Info: 23000 | 342 22657 | 34 966 | 88962| 0.66 13.08| +Info: 24000 | 408 23591 | 66 934 | 88119| 0.65 13.73| +Info: 25000 | 487 24512 | 79 921 | 87318| 0.79 14.52| +Info: 26000 | 575 25424 | 88 912 | 86561| 0.79 15.31| +Info: 27000 | 658 26341 | 83 917 | 85860| 0.66 15.97| +Info: 28000 | 768 27231 | 110 890 | 85094| 0.75 16.72| +Info: 29000 | 850 28149 | 82 918 | 84271| 0.73 17.45| +Info: 30000 | 987 29012 | 137 863 | 83573| 0.90 18.35| +Info: 31000 | 1104 29895 | 117 883 | 82891| 0.88 19.23| +Info: 32000 | 1194 30805 | 90 910 | 82097| 0.74 19.96| +Info: 33000 | 1312 31687 | 118 882 | 81364| 0.73 20.69| +Info: 34000 | 1398 32601 | 86 914 | 80496| 0.67 21.36| +Info: 35000 | 1530 33469 | 132 868 | 79771| 0.74 22.10| +Info: 36000 | 1683 34316 | 153 847 | 79110| 0.84 22.94| +Info: 37000 | 1794 35205 | 111 889 | 78356| 0.70 23.64| +Info: 38000 | 1948 36051 | 154 846 | 77671| 0.78 24.42| +Info: 39000 | 2112 36887 | 164 836 | 77049| 0.96 25.38| +Info: 40000 | 2309 37690 | 197 803 | 76517| 1.08 26.46| +Info: 41000 | 2405 38594 | 96 904 | 75710| 0.67 27.14| +Info: 42000 | 2575 39424 | 170 830 | 75021| 0.88 28.02| +Info: 43000 | 2741 40258 | 166 834 | 74388| 0.95 28.97| +Info: 44000 | 3006 40993 | 265 735 | 73977| 1.12 30.08| +Info: 45000 | 3109 41890 | 103 897 | 73144| 0.78 30.86| +Info: 46000 | 3220 42779 | 111 889 | 72327| 0.80 31.66| +Info: 47000 | 3404 43595 | 184 816 | 71645| 0.97 32.63| +Info: 48000 | 3543 44456 | 139 861 | 70931| 0.79 33.42| +Info: 49000 | 3679 45320 | 136 864 | 70198| 0.94 34.37| +Info: 50000 | 3893 46031 | 214 711 | 69611| 1.31 35.68| +Info: 51000 | 4183 46715 | 290 684 | 69286| 1.92 37.59| +Info: 52000 | 4280 47527 | 97 812 | 68466| 0.81 38.40| +Info: 53000 | 4484 48289 | 204 762 | 67948| 1.11 39.51| +Info: 54000 | 4673 49094 | 189 805 | 67375| 1.32 40.83| +Info: 55000 | 4780 49966 | 107 872 | 66588| 0.81 41.64| +Info: 56000 | 4895 50849 | 115 883 | 65765| 0.73 42.37| +Info: 57000 | 5238 51502 | 343 653 | 65489| 1.79 44.16| +Info: 58000 | 5460 52273 | 222 771 | 64954| 1.12 45.28| +Info: 59000 | 5598 53123 | 138 850 | 64153| 0.80 46.07| +Info: 60000 | 5814 53902 | 216 779 | 63562| 1.16 47.23| +Info: 61000 | 5994 54722 | 180 820 | 62859| 0.94 48.17| +Info: 62000 | 6216 55496 | 222 774 | 62305| 1.20 49.37| +Info: 63000 | 6365 56345 | 149 849 | 61528| 0.84 50.20| +Info: 64000 | 6482 57222 | 117 877 | 60822| 0.69 50.90| +Info: 65000 | 6670 58030 | 188 808 | 60269| 0.99 51.88| +Info: 66000 | 6821 58872 | 151 842 | 59576| 1.02 52.91| +Info: 67000 | 6967 59707 | 146 835 | 58793| 0.82 53.73| +Info: 68000 | 7138 60497 | 171 790 | 58132| 1.05 54.78| +Info: 69000 | 7304 61284 | 166 787 | 57353| 0.93 55.71| +Info: 70000 | 7556 61988 | 252 704 | 56847| 1.46 57.17| +Info: 71000 | 8015 62529 | 459 541 | 56915| 2.66 59.83| +Info: 72000 | 8317 63199 | 302 670 | 56447| 1.43 61.27| +Info: 73000 | 8431 64022 | 114 823 | 55623| 0.63 61.89| +Info: 74000 | 8686 64735 | 255 713 | 55061| 1.43 63.33| +Info: 75000 | 8837 65563 | 151 828 | 54405| 0.91 64.23| +Info: 76000 | 9067 66307 | 230 744 | 53811| 1.33 65.57| +Info: 77000 | 9233 67105 | 166 798 | 53038| 0.85 66.42| +Info: 78000 | 9343 67987 | 110 882 | 52242| 0.86 67.28| +Info: 79000 | 9554 68769 | 211 782 | 51762| 1.36 68.64| +Info: 80000 | 9741 69573 | 187 804 | 51029| 1.06 69.70| +Info: 81000 | 9872 70430 | 131 857 | 50254| 0.91 70.61| +Info: 82000 | 10174 71122 | 302 692 | 49835| 1.91 72.52| +Info: 83000 | 10436 71845 | 262 723 | 49406| 1.63 74.15| +Info: 84000 | 10577 72695 | 141 850 | 48657| 1.04 75.19| +Info: 85000 | 10728 73538 | 151 843 | 47963| 1.05 76.23| +Info: 86000 | 10824 74437 | 96 899 | 47191| 0.71 76.94| +Info: 87000 | 10897 75359 | 73 922 | 46280| 0.53 77.47| +Info: 88000 | 10970 76278 | 73 919 | 45410| 0.53 78.00| +Info: 89000 | 11111 77130 | 141 852 | 44600| 0.76 78.76| +Info: 90000 | 11225 77964 | 114 834 | 43717| 0.56 79.33| +Info: 91000 | 11336 78792 | 111 828 | 42863| 0.67 79.99| +Info: 92000 | 11489 79530 | 153 738 | 42057| 0.67 80.66| +Info: 93000 | 11805 80214 | 316 684 | 42030| 2.21 82.87| +Info: 94000 | 12016 80923 | 211 709 | 41309| 0.97 83.84| +Info: 95000 | 12251 81655 | 235 732 | 40713| 1.28 85.12| +Info: 96000 | 12442 82418 | 191 763 | 39952| 0.73 85.85| +Info: 97000 | 12629 83199 | 187 781 | 39171| 0.76 86.61| +Info: 98000 | 13104 83724 | 475 525 | 39187| 2.92 89.52| +Info: 99000 | 13445 84369 | 341 645 | 38741| 2.08 91.61| +Info: 100000 | 13827 84983 | 382 614 | 38519| 2.39 94.00| +Info: 101000 | 14150 85653 | 323 670 | 38049| 1.56 95.55| +Info: 102000 | 14415 86376 | 265 723 | 37521| 1.40 96.95| +Info: 103000 | 14637 87120 | 222 744 | 36847| 1.29 98.24| +Info: 104000 | 14738 87971 | 101 851 | 35950| 0.60 98.84| +Info: 105000 | 14803 88803 | 65 832 | 35027| 0.51 99.36| +Info: 106000 | 14904 89643 | 101 840 | 34215| 0.85 100.21| +Info: 107000 | 14964 90474 | 60 831 | 33293| 0.66 100.87| +Info: 108000 | 15033 91322 | 69 848 | 32379| 0.59 101.46| +Info: 109000 | 15094 92200 | 61 878 | 31515| 0.60 102.06| +Info: 110000 | 15165 93038 | 71 838 | 30623| 0.58 102.63| +Info: 111000 | 15250 93825 | 85 787 | 29742| 0.62 103.25| +Info: 112000 | 15334 94563 | 84 738 | 28858| 0.66 103.92| +Info: 113000 | 15416 95303 | 82 740 | 27995| 0.56 104.47| +Info: 114000 | 15472 96069 | 56 766 | 27071| 0.55 105.02| +Info: 115000 | 15537 96894 | 65 825 | 26137| 0.51 105.53| +Info: 116000 | 15595 97710 | 58 816 | 25215| 0.51 106.04| +Info: 117000 | 15659 98505 | 64 795 | 24279| 0.52 106.56| +Info: 118000 | 15729 99299 | 70 794 | 23358| 0.68 107.24| +Info: 119000 | 15787 100125 | 58 826 | 22420| 0.51 107.75| +Info: 120000 | 15852 100956 | 65 831 | 21678| 0.57 108.33| +Info: 121000 | 15937 101754 | 85 798 | 20813| 0.62 108.95| +Info: 122000 | 16005 102629 | 68 875 | 19901| 0.58 109.53| +Info: 123000 | 16086 103514 | 81 885 | 18988| 0.63 110.16| +Info: 124000 | 16190 104389 | 104 875 | 18111| 0.70 110.86| +Info: 125000 | 16291 105194 | 101 805 | 17235| 0.65 111.51| +Info: 126000 | 16376 105980 | 85 786 | 16331| 0.64 112.15| +Info: 127000 | 16504 106762 | 128 782 | 15495| 0.79 112.94| +Info: 128000 | 16607 107604 | 103 842 | 14604| 0.71 113.65| +Info: 129000 | 16726 108424 | 119 820 | 13730| 0.67 114.32| +Info: 130000 | 16825 109281 | 99 857 | 12833| 0.76 115.08| +Info: 131000 | 16904 110145 | 79 864 | 11912| 0.59 115.67| +Info: 132000 | 17032 110980 | 128 835 | 11063| 0.75 116.41| +Info: 133000 | 17110 111881 | 78 901 | 10149| 0.61 117.03| +Info: 134000 | 17163 112749 | 53 868 | 9209| 0.55 117.58| +Info: 135000 | 17237 113573 | 74 824 | 8294| 0.52 118.09| +Info: 136000 | 17304 114453 | 67 880 | 7372| 0.63 118.72| +Info: 137000 | 17531 115226 | 227 773 | 6744| 1.12 119.84| +Info: 138000 | 17793 115964 | 262 738 | 6018| 0.72 120.56| +Info: 139000 | 18042 116715 | 249 751 | 5287| 0.77 121.33| +Info: 140000 | 18340 117417 | 298 702 | 4783| 1.10 122.43| +Info: 141000 | 18603 118154 | 263 737 | 4109| 0.71 123.14| +Info: 142000 | 18878 118879 | 275 725 | 3492| 0.96 124.09| +Info: 143000 | 19135 119622 | 257 743 | 2775| 0.66 124.75| +Info: 144000 | 19407 120350 | 272 728 | 2048| 0.58 125.34| +Info: 145000 | 19638 121113 | 231 763 | 1282| 0.64 125.98| +Info: 146000 | 19645 121745 | 7 632 | 291| 0.46 126.45| +Info: 146290 | 19645 121917 | 0 172 | 0| 0.34 126.78| +Info: Routing complete. +Info: Router1 time 126.78s +Info: Checksum: 0x323f3232 + +Info: Critical path report for clock '$glbnet$core_clk' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_TRELLIS_FF_Q.Q +Info: routing 5.85 6.37 Net bridge.por_shift[7] (9,8) -> (32,83) +Info: Sink bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_LUT4_D.D +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: uart_tx.sv:11.23-11.28 +Info: uart_bridge.sv:59.7-66.6 +Info: logic 0.24 6.61 Source bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_LUT4_D.F +Info: routing 2.64 9.25 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_D[0] (32,83) -> (76,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 9.49 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.F +Info: routing 1.20 10.69 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_COUT_CCU2C_CIN_S0_PFUMX_Z_BLUT_LUT4_Z_B[1] (76,77) -> (80,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B.B +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 10.92 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B.F +Info: routing 0.00 10.92 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B_Z (80,77) -> (80,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C.F1 +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:133.22-133.24 +Info: logic 0.17 11.09 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C.OFX +Info: routing 1.16 12.24 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_A1_S0_LUT4_Z_C_PFUMX_Z_C0[3] (80,77) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 12.69 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.69 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.69 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.69 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.76 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.76 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.83 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.83 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.83 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.83 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.90 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.90 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.98 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.98 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.98 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.98 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 13.05 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 13.05 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 13.05 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 13.05 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 13.12 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 13.12 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 13.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 1.38 14.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0[0] (82,74) -> (85,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 15.35 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 15.35 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN (85,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 15.42 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 15.42 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 15.42 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 15.42 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 15.86 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.22 16.08 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D[1] (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 16.32 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.91 17.23 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (86,73) -> (87,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 17.67 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 17.67 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN (87,72) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 17.75 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 17.75 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_FCI_INT (88,72) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 18.15 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 1.14 19.29 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0[1] (88,72) -> (86,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 19.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 1.03 20.56 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1[1] (86,74) -> (85,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 21.00 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 21.00 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (85,74) -> (85,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 21.00 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 21.00 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (85,74) -> (86,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 21.44 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 22.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (86,74) -> (85,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 22.61 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.88 23.49 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (85,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 23.94 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 23.94 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (84,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 24.01 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 24.01 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (84,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 24.41 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.80 25.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0[1] (84,75) -> (85,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 25.44 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 0.89 26.34 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[1] (85,75) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 26.78 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 26.78 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (85,76) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 26.78 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 26.78 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (85,76) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 27.23 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.80 28.02 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (85,76) -> (86,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 28.26 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0_LUT4_Z.F +Info: routing 1.03 29.29 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0[1] (86,76) -> (88,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 29.73 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 29.73 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (88,76) -> (88,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 30.14 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.67 30.80 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (88,76) -> (87,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 31.04 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 1.04 32.08 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[1] (87,75) -> (89,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 32.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 32.53 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (89,75) -> (89,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 32.97 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.66 33.63 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (89,75) -> (90,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 33.87 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.89 34.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (90,75) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 35.21 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 35.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (90,74) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 35.28 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 35.28 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (90,74) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 35.68 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.88 36.56 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (90,74) -> (90,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 36.79 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 1.12 37.91 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[1] (90,73) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 38.36 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 38.36 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (90,71) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 38.36 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 38.36 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (90,71) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 38.80 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 39.73 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (90,71) -> (89,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 39.97 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 1.12 41.09 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (89,72) -> (88,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 41.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 41.53 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (88,73) -> (89,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 41.61 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 41.61 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (89,73) -> (89,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 42.01 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.93 42.94 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (89,73) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 43.18 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 1.12 44.30 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1[1] (88,72) -> (84,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 44.75 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 44.75 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (84,72) -> (85,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 45.19 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 46.12 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[2] (85,72) -> (87,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 46.35 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 0.87 47.22 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z (87,71) -> (87,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1$CCU2_COMB1.B +Info: logic 0.45 47.67 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1$CCU2_COMB1.FCO +Info: routing 0.00 47.67 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT (87,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.74 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.74 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.74 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.74 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.81 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.81 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.81 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.81 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.88 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.88 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.88 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.88 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.96 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.96 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.96 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.96 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.03 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.03 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.03 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.03 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.10 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.10 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.10 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.10 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.17 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.17 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.17 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.17 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.24 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.24 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.31 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.31 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.31 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.31 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.45 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.45 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.45 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.45 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.52 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.52 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (91,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.59 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.59 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (91,69) -> (91,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.59 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.59 Net $nextpnr_CCU2C_145$CIN (91,69) -> (91,69) +Info: Sink $nextpnr_CCU2C_145$CCU2_COMB0.FCI +Info: logic 0.44 49.04 Source $nextpnr_CCU2C_145$CCU2_COMB0.F +Info: routing 1.11 50.15 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT[6] (91,69) -> (97,64) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 50.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_C.F +Info: routing 2.47 52.85 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_PFUMX_C0_Z[5] (97,64) -> (77,50) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 53.11 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 1.11 54.21 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C[1] (77,50) -> (77,53) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z.C +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 54.45 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z.F +Info: routing 1.69 56.14 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD[5] (77,53) -> (81,63) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 56.40 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.65 57.05 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD[5] (81,63) -> (82,66) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 57.31 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 1.67 58.98 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z[6] (82,66) -> (72,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 59.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.97 60.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] (72,75) -> (73,78) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_A.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 60.47 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_A.OFX +Info: routing 0.97 61.44 Net bridge.tx_data_q_TRELLIS_FF_Q_2_DI_LUT4_Z_C[4] (73,78) -> (71,81) +Info: Sink bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 61.69 Source bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 1.23 62.93 Net bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (71,81) -> (69,88) +Info: Sink bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C.C +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 63.16 Source bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C.F +Info: routing 0.94 64.11 Net bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_Z[5] (69,88) -> (67,86) +Info: Sink bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI_PFUMX_Z_BLUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 64.36 Source bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.92 65.28 Net bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI (67,86) -> (67,85) +Info: Sink bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8.M +Info: setup 0.00 65.28 Source bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8.M +Info: 19.53 ns logic, 45.75 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$core_clk': +Info: type curr total name +Info: source 0.00 0.00 Source uart_rx$tr_io.O +Info: routing 2.30 2.30 Net uart_rx$TRELLIS_IO_IN (0,89) -> (33,89) +Info: Sink bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: Defined in: +Info: ulx3s_packet_top.sv:6.17-6.24 +Info: setup 0.00 2.30 Source bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: 0.00 ns logic, 2.30 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$core_clk' -> '': +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source bridge.utx.tx_serial_TRELLIS_FF_Q.Q +Info: routing 5.74 6.27 Net uart_tx$TRELLIS_IO_OUT (65,87) -> (0,56) +Info: Sink uart_tx$tr_io.I +Info: Defined in: +Info: ulx3s_packet_top.sv:7.17-7.24 +Info: 0.52 ns logic, 5.74 ns routing + +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) + +Info: Max delay -> posedge $glbnet$core_clk: 2.30 ns +Info: Max delay posedge $glbnet$core_clk -> : 6.27 ns + +Info: Slack histogram: +Info: legend: * represents 44 endpoint(s) +Info: + represents [1,44) endpoint(s) +Info: [ 34721, 37938) |**+ +Info: [ 37938, 41155) |+ +Info: [ 41155, 44372) | +Info: [ 44372, 47589) | +Info: [ 47589, 50806) | +Info: [ 50806, 54023) | +Info: [ 54023, 57240) | +Info: [ 57240, 60457) | +Info: [ 60457, 63674) |****+ +Info: [ 63674, 66891) |*************+ +Info: [ 66891, 70108) |******************+ +Info: [ 70108, 73325) |*****************************+ +Info: [ 73325, 76542) |******+ +Info: [ 76542, 79759) |+ +Info: [ 79759, 82976) |*************+ +Info: [ 82976, 86193) |**********************************+ +Info: [ 86193, 89410) |************************************************************ +Info: [ 89410, 92627) |**********************************************+ +Info: [ 92627, 95844) |********************************+ +Info: [ 95844, 99061) |**+ + +Info: Program finished normally. diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/timing.txt b/evidence/lsc1-09-cleanroom/clean-build-1/timing.txt new file mode 100644 index 00000000..a3a0974f --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/timing.txt @@ -0,0 +1,6 @@ +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) +Info: Slack histogram: diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/tool_versions.txt b/evidence/lsc1-09-cleanroom/clean-build-1/tool_versions.txt new file mode 100644 index 00000000..a7f82e9c --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/tool_versions.txt @@ -0,0 +1,5 @@ +=== TOOL VERSIONS (LSC-1 PACKET UART) === +Yosys 0.33 (git sha1 2584903a060) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.11.1) +Project Trellis ecppack Version 1.4-2build4 +date: 2026-09-06T00:58:29Z diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.bit b/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.bit new file mode 100644 index 0000000000000000000000000000000000000000..c4a699369d754237f7a4bddbd39be7a8d45f67df GIT binary patch literal 1927725 zcmeFa37i~9c{cubZ_jM+cx8H5BY7-@sTr@nmO-4U8I9zTEMO#LFa*d*UW055 zNV3Uia@LMk@>&R32?549VI+hjJ0^%L2f0SV*ut0~bA=>?D3I`lBpf+N@<9^+pX%8j z?P|BXdYo$iouBH}s=K!-g@hZ{j1>$z*nm21jZ ztzJowKmPb1eiDbrUr0pX#{cqAX-xrVj{ocMzj@%QAK>&9k}p5<_)`cCpuFBPfTB~x zFci&?(IFK-h9Sd{ngP`v#ts>VR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-x zR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!X 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zUta?utBj|l`cU2XHe8&*`$Dw_Z5b|WCd-g{IkLn7RSTjH3wgCR3Jg?}hTfKBplb20 zM2My%{L1=b|9_6l>O+g5M+RP(;e*H+g=_4}mxziM=eQ5G$kI-7)C8paP}(+uo#S lNy*|LH6LsJtpN_u`? literal 0 HcmV?d00001 diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.config b/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.config new file mode 100644 index 00000000..0b0dc4d2 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.config @@ -0,0 +1,496803 @@ +.device LFE5U-85F + +.comment Part: LFE5U-85F-6CABGA381 + +.tile CIB_R10C39:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C40:CIB_DSP +arc: N1_V02N0501 S1_V02N0401 + +.tile CIB_R10C41:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R10C42:CIB_DSP +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 N1_V02S0301 + +.tile CIB_R10C43:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 V01N0001 + +.tile CIB_R10C44:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 + +.tile CIB_R10C45:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R10C46:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R10C47:CIB_DSP +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 + +.tile CIB_R10C48:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 V01N0001 + +.tile CIB_R10C49:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 S1_V02N0201 + +.tile CIB_R10C50:CIB_DSP +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0401 V01N0001 + +.tile CIB_R10C51:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R10C52:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 + +.tile CIB_R10C54:CIB_DSP +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R10C7:CIB_DSP +arc: N1_V02N0201 N3_V06S0103 + +.tile CIB_R11C1:CIB_LR +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R13C1:CIB_LR +arc: N1_V02N0301 S3_V06N0003 + +.tile CIB_R17C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R19C1:CIB_LR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R22C100:CIB_EBR +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 + +.tile CIB_R22C101:CIB_EBR +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C102:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R22C103:CIB_EBR +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R22C104:CIB_EBR +arc: E1_H02E0301 V06N0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R22C105:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 E3_H06W0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R22C106:CIB_EBR +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R22C107:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R22C108:CIB_EBR +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R22C109:CIB_EBR +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R22C110:CIB_EBR +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C111:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R22C112:CIB_EBR +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C113:CIB_EBR +arc: W3_H06W0103 V06N0103 + +.tile CIB_R22C14:CIB_EBR +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 + +.tile CIB_R22C16:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R22C18:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0201 N1_V02S0701 + +.tile CIB_R22C19:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R22C20:CIB_EBR +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 + +.tile CIB_R22C21:CIB_EBR +arc: N1_V02N0501 H02W0501 + +.tile CIB_R22C22:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 S3_V06N0303 + +.tile CIB_R22C23:CIB_EBR +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 + +.tile CIB_R22C24:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 + +.tile CIB_R22C25:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R22C33:CIB_EBR +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0100 N3_V06S0303 + +.tile CIB_R22C34:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C35:CIB_EBR +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 + +.tile CIB_R22C36:CIB_EBR +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0401 N3_V06S0203 + +.tile CIB_R22C37:CIB_EBR +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 + +.tile CIB_R22C38:CIB_EBR +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N1_V01S0000 + +.tile CIB_R22C39:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 + +.tile CIB_R22C40:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C41:CIB_EBR +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R22C42:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 + +.tile CIB_R22C43:CIB_EBR +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06E0303 + +.tile CIB_R22C44:CIB_EBR +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R22C45:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R22C46:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R22C47:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R22C48:CIB_EBR +arc: E1_H02E0001 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R22C49:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R22C50:CIB_EBR +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 + +.tile CIB_R22C51:CIB_EBR +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R22C52:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R22C53:CIB_EBR +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 + +.tile CIB_R22C54:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0401 S3_V06N0203 + +.tile CIB_R22C55:CIB_EBR +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R22C56:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 V06S0003 + +.tile CIB_R22C57:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R22C58:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R22C59:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C60:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C61:CIB_EBR +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R22C62:CIB_EBR +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C63:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0201 V02S0201 + +.tile CIB_R22C64:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C65:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C66:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C67:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R22C68:CIB_EBR +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C69:CIB_EBR +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R22C70:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C71:CIB_EBR +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C72:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C73:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R22C74:CIB_EBR +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C75:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E1_H02W0301 + +.tile CIB_R22C76:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C77:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 + +.tile CIB_R22C78:CIB_EBR +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R22C79:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V01N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C80:CIB_EBR +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V02S0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 V01N0101 + +.tile CIB_R22C81:CIB_EBR +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R22C82:CIB_EBR +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 + +.tile CIB_R22C83:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R22C84:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R22C85:CIB_EBR +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R22C86:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C87:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 + +.tile CIB_R22C88:CIB_EBR +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 + +.tile CIB_R22C89:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R22C90:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0401 E3_H06W0203 + +.tile CIB_R22C91:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E3_H06W0303 + +.tile CIB_R22C92:CIB_EBR +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C93:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 + +.tile CIB_R22C94:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C95:CIB_EBR +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 + +.tile CIB_R22C96:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C97:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C98:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R22C99:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R23C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R25C1:CIB_LR +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R29C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R31C1:CIB_LR +arc: N3_V06N0203 S1_V02N0701 + +.tile CIB_R33C1:CIB_LR +arc: N1_V02N0701 E1_H02W0701 + +.tile CIB_R34C100:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C101:CIB_DSP +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C102:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C103:CIB_DSP +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R34C104:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C105:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R34C106:CIB_DSP +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R34C107:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C108:CIB_DSP +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R34C109:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C110:CIB_DSP +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R34C111:CIB_DSP +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C112:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C113:CIB_DSP +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C114:CIB_DSP +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0401 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R34C115:CIB_DSP +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 + +.tile CIB_R34C116:CIB_DSP +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0201 S3_V06N0103 + +.tile CIB_R34C14:CIB_DSP +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 N1_V02S0501 + +.tile CIB_R34C15:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R34C16:CIB_DSP +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0301 N1_V01S0100 + +.tile CIB_R34C17:CIB_DSP +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 + +.tile CIB_R34C18:CIB_DSP +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0601 + +.tile CIB_R34C19:CIB_DSP +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R34C20:CIB_DSP +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R34C21:CIB_DSP +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C22:CIB_DSP +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R34C23:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 + +.tile CIB_R34C24:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R34C25:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 + +.tile CIB_R34C26:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 E1_H02W0401 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R34C27:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H02E0601 + +.tile CIB_R34C28:CIB_DSP +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R34C29:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R34C30:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 + +.tile CIB_R34C31:CIB_DSP +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0101 H02W0101 + +.tile CIB_R34C32:CIB_DSP +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C33:CIB_DSP +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0103 N3_V06S0103 + +.tile CIB_R34C34:CIB_DSP +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 + +.tile CIB_R34C35:CIB_DSP +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R34C36:CIB_DSP +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R34C37:CIB_DSP +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C38:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R34C39:CIB_DSP +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 + +.tile CIB_R34C40:CIB_DSP +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C41:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R34C42:CIB_DSP +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C43:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R34C44:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N3_V06S0303 + +.tile CIB_R34C45:CIB_DSP +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C46:CIB_DSP +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 + +.tile CIB_R34C47:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C48:CIB_DSP +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C49:CIB_DSP +arc: E1_H02E0601 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R34C50:CIB_DSP +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R34C51:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C52:CIB_DSP +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C53:CIB_DSP +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R34C54:CIB_DSP +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R34C55:CIB_DSP +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R34C56:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R34C57:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 + +.tile CIB_R34C58:CIB_DSP +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 + +.tile CIB_R34C59:CIB_DSP +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R34C60:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 + +.tile CIB_R34C61:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C62:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R34C63:CIB_DSP +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0601 H06E0303 + +.tile CIB_R34C64:CIB_DSP +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R34C65:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0301 V06S0003 + +.tile CIB_R34C66:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R34C67:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C68:CIB_DSP +arc: E1_H02E0001 V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 V01N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C69:CIB_DSP +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C70:CIB_DSP +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R34C71:CIB_DSP +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C72:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 + +.tile CIB_R34C73:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C74:CIB_DSP +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C75:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C76:CIB_DSP +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R34C77:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C78:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C79:CIB_DSP +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R34C80:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R34C81:CIB_DSP +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 V02S0501 + +.tile CIB_R34C82:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C83:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile CIB_R34C84:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02W0701 + +.tile CIB_R34C85:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C86:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R34C87:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R34C88:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 + +.tile CIB_R34C89:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02S0501 + +.tile CIB_R34C90:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 + +.tile CIB_R34C91:CIB_DSP +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R34C92:CIB_DSP +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R34C93:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R34C94:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H01W0000 + +.tile CIB_R34C95:CIB_DSP +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C96:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 + +.tile CIB_R34C97:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C98:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C99:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R35C1:CIB_LR +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 + +.tile CIB_R37C1:CIB_LR +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R3C1:CIB_LR +arc: V01S0100 S3_V06N0303 + +.tile CIB_R41C1:CIB_LR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R46C100:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C101:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R46C102:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R46C103:CIB_EBR +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C104:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C105:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C106:CIB_EBR +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R46C107:CIB_EBR +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06S0203 + +.tile CIB_R46C108:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C109:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R46C110:CIB_EBR +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R46C111:CIB_EBR +arc: N1_V02N0601 V01N0001 + +.tile CIB_R46C112:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S1_V02N0201 + +.tile CIB_R46C113:CIB_EBR +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R46C116:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R46C20:CIB_EBR +arc: N1_V02N0201 N3_V06S0103 + +.tile CIB_R46C21:CIB_EBR +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 + +.tile CIB_R46C22:CIB_EBR +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C23:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R46C24:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 + +.tile CIB_R46C25:CIB_EBR +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R46C26:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R46C27:CIB_EBR +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R46C28:CIB_EBR +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 + +.tile CIB_R46C29:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R46C30:CIB_EBR +arc: N1_V02N0301 H02E0301 + +.tile CIB_R46C31:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 + +.tile CIB_R46C32:CIB_EBR +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 + +.tile CIB_R46C33:CIB_EBR +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H02W0601 + +.tile CIB_R46C34:CIB_EBR +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C35:CIB_EBR +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 V01N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C36:CIB_EBR +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R46C37:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R46C38:CIB_EBR +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0701 N3_V06S0203 + +.tile CIB_R46C39:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R46C40:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C41:CIB_EBR +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 + +.tile CIB_R46C42:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C43:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R46C44:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C45:CIB_EBR +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R46C46:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C47:CIB_EBR +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R46C48:CIB_EBR +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C49:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R46C50:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C51:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C52:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0501 V02N0501 + +.tile CIB_R46C53:CIB_EBR +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R46C54:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 + +.tile CIB_R46C55:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 + +.tile CIB_R46C56:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C57:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 + +.tile CIB_R46C58:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C59:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C60:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 + +.tile CIB_R46C61:CIB_EBR +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R46C62:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C63:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0601 + +.tile CIB_R46C64:CIB_EBR +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R46C65:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C66:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E1_H02W0001 + +.tile CIB_R46C67:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C68:CIB_EBR +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C69:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R46C70:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C71:CIB_EBR +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R46C72:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 + +.tile CIB_R46C73:CIB_EBR +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C74:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C75:CIB_EBR +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R46C76:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W3_H06E0303 + +.tile CIB_R46C77:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02N0601 + +.tile CIB_R46C78:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 + +.tile CIB_R46C79:CIB_EBR +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C80:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C81:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C82:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R46C83:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 + +.tile CIB_R46C84:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C85:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 V02N0601 + +.tile CIB_R46C86:CIB_EBR +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C87:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C88:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0701 W3_H06E0203 + +.tile CIB_R46C89:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R46C90:CIB_EBR +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R46C91:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0003 + +.tile CIB_R46C92:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C93:CIB_EBR +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C94:CIB_EBR +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C95:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C96:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0201 + +.tile CIB_R46C97:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R46C98:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R46C99:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R47C1:CIB_LR +arc: N3_V06N0303 JF5 + +.tile CIB_R4C1:CIB_PLL0 +arc: E3_H06E0103 JQ2 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: JA4 N1_V01S0100 +arc: JB1 V02N0301 +arc: JB4 E1_H02W0301 +arc: JC2 H00L0000 +arc: JC4 V00T0000 +arc: JCLK1 V02N0701 +arc: JD2 V02N0001 +arc: JD3 H00R0000 +arc: JD4 V02N0401 +arc: JLSR0 V00B0100 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: PLLCSOUT_PLLREFCS CLK1_PLLREFCS + +.tile CIB_R58C100:CIB_DSP +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 V01N0001 + +.tile CIB_R58C101:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C107:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 + +.tile CIB_R58C110:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C113:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C116:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R58C1:CIB_LR_S +arc: JA0 H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R58C22:CIB_DSP +arc: N3_V06N0203 E3_H06W0203 + +.tile CIB_R58C23:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C25:CIB_DSP +arc: N3_V06N0203 H06W0203 + +.tile CIB_R58C26:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R58C28:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C29:CIB_DSP +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0701 V06N0203 + +.tile CIB_R58C2:CIB_DSP +arc: W1_H02W0501 N1_V01S0100 + +.tile CIB_R58C30:CIB_DSP +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 + +.tile CIB_R58C31:CIB_DSP +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0601 E3_H06W0303 + +.tile CIB_R58C32:CIB_DSP +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R58C33:CIB_DSP +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 + +.tile CIB_R58C34:CIB_DSP +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R58C35:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R58C36:CIB_DSP +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 V06N0203 + +.tile CIB_R58C37:CIB_DSP +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C38:CIB_DSP +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0103 V06S0103 + +.tile CIB_R58C39:CIB_DSP +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C40:CIB_DSP +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C41:CIB_DSP +arc: E1_H02E0201 S3_V06N0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C42:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0003 V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C43:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C44:CIB_DSP +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H02E0601 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 + +.tile CIB_R58C45:CIB_DSP +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C46:CIB_DSP +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R58C47:CIB_DSP +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C48:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R58C49:CIB_DSP +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C50:CIB_DSP +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R58C51:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C52:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C53:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02E0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C54:CIB_DSP +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C55:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C56:CIB_DSP +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R58C57:CIB_DSP +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R58C58:CIB_DSP +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C59:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R58C60:CIB_DSP +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C61:CIB_DSP +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0303 H06E0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C62:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R58C63:CIB_DSP +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 + +.tile CIB_R58C64:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R58C65:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C66:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C67:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C68:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R58C69:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V01N0001 + +.tile CIB_R58C70:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R58C71:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C72:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C73:CIB_DSP +arc: E1_H01E0001 JF4 +arc: E1_H01E0101 JF7 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 JF6 +arc: JB4 W1_H02E0101 +arc: JCE2 H00R0000 +arc: JCE3 H00L0000 +arc: JD5 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 JF5 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 JF4 +arc: W3_H06W0303 V01N0101 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 + +.tile CIB_R58C74:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 JF0 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R58C75:CIB_DSP +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0000 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02W0401 +arc: W3_H06W0003 E1_H02W0001 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R58C76:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R58C77:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C78:CIB_DSP +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C79:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 E1_H01W0100 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R58C80:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C81:CIB_DSP +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C82:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C83:CIB_DSP +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 E1_H02W0001 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R58C84:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R58C85:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C86:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C87:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C88:CIB_DSP +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 H06E0303 + +.tile CIB_R58C89:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 + +.tile CIB_R58C90:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R58C91:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C92:CIB_DSP +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C93:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C94:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C95:CIB_DSP +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R58C96:CIB_DSP +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 V02N0201 + +.tile CIB_R58C97:CIB_DSP +arc: E1_H02E0301 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R58C98:CIB_DSP +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C99:CIB_DSP +arc: N1_V02N0301 W1_H02E0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 N1_V01S0000 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R5C125:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C101:CIB_EBR +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R70C107:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C110:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C113:CIB_EBR +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R70C116:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C28:CIB_EBR +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R70C29:CIB_EBR +arc: N1_V02N0501 N1_V01S0100 + +.tile CIB_R70C30:CIB_EBR +arc: E1_H02E0001 V06S0003 + +.tile CIB_R70C31:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 + +.tile CIB_R70C32:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 N1_V02S0401 + +.tile CIB_R70C33:CIB_EBR +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R70C34:CIB_EBR +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 + +.tile CIB_R70C35:CIB_EBR +arc: W1_H02W0101 V06S0103 + +.tile CIB_R70C36:CIB_EBR +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 + +.tile CIB_R70C37:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R70C38:CIB_EBR +arc: N1_V02N0101 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0601 + +.tile CIB_R70C39:CIB_EBR +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 N3_V06S0003 + +.tile CIB_R70C40:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R70C41:CIB_EBR +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R70C42:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 + +.tile CIB_R70C43:CIB_EBR +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R70C44:CIB_EBR +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 V01N0101 + +.tile CIB_R70C45:CIB_EBR +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N1_V02S0601 + +.tile CIB_R70C46:CIB_EBR +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 + +.tile CIB_R70C47:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R70C48:CIB_EBR +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N1_V01S0000 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R70C49:CIB_EBR +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0701 N1_V02S0701 + +.tile CIB_R70C50:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R70C51:CIB_EBR +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N1_V01S0000 + +.tile CIB_R70C52:CIB_EBR +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C53:CIB_EBR +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0501 N1_V02S0501 + +.tile CIB_R70C54:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R70C55:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0101 N1_V01S0100 + +.tile CIB_R70C56:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R70C57:CIB_EBR +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V01N0001 + +.tile CIB_R70C58:CIB_EBR +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0301 V02S0301 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C59:CIB_EBR +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 + +.tile CIB_R70C60:CIB_EBR +arc: E1_H02E0001 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 + +.tile CIB_R70C61:CIB_EBR +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R70C62:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R70C63:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 + +.tile CIB_R70C64:CIB_EBR +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C65:CIB_EBR +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0701 S3_V06N0203 + +.tile CIB_R70C66:CIB_EBR +arc: E1_H02E0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R70C67:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 + +.tile CIB_R70C68:CIB_EBR +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0301 N1_V01S0100 + +.tile CIB_R70C69:CIB_EBR +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R70C70:CIB_EBR +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R70C71:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile CIB_R70C72:CIB_EBR +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R70C73:CIB_EBR +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile CIB_R70C74:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S3_V06N0003 + +.tile CIB_R70C75:CIB_EBR +arc: E1_H02E0101 V06S0103 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 + +.tile CIB_R70C76:CIB_EBR +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0201 H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R70C77:CIB_EBR +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06W0203 + +.tile CIB_R70C78:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 + +.tile CIB_R70C79:CIB_EBR +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 + +.tile CIB_R70C80:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R70C81:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 S3_V06N0303 + +.tile CIB_R70C82:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 V01N0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R70C83:CIB_EBR +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0201 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 + +.tile CIB_R70C84:CIB_EBR +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R70C85:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0101 H02W0101 + +.tile CIB_R70C86:CIB_EBR +arc: E3_H06E0203 H01E0001 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0101 V06S0103 + +.tile CIB_R70C87:CIB_EBR +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0601 + +.tile CIB_R70C88:CIB_EBR +arc: W3_H06W0003 V06S0003 + +.tile CIB_R70C89:CIB_EBR +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06E0203 + +.tile CIB_R70C90:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 + +.tile CIB_R70C91:CIB_EBR +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0303 V01N0101 + +.tile CIB_R70C92:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R70C93:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 + +.tile CIB_R70C94:CIB_EBR +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 + +.tile CIB_R7C1:CIB_LR +arc: N1_V02N0101 H06W0103 + +.tile CIB_R82C35:CIB_EBR +arc: E1_H02E0101 V06S0103 + +.tile CIB_R82C36:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H06W0003 + +.tile CIB_R82C37:CIB_EBR +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 + +.tile CIB_R82C38:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 S1_V02N0601 + +.tile CIB_R82C39:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R82C40:CIB_EBR +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 N1_V02S0201 + +.tile CIB_R82C41:CIB_EBR +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 V06N0103 + +.tile CIB_R82C42:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R82C43:CIB_EBR +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R82C47:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R82C48:CIB_EBR +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 + +.tile CIB_R82C49:CIB_EBR +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 + +.tile CIB_R82C50:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0401 + +.tile CIB_R82C51:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 N1_V02S0101 + +.tile CIB_R82C52:CIB_EBR +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 + +.tile CIB_R82C53:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0701 V02S0701 + +.tile CIB_R82C54:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R82C55:CIB_EBR +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 + +.tile CIB_R82C56:CIB_EBR +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R82C57:CIB_EBR +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R82C58:CIB_EBR +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 + +.tile CIB_R82C59:CIB_EBR +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 V01N0001 + +.tile CIB_R82C60:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R82C61:CIB_EBR +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 W3_H06E0003 + +.tile CIB_R82C62:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 + +.tile CIB_R82C63:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V01S0000 + +.tile CIB_R82C64:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0501 V01N0101 + +.tile CIB_R82C65:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R82C66:CIB_EBR +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0301 H06W0003 +arc: W1_H02W0401 E1_H02W0101 + +.tile CIB_R82C67:CIB_EBR +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R82C68:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 + +.tile CIB_R82C69:CIB_EBR +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R82C70:CIB_EBR +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N1_V02S0601 + +.tile CIB_R82C71:CIB_EBR +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0001 N1_V02S0001 + +.tile CIB_R82C72:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 E1_H02W0601 + +.tile CIB_R82C73:CIB_EBR +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0501 N1_V02S0501 + +.tile CIB_R82C74:CIB_EBR +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R82C75:CIB_EBR +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0201 H06W0103 + +.tile CIB_R82C76:CIB_EBR +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N3_V06S0303 + +.tile CIB_R82C77:CIB_EBR +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0001 S1_V02N0501 +arc: W1_H02W0401 V06S0203 + +.tile CIB_R82C78:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R82C79:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 N1_V01S0100 + +.tile CIB_R82C82:CIB_EBR +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 + +.tile CIB_R89C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R94C123:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C46:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C47:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C48:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C49:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C50:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C51:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C52:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C53:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C54:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C55:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C56:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C57:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R94C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C71:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C72:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C73:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C74:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C75:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C76:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C77:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C78:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C79:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R94C80:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C81:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C82:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R9C1:CIB_LR +arc: N3_V06N0303 S1_V02N0601 + +.tile MIB_R0C67:TMID_0 +arc: G_TDCC0CLKI G_JULCPLL0CLKOP + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R22C113:EBR_SPINE_UR2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C12:EBR_SPINE_UL2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C30:EBR_SPINE_UL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C57:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C67:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R22C68:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R22C77:EBR_SPINE_UR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C95:EBR_SPINE_UR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R36C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R47C0:PICL0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R48C0:PICL1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R4C0:PLL0_UL +arc: E1_CLKFB E1_CLKINTFB +arc: E1_REFCLK1 E1_JREFCLK1_0 + +.tile MIB_R57C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.DRIVE 4 + +.tile MIB_R58C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R70C113:EBR_SPINE_LR2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C30:EBR_SPINE_LL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C57:EBR_SPINE_LL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C67:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R70C68:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R70C77:EBR_SPINE_LR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C95:EBR_SPINE_LR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R89C0:PICL0_DQS2 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R90C0:PICL1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOB.PULLMODE UP + +.tile MIB_R95C101:PICB0 +unknown: F0B1 + +.tile MIB_R95C102:PICB1 +unknown: F0B1 + +.tile MIB_R95C103:PICB0 +unknown: F0B1 + +.tile MIB_R95C104:PICB1 +unknown: F0B1 + +.tile MIB_R95C105:PICB0 +unknown: F0B1 + +.tile MIB_R95C106:PICB1 +unknown: F0B1 + +.tile MIB_R95C107:PICB0 +unknown: F0B1 + +.tile MIB_R95C108:PICB1 +unknown: F0B1 + +.tile MIB_R95C110:PICB0 +unknown: F0B1 + +.tile MIB_R95C111:PICB1 +unknown: F0B1 + +.tile MIB_R95C112:PICB0 +unknown: F0B1 + +.tile MIB_R95C113:PICB1 +unknown: F0B1 + +.tile MIB_R95C114:PICB0 +unknown: F0B1 + +.tile MIB_R95C115:PICB1 +unknown: F0B1 + +.tile MIB_R95C116:PICB0 +unknown: F0B1 + +.tile MIB_R95C117:PICB1 +unknown: F0B1 + +.tile MIB_R95C119:PICB0 +unknown: F0B1 + +.tile MIB_R95C120:PICB1 +unknown: F0B1 + +.tile MIB_R95C121:PICB0 +unknown: F0B1 + +.tile MIB_R95C122:PICB1 +unknown: F0B1 + +.tile MIB_R95C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R95C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R95C96:PICB0 +unknown: F0B1 + +.tile MIB_R95C97:PICB1 +unknown: F0B1 + +.tile MIB_R95C98:PICB0 +unknown: F0B1 + +.tile MIB_R95C99:PICB1 +unknown: F0B1 + +.tile R11C38:PLC2 +arc: E1_H01E0001 E3_H06W0003 + +.tile R11C39:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 + +.tile R11C3:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R11C40:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0101 H02W0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0010001110101111 +word: SLICEC.K0.INIT 0010001110101111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000101110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A4 N1_V01N0101 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1100111000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C42:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02S0601 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C43:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 H02W0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +word: SLICED.K0.INIT 1111000001100110 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1100111000000010 +word: SLICEB.K1.INIT 1100111000000010 +word: SLICEC.K1.INIT 1010001110101100 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B4 H02W0101 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M3 H02W0201 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C45:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 N1_V02S0501 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR0 H02E0301 +arc: M0 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C46:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B6 H02W0301 +arc: C0 F4 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 W1_H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +word: SLICEB.K0.INIT 1110101001001000 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K0.INIT 1000101110111000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C47:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H00L0000 +arc: B6 V02N0501 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1110101001100000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1010111000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C48:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 V02N0501 +arc: A0 H02W0701 +arc: A3 N1_V02S0701 +arc: A4 W1_H02E0701 +arc: B0 N1_V02S0301 +arc: B2 H01W0100 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 E1_H02W0601 +arc: C6 W1_H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R11C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q2 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101110000010000 +word: SLICEB.K1.INIT 1100110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C50:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C4 V00T0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R11C52:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V02N0401 +arc: B0 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: F0 F5A_SLICE +arc: M0 H02W0601 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R11C53:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 + +.tile R12C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B3 E1_H01W0100 +arc: B7 E1_H02W0301 +arc: C1 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: D0 V00T0100 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: V00T0100 F1 +arc: V01S0000 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R12C40:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 H01E0001 +arc: V00B0100 V02S0101 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: A3 F7 +arc: A5 V00T0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0401 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1100110000001100 +word: SLICEA.K0.INIT 0000101001101010 +word: SLICEA.K1.INIT 0000110000111100 +word: SLICEB.K0.INIT 0001111100100000 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 0000110001101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 V02S0101 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0301 +arc: B3 V02N0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R12C42:PLC2 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A6 H02E0701 +arc: B0 V02S0101 +arc: B3 W1_H02E0101 +arc: B7 F3 +arc: C0 F6 +arc: C1 F6 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: N3_V06N0303 F6 +arc: S1_V02S0501 F5 +arc: V01S0100 F7 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1010001110101100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0011111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R12C43:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0000 +arc: A1 W1_H02E0701 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: B6 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D6 V02N0401 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1101100011011000 +word: SLICED.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R12C44:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 E1_H01W0100 + +.tile R12C45:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q6 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1010000010101100 +word: SLICEA.K1.INIT 1010111110101100 +word: SLICEB.K0.INIT 1100000011001010 +word: SLICEB.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C46:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: M0 E1_H02W0601 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F0 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111111000110010 +word: SLICEB.K1.INIT 1100110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C47:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 W1_H02E0501 +arc: B0 W1_H02E0301 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C4 H02E0601 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C48:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02E0101 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0100 +arc: A2 H02E0501 +arc: A6 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: V00B0100 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1110110001100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C49:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: B2 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0401 F6 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1101110010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1110110001100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R12C50:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: A0 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 W1_H02E0101 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R12C51:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 E1_H02W0201 +arc: A0 W1_H02E0701 +arc: A2 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 V00B0100 +arc: D4 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C52:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 H01E0001 +arc: V00T0100 V02S0501 +arc: A0 H02E0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: H01W0000 Q4 +arc: LSR0 V00T0100 +arc: M0 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C53:PLC2 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 + +.tile R12C54:PLC2 +arc: N1_V02N0601 W3_H06E0303 + +.tile R13C101:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R13C104:PLC2 +arc: S1_V02S0501 N3_V06S0303 + +.tile R13C107:PLC2 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C17:PLC2 +arc: E3_H06E0303 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile R13C23:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R13C29:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R13C35:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E3_H06E0203 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEB.K0.INIT 1010111110100011 +word: SLICEB.K1.INIT 0101010000000000 +word: SLICEC.K0.INIT 1100000001000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 0000000000000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R13C40:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V01N0101 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A5 H02E0501 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 H02W0301 +arc: B7 F1 +arc: C0 F4 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 Q7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 Q7 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q7 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000000011101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000000010011 +word: SLICEA.K0.INIT 1111111101001111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R13C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: V01S0000 F6 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +word: SLICED.K0.INIT 0101010100010001 +word: SLICEC.K0.INIT 0011001000100010 +word: SLICEA.K0.INIT 0000001100000000 +word: SLICEA.K1.INIT 1010101110101010 +word: SLICED.K1.INIT 0000000001001100 +word: SLICEC.K1.INIT 0101010101010100 +word: SLICEB.K0.INIT 1111110111001100 +word: SLICEB.K1.INIT 0011000100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R13C42:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 V00T0000 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H00R0100 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02N0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: M4 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 F7 +arc: V00B0100 F7 +arc: V00T0000 Q2 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q7 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0000000001110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111100010001000 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110101010101010 +word: SLICEB.K1.INIT 0000000000101010 +word: SLICEB.K0.INIT 1111111110001000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R13C43:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02E0601 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 H01E0101 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B2 E1_H02W0301 +arc: B3 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: N1_V02N0401 F4 +arc: N3_V06N0203 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0000001100000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 0101111101010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R13C44:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V02N0101 +arc: A0 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C45:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 + +.tile R13C46:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q6 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICEA.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C47:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1011000110100000 +word: SLICEA.K1.INIT 1111010111100100 +word: SLICEB.K0.INIT 1000110110001000 +word: SLICEB.K1.INIT 1101110111011000 +word: SLICEC.K0.INIT 1111001000000010 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C48:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100110000001010 +word: SLICEB.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICEC.K1.INIT 1100110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C49:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 H02E0301 +arc: B2 H00R0100 +arc: C0 E1_H01W0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: LSR1 V00T0000 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C50:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 H01E0001 +arc: A0 H02E0701 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V01S0100 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C51:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 + +.tile R13C52:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H06E0303 + +.tile R13C53:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C56:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R13C59:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C62:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C65:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C68:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 + +.tile R13C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C72:PLC2 +arc: S3_V06S0103 H01E0101 + +.tile R13C77:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C83:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C89:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C95:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C96:PLC2 +arc: S1_V02S0701 S3_V06N0203 + +.tile R13C97:PLC2 +arc: S1_V02S0701 S3_V06N0203 + +.tile R14C15:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R14C18:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R14C33:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R14C35:PLC2 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0103 E3_H06W0103 + +.tile R14C38:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R14C39:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0201 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: A1 F5 +arc: B1 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: C1 F4 +arc: C4 V00T0000 +arc: C5 V02S0001 +arc: D1 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R14C40:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0701 +arc: V00B0000 H02E0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B7 H02W0301 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 0000001100000101 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 1100110011011100 +word: SLICEA.K0.INIT 1000100011111111 +word: SLICEA.K1.INIT 0000000010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R14C41:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B5 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 0000110100000000 +word: SLICEB.K0.INIT 0000111100001110 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 1111101011111010 +word: SLICEC.K1.INIT 1100101000001010 +word: SLICED.K0.INIT 0000000011110101 +word: SLICED.K1.INIT 0000000001110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R14C42:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 V02N0601 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 E1_H01W0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0111000001110111 +word: SLICEA.K1.INIT 1111000011100000 +word: SLICED.K0.INIT 1111000000110000 +word: SLICEB.K0.INIT 0000000001110000 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICEC.K1.INIT 1000100010001100 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C43:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V01N0001 +arc: A0 H00L0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 F7 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H01E0001 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 0000110000000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111110010101010 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1011001100110011 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R14C44:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06E0203 + +.tile R14C45:PLC2 +arc: H00R0000 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B7 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R14C46:PLC2 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R14C47:PLC2 +arc: N1_V02N0401 V01N0001 + +.tile R14C48:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R14C50:PLC2 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0601 V01N0001 + +.tile R14C51:PLC2 +arc: S1_V02S0701 H06W0203 + +.tile R14C52:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0601 E1_H01W0000 + +.tile R14C53:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: V00B0100 V02N0301 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 1111001111100010 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R14C54:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C7 H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111100100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICEC.K0.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R14C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 H02W0001 +arc: H00L0100 W1_H02E0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02N0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0101 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: D5 F0 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0100 F5 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111101011001010 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000110100001000 +word: SLICEC.K1.INIT 1010111110101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R14C56:PLC2 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R14C58:PLC2 +arc: S1_V02S0301 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 + +.tile R14C59:PLC2 +arc: V00B0000 S1_V02N0201 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R14C60:PLC2 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: A0 E1_H02W0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C61:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R14C62:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H00L0000 +arc: A2 F7 +arc: A3 F7 +arc: A5 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02W0401 +arc: C7 V00T0100 +arc: D0 V00T0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00T0000 +arc: V00T0000 F0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010110011111111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 1111000011100000 +word: SLICEB.K1.INIT 0000000011100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C63:PLC2 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 H02E0501 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 V01N0001 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEB.K0.INIT 1110111011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R14C64:PLC2 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 + +.tile R14C65:PLC2 +arc: S1_V02S0501 H06W0303 + +.tile R14C66:PLC2 +arc: S3_V06S0303 N3_V06S0303 +arc: B3 H02W0101 +arc: C3 V02N0601 +arc: D3 S1_V02N0001 +arc: F3 F3_SLICE +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0011000000111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R14C67:PLC2 +arc: A0 V02N0501 +arc: A3 F5 +arc: A5 S1_V02N0301 +arc: B0 H02W0301 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C3 E1_H01W0000 +arc: C5 V02N0001 +arc: D0 E1_H02W0001 +arc: D3 F0 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICEA.K0.INIT 0000111000000100 +word: SLICEB.K1.INIT 1111001111100010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C68:PLC2 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 V01N0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 F0 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: V00B0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 0011001000000010 +word: SLICED.K0.INIT 1111101111001000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C69:PLC2 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V01N0101 + +.tile R14C70:PLC2 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 + +.tile R14C81:PLC2 +arc: S1_V02S0101 S3_V06N0103 + +.tile R14C89:PLC2 +arc: E3_H06E0303 S3_V06N0303 + +.tile R14C95:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R14C98:PLC2 +arc: S3_V06S0003 H06E0003 + +.tile R15C100:PLC2 +arc: S1_V02S0601 S3_V06N0303 + +.tile R15C104:PLC2 +arc: S1_V02S0501 N1_V02S0501 + +.tile R15C105:PLC2 +arc: S1_V02S0301 S3_V06N0003 +arc: W3_H06W0003 S3_V06N0003 + +.tile R15C106:PLC2 +arc: S1_V02S0301 S3_V06N0003 + +.tile R15C107:PLC2 +arc: S1_V02S0501 N1_V02S0501 + +.tile R15C23:PLC2 +arc: S3_V06S0103 E3_H06W0103 + +.tile R15C26:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R15C29:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R15C32:PLC2 +arc: S3_V06S0003 H06W0003 + +.tile R15C35:PLC2 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0203 E3_H06W0203 +arc: D0 V02S0001 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: S3_V06S0003 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R15C36:PLC2 +arc: S1_V02S0501 E1_H01W0100 + +.tile R15C37:PLC2 +arc: H00L0000 V02N0001 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 H02W0401 +arc: A0 H00L0000 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 0101110100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C38:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R15C39:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: S3_V06S0303 E1_H01W0100 +arc: A1 N1_V02S0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111110011 +word: SLICEA.K1.INIT 0101010111110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R15C40:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 N1_V01S0100 +arc: B0 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 N1_V02S0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +word: SLICEA.K0.INIT 0000000010110000 +word: SLICEA.K1.INIT 0101000011110000 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 0101000000010000 +word: SLICEC.K0.INIT 0111011100000000 +word: SLICEC.K1.INIT 0000100000001100 +word: SLICED.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 H01E0101 +arc: A0 H02E0501 +arc: A1 H02E0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 H02W0701 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C5 N1_V02S0201 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 N1_V02S0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: S1_V02S0001 F0 +arc: V01S0100 F4 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0101111100000000 +word: SLICEA.K1.INIT 0000110000000100 +word: SLICEB.K0.INIT 0010101000101010 +word: SLICEB.K1.INIT 0000000010001010 +word: SLICEC.K0.INIT 0111011100000000 +word: SLICEC.K1.INIT 0000110100000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R15C42:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q5 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0111001001010000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1010110000001100 +word: SLICED.K0.INIT 1111101011111010 +word: SLICED.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C43:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0501 +arc: A2 H01E0001 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: B0 F1 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C2 H02E0401 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0401 F6 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0000000000001100 +word: SLICEA.K0.INIT 1100111011001100 +word: SLICEC.K0.INIT 0000000001010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R15C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F7 +arc: H01W0100 F5 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110010001000100 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 0000111100001010 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICEC.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R15C45:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 V02S0501 +arc: A2 H01E0001 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 0011011100001000 +word: SLICEB.K0.INIT 0111011100000111 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICED.K1.INIT 0000000000101000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C46:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000001000001010 +word: SLICEA.K0.INIT 0000101011110000 +word: SLICEA.K1.INIT 0010100011001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011101110000000 +word: SLICEC.K0.INIT 0011001000100010 +word: SLICEC.K1.INIT 0000000001100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C47:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B7 H02E0301 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C7 V00T0000 +arc: D1 W1_H02E0001 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N1_V01N0001 F7 +arc: N1_V02N0101 F3 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F1 +word: SLICEB.K0.INIT 0000001000100010 +word: SLICED.K1.INIT 0000001000100010 +word: SLICEA.K1.INIT 0000001000100010 +word: SLICEB.K1.INIT 0000001000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C48:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: A2 E1_H01E0001 +arc: B2 H01W0100 +arc: C2 E1_H02W0401 +arc: D2 E1_H02W0001 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100000011010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R15C49:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 + +.tile R15C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 F7 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0101000101000000 +word: SLICEB.K0.INIT 1110111011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011100000000000 +word: SLICEA.K1.INIT 1011100011111111 +word: SLICEB.K1.INIT 1010100000100000 +word: SLICEC.K0.INIT 1111111000110010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R15C51:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICED.K0.INIT 0000000011011000 +word: SLICEC.K1.INIT 0000000010100011 +word: SLICED.K1.INIT 0000000000010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C52:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: A0 H02E0501 +arc: A2 V02N0701 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R15C53:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 H00L0000 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C54:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0201 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R15C55:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 W1_H02E0301 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C56:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C57:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 F5 +arc: B0 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02E0201 +arc: D3 F0 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 1100100000001000 +word: SLICEA.K0.INIT 0100000001010001 +word: SLICED.K0.INIT 0000000011100000 +word: SLICEB.K0.INIT 0000111100110011 +word: SLICEB.K1.INIT 0000000000010101 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C58:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 V01N0101 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEC.K1.INIT 1111110010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 0000110000001010 +word: SLICED.K1.INIT 1111111000110010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C59:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 W3_H06E0103 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: V00T0000 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 1100111111001010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C60:PLC2 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H02W0601 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D3 H02W0001 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C61:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A4 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: B4 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D4 V00B0000 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000011010001 +word: SLICEA.K0.INIT 0000000011100000 +word: SLICED.K0.INIT 0000000000010101 +word: SLICEA.K1.INIT 0000000100010001 +word: SLICEC.K0.INIT 0000110100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R15C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0100 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101111110001111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101001100000000 +word: SLICED.K0.INIT 0000000011111110 +word: SLICED.K1.INIT 0000000000110010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C63:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 H01E0101 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0601 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 0010001100100000 +word: SLICED.K0.INIT 0000001000000111 +word: SLICEC.K1.INIT 0000000100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 0000110100001000 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C66:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0501 +arc: W1_H02W0301 H01E0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 E1_H02W0101 +arc: B6 F3 +arc: C0 W1_H02E0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: N1_V01N0101 F4 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111100010 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICED.K0.INIT 1111010111100100 +word: SLICEC.K0.INIT 1111000011101110 +word: SLICEC.K1.INIT 0101000001011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R15C67:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 S1_V02N0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F6 +arc: V00T0100 F1 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 0000111000000100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 1101100011111111 +word: SLICED.K0.INIT 0000110100001000 +word: SLICED.K1.INIT 1111110110101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02N0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V00B0100 F7 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R15C69:PLC2 +arc: H01W0100 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: A2 H02W0701 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C70:PLC2 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C71:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 + +.tile R15C74:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R15C77:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R15C80:PLC2 +arc: E1_H02E0501 V02N0501 + +.tile R15C81:PLC2 +arc: E1_H02E0101 V02S0101 + +.tile R15C82:PLC2 +arc: A0 H02W0701 +arc: A2 E1_H02W0701 +arc: A6 W1_H02E0501 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R15C83:PLC2 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R15C84:PLC2 +arc: S1_V02S0101 H01E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 V02N0701 + +.tile R15C88:PLC2 +arc: E3_H06E0203 S3_V06N0203 + +.tile R15C89:PLC2 +arc: E3_H06E0003 S3_V06N0003 + +.tile R15C93:PLC2 +arc: S1_V02S0101 E3_H06W0103 + +.tile R15C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: V01S0100 S3_V06N0303 + +.tile R15C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0301 W3_H06E0003 + +.tile R15C96:PLC2 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 H01E0001 + +.tile R15C97:PLC2 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 + +.tile R15C99:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R16C100:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 H02E0701 +arc: A6 V02N0301 +arc: B0 V02N0301 +arc: B1 H02W0101 +arc: B3 F1 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C3 F6 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D3 F0 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C101:PLC2 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 V02N0701 + +.tile R16C102:PLC2 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: W1_H02W0601 S1_V02N0601 + +.tile R16C103:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C104:PLC2 +arc: S3_V06S0103 W3_H06E0103 + +.tile R16C105:PLC2 +arc: S1_V02S0301 H06W0003 + +.tile R16C106:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 H06E0303 + +.tile R16C107:PLC2 +arc: V00B0000 S1_V02N0001 +arc: A0 V02S0501 +arc: A3 H02W0501 +arc: A4 V00B0000 +arc: B2 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C108:PLC2 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: F0 F0_SLICE +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C33:PLC2 +arc: S3_V06S0303 H06W0303 + +.tile R16C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R16C37:PLC2 +arc: E1_H02E0201 H01E0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B6 V02N0701 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C38:PLC2 +arc: H00R0100 H02E0501 +arc: V00T0000 V02N0401 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR1 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0111001101000000 +word: SLICEB.K1.INIT 0101000011001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C39:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: S3_V06S0203 H06W0203 + +.tile R16C40:PLC2 +arc: E1_H02E0301 V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0303 E1_H02W0501 + +.tile R16C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0401 S1_V02N0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 F5 +arc: A5 V02S0101 +arc: B2 E1_H02W0301 +arc: B5 V02S0701 +arc: C2 E1_H02W0401 +arc: C5 V02S0201 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F2 +arc: W1_H02W0201 F2 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICEB.K0.INIT 0000000000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R16C42:PLC2 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A1 E1_H02W0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0501 +arc: A6 V02S0301 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 W1_H02E0301 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +arc: V01S0100 Q3 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100110000001100 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000101011111010 +word: SLICEC.K0.INIT 0000000011111010 +word: SLICEA.K1.INIT 0001000100110001 +word: SLICEB.K0.INIT 1111001111111111 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R16C43:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0701 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: A0 F5 +arc: A1 V02S0701 +arc: A3 V00B0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B3 V02S0101 +arc: B5 V02S0501 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 Q0 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +word: SLICED.K1.INIT 1010001000100010 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 0111111100000000 +word: SLICED.K0.INIT 0001001100110011 +word: SLICEA.K0.INIT 0010111100101111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1100101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C44:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0000001100000111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0111011100000000 +word: SLICEB.K0.INIT 0001000000000000 +word: SLICEB.K1.INIT 1111111000110010 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R16C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 H02E0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A7 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 0000000010001011 +word: SLICEC.K0.INIT 0010001100100000 +word: SLICEA.K1.INIT 1111111000001110 +word: SLICED.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R16C47:PLC2 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1111001110111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C48:PLC2 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E3_H06W0303 + +.tile R16C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B5 H02W0301 +arc: B7 V00B0100 +arc: C5 V02S0201 +arc: C7 V02N0201 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICEC.K1.INIT 0011000100000001 +word: SLICED.K1.INIT 0000000100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C50:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEC.K1.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R16C51:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111011110010 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C52:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 W3_H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V02N0701 F7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000101100001000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C53:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: B0 H02W0301 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C54:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0501 +arc: A3 V01N0101 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000110100000001 +word: SLICED.K0.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R16C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: A3 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 Q2 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q2 +arc: V00B0100 F7 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEC.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R16C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0101000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R16C57:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B4 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C4 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R16C59:PLC2 +arc: H00L0000 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02S0101 +arc: A4 S1_V02N0301 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F7 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000010101100 +word: SLICED.K1.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 H02W0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V01N0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: D0 V00T0100 +arc: D1 H00R0000 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000111000000010 +word: SLICEA.K1.INIT 1111111111001010 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R16C61:PLC2 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 V02S0401 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000101000001000 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111001010 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1111111001010100 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1111001110111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C62:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A0 V02N0701 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B7 V02N0501 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C63:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D3 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R16C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C65:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V02S0201 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C66:PLC2 +arc: E1_H02E0301 V01N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 F7 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B5 F3 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 0011000100100000 +word: SLICEC.K0.INIT 1111001111100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R16C67:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: A3 V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D4 V01N0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H01E0101 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1101100011011000 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1011100011111111 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 1111111110111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C68:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 S3_V06N0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: A4 H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D4 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0001 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R16C69:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C70:PLC2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 H02W0401 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C71:PLC2 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V01N0001 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C72:PLC2 +arc: W1_H02W0101 V01N0101 + +.tile R16C73:PLC2 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02N0101 + +.tile R16C75:PLC2 +arc: E3_H06E0103 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: V01S0000 S3_V06N0103 + +.tile R16C80:PLC2 +arc: N1_V02N0501 S1_V02N0401 + +.tile R16C81:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C82:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 S1_V02N0601 + +.tile R16C83:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: A3 S1_V02N0501 +arc: A5 V00B0000 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 V02N0301 +arc: B4 V02N0701 +arc: B6 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C84:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0301 S1_V02N0301 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C85:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: S1_V02S0301 W1_H02E0301 + +.tile R16C87:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C88:PLC2 +arc: E1_H02E0201 S1_V02N0201 + +.tile R16C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R16C90:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: S1_V02S0701 H02E0701 + +.tile R16C91:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C92:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06E0203 + +.tile R16C93:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 + +.tile R16C94:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 + +.tile R16C95:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C96:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 E1_H02W0101 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 F5 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0701 +arc: B7 F3 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 F6 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C97:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02E0701 + +.tile R16C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 + +.tile R16C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 + +.tile R17C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D2 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 F0 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: V00B0000 F4 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C101:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 W1_H02E0501 +arc: A2 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B4 V00B0100 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0000 F5 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile R17C103:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 H01E0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 S3_V06N0103 + +.tile R17C104:PLC2 +arc: H00L0000 E1_H02W0201 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A1 H00L0000 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D2 F0 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C105:PLC2 +arc: E1_H02E0701 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0101 E1_H01W0100 +arc: B0 V02S0301 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C106:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0701 V02N0701 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C107:PLC2 +arc: N1_V02N0501 H01E0101 +arc: V00T0000 W1_H02E0001 +arc: A0 S1_V02N0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 H02E0701 +arc: B2 H02E0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C108:PLC2 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 V06N0203 +arc: B2 S1_V02N0101 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 F0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R17C109:PLC2 +arc: W1_H02W0601 S3_V06N0303 + +.tile R17C35:PLC2 +arc: E1_H02E0301 N1_V02S0301 + +.tile R17C36:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: V00T0000 E1_H02W0001 +arc: A5 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B6 N1_V02S0501 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C37:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A6 N1_V01S0100 +arc: B6 V02S0501 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D6 V02S0401 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0401 Q6 +arc: S1_V02S0001 F0 +arc: S1_V02S0601 Q6 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0010001011110000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R17C38:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C39:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R17C3:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R17C40:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 H06E0103 + +.tile R17C41:PLC2 +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0401 + +.tile R17C42:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0701 W3_H06E0203 + +.tile R17C43:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 E1_H01W0100 +arc: B3 H02E0301 +arc: C0 H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111111111111100 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEB.K1.INIT 0000111011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R17C44:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A3 H02W0701 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B5 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C3 V02S0601 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F7 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C45:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A6 E1_H01W0000 +arc: B6 V00T0000 +arc: C6 V02S0201 +arc: D6 H02W0001 +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 0000000011100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C46:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02N0101 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 W1_H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C47:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: A2 H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C48:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R17C49:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: A3 H01E0001 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C50:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A2 W1_H02E0701 +arc: A4 H02E0501 +arc: A6 V02S0101 +arc: B1 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 0000010010101110 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K0.INIT 0101000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C51:PLC2 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 F7 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICED.K0.INIT 1010100000100000 +word: SLICED.K1.INIT 0000000011100010 +word: SLICEC.K0.INIT 1111000011101110 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R17C52:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: B1 H02W0101 +arc: B2 S1_V02N0101 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R17C53:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 0000010010101110 +word: SLICED.K1.INIT 0100111001001110 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: A1 E1_H01E0001 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B7 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0011000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C55:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 V01N0001 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: A6 N1_V02S0301 +arc: B0 H02E0101 +arc: B2 N1_V02S0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D5 F2 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1111101011011000 +word: SLICED.K0.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C56:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 F6 +arc: C4 F6 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 F4 +arc: S1_V02S0401 Q6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000101001001110 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R17C57:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0000 V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C58:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A2 H02W0501 +arc: A5 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B5 V02N0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C5 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C59:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A6 V00T0100 +arc: B2 H00R0000 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R17C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C61:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C62:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H02W0501 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0000000010101100 +word: SLICEB.K1.INIT 0000000000110101 +word: SLICEC.K1.INIT 0000001000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C63:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C64:PLC2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0201 S3_V06N0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C65:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C66:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: A3 S1_V02N0501 +arc: A6 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0010011100100010 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C67:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: B1 Q1 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R17C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: B1 Q1 +arc: C0 H02W0601 +arc: C2 H00L0000 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C69:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F7 +arc: A7 Q7 +arc: C3 E1_H02W0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R17C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 H02W0401 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R17C71:PLC2 +arc: H00R0000 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A3 E1_H02W0501 +arc: A7 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C0 V02N0601 +arc: C5 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R17C72:PLC2 +arc: H00R0000 H02E0601 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q5 +arc: M0 H02W0601 +arc: M2 E1_H02W0601 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 0101010100001100 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001111110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C73:PLC2 +arc: N1_V02N0101 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 + +.tile R17C74:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0103 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C75:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V01N0101 +arc: A5 Q5 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C76:PLC2 +arc: E3_H06E0303 H01E0101 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C78:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0303 E3_H06W0303 + +.tile R17C79:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: H01W0000 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 V02N0401 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: B0 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B6 V00T0000 +arc: C0 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 F6 +arc: C6 H02E0401 +arc: D0 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C80:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0401 F6 +arc: V00B0000 F4 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C81:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 W3_H06E0303 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C82:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 + +.tile R17C83:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 + +.tile R17C84:PLC2 +arc: E1_H02E0601 V01N0001 +arc: A6 N1_V02S0101 +arc: B6 N1_V01S0000 +arc: C6 V02N0201 +arc: D6 E1_H02W0001 +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C85:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A2 S1_V02N0701 +arc: A5 V02N0301 +arc: B0 V02S0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C86:PLC2 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 W3_H06E0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: F0 F0_SLICE +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R17C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 + +.tile R17C88:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 + +.tile R17C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 + +.tile R17C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: B1 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R17C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 W1_H02E0101 +arc: C1 V02S0401 +arc: C3 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N1_V01N0101 F0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C92:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R17C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 W1_H02E0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C94:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 + +.tile R17C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A6 H02W0701 +arc: B1 H02W0101 +arc: B3 V02N0301 +arc: B6 S1_V02N0701 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C6 V00T0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C96:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0100 +arc: A1 H01E0001 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0301 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C97:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S3_V06S0003 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B5 F3 +arc: B6 H02E0101 +arc: C2 F6 +arc: C3 H00R0100 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F2 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F5 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: B0 F3 +arc: B1 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 F4 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00T0100 F1 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R18C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: D0 S1_V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D5 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R18C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 E1_H02W0501 +arc: A3 N1_V02S0501 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 E1_H02W0501 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: D0 N1_V02S0001 +arc: D2 H02W0201 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 F0 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 F3 +arc: H01W0100 F6 +arc: N1_V01N0101 F4 +arc: V00B0100 F5 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C102:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 F1 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F4 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000100000100010 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C103:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 F7 +arc: A2 H00L0100 +arc: A7 H02E0701 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C7 V02S0001 +arc: D1 F2 +arc: D2 H00R0000 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C104:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A4 F7 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0301 +arc: B4 F1 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D4 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C105:PLC2 +arc: H00L0000 E1_H02W0201 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A2 F7 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C106:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 V02N0601 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C107:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R18C108:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R18C109:PLC2 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile R18C110:PLC2 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0103 E1_H02W0201 + +.tile R18C111:PLC2 +arc: W3_H06W0003 S3_V06N0003 + +.tile R18C112:PLC2 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 + +.tile R18C113:PLC2 +arc: W3_H06W0103 S3_V06N0103 + +.tile R18C32:PLC2 +arc: S3_V06S0003 E3_H06W0003 + +.tile R18C35:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H06W0003 + +.tile R18C37:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02S0001 +arc: B4 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: D0 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R18C38:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: A0 H02E0701 +arc: B0 V02S0101 +arc: C0 H02E0601 +arc: D0 V02S0201 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: S3_V06S0003 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0010000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R18C39:PLC2 +arc: E1_H02E0601 V06S0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R18C40:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V06S0203 +arc: S1_V02S0001 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V06S0203 + +.tile R18C41:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0001 Q6 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1011101100001010 +word: SLICEA.K1.INIT 1000101000001010 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 1011000010111010 +word: SLICEC.K1.INIT 1000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C43:PLC2 +arc: E1_H02E0401 S1_V02N0401 + +.tile R18C44:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: A2 H02W0701 +arc: B2 H00R0000 +arc: C2 H02E0401 +arc: D2 S1_V02N0001 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEB.K0.INIT 0000010100010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R18C45:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A5 S1_V02N0301 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D5 V02N0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q4 +arc: F5 F5_SLICE +arc: H01W0000 Q7 +arc: M4 H02W0401 +arc: M7 E1_H01W0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C46:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0601 +arc: V01S0100 S3_V06N0303 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B3 F1 +arc: B4 H01E0101 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 V02S0601 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 W1_H02E0301 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C47:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 V02S0301 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C48:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: A0 H01E0001 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A4 F7 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0010001100100000 +word: SLICEA.K1.INIT 1110111111101100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1111001111100010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000101010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C50:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: A1 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C1 F4 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICED.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C51:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0100010011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C52:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: A3 F5 +arc: A5 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D3 S1_V02N0201 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 W1_H02E0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C53:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B7 S1_V02N0501 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C54:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H01E0001 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 Q4 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C55:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B3 H00R0000 +arc: B7 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 V02S0401 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R18C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 F5 +arc: A5 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 N1_V02S0001 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR1 V00T0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: B1 V00B0000 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V00B0000 Q6 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0111011101000100 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R18C58:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 V00T0100 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R18C59:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 W1_H02E0001 +arc: D3 V01S0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R18C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0701 +arc: B0 F3 +arc: B3 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 S1_V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q6 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C61:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V01N0101 +arc: A5 V02N0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 V02N0101 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0601 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R18C62:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011000011111100 +word: SLICEB.K1.INIT 0011000011111100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 H02W0501 +arc: B0 V02N0101 +arc: B5 H02W0301 +arc: C0 S1_V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V01N0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0010001100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C64:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C5 W1_H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D5 E1_H02W0001 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111111001010 +word: SLICED.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R18C65:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0010111000101110 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0101010000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C66:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 W1_H02E0701 +arc: A5 V00T0100 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 W1_H02E0001 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M1 H00R0000 +arc: M2 E1_H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0100010101000000 +word: SLICEB.K1.INIT 1110111111101010 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C67:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 S1_V02N0701 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A4 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B7 H02W0101 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 E1_H01W0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1101000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R18C68:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V01N0101 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 V02N0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C69:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02E0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q1 +arc: S1_V02S0601 F4 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C70:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 H06W0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H02E0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B3 F1 +arc: C0 H02E0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 N1_V02S0001 +arc: D5 E1_H02W0201 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C71:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0501 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 F3 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B5 F1 +arc: B6 V02S0701 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 Q7 +arc: S1_V02S0701 Q7 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0010011100100010 +word: SLICED.K1.INIT 0101000011111010 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R18C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011101000111010 +word: SLICEB.K0.INIT 0000110000101110 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0100010011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R18C73:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F2 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R18C74:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H01W0100 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C75:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: B0 H01W0100 +arc: B5 S1_V02N0501 +arc: C0 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 W1_H02E0101 +arc: B2 V02S0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C2 H00L0000 +arc: C6 H02W0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 H02E0201 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R18C77:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A5 Q5 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V00B0100 F7 +arc: V01S0000 Q5 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C78:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C79:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C4 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 F7 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C80:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 W1_H02E0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 H02E0101 +arc: B4 F3 +arc: C1 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 F2 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: S1_V02S0601 F4 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C81:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V01N0101 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C82:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H02E0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C84:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C85:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 + +.tile R18C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: A1 H00L0000 +arc: B1 S1_V02N0101 +arc: C1 V02N0401 +arc: D1 E1_H02W0201 +arc: F1 F1_SLICE +arc: S1_V02S0301 F1 +word: SLICEA.K1.INIT 1000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: A6 W1_H02E0701 +arc: B6 V02N0501 +arc: C6 H02W0601 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: V01S0000 F6 +word: SLICED.K0.INIT 1000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C90:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A7 H02E0501 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: S1_V02S0601 F6 +arc: S3_V06S0203 F4 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001101010101 +word: SLICEC.K0.INIT 0011111101011111 +word: SLICEC.K1.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C91:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A3 N1_V02S0501 +arc: A4 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: S1_V02S0501 F5 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1101010100000000 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEC.K0.INIT 1101010100000000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 1000111100000000 +word: SLICEA.K1.INIT 1000000010101010 +word: SLICEC.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A4 S1_V02N0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 H02W0101 +arc: C1 H02E0601 +arc: C2 W1_H02E0601 +arc: C3 F4 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D1 V02S0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: V01S0000 F3 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1011001100000000 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K1.INIT 0000000000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R18C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A2 H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 E1_H02W0401 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A6 H02W0701 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D5 V02S0401 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +word: SLICEB.K0.INIT 0000000000101010 +word: SLICEB.K1.INIT 1111111100101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A6 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B5 S1_V02N0501 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 F0 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: S1_V02S0401 F6 +arc: V01S0000 F3 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000100000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C96:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 V00B0000 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 W1_H02E0301 +arc: B3 H00R0100 +arc: B4 W1_H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 V00B0100 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0401 F6 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 V02S0501 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D0 V02S0201 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 F0 +arc: D5 F2 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100001100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0101 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0011001101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R18C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000110000111111 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 E1_H02W0501 +arc: A2 V02S0701 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0001 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 F2 +arc: D5 N1_V02S0601 +arc: D6 V02S0401 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 F4 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: V00T0100 F3 +arc: V01S0000 F1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R19C102:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C103:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H00L0100 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C104:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 V02N0501 +arc: A5 V02N0101 +arc: A7 H02E0701 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B6 V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R19C105:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H02W0701 +arc: A5 V02N0301 +arc: B3 V02S0101 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: C3 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: D3 H02W0201 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R19C106:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C107:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 H01E0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C108:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C109:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 V01N0101 +arc: A0 H02E0701 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 S1_V02N0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C110:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 S1_V02N0501 +arc: S1_V02S0501 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H01E0001 +arc: B0 H00R0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C111:PLC2 +arc: W1_H02W0101 V01N0101 + +.tile R19C112:PLC2 +arc: W3_H06W0203 N1_V01S0000 + +.tile R19C113:PLC2 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R19C15:PLC2 +arc: V01S0000 S3_V06N0103 + +.tile R19C17:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R19C18:PLC2 +arc: S1_V02S0101 S3_V06N0103 + +.tile R19C21:PLC2 +arc: S1_V02S0201 S3_V06N0103 +arc: V01S0000 S3_V06N0103 + +.tile R19C33:PLC2 +arc: S1_V02S0301 E1_H02W0301 + +.tile R19C34:PLC2 +arc: B5 E1_H02W0101 +arc: D5 V02N0401 +arc: F5 F5_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R19C35:PLC2 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: B1 E1_H02W0301 +arc: D1 E1_H02W0001 +arc: F1 F1_SLICE +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R19C36:PLC2 +arc: H00L0000 H02W0001 +arc: A3 N1_V02S0501 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: S3_V06S0003 F3 +arc: V01S0000 F2 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R19C37:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: C0 H00R0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C7 E1_H01E0101 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 F0 +arc: D5 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: S1_V02S0001 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000000001010101 +word: SLICEA.K0.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R19C38:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 F1 +arc: B4 F1 +arc: C1 V02S0601 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F0 +arc: V01S0000 F6 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R19C39:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0601 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A6 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: LSR0 H02E0301 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1011101100001010 +word: SLICEA.K1.INIT 1000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: LSR0 H02W0301 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C41:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: A0 H02W0701 +arc: A1 H01E0001 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F1 +arc: S1_V02S0001 F0 +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010100000000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICED.K0.INIT 1111010100110000 +word: SLICED.K1.INIT 1101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C42:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0301 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B3 H02E0101 +arc: B5 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R19C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 H00L0000 +arc: A6 E1_H02W0501 +arc: B0 V00B0000 +arc: C0 H02E0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 W1_H02E0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C44:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A1 F5 +arc: A5 Q5 +arc: B1 S1_V02N0301 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: N1_V02N0401 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 1111111111100010 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1111111000001110 +word: SLICEC.K0.INIT 0000110100001000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R19C46:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: A1 W1_H02E0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: A7 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101110001011100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101001101011111 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEC.K1.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R19C47:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q2 +arc: N1_V02N0701 Q7 +arc: S1_V02S0501 Q7 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R19C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: A0 F5 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0011111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R19C49:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A4 F7 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: A0 S1_V02N0501 +arc: A3 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: C1 H00L0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 N1_V01S0000 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: B6 V02N0501 +arc: B7 H01E0101 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 H02E0001 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H01E0001 +arc: A2 F5 +arc: A5 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0301 Q3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0101000001011100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C53:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0101000001011100 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R19C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H00L0100 +arc: A7 H02E0501 +arc: B2 H00R0100 +arc: B5 H02W0101 +arc: B7 V02N0701 +arc: C2 H02E0401 +arc: C5 V00T0100 +arc: C7 V02N0001 +arc: D2 H00R0000 +arc: D5 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0101001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R19C55:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0701 +arc: B0 V01N0001 +arc: B2 H00R0000 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F4 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 0011000000111010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 V06N0203 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C57:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A2 H02W0701 +arc: A3 F7 +arc: A5 E1_H01W0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 W1_H02E0301 +arc: B7 V00B0100 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F4 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000111101000100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C58:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 F7 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 F4 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000001110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C59:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B4 V02N0501 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C2 F6 +arc: C3 V02S0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C60:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: B1 H02E0101 +arc: B3 F1 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C61:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0301 W1_H02E0301 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0701 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V02N0501 +arc: A6 V02N0301 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B3 E1_H02W0301 +arc: B5 F1 +arc: B6 F1 +arc: B7 F1 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0011001100001010 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C64:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C4 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR0 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0000111100100010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0100010001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C65:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 N1_V02S0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: V01S0000 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICEB.K1.INIT 1111111110101100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C66:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A5 H02W0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0101111101010000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C67:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H02W0701 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B5 F3 +arc: C0 V02N0401 +arc: C2 N1_V01N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02S0101 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C2 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0501 Q5 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 0100010001110100 +word: SLICEB.K1.INIT 0111011101000100 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C69:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B6 V01S0000 +arc: C0 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C70:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A4 W1_H02E0701 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B5 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0000110000101110 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C71:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A6 H02E0701 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 H01W0000 +arc: D6 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 H02E0601 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F3 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C72:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F5 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C73:PLC2 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A4 V02N0101 +arc: A6 V02S0101 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N1_V01N0101 F0 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R19C74:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A5 V02S0101 +arc: B0 H02W0101 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1011101100000000 +word: SLICED.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 H01E0001 +arc: H00L0100 V02S0101 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F5 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C76:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 V01N0001 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C77:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 V01N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B4 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R19C78:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B4 F3 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0401 +arc: C4 F6 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C80:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 V02S0501 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R19C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B4 H01E0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C83:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H02W0701 +arc: A1 H02E0501 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C84:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 E1_H01E0001 +arc: A1 F5 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 F2 +arc: D2 H02W0001 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C85:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: C0 H02W0601 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 H02W0701 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F4 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1000110010001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 + +.tile R19C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: B0 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R19C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B7 S1_V02N0501 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000000001001100 +word: SLICEB.K1.INIT 1111111101001100 +word: SLICEC.K0.INIT 0011111100111111 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V02S0401 +arc: C3 S1_V02N0401 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0001000110111011 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A2 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 V02N0701 +arc: C1 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000011100000000 +word: SLICEC.K1.INIT 1111011111110000 +word: SLICED.K0.INIT 0101111101011111 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C92:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V01S0000 +arc: C1 V02N0401 +arc: C3 H02E0601 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 F2 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 0001000100010011 +word: SLICEC.K1.INIT 1111011111110000 +word: SLICEC.K0.INIT 0000011100000000 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEB.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0010001000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 F4 +arc: C7 V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000010001000100 +word: SLICEA.K1.INIT 1010111011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0501 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 V02N0701 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R19C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 V00T0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: V01S0000 F5 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000011110000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C96:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C97:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 V02S0501 +arc: B5 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: D2 F0 +arc: D3 E1_H02W0001 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C99:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 V02S0001 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICEA.K1.INIT 1100111011101110 +word: SLICEA.K0.INIT 0000001000100010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0301 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 W1_H02E0101 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 V00T0100 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: A6 H02E0501 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C102:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C103:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 N1_V02S0101 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: D0 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V02N0301 F3 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C104:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 S1_V02N0701 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 N1_V02S0001 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C106:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A4 F7 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C107:PLC2 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A3 H02W0701 +arc: A5 Q5 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C108:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C109:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C110:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0203 V01N0001 +arc: A1 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 N1_V01S0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 F3 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1100111100000000 +word: SLICEB.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C111:PLC2 +arc: S3_V06S0003 H01E0001 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02N0701 +arc: A5 E1_H01W0000 +arc: B0 V00T0000 +arc: B5 V02N0701 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1011101100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C112:PLC2 +arc: H00R0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 V02N0701 +arc: B0 V01N0001 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C113:PLC2 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile R20C13:PLC2 +arc: E3_H06E0303 S3_V06N0303 + +.tile R20C14:PLC2 +arc: E1_H02E0501 V02N0501 + +.tile R20C15:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 + +.tile R20C16:PLC2 +arc: S1_V02S0301 S3_V06N0003 +arc: V01S0100 S3_V06N0303 +arc: A0 V02N0501 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR1 W1_H02E0501 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C18:PLC2 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0601 E1_H02W0601 +arc: B0 V00B0000 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H00L0000 F0 +arc: LSR0 E1_H02W0501 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C19:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: B0 V02N0101 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: E1_H02E0601 Q6 +arc: F0 F5A_SLICE +arc: LSR0 H02W0501 +arc: M0 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C20:PLC2 +arc: E1_H02E0501 V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: B0 E1_H01W0100 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: LSR1 V00T0100 +arc: M0 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C21:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C22:PLC2 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V02N0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: F0 F5A_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: LSR0 W1_H02E0501 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V00T0100 Q3 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C25:PLC2 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 + +.tile R20C33:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R20C34:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0201 H02W0201 +arc: V00T0000 V02N0601 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A7 H02W0701 +arc: B1 H00R0100 +arc: B3 H02W0101 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C5 H02W0601 +arc: C7 V00T0000 +arc: D0 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R20C35:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 E1_H02W0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A7 H02W0701 +arc: B2 F1 +arc: B3 H00R0100 +arc: B5 E1_H02W0301 +arc: B7 V00B0100 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0001 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +arc: V01S0100 F7 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEC.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R20C36:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02W0401 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: B4 F3 +arc: B6 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F1 +arc: S3_V06S0303 F6 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000110000001100 +word: SLICEA.K1.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R20C37:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A3 V02N0701 +arc: A4 F5 +arc: B3 V02N0101 +arc: B5 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D4 H00R0100 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0201 F0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0000 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 0010001000100010 +word: SLICEC.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R20C38:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0401 +arc: C4 H01E0001 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K1.INIT 0100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C39:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: B4 V02N0501 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 F0 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R20C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1101010111000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R20C41:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0203 V01N0001 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 H02E0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C42:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02E0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 S1_V02N0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICED.K0.INIT 1011101100001010 +word: SLICED.K1.INIT 1011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C43:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0101 V06S0103 +arc: A0 F7 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D4 V02N0601 +arc: D7 H02E0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C44:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V06N0003 +arc: A0 V01N0101 +arc: A2 V02S0501 +arc: A3 E1_H01E0001 +arc: B1 Q1 +arc: B3 V02N0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: A0 F7 +arc: A2 V02S0501 +arc: A4 V02N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 F6 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 0101000101000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000111000000010 +word: SLICEA.K0.INIT 1111001111100010 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R20C46:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V01N0001 +arc: A0 H02W0501 +arc: A3 V02N0701 +arc: A7 E1_H01W0000 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D7 S1_V02N0601 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R20C47:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: M0 V00B0000 +arc: M1 H02E0001 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F2 +arc: V00B0100 Q5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 S1_V02N0701 +arc: A1 V01N0101 +arc: A2 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 N1_V02S0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A3 H02W0501 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: B1 V00B0000 +arc: B4 V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q7 +arc: V00B0000 F6 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C50:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F7 +arc: A3 S1_V02N0701 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 H01W0100 +arc: B3 V01N0001 +arc: B5 V02S0501 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C5 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 V01S0100 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010000010001000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C51:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 N1_V02S0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011000000111010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R20C52:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A5 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B6 S1_V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F6 +arc: S1_V02S0401 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R20C53:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06S0203 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H00R0000 +arc: B1 V00B0000 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B7 V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R20C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0701 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000000001110111 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H02E0501 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C1 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000111101000100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C57:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0501 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R20C58:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A4 F7 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 H02E0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 F6 +arc: C5 F6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 F7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 0001000100110011 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R20C59:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: B0 N1_V02S0101 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: C0 N1_V02S0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C60:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 V01N0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 V02N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 H02W0701 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: C0 F4 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C62:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 F7 +arc: A7 H00R0000 +arc: B1 H01W0100 +arc: B2 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F2 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R20C63:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0501 +arc: A3 V00T0000 +arc: A5 S1_V02N0301 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B5 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F7 +arc: V00T0000 Q0 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R20C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 E1_H02W0601 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 F1 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q7 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 0101010000000100 +word: SLICED.K1.INIT 1111111001010100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000000010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: A3 H02W0501 +arc: A4 W1_H02E0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: V00T0100 F3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M1 H02E0001 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000000001110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEC.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C67:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0100110001001100 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 H02W0201 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A3 S1_V02N0701 +arc: A5 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEB.K0.INIT 1011111110001100 +word: SLICEB.K1.INIT 1010111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C69:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B1 V00T0000 +arc: B4 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: S3_V06S0303 F6 +arc: V00B0000 F6 +arc: V00B0100 F5 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R20C70:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B5 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R20C71:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 H01E0001 +arc: A4 W1_H02E0501 +arc: A7 H02W0501 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B7 V02N0701 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 W1_H02E0401 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 Q3 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R20C72:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A7 H02W0701 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: V00B0100 F7 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R20C73:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A4 V00T0000 +arc: B1 V00B0000 +arc: B4 H02E0101 +arc: C0 F4 +arc: C1 V02N0401 +arc: C4 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 V01N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: C0 H00R0100 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V06S0103 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 F7 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B1 V00B0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 F0 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F1 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C76:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: E1_H02E0001 Q2 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 Q5 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: S1_V02S0401 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C78:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A6 V02S0101 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 F7 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICED.K1.INIT 1111000000110000 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 V02S0501 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 F1 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R20C80:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0601 F6 +arc: V00B0000 F4 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C81:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F7 +arc: A2 V01N0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: V01S0000 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B6 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 Q6 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C84:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 E1_H01W0000 + +.tile R20C85:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C86:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D4 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V02S0001 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C88:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0101000011110000 +word: SLICEA.K0.INIT 0000000001110000 +word: SLICEA.K1.INIT 1111111101110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C89:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0001000001010000 +word: SLICEA.K1.INIT 1011101011111010 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICEB.K0.INIT 0001000001010000 +word: SLICEB.K1.INIT 1011101011111010 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R20C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 N1_V02S0701 +arc: A2 V00T0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0101 +arc: B4 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 F0 +arc: D4 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000001010111 +word: SLICEB.K0.INIT 0101011100000000 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0011011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C91:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A1 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 0101111100000000 +word: SLICEB.K1.INIT 0001101100011011 +word: SLICED.K1.INIT 1000000011001100 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEC.K0.INIT 0100010001001100 +word: SLICEB.K0.INIT 0011001111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R20C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H00R0000 +arc: A3 F7 +arc: A4 V02S0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 H02W0701 +arc: B1 E1_H02W0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 W1_H02E0401 +arc: C3 F6 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0001 +arc: D5 N1_V02S0601 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C93:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 V00B0000 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C1 V02S0601 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F2 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000110000 +word: SLICED.K1.INIT 1101000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 V01N0101 +arc: C7 F6 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F4 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1010010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 F7 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02S0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 F2 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100001100000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000010010000100 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R20C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 F4 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R20C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A0 F5 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: A3 V00B0000 +arc: A4 F7 +arc: A5 V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R20C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H02W0301 +arc: A1 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 H02E0401 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: S1_V02S0201 F0 +arc: V00B0100 F7 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 W1_H02E0701 +arc: A7 N1_V02S0101 +arc: B1 V00T0000 +arc: B3 H01W0100 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C1 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D1 V00T0100 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02S0501 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0101 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: N1_V01N0001 F7 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 V00B0100 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 N1_V02S0701 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C1 H02E0401 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0000001111001111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100001100000000 +word: SLICEA.K0.INIT 0011001111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R21C103:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: V01S0100 F3 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C104:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A2 F7 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C105:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 H02E0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 F7 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B3 F1 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C7 H02W0601 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 F0 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C106:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A6 N1_V02S0101 +arc: B0 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0701 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: C0 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C107:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H01E0001 +arc: A2 H02W0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D1 F2 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C108:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V01N0001 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C109:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R21C110:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 H02W0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H06W0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A7 N1_V01S0100 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 F0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R21C111:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R21C112:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C113:PLC2 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile R21C114:PLC2 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 S3_V06N0103 + +.tile R21C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: A0 V02N0701 +arc: B0 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011101000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C15:PLC2 +arc: H00L0100 E1_H02W0301 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: A0 H00L0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1100110001011010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R21C16:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0101 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1011111000010100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1000100010111000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C17:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A7 N1_V01N0101 +arc: B0 H02E0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: S3_V06S0003 Q3 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C18:PLC2 +arc: H00L0000 H02E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A4 N1_V01S0100 +arc: A6 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 W1_H02E0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1000100011011000 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1000100011011000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C19:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A4 N1_V01S0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V01S0000 +arc: C0 F4 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C20:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010000010101100 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICEB.K0.INIT 1010000011100100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C21:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C22:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C23:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H02W0201 +arc: M4 H02E0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0201 Q2 +arc: W1_H02W0101 Q3 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K0.INIT 1111010000000100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C24:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0000 H02W0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00R0000 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 Q7 +arc: B0 E1_H01W0100 +arc: B2 H02E0301 +arc: C0 V02N0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C25:PLC2 +arc: H00L0100 W1_H02E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H02E0501 +arc: A4 S1_V02N0101 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 F0 +arc: LSR0 V00B0100 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1101000111100010 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C26:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0701 S1_V02N0701 + +.tile R21C29:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R21C32:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: S3_V06S0103 N3_V06S0003 + +.tile R21C33:PLC2 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0701 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 H02W0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A6 N1_V02S0301 +arc: B0 F3 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C34:PLC2 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F7 +arc: A4 V00T0000 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1000100011111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A3 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: C0 V02N0601 +arc: C2 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D4 H01W0000 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R21C36:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 Q1 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000001010000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C37:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B3 S1_V02N0301 +arc: B5 H00L0000 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 F4 +arc: C2 H00R0100 +arc: C3 V02S0601 +arc: C4 N1_V02S0001 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R21C38:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 F2 +arc: V01S0100 F1 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000010000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R21C39:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A7 V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R21C40:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H00L0100 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A6 F5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1100111000001010 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02S0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q4 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1000100011111000 +word: SLICEC.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C42:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 E1_H01W0000 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 V02S0701 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C43:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00R0000 +arc: A4 W1_H02E0701 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 F6 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H01W0000 +arc: D5 N1_V02S0601 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C44:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0701 +arc: A1 F5 +arc: A2 H02E0701 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICED.K0.INIT 0000111101110111 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C45:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 H01E0001 +arc: A5 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1110010011101110 +word: SLICEA.K1.INIT 1011101111110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C46:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: B1 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0401 F4 +arc: S1_V02S0401 F6 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06N0303 +arc: A0 H02E0501 +arc: A1 E1_H02W0501 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B3 F1 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D3 H02E0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M1 W1_H02E0001 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0401 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0501 +arc: A1 H01E0001 +arc: A5 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C2 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 Q7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0101001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C49:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 V02N0501 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 Q5 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICEA.K1.INIT 1011100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C50:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C51:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: A3 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: V01S0100 F1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001100010011 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R21C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: S1_V02S0001 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000101010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R21C53:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A7 V00T0100 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0111011101000100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R21C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEA.K0.INIT 1111001110101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 V02S0601 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0601 F6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C56:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 S1_V02N0501 +arc: A3 V00T0000 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: S1_V02S0201 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1110001011111111 +word: SLICEA.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C57:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A6 F7 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 1111111001010100 +word: SLICED.K0.INIT 0000000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C58:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A6 V00T0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 H02E0601 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q3 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 F5 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C60:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: S3_V06S0203 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0010001001110010 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: B0 H02E0301 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: C0 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 Q4 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R21C62:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B7 N1_V02S0701 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V01S0100 Q1 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C63:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H01E0001 +arc: A5 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V02N0101 F1 +arc: S1_V02S0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110001011100010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C64:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H00R0100 Q5 +arc: H01W0100 F6 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1011100010111000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101100011011000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A5 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0301 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 V02S0601 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 H00R0100 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B6 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0100 Q5 +arc: H01W0100 Q3 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 0001010110111111 +word: SLICED.K0.INIT 0001001100010011 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C68:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: W1_H02W0401 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1110001011111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R21C69:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEA.K1.INIT 1101110111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0101 +arc: B3 V02S0101 +arc: B7 W1_H02E0301 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0501 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C71:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A6 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: C0 H00L0000 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F5 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C72:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 V02S0101 +arc: A7 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0011111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C73:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A5 H02E0501 +arc: B0 V02N0301 +arc: B5 H00L0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R21C74:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: C0 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C75:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A3 H02W0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B7 N1_V01S0000 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0401 +arc: C7 F4 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 S1_V02N0401 +arc: D7 H01W0000 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0101 F1 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1010000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C76:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0001 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 N1_V01S0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: C0 W1_H02E0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C77:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 F4 +arc: C3 F4 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 N1_V02S0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B5 H02W0101 +arc: C0 H00L0000 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R21C79:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B5 V02N0701 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C3 F6 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H02W0701 +arc: A1 H00R0000 +arc: A3 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C1 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C81:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V02S0701 +arc: A5 E1_H02W0701 +arc: A6 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C82:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: A0 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 W1_H02E0301 +arc: B4 V02S0501 +arc: B6 H02W0301 +arc: C1 H02E0401 +arc: C2 F6 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D6 V02S0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R21C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 H02E0701 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B6 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 H01E0101 +arc: D4 H02W0201 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 F5 +arc: A5 H02W0701 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B5 V02S0701 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V02N0001 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEB.K0.INIT 1100111100000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001010000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R21C85:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 V06S0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A6 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C6 E1_H02W0401 +arc: D1 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M0 H02E0601 +arc: S1_V02S0201 F0 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C86:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 N1_V02S0001 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H02W0501 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0501 +arc: B5 S1_V02N0701 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V00B0100 F7 +arc: V00T0100 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 V00T0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F4 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101010100000000 +word: SLICEB.K1.INIT 0000000000000011 +word: SLICED.K1.INIT 1000000011001100 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R21C89:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 V02N0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A7 W1_H02E0701 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICEB.K0.INIT 0101111100111111 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICED.K0.INIT 0011111100111111 +word: SLICED.K1.INIT 0001110100011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R21C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A5 V02N0301 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0001010100000000 +word: SLICEB.K1.INIT 1011111110101010 +word: SLICEC.K0.INIT 0011111100111111 +word: SLICEC.K1.INIT 0100011101000111 +word: SLICED.K0.INIT 0000000001001100 +word: SLICED.K1.INIT 1111111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R21C91:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V02N0301 +arc: A6 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000001100010011 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000110000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R21C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D2 F0 +arc: D3 H01E0101 +arc: D4 N1_V02S0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001010000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R21C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H01W0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1011101100001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C1 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 F7 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A5 H02E0701 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C4 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: N3_V06N0303 F5 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C96:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A6 W1_H02E0501 +arc: A7 N1_V01S0100 +arc: B0 F1 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 V02S0601 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: D0 E1_H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F0 +arc: N3_V06N0103 F1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R21C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C1 N1_V01N0001 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C7 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 V02S0201 +arc: D1 N1_V02S0001 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B4 H02W0301 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: C0 E1_H02W0601 +arc: C1 H00R0100 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F4 +arc: V00T0000 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C101:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R23C102:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 H02E0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 N1_V02S0701 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0701 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V00B0100 +arc: C2 W1_H02E0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 F6 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +arc: S1_V02S0501 F5 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C103:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A2 H00L0100 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 S1_V02N0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C2 V02S0601 +arc: C5 V01N0101 +arc: C6 N1_V02S0201 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: N1_V01N0001 F6 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C104:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: C5 H02E0401 +arc: D0 V00T0100 +arc: D5 V02S0601 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 F5 +arc: A5 S1_V02N0301 +arc: A6 V02S0101 +arc: A7 E1_H02W0701 +arc: B0 H02E0301 +arc: B3 H00R0100 +arc: B4 F3 +arc: B5 V02S0501 +arc: B7 N1_V02S0501 +arc: C0 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C106:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0501 +arc: A1 F5 +arc: A3 H02E0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B1 F3 +arc: B3 H02E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 W1_H02E0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D3 N1_V01S0000 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0101 F1 +arc: S1_V02S0001 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C107:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0101 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V02N0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C108:PLC2 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1000001011000011 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R23C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H01E0001 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C110:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C111:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A3 N1_V02S0501 +arc: B0 V00B0000 +arc: C0 S1_V02N0401 +arc: C3 H02W0601 +arc: D0 E1_H02W0201 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: M0 V00T0000 +arc: V01S0000 F0 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C112:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F6 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C113:PLC2 +arc: H00L0000 H02E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C114:PLC2 +arc: N1_V02N0401 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C13:PLC2 +arc: S1_V02S0501 E1_H02W0501 + +.tile R23C14:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A4 E1_H02W0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C15:PLC2 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A2 V02N0501 +arc: A4 H02W0701 +arc: B0 V00B0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: C0 H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C16:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0501 Q7 +arc: V01S0000 F4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C17:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 V02N0601 +arc: A0 V01N0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: B4 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: LSR1 H02W0501 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 F0 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111011000000110 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C18:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 N1_V02S0501 +arc: A6 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1011111000010100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C19:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A6 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B4 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C20:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 H02E0501 +arc: A2 V00T0000 +arc: A4 H02W0701 +arc: B0 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H01E0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C21:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A2 V00T0000 +arc: A4 V00T0000 +arc: A6 V02N0101 +arc: B0 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: V01S0000 F6 +arc: V01S0100 Q5 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C22:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q3 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C23:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B4 H00L0000 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K0.INIT 1111010000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C24:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 E1_H01E0001 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B4 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100111000000010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C25:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: V01S0100 F4 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100110001011010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C26:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 H01E0101 +arc: A0 H01E0001 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C31:PLC2 +arc: S3_V06S0003 E3_H06W0003 + +.tile R23C32:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 + +.tile R23C33:PLC2 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 E1_H02W0701 +arc: A0 F5 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: C0 N1_V01S0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 N1_V02S0201 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C34:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 F4 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1011001110100000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C35:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B5 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C36:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A2 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C5 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 N1_V02S0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1010000010100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R23C37:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A4 F5 +arc: A6 H00L0000 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 H00L0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C38:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A6 F5 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: B1 F3 +arc: B2 H00L0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 N1_V02S0201 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110001010000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100000011101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C39:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A0 F5 +arc: A1 F7 +arc: A2 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000100011111000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K0.INIT 1101010111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C3:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R23C40:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A0 F7 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C41:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: B5 H02E0101 +arc: B6 N1_V02S0501 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D6 W1_H02E0201 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C42:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06S0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 V02S0501 +arc: A1 H01E0001 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 N1_V02S0601 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: W1_H02W0101 F3 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C43:PLC2 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 F5 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: M0 H02W0601 +arc: M1 H02W0001 +arc: M2 H02W0601 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0601 F4 +arc: V00B0100 Q7 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C44:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A3 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B4 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICED.K0.INIT 0000011111110111 +word: SLICED.K1.INIT 0101001101011111 +word: SLICEA.K1.INIT 1101111110001010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C45:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEC.K0.INIT 1010100000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICEB.K1.INIT 0101001101011111 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R23C46:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000001100110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R23C47:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H02W0101 +arc: B4 V02N0501 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: N3_V06N0303 F6 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C48:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 F7 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B1 E1_H01W0100 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H01E0001 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B3 F1 +arc: B5 H00R0000 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 E1_H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: N3_V06N0203 F7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: A0 S1_V02N0501 +arc: A1 H02E0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 V02N0301 +arc: B4 F1 +arc: B5 F1 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A0 F7 +arc: A1 H00L0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C52:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B2 H02W0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C53:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02W0701 +arc: A3 F7 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F7 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0100 Q7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0001010110111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H01E0001 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 V00B0000 +arc: B2 V02N0101 +arc: B3 N1_V02S0101 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: C0 E1_H01W0000 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F6 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0011001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C55:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: A1 H02W0501 +arc: A2 F7 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 N1_V02S0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H01E0101 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1000100010100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A3 H02W0701 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: V00T0100 Q1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0101010000000100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B7 V00B0100 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C58:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A2 E1_H01E0001 +arc: A5 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 N1_V01S0100 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R23C59:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R23C60:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B0 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: B0 F3 +arc: B2 S1_V02N0301 +arc: B3 V02S0301 +arc: C0 H02E0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +word: SLICEB.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1101111111010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M4 E1_H02W0401 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0601 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C63:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 S1_V02N0501 +arc: A3 V02S0701 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B7 N1_V02S0701 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D7 H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C64:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A5 N1_V02S0101 +arc: A6 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F4 +arc: N3_V06N0103 F1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C65:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0301 +arc: C0 V02S0401 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q7 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001101101011111 +word: SLICEA.K0.INIT 0000110100001000 +word: SLICEA.K1.INIT 1110111111101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C66:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C67:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H00L0000 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B6 F1 +arc: B7 V02N0701 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M5 E1_H02W0001 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 F6 +arc: V00B0100 Q5 +arc: W1_H02W0101 F3 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R23C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 N1_V02S0101 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B5 H02E0301 +arc: B6 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 F4 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F2 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000011111110111 +word: SLICEA.K1.INIT 1010111111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C69:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: N1_V02N0501 F7 +arc: W1_H02W0001 F0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R23C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: B3 V01N0001 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0100 Q7 +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A7 E1_H02W0501 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C5 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: V01S0000 F6 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000010010101110 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C72:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A5 H02E0501 +arc: B3 V02N0101 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 H02E0601 +arc: N1_V01N0001 F5 +arc: N1_V02N0701 F7 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C73:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 S1_V02N0101 +arc: A7 H02E0501 +arc: B2 E1_H02W0301 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C2 N1_V01N0001 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D2 V00T0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N3_V06N0303 F5 +arc: V01S0000 F2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C74:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B1 H02W0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 F4 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V01N0101 F0 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001000100110011 +word: SLICEA.K0.INIT 0101000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R23C75:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 F5 +arc: A4 S1_V02N0301 +arc: A5 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C1 H00R0100 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 H02E0401 +arc: D1 H01E0101 +arc: D4 N1_V02S0401 +arc: D5 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: S3_V06S0003 F0 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C76:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 V00B0100 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C77:PLC2 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H02W0501 +arc: A7 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C78:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: B0 E1_H02W0301 +arc: B1 V02S0301 +arc: B2 N1_V02S0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R23C79:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C80:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C81:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A4 V02N0101 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K0.INIT 1100000011110000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R23C82:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1111000001010000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B4 V01S0000 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V02S0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C84:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A6 F5 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 F4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: A1 V02S0501 +arc: A4 H02W0501 +arc: A5 V02N0301 +arc: A6 F5 +arc: B1 H00R0100 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: B6 E1_H02W0101 +arc: C1 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: D1 W1_H02E0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 F0 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 H02W0601 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 F1 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C7 V01N0101 +arc: D0 E1_H02W0001 +arc: D1 F0 +arc: D2 H02W0201 +arc: D4 F2 +arc: D5 V01N0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C87:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 F6 +arc: C4 H02W0601 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R23C88:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 H02W0501 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 V02S0401 +arc: C1 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0501 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0101010100110011 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICED.K0.INIT 0001000001010000 +word: SLICED.K1.INIT 1101110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: S1_V02S0501 F7 +arc: V01S0000 F0 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02W0501 +arc: A2 N1_V02S0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: B0 V00B0000 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: C2 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1100010001000100 +word: SLICEA.K0.INIT 0000000000100010 +word: SLICEC.K1.INIT 0000000101010101 +word: SLICEB.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R23C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V02N0301 +arc: B2 H02W0301 +arc: B4 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 V00T0100 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D4 H00L0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K0.INIT 1000111100000000 +word: SLICED.K0.INIT 0000000000001100 +word: SLICEB.K0.INIT 0000000001010111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R23C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0000 +arc: A5 F7 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 F3 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C7 W1_H02E0401 +arc: D0 N1_V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 H02W0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C7 H01E0001 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F0 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C94:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A4 E1_H02W0501 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 E1_H02W0701 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02S0401 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R23C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 E1_H02W0301 +arc: B6 F1 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 H02W0701 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: D0 V02S0001 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R23C97:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 F7 +arc: A2 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: S3_V06S0003 F3 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0701 +arc: A3 E1_H01E0001 +arc: A4 W1_H02E0701 +arc: A5 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: N1_V02N0501 F5 +arc: V01S0000 F0 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: B0 W1_H02E0301 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 F4 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0501 +arc: B0 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 V02N0701 +arc: C0 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0101 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 F5 +arc: B1 V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 F4 +arc: D1 H01E0101 +arc: D3 H02W0001 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: M2 V00B0100 +arc: N1_V02N0601 F6 +arc: S3_V06S0203 F7 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C103:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 H00R0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1001000010010000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R24C104:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 S1_V02N0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 S1_V02N0401 +arc: D5 V02S0401 +arc: D6 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R24C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V01S0100 +arc: A5 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 H01E0101 +arc: B5 W1_H02E0101 +arc: B7 V00B0000 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 H00R0000 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 F5 +arc: B0 H00R0100 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 F3 +arc: C0 H00L0100 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 F4 +arc: D0 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C107:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 V02N0501 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 V00T0000 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: D1 W1_H02E0001 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: S1_V02S0201 F0 +arc: V00B0100 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C108:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: S1_V02S0201 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R24C109:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: A5 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 F7 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C110:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 E1_H02W0501 +arc: A2 V02S0701 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C111:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C112:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A1 V02S0501 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1011101100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C113:PLC2 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 V01N0101 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1111000001010000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C114:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V01N0101 +arc: B0 V02N0101 +arc: B3 E1_H01W0100 +arc: C0 H00L0000 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C115:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C117:PLC2 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R24C13:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: M0 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C14:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C15:PLC2 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C16:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 Q5 +arc: B0 H02W0301 +arc: B1 H01W0100 +arc: B2 H02W0101 +arc: B4 E1_H02W0301 +arc: C0 V02N0601 +arc: C2 V02N0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: S1_V02S0301 Q1 +arc: V00T0000 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C17:PLC2 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V06S0003 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C18:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: C0 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C19:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C20:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B6 E1_H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0701 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C21:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 H01E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A6 W1_H02E0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C22:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 V02N0301 +arc: A6 E1_H02W0701 +arc: B0 V01N0001 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: C0 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H02E0001 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q1 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C23:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A6 V02N0301 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 Q0 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C24:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A2 V02S0501 +arc: B2 V02N0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: LSR1 V00T0000 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C25:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: B6 H01E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q7 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C26:PLC2 +arc: N1_V02N0301 H02E0301 + +.tile R24C31:PLC2 +arc: S3_V06S0103 E3_H06W0103 + +.tile R24C32:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V02S0301 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 E1_H01W0000 + +.tile R24C33:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: A0 N1_V02S0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111010001000100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010000011101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C34:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: A0 E1_H01E0001 +arc: A1 F7 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: S1_V02S0301 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C35:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 S1_V02N0501 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 F7 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C37:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 H01E0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 H00L0100 +arc: A5 H02E0501 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C38:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 S1_V02N0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 F4 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1010000011101100 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111010001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C39:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 H01E0001 +arc: C0 V02S0401 +arc: C2 S1_V02N0401 +arc: C5 V00T0000 +arc: D0 V02S0201 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R24C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 V01N0101 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A7 N1_V01S0100 +arc: B0 F1 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 F6 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D6 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: S1_V02S0601 F6 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C41:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 V02S0301 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B3 E1_H02W0101 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 V02S0601 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V01S0000 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: C6 F4 +arc: C7 H01E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000010000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C43:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 F3 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F4 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C44:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A3 H00L0100 +arc: B3 V02N0101 +arc: C3 H02W0401 +arc: D3 V02S0201 +arc: F3 F3_SLICE +arc: N1_V02N0301 F3 +word: SLICEB.K1.INIT 0101001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C45:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0601 F6 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C46:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B6 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D4 F0 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +word: SLICEC.K0.INIT 1000110010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C47:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: B2 V02S0101 +arc: C1 H02W0601 +arc: C2 H00R0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R24C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V06N0203 +arc: A1 H00R0000 +arc: A4 V02N0101 +arc: A5 H02W0501 +arc: A7 E1_H01W0000 +arc: B2 V02S0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C1 V02N0401 +arc: C3 W1_H02E0401 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: A7 V00T0100 +arc: B0 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C3 H02E0601 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D3 H02E0001 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: N1_V01N0101 F0 +arc: N1_V02N0701 F7 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F6 +arc: S1_V02S0201 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1110110001001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1010000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C51:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 W1_H02E0501 +arc: A1 H01E0001 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 E1_H02W0101 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R24C52:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 S1_V02N0701 +arc: B6 V02S0501 +arc: C0 F6 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C53:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 E1_H02W0101 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 W1_H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C54:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C55:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C56:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F1 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 0011010100111111 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000011100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C57:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H01E0001 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M0 H02E0601 +arc: M1 W1_H02E0001 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F5 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R24C58:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02E0701 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0103 F2 +arc: S1_V02S0201 Q2 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V00T0000 +arc: A7 H02E0701 +arc: B1 V02N0101 +arc: B2 H01W0100 +arc: B4 H02W0101 +arc: B5 S1_V02N0501 +arc: B7 V02N0501 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F4 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 0001000011011100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R24C60:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A4 E1_H01W0000 +arc: A5 H02E0501 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H01W0000 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F6 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R24C61:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0701 +arc: A3 F5 +arc: A4 F5 +arc: A5 V00T0100 +arc: B1 V00B0000 +arc: B4 V00B0100 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 0100011101110111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C62:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0501 +arc: A5 S1_V02N0101 +arc: B1 H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M0 V00T0000 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F5 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C63:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 N1_V02S0301 +arc: B1 V00B0000 +arc: B5 V02N0501 +arc: C1 H02W0601 +arc: C5 N1_V02S0201 +arc: D1 V00B0100 +arc: D5 H02E0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C64:PLC2 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1111001111100010 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C65:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R24C66:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A3 H02W0501 +arc: A6 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: C1 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 1110010000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEA.K0.INIT 1110111001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C67:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A3 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 V02N0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1110001011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 F6 +arc: V00T0000 F2 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1110001011111111 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 F0 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C70:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 W1_H02E0701 +arc: A3 V02S0501 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A7 E1_H01W0000 +arc: B3 H02E0101 +arc: B5 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F5 +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R24C71:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 S1_V02N0701 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A6 H02W0501 +arc: B1 E1_H02W0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C1 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H01E0101 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: V01S0100 Q5 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010001010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C72:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 H02E0501 +arc: A6 S1_V02N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0303 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R24C73:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A3 V02N0501 +arc: B0 F3 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: C0 H00L0100 +arc: C3 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C74:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 F1 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0601 +arc: C2 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 F0 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C75:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: H00L0100 V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 H02E0701 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B2 H02W0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C2 S1_V02N0401 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: D2 V00B0100 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C76:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A4 V00T0000 +arc: A6 S1_V02N0301 +arc: B1 Q1 +arc: B4 V02S0701 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D4 W1_H02E0001 +arc: D6 V00B0000 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C77:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 H02E0501 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 F1 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D7 N1_V02S0601 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C78:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A4 V02S0301 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C79:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C80:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q4 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C81:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 V00T0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B7 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D7 H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C82:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 V02N0101 +arc: B3 H02W0301 +arc: C0 H02E0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0701 V06S0203 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B4 F1 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 H02E0701 +arc: A6 W1_H02E0701 +arc: B0 H02E0101 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H01W0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 H02W0501 +arc: A4 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B2 E1_H02W0101 +arc: B4 H00L0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 S1_V02N0401 +arc: C4 F6 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D2 H02W0001 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 N3_V06S0103 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 N1_V02S0701 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0101 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B7 V02N0501 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C7 V02N0001 +arc: D1 H02E0001 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C87:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0000 +arc: A3 V00B0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0601 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: A4 S1_V02N0101 +arc: B0 V00B0000 +arc: B4 V02S0701 +arc: C0 V02N0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02S0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 S1_V02N0701 +arc: A2 V02N0701 +arc: B1 H01W0100 +arc: B3 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C7 V02S0201 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICED.K1.INIT 0011111100000000 +word: SLICEB.K0.INIT 0101111101011111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06N0303 +arc: A1 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C3 S1_V02N0401 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D6 F0 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N3_V06N0203 F4 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 0000000000100010 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICED.K1.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06N0203 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 H02E0301 +arc: C2 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: D0 W1_H02E0201 +arc: D1 H01E0101 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F6 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0001000111011101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R24C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0701 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000100001000100 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0101010100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R24C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 W1_H02E0101 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 S1_V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F7 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: A1 H01E0001 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: B4 H00L0000 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: C1 V02S0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0601 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 N1_V02S0001 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F1 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R24C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0001 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D5 H01W0000 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0100 F7 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 F4 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 E1_H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: V01S0000 F6 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 N1_V02S0101 +arc: B1 V01N0001 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 N1_V02S0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C99:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0101000001010000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 V02N0701 +arc: A2 F7 +arc: A3 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02S0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C102:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H01E0001 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: B6 V00B0100 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: D0 H02W0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: N1_V02N0301 F1 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000001000000000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C103:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 F7 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 V01S0100 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R25C104:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: B1 H02W0101 +arc: C1 H00R0100 +arc: D1 E1_H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C105:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R25C106:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A7 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C107:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: B5 H02E0301 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 N1_V01S0100 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R25C108:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B7 N1_V01S0000 +arc: C1 H02W0601 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C109:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: B1 H02E0101 +arc: B2 H02W0301 +arc: B4 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 F1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C110:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C111:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B7 V02N0701 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0701 Q7 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C112:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 H01E0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R25C113:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1101110100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C114:PLC2 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C115:PLC2 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 S3_V06N0303 + +.tile R25C13:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: A0 E1_H02W0701 +arc: A2 N1_V02S0501 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02E0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C15:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 H01E0101 +arc: A0 H02W0501 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A6 V02N0101 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: B4 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C16:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C17:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V01N0101 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0401 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0601 Q4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C18:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 V02N0701 +arc: B6 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q7 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICED.K0.INIT 1101100011011000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C19:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0000 +arc: A2 N1_V02S0501 +arc: B0 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C0 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010001110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C20:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0101 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q7 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C21:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 E1_H01W0000 +arc: A2 E1_H02W0701 +arc: B0 H02W0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0501 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C22:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C23:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B4 V02S0501 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C24:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 H02W0701 +arc: B0 V02S0301 +arc: B2 H00L0000 +arc: C0 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V01N0101 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C25:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H01E0101 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C26:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: W1_H02W0701 S1_V02N0701 + +.tile R25C27:PLC2 +arc: W1_H02W0401 W3_H06E0203 + +.tile R25C32:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 + +.tile R25C33:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: H00L0000 H02E0001 +arc: H00R0100 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 F5 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 N1_V02S0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C34:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H02W0501 +arc: A1 H01E0001 +arc: A2 F7 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010000011101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C35:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 H01E0001 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q4 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010000011101100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1011101000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C36:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C37:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 F7 +arc: A3 H02E0701 +arc: B0 V00T0000 +arc: B5 H02E0101 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C5 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V00T0100 +arc: D5 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C38:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: A0 V01N0101 +arc: A1 H00L0000 +arc: A3 H02E0701 +arc: A5 H02E0501 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 H02E0601 +arc: C5 W1_H02E0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D3 V02S0001 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C39:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 H02W0501 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1101100011011000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 E1_H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H01E0101 +arc: B6 V02N0701 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000111110001000 +word: SLICED.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 F3 +arc: B2 H02W0301 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C42:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: A0 N1_V02S0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B7 N1_V02S0701 +arc: C0 W1_H02E0601 +arc: C1 F4 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 H02W0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V02N0301 F1 +arc: V01S0000 F3 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C43:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H00L0100 +arc: B3 S1_V02N0101 +arc: C3 W1_H02E0401 +arc: D3 H02E0201 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C44:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F7 +arc: A2 H02E0501 +arc: A4 H02W0701 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B2 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C2 V02N0401 +arc: C4 V02N0201 +arc: C7 H02E0601 +arc: D0 E1_H02W0001 +arc: D2 H00R0000 +arc: D4 F2 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F0 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R25C45:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R25C46:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B3 H02W0301 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: S3_V06S0203 Q4 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C47:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: A4 E1_H01W0000 +arc: B3 H02W0301 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 Q3 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R25C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: A7 H02E0701 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: V00B0000 F6 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R25C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A6 W1_H02E0501 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F2 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1010100000100000 +word: SLICEB.K0.INIT 1010110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C50:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 V02S0301 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1101111111010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C51:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V00T0000 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 Q4 +arc: E1_H02E0501 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0601 F4 +arc: V00T0100 F3 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEB.K1.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C53:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A7 H00R0000 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 N1_V02S0501 +arc: B7 S1_V02N0501 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H01E0001 +arc: C5 V01N0101 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D7 H00L0100 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: S1_V02S0401 F4 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0101000001000100 +word: SLICEB.K1.INIT 1111111010101110 +word: SLICED.K1.INIT 0011001000010000 +word: SLICEC.K1.INIT 1111111000110010 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R25C54:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02E0301 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02E0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V02S0001 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: N1_V02N0301 F1 +arc: N3_V06N0003 F0 +arc: V00B0000 F6 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0010001000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C55:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: B0 V00T0000 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C56:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 E1_H01W0000 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0601 F6 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101000001011100 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D1 F2 +arc: D2 V02N0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R25C58:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A5 H02W0501 +arc: B0 V01N0001 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R25C59:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 F5 +arc: A2 V02S0701 +arc: A5 V00T0100 +arc: B3 S1_V02N0101 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C60:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: C0 F4 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0011111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R25C61:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A3 H02E0701 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C62:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A6 N1_V01S0100 +arc: B3 H02W0101 +arc: C0 H02W0401 +arc: C3 N1_V01S0100 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0301 F3 +arc: S1_V02S0601 Q4 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A3 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R25C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A6 H02W0501 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C65:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: B0 S1_V02N0301 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R25C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: A4 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V01N0101 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 F3 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0000101001001110 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 1100000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C68:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 N1_V02S0501 +arc: A5 N1_V02S0101 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C5 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D5 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00R0100 F5 +arc: H01W0100 F5 +arc: M0 V00B0000 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C69:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 E1_H02W0501 +arc: A5 V02S0301 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B7 E1_H02W0101 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 H02E0601 +arc: M6 H02E0401 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 0001101101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0011010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C70:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0101 +arc: B3 F1 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 Q3 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K0.INIT 0000010010101110 +word: SLICED.K1.INIT 0100010011101110 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C71:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B3 V02S0101 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D5 V02S0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R25C72:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A5 V02N0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B3 V02S0101 +arc: B5 F1 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q1 +arc: V01S0000 F1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C73:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02E0501 +arc: B1 E1_H02W0101 +arc: C1 H02E0401 +arc: D1 V02N0201 +arc: F1 F1_SLICE +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C74:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A6 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 N1_V02S0401 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: V01S0000 F3 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C75:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 V02S0401 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C77:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R25C78:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H02W0701 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B6 V02N0701 +arc: C0 S1_V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C79:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 E1_H02W0701 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 F3 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C80:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A7 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C81:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A6 F7 +arc: A7 V02N0301 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B6 F3 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 V02N0001 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0401 F6 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A6 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B4 V02N0701 +arc: B6 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101110100001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B6 S1_V02N0501 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 F4 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F5 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 N1_V02S0501 +arc: A1 F7 +arc: A2 H02W0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0001 F0 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D1 W1_H02E0001 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C87:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 F0 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C88:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: A6 H02W0701 +arc: B4 V02N0701 +arc: C4 V00T0100 +arc: C6 V00T0000 +arc: D4 E1_H02W0201 +arc: D6 N1_V02S0401 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R25C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V01N0101 +arc: B6 H02W0101 +arc: C6 S1_V02N0001 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 1100111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R25C90:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: C7 W1_H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: V01S0000 F4 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICEC.K0.INIT 0011001111111111 +word: SLICEC.K1.INIT 0000110000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R25C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H00R0000 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 F3 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C2 F4 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F2 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001000100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R25C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: B0 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: C0 V02N0601 +arc: C6 V02N0201 +arc: D0 W1_H02E0201 +arc: D4 V02S0401 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R25C93:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 H02W0301 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A4 S1_V02N0301 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B4 V02S0701 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: C4 V02S0001 +arc: C6 V01N0101 +arc: C7 N1_V02S0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 H02E0201 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F4 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R25C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D1 W1_H02E0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0701 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C1 N1_V01S0100 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 W1_H02E0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: V01S0100 F3 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R25C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 F4 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: V00T0000 F2 +arc: V01S0000 F3 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 E1_H02W0701 +arc: B0 F3 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 H02W0001 +arc: D3 W1_H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F1 +arc: V01S0100 F4 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C101:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D3 V02S0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A2 F7 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B2 H01W0100 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 H01E0001 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: D0 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F6 +arc: S1_V02S0201 F2 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICED.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C103:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02S0101 +arc: B4 V02S0501 +arc: C4 V00T0100 +arc: D4 H02W0001 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C104:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 F5 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 V00T0100 +arc: B3 V01N0001 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D5 V00B0000 +arc: D6 E1_H02W0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 0000000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0100 F4 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C106:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 F5 +arc: A5 H02W0501 +arc: A7 W1_H02E0701 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B5 V00B0100 +arc: B7 N1_V02S0501 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D5 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C107:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C108:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0501 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 W1_H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: S3_V06S0003 Q0 +arc: V01S0000 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C109:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H02W0501 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 F1 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02S0001 +arc: D0 N1_V02S0001 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D5 N1_V02S0601 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C110:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06S0203 +arc: A0 F5 +arc: A1 V02N0501 +arc: A2 N1_V02S0701 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0301 +arc: A6 F7 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 N1_V02S0001 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D6 F2 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C111:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V02S0301 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C112:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02S0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D5 V01N0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C113:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F3 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1101000011010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C114:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C115:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: B0 V02N0101 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C116:PLC2 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile R26C117:PLC2 +arc: W1_H02W0401 S1_V02N0401 + +.tile R26C13:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: A0 V01N0101 +arc: B0 E1_H01W0100 +arc: B1 V01N0001 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: M0 V00B0100 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R26C14:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: A0 S1_V02N0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C15:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0100 +arc: A4 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C16:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A6 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 F4 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000101110111000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1101111000010010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C17:PLC2 +arc: E1_H02E0601 V02S0601 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: A2 H00L0100 +arc: A4 N1_V02S0101 +arc: B0 W1_H02E0101 +arc: B4 H02E0301 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D5 H00R0100 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C18:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1110001011100010 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C19:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 + +.tile R26C20:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: A0 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C21:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V01S0000 F6 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A6 H02E0701 +arc: B0 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q7 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1101111000010010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C23:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 V06N0203 +arc: A0 H02E0501 +arc: A2 W1_H02E0501 +arc: A4 H02W0701 +arc: A6 W1_H02E0501 +arc: B0 V01N0001 +arc: B2 V02S0301 +arc: B4 H01E0101 +arc: C0 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C24:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A6 S1_V02N0101 +arc: B0 H02E0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 W1_H02E0301 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1000101110111000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C25:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 1101111000010010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1101111000010010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C26:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V02N0701 + +.tile R26C31:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: S1_V02S0501 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C32:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 H02W0301 +arc: C0 F6 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000010001010100 +word: SLICEA.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C33:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H00R0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 V02N0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D5 H02W0001 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 0000001000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C34:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A6 F5 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: D0 W1_H02E0001 +arc: D2 E1_H02W0001 +arc: D3 F0 +arc: D4 F2 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C35:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: B1 H02E0101 +arc: B7 V02S0701 +arc: C1 S1_V02N0601 +arc: C7 E1_H01E0101 +arc: D1 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R26C36:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 + +.tile R26C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V01S0000 S3_V06N0103 + +.tile R26C38:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 N3_V06S0003 +arc: A0 W1_H02E0501 +arc: A1 F7 +arc: A3 H02E0701 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 V02S0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D1 F0 +arc: D3 V02S0001 +arc: D7 W1_H02E0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 S1_V02N0501 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0701 +arc: A4 V00T0100 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C41:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V02S0501 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0203 F7 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C42:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 F7 +arc: A7 N1_V02S0301 +arc: B1 V00B0000 +arc: B4 V02S0501 +arc: B7 S1_V02N0501 +arc: C1 H02E0601 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C7 H01E0001 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C43:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 V06N0103 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 N1_V02S0701 +arc: A4 E1_H02W0501 +arc: A5 V02S0101 +arc: A6 V02N0301 +arc: A7 F5 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02E0101 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 W1_H02E0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 W1_H02E0201 +arc: D6 F2 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000001110010 +word: SLICEB.K0.INIT 0000000000111010 +word: SLICED.K0.INIT 0101000001010001 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C44:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: A6 W1_H02E0501 +arc: B0 H02W0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 H02W0401 +arc: C4 V02S0201 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A5 W1_H02E0501 +arc: A7 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 F1 +arc: B5 V02S0701 +arc: B7 V00B0000 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D7 H02E0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N3_V06N0003 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEB.K1.INIT 1010100000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C46:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F7 +arc: A5 S1_V02N0101 +arc: A7 Q7 +arc: B5 V00B0100 +arc: C0 H00R0100 +arc: C1 V02S0401 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D5 S1_V02N0401 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 W1_H02E0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 F7 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C47:PLC2 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C48:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A4 S1_V02N0301 +arc: A6 H02W0501 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 F6 +arc: C6 H02E0601 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000011111110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R26C49:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100101011111010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C50:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00R0000 +arc: A7 V02N0101 +arc: B1 E1_H01W0100 +arc: B6 V02N0701 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C51:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 F1 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1110010011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1110010000000000 +word: SLICEC.K1.INIT 1110010011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C52:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 V02N0501 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 F1 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 0000000010111000 +word: SLICEC.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C54:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0100 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C55:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A3 H02W0501 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: M2 H02E0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q0 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C56:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 H02E0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B3 N1_V02S0301 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0011010100111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R26C59:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 F3 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEB.K0.INIT 1111000011101110 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R26C61:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +word: SLICEB.K0.INIT 0000110100001000 +word: SLICEB.K1.INIT 1111110111111000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111111000001110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICED.K1.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1101110110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V01N0101 +arc: A1 F7 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 F3 +arc: B2 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0203 F4 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 1001000010011001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICEA.K1.INIT 1011111110110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C64:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 1011100011111100 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEA.K1.INIT 1110111000101110 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEB.K1.INIT 1101110111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEC.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C66:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 Q3 +arc: V00T0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q3 +word: SLICEC.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C67:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 H02E0501 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: B0 V00B0000 +arc: B2 H02E0101 +arc: B4 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: C0 E1_H01W0000 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C69:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B7 V02N0501 +arc: C1 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R26C70:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 F7 +arc: A4 H02E0701 +arc: A7 Q7 +arc: B1 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F4 +arc: V01S0100 Q7 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C71:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 N1_V02S0701 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B3 S1_V02N0301 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D3 E1_H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V02N0501 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R26C73:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 V02S0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A3 H00L0100 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0101000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R26C74:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A3 F5 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: B0 V02N0101 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: C0 H00R0100 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: D0 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100000000110000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C75:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: B1 V02S0301 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: C1 H00L0100 +arc: C4 V01N0101 +arc: C5 E1_H02W0601 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F5 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C76:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 W1_H02E0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 N1_V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 N1_V01S0100 +arc: B4 N1_V01S0000 +arc: C4 V02S0201 +arc: D4 H00R0100 +arc: F4 F4_SLICE +arc: V01S0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 H02E0501 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 F3 +arc: B7 H02E0101 +arc: C1 N1_V02S0401 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: V01S0000 F0 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C79:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 H01W0100 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C80:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 V06S0303 +arc: A1 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C81:PLC2 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 H02E0301 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 V00T0000 +arc: B0 H02W0101 +arc: B2 V02N0301 +arc: B3 H02E0301 +arc: B5 S1_V02N0501 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C5 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: D5 F2 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C82:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0303 E1_H02W0601 + +.tile R26C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B2 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C5 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 F0 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R26C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 S1_V02N0101 +arc: B2 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010010100000000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C85:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 F5 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R26C86:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0701 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F5 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C87:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: B1 V00T0000 +arc: B2 H02W0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: C0 V02N0601 +arc: C1 F4 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000100000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R26C88:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06S0003 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02S0501 +arc: A1 H02W0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: D0 H01E0101 +arc: D1 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 0100010001001100 +word: SLICEA.K1.INIT 0011011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B5 N1_V01S0000 +arc: C1 H00L0100 +arc: C5 S1_V02N0001 +arc: D0 V02S0201 +arc: D1 H02W0201 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111001111 +word: SLICEC.K1.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C91:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 W1_H02E0601 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: N1_V02N0301 F1 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1100001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R26C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D2 F0 +arc: D3 F2 +arc: D4 E1_H01W0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: D6 F0 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0303 F6 +arc: S3_V06S0103 F1 +arc: V01S0000 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C94:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 W1_H02E0401 +arc: C2 H00L0100 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: D2 E1_H02W0201 +arc: D5 H02W0001 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +arc: V00T0000 F2 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R26C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B1 H00R0100 +arc: B3 F1 +arc: B6 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C3 E1_H01W0000 +arc: C6 S1_V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D6 S1_V02N0601 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F6 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000010000000 +word: SLICEA.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R26C96:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 H02W0701 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 W1_H02E0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 H00R0000 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F3 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B0 F3 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 W1_H02E0601 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R26C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: A7 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 F0 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0101 F1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0501 +arc: A7 F5 +arc: B0 W1_H02E0301 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 H02W0401 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 F2 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C101:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 W1_H02E0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 W1_H02E0301 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 F4 +arc: D0 F2 +arc: D1 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A4 V00T0000 +arc: A7 V02S0301 +arc: B1 H02W0101 +arc: B4 E1_H02W0301 +arc: B7 V02N0701 +arc: C1 V02N0401 +arc: C4 N1_V02S0201 +arc: C7 E1_H02W0601 +arc: D1 V02S0001 +arc: D4 N1_V02S0401 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C103:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A4 V02N0101 +arc: A6 N1_V02S0101 +arc: B0 H02W0101 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +arc: C0 S1_V02N0401 +arc: C4 V02S0201 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: D0 H02W0201 +arc: D4 H02E0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R27C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0101 +arc: B3 V02N0101 +arc: B4 F3 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V02N0501 F7 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C105:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 H02E0701 +arc: B0 W1_H02E0101 +arc: B3 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: D0 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00L0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R27C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00B0000 +arc: A5 H02W0501 +arc: B2 V02N0301 +arc: B5 S1_V02N0501 +arc: C2 N1_V02S0601 +arc: C5 V00B0100 +arc: D2 V01S0100 +arc: D5 H00R0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C107:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 S1_V02N0501 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 E1_H02W0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F3 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R27C108:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 H00R0100 +arc: B1 N1_V02S0101 +arc: B2 V02N0101 +arc: B3 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 F1 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 V00B0100 +arc: D0 H02E0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0100 F3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C109:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H01E0001 +arc: A5 V02S0101 +arc: A7 F5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C110:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C111:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F7 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C112:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0303 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1010001001010001 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R27C113:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C114:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0101 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 W1_H02E0001 +arc: D4 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C115:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: B0 H02E0101 +arc: B1 E1_H01W0100 +arc: B4 V02N0701 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEC.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C116:PLC2 +arc: S1_V02S0501 H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R27C117:PLC2 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06S0203 + +.tile R27C12:PLC2 +arc: E1_H02E0701 E1_H01W0100 + +.tile R27C13:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0301 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C14:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 V00B0000 +arc: B2 H00L0000 +arc: B4 V02S0701 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C15:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02W0501 +arc: B0 V00B0000 +arc: B2 N1_V02S0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C16:PLC2 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A6 V02S0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010001110100000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1010110010101100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C17:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 H01E0001 +arc: A0 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C4 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V00B0100 +arc: D6 V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 W1_H02E0401 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C18:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1000100011011000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1000100011011000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C19:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 N1_V01S0100 + +.tile R27C20:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V02S0501 +arc: A4 H02E0501 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C21:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A6 N1_V01N0101 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C22:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A6 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C23:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C24:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q1 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C25:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C26:PLC2 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H01E0001 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: F0 F5A_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +word: SLICEA.K0.INIT 1010001110101100 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R27C27:PLC2 +arc: W1_H02W0201 S1_V02N0201 + +.tile R27C28:PLC2 +arc: W1_H02W0501 S1_V02N0501 + +.tile R27C29:PLC2 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R27C30:PLC2 +arc: E1_H02E0601 S1_V02N0601 + +.tile R27C31:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: A0 H00L0000 +arc: A7 H00L0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C32:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 H01E0001 +arc: A2 F7 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 F7 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 H01E0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 N1_V02S0201 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 0001001100010000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEA.K1.INIT 0000000011001101 +word: SLICEC.K1.INIT 0000000010101011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C33:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 V02N0701 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0001000101010000 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C34:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02W0401 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A6 V02N0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C4 N1_V02S0001 +arc: C6 V00T0000 +arc: D4 V00B0000 +arc: D6 E1_H02W0001 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: A2 F7 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C36:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A5 N1_V02S0101 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B2 H02E0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F6 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C37:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A3 V02N0501 +arc: A7 V00T0100 +arc: B3 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V00T0100 F3 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C38:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 S1_V02N0601 + +.tile R27C39:PLC2 +arc: E1_H02E0001 V06N0003 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D0 S1_V02N0201 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: N1_V01N0101 F0 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEA.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C40:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEB.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICEA.K0.INIT 0000001100100010 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C42:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A2 S1_V02N0501 +arc: A3 V02N0701 +arc: A6 H02E0701 +arc: B0 V02N0301 +arc: B2 F3 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: C0 H02E0601 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: D0 H02W0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: V00B0000 F4 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEB.K0.INIT 0001000100110011 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C43:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 F7 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 F5 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +arc: V00B0100 F5 +arc: V00T0000 Q0 +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A5 N1_V02S0301 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C7 H01E0001 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D2 V02S0001 +arc: D3 F0 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: S3_V06S0303 F5 +arc: V00B0000 F4 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 0000000001110010 +word: SLICEB.K0.INIT 0000001100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C45:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F6 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C46:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A1 N1_V02S0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A7 H02E0701 +arc: B4 V02N0501 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C1 H00R0100 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F5 +arc: V00B0100 Q7 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02S0501 +arc: A6 N1_V01N0101 +arc: B0 V02S0301 +arc: B6 V00T0000 +arc: C0 H02W0401 +arc: C3 H02E0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q7 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0201 Q0 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1000110010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A7 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C3 F6 +arc: C4 Q4 +arc: C6 H02E0601 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 F5 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B5 H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1010100000100000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101010000000100 +word: SLICEB.K1.INIT 1111111011001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 E1_H02W0701 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0100 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +word: SLICED.K1.INIT 1010100000100000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C51:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 F7 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 W1_H02E0301 +arc: B3 E1_H01W0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C53:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A3 S1_V02N0501 +arc: A7 V02N0101 +arc: B0 F3 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02N0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C54:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02E0301 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0000 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R27C55:PLC2 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: B1 N1_V02S0101 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C56:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A6 H02E0701 +arc: B0 S1_V02N0301 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0000001100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R27C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 V02N0101 +arc: A6 V02S0301 +arc: B0 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B6 N1_V01S0000 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C4 H02E0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1010000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R27C58:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICEA.K0.INIT 1101100011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C59:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02S0501 +arc: A4 V00B0000 +arc: A7 H00R0000 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 V02S0501 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C60:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 S1_V02N0301 +arc: B0 V02N0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R27C61:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H01E0001 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 F1 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C62:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: B0 H02W0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011111110000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A7 H02E0701 +arc: B1 H02W0101 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 H02E0401 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 N1_V02S0201 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0011010100111111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1101000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C64:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: C3 H02E0601 +arc: C5 V02S0001 +arc: D2 W1_H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 V02N0401 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C65:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H02E0501 +arc: A3 F7 +arc: A6 N1_V02S0301 +arc: A7 N1_V01N0101 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D3 H00R0000 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: N3_V06N0303 F6 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: C0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: M0 H02W0601 +arc: M5 H02W0001 +arc: MUXCLK2 CLK0 +word: SLICEA.K0.INIT 0101010100110000 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C67:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K0.INIT 1101100011011000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C68:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02W0501 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C4 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D4 V02S0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1000100010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C69:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 F7 +arc: B7 H02W0301 +arc: C1 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: M0 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R27C70:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02W0701 +arc: A7 E1_H01W0000 +arc: C2 H02W0401 +arc: C7 H02W0401 +arc: D2 N1_V01S0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICEB.K0.INIT 0000000001011111 +word: SLICED.K1.INIT 0000000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C71:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 V06N0303 +arc: A1 N1_V02S0501 +arc: A3 S1_V02N0701 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C72:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: B0 H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 F1 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: V01S0100 F1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C73:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0203 E3_H06W0103 + +.tile R27C74:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 N1_V02S0101 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 F3 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0601 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C75:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D2 N1_V02S0201 +arc: D3 H02W0001 +arc: D4 F2 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C76:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V01N0101 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H02E0301 +arc: B4 V02N0701 +arc: B6 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 W1_H02E0401 +arc: C4 H02E0601 +arc: C6 F4 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 S1_V02N0401 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0000 +arc: S1_V02S0201 F0 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C77:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 N3_V06S0003 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C7 N1_V02S0001 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F7 +arc: S1_V02S0301 F3 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C78:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A1 W1_H02E0501 +arc: A2 V02S0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 W1_H02E0301 +arc: B6 F3 +arc: B7 V02S0501 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 N1_V02S0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 N1_V02S0201 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02E0601 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C79:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 F7 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 H00R0100 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 F3 +arc: B6 F1 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 F0 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C80:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 W1_H02E0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B7 F3 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0701 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010010100000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C81:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: A1 E1_H02W0501 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0201 +arc: D7 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C82:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 W1_H02E0501 +arc: A2 H02W0501 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 F7 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B4 W1_H02E0301 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C85:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V01N0101 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 W1_H02E0301 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F7 +word: SLICED.K1.INIT 0000110000001100 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C86:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0301 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 F0 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D6 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C88:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000001110000 +word: SLICEB.K1.INIT 1111111101110000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEA.K1.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 H02W0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B6 N1_V01S0000 +arc: C1 H00L0100 +arc: C3 W1_H02E0401 +arc: C6 V00T0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D6 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICED.K0.INIT 1000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0501 +arc: A2 V01N0101 +arc: A3 V02S0701 +arc: A5 N1_V02S0301 +arc: A6 V00T0100 +arc: A7 F5 +arc: B0 W1_H02E0101 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C5 W1_H02E0601 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 E1_H02W0001 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0101 F4 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C91:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 W1_H02E0301 +arc: B1 H02E0301 +arc: B2 N1_V02S0101 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C1 W1_H02E0601 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 V02S0001 +arc: D1 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: B7 F3 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 V01N0101 +arc: C6 V02S0001 +arc: C7 F6 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: V00T0000 F0 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: B0 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: C0 H00L0100 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C94:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000010000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1011101100001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +arc: V00B0100 F7 +arc: V00T0000 F0 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C96:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 W1_H02E0701 +arc: A1 H01E0001 +arc: A2 V02S0501 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: V00T0000 F2 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D2 H02E0201 +arc: D4 F0 +arc: D5 N1_V02S0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F4 +arc: V00B0100 F7 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R27C98:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C2 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0601 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F1 +arc: N1_V01N0001 F3 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C99:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0301 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B2 W1_H02E0101 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: D0 V02S0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0100010001000100 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R28C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 V01S0000 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 E1_H02W0001 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0201 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A5 E1_H02W0701 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H00R0000 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 N1_V01S0100 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: D0 H02E0001 +arc: D2 V02S0001 +arc: D3 F2 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: V00T0100 F3 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R28C103:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R28C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F7 +arc: A2 H00L0100 +arc: A7 H00L0000 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0101 +arc: B7 H02W0101 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C7 S1_V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C105:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B3 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 N1_V01S0100 +arc: C3 H02W0401 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F0 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100001100000000 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R28C106:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C7 V00B0100 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C107:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 E1_H02W0301 +arc: B6 W1_H02E0101 +arc: B7 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1001100100000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C108:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 F1 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 V02S0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 F0 +arc: D4 N1_V02S0601 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0101 F3 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C109:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A1 F5 +arc: A2 N1_V02S0501 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B2 V01N0001 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C110:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02W0001 +arc: H00R0000 V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 V02N0501 +arc: A2 S1_V02N0501 +arc: A4 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B4 H00L0000 +arc: B6 F1 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C4 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 H02W0201 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V01S0100 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1101000000001101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010010100100001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C111:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A6 N1_V01S0100 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B6 N1_V02S0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C112:PLC2 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 F7 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B3 N1_V02S0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C6 V02S0201 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 F0 +arc: D3 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1111000000110000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R28C113:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C114:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C115:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: B2 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R28C116:PLC2 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02S0501 +arc: B0 H02W0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: W1_H02W0301 V01N0101 + +.tile R28C118:PLC2 +arc: W1_H02W0401 V01N0001 + +.tile R28C13:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 S1_V02N0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: B0 H02W0301 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V01S0100 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: LSR1 V00B0100 +arc: M0 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C14:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C15:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A4 N1_V02S0101 +arc: A6 N1_V01S0100 +arc: A7 Q7 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C16:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S1_V02N0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 V06N0103 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B0 V02S0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: C0 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C17:PLC2 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: A0 H00R0000 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100010111001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C18:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: B0 W1_H02E0101 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1000101110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C19:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: H00R0100 H02W0501 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H02E0301 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: V00T0000 Q0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1011100011001000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C20:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V01N0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 V02S0701 +arc: A2 V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C21:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 H02E0701 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V01N0001 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1110101001100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B2 V02S0301 +arc: B4 V02N0501 +arc: B6 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: LSR0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110000001010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R28C23:PLC2 +arc: N1_V02N0201 H02E0201 +arc: V00T0100 H02E0301 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 Q5 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q1 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010111011000000 +word: SLICEA.K1.INIT 1111000011000000 +word: SLICEB.K0.INIT 1110101001001000 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K0.INIT 1110101001001000 +word: SLICEC.K1.INIT 1010101010001000 +word: SLICED.K0.INIT 1010111011000000 +word: SLICED.K1.INIT 1111000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C24:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: A4 V00T0100 +arc: B2 N1_V02S0301 +arc: C2 V02N0401 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 Q1 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C25:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: B0 V02N0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C26:PLC2 +arc: W1_H02W0501 V02N0501 + +.tile R28C27:PLC2 +arc: W1_H02W0201 V02N0201 + +.tile R28C29:PLC2 +arc: E1_H02E0001 V02S0001 +arc: V01S0100 S3_V06N0303 + +.tile R28C30:PLC2 +arc: H00L0000 E1_H02W0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: A3 F5 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B3 H01W0100 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C31:PLC2 +arc: E1_H02E0301 V02N0301 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V00B0000 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: D0 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000001000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C32:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: B2 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02S0601 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0201 F2 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C33:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0301 +arc: A7 N1_V01N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 F3 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F1 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICEB.K1.INIT 0001000101010000 +word: SLICEC.K1.INIT 0101000001010001 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C34:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H02E0701 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B1 H00R0100 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 F6 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEA.K0.INIT 0001010100000100 +word: SLICEA.K1.INIT 0000001000110010 +word: SLICED.K1.INIT 0101010100000001 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C35:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 F6 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 E1_H02W0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000000001110100 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C36:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 E1_H02W0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B4 H00L0000 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C37:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0000 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 F5 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0000000011110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C38:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: B1 H02W0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 F1 +arc: C1 W1_H02E0401 +arc: C3 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D1 W1_H02E0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F6 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R28C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06S0003 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 F6 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C40:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 V06S0003 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F0 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B0 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 0010001000100011 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V01N0101 +arc: A3 V01N0101 +arc: A4 F7 +arc: A5 H02W0701 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0100 F5 +word: SLICEB.K1.INIT 1110010000000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1110010000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICED.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C43:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 F5 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0000011100000100 +word: SLICED.K1.INIT 0000110000001101 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0100010001000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C44:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 S1_V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B3 H02E0101 +arc: B4 F1 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A1 V01N0101 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A5 N1_V02S0301 +arc: A6 E1_H01W0000 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 0010001000100011 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C46:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H00R0000 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010100000100000 +word: SLICED.K1.INIT 0001001100000010 +word: SLICEC.K0.INIT 0000010101000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C47:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B3 E1_H02W0301 +arc: C3 H00L0100 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R28C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C49:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 H01W0100 +arc: B4 H02E0101 +arc: B5 F1 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 F6 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICED.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111001010100 +word: SLICEC.K0.INIT 1011101110001000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R28C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: B5 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C3 V02N0401 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D5 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICEA.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C52:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C53:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 N1_V02S0501 +arc: A3 F7 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 H02E0301 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1101100011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101000010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C54:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02E0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 H02E0501 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C1 N1_V01S0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M5 H02W0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 F7 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F6 +arc: V00B0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C55:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H00R0000 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A7 H02W0501 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C56:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B5 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C3 V02N0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R28C57:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02N0701 +arc: A5 V02S0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D5 H02E0201 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C58:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B3 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R28C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A6 H00L0000 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0010001011101110 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEA.K0.INIT 1011111110110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0501 +arc: A3 H00L0100 +arc: B3 V01N0001 +arc: C0 H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C61:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A6 S1_V02N0101 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 W1_H02E0301 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A7 H02W0701 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B7 H02W0301 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C7 H02W0601 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 0000111101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICED.K0.INIT 1000101010000000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C64:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F2 +arc: V00T0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C65:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A6 W1_H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 S1_V02N0401 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1110001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C66:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: V01S0100 Q5 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0301 +arc: A5 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: N1_V01N0001 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICEB.K1.INIT 0000000001110111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 S1_V02N0501 +arc: A5 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F5 +arc: V01S0000 F2 +arc: W3_H06W0203 Q4 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B5 E1_H02W0301 +arc: B7 V01S0000 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C5 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0010011100100010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R28C70:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A5 H02W0701 +arc: B0 H02W0101 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R28C71:PLC2 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 H01E0001 +arc: A6 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02N0301 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0201 Q0 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C72:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: B6 W1_H02E0101 +arc: C6 S1_V02N0201 +arc: D6 V01N0001 +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R28C73:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile R28C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E1_H01W0000 + +.tile R28C75:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V01N0001 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C76:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N3_V06S0103 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 V00B0000 +arc: A3 E1_H01E0001 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C4 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C77:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A4 V02S0301 +arc: B4 V02S0701 +arc: C4 V02S0001 +arc: D4 V00B0000 +arc: E1_H01E0001 F4 +arc: F4 F4_SLICE +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C78:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 H00L0000 +arc: B0 S1_V02N0301 +arc: B1 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C79:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 V01N0001 +arc: A0 H00L0000 +arc: A2 F7 +arc: A6 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0101 +arc: B2 H00R0000 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 H02W0401 +arc: C6 V02N0201 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D6 H00L0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C80:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0501 +arc: A2 H01E0001 +arc: A5 E1_H02W0501 +arc: A6 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 V01N0001 +arc: B5 F1 +arc: B6 S1_V02N0701 +arc: C1 E1_H02W0401 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0101 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: S1_V02S0701 F5 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C81:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02W0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: A6 W1_H02E0701 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 H02E0001 +arc: D4 V01N0001 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F7 +arc: V00T0000 F2 +arc: V00T0100 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 0011000000110000 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00R0000 +arc: A5 V02S0101 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D5 V00B0000 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C83:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A6 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 V02S0701 +arc: B5 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 H00L0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C85:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 0010001000100010 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: A0 H00R0000 +arc: A2 H02W0701 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 F5 +arc: B1 H02W0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 V00T0000 +arc: B0 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C6 V02N0201 +arc: D0 S1_V02N0201 +arc: D2 N1_V02S0201 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F6 +arc: N3_V06N0303 F6 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R28C88:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICEC.K0.INIT 0000000001001100 +word: SLICEC.K1.INIT 1111111101001100 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0101010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 V06N0303 +arc: A0 H00L0000 +arc: A5 V02S0301 +arc: B0 H00R0100 +arc: C0 N1_V01N0001 +arc: D0 V00T0100 +arc: D5 H00L0100 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R28C91:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0003 V06N0003 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0301 +arc: B3 H02W0301 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 V02S0201 +arc: D1 S1_V02N0001 +arc: D2 F0 +arc: D3 V02S0001 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: N1_V02N0601 F4 +arc: V01S0000 F3 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F7 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0000 +arc: B3 F1 +arc: B4 W1_H02E0301 +arc: B5 H01E0101 +arc: B6 E1_H02W0101 +arc: B7 H01E0101 +arc: C0 F4 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 E1_H02W0601 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R28C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V02S0701 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: B1 H02E0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 N1_V02S0701 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: N1_V01N0101 F3 +arc: N3_V06N0303 F5 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F3 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C96:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 F5 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: C7 V02S0001 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R28C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C2 E1_H02W0601 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 F4 +arc: D0 V02S0001 +arc: D2 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0010001000100010 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 F1 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F4 +arc: V01S0000 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H00R0100 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R29C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B0 H00R0100 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 F0 +arc: D5 H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0101000001010000 +word: SLICEA.K1.INIT 0100010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A2 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B6 V02S0501 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1011000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H01E0101 +arc: C0 E1_H02W0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C5 V00T0100 +arc: C7 F6 +arc: D0 V00B0100 +arc: D1 F2 +arc: D2 V02N0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C103:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B1 W1_H02E0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C104:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A3 W1_H02E0701 +arc: A5 H02E0701 +arc: A7 W1_H02E0701 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B5 H02W0101 +arc: B7 N1_V02S0701 +arc: C1 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0100 +arc: C7 V00T0000 +arc: D1 N1_V02S0201 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C105:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 N1_V02S0501 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C106:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: S3_V06S0003 F3 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C107:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 W1_H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C109:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 0000000100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 + +.tile R29C110:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 N1_V02S0101 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H02W0401 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: S3_V06S0003 Q0 +arc: V01S0100 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C111:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A3 N1_V02S0701 +arc: A4 F5 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 F3 +arc: B7 H02E0301 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0701 +arc: A6 N1_V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 F5 +arc: V01S0000 Q4 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1000010010100101 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C113:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02S0401 +arc: C3 V02S0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0001 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C114:PLC2 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000000110000 +word: SLICED.K0.INIT 1100100000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C115:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06S0103 +arc: B5 V02N0501 +arc: C5 V02N0001 +arc: D5 E1_H02W0201 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1100110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C116:PLC2 +arc: N1_V02N0201 H02E0201 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 + +.tile R29C117:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: B0 V00T0000 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C118:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 + +.tile R29C13:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0303 V06N0303 + +.tile R29C14:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: B0 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 H02E0101 +arc: C0 V02S0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C15:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 H01E0101 +arc: A2 V00T0000 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 V02S0501 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110001011010 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C16:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 F3 +arc: B3 E1_H01W0100 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K1.INIT 1010101000111100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C17:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C18:PLC2 +arc: H00L0000 H02W0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 W1_H02E0501 +arc: B0 H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C19:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 V01N0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C20:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V01N0101 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0001 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00T0100 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 Q7 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1110110001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011111010 +word: SLICEB.K1.INIT 1100110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C21:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A2 V00T0000 +arc: A3 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q7 +arc: E3_H06E0203 Q7 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1100110011111010 +word: SLICEB.K1.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100111111001010 +word: SLICEC.K1.INIT 1100000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C22:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0103 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q6 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111111000110010 +word: SLICEA.K1.INIT 1100111000000010 +word: SLICEB.K0.INIT 1011101110111000 +word: SLICEB.K1.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C23:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 H02E0501 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0001 +arc: D3 H01E0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 F1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R29C24:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: W1_H02W0401 N1_V01S0000 +arc: A2 V01N0101 +arc: A5 Q5 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D7 H01W0000 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: V00T0100 Q3 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C25:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A5 V00T0100 +arc: B0 V02N0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02W0001 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C26:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H01E0001 +arc: B0 H01W0100 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D3 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 0101001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C27:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00T0000 +arc: C0 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D6 V02N0601 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R29C28:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0003 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C29:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 H02W0101 +arc: A0 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C32:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A7 W1_H02E0701 +arc: B1 V02N0101 +arc: B4 H02W0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C33:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: B0 S1_V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 W1_H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: N1_V01N0001 F7 +arc: S1_V02S0501 F5 +arc: V00T0000 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1010000010001000 +word: SLICEC.K0.INIT 0001001100000010 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 F7 +arc: A2 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A6 N1_V01S0100 +arc: A7 H02W0501 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 F3 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010000001110 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K1.INIT 0000110000001101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C35:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A6 H02W0501 +arc: B0 V02N0301 +arc: B2 E1_H02W0301 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 F5 +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1101100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C36:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 F6 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F3 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B2 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 F2 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C38:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 0001010100010000 +word: SLICEC.K1.INIT 0000001100100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 N1_V02S0701 +arc: A4 V00T0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: D0 H02E0201 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100010010000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C3:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R29C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A5 V00B0000 +arc: A6 N1_V01N0101 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000110000001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C41:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V06S0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A5 V02N0301 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 F1 +arc: B6 V00T0000 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 F4 +arc: C6 V00B0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000010101011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 F1 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C43:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A3 V00B0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B3 H02E0301 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 H02E0101 +arc: C0 F6 +arc: C3 V02S0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0001 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C44:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 F3 +arc: B6 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEC.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0000000011110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C45:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 E1_H01W0000 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 H02W0301 +arc: B3 E1_H01W0100 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 F0 +arc: D7 F0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 1010100000100000 +word: SLICEC.K1.INIT 0000000001110100 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICED.K0.INIT 0010001000100011 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C46:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02E0601 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEA.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A3 H02E0501 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D5 N1_V02S0401 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B3 H02E0301 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: E1_H02E0401 Q6 +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C49:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: B1 V02S0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N3_V06N0203 F4 +arc: S1_V02S0401 F6 +arc: V00T0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1110000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C50:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 H00L0100 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 H02W0101 +arc: C0 S1_V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000110000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C51:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V01S0100 +arc: B1 H02E0301 +arc: B3 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 F6 +arc: C3 V02N0601 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D3 S1_V02N0201 +arc: D7 V02S0601 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1011100010111000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C52:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B0 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C53:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A2 E1_H01E0001 +arc: A5 E1_H02W0501 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C54:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F7 +arc: A4 F7 +arc: A5 F7 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B7 V01S0000 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 F4 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0111011101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R29C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V01N0101 +arc: A1 H02E0501 +arc: A3 S1_V02N0701 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B3 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D3 V01S0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K1.INIT 1010110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C56:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A5 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B7 V02N0501 +arc: C0 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F0 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 0101010100111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R29C57:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V02N0701 +arc: A6 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C1 V02S0401 +arc: C3 E1_H01W0000 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D6 H02W0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 F3 +arc: V00B0100 Q5 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R29C58:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0701 +arc: B2 V02S0301 +arc: C2 S1_V02N0401 +arc: D2 H02W0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEB.K0.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 S1_V02N0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 V02N0601 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111110001011100 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 1101111110001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C60:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 F1 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0501 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C61:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 S1_V02N0501 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C3 H00L0000 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M2 N1_V01N0001 +arc: W1_H02W0201 F2 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R29C62:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: B0 V02N0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R29C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V02N0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: H01W0100 Q7 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0401 F6 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C64:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 F7 +arc: A5 F7 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: C0 V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C65:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02E0501 +arc: A5 S1_V02N0101 +arc: B1 W1_H02E0301 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: E1_H01E0101 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C66:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A3 V02S0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 W1_H02E0201 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1101111111010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C67:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B2 E1_H02W0301 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F7 +arc: V01S0100 F0 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEA.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0001010110111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A5 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C5 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 W1_H02E0201 +arc: D4 H01W0000 +arc: D5 V02N0601 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q6 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +arc: V01S0100 Q6 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1010001010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C69:PLC2 +arc: E1_H02E0601 V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V02N0501 +arc: C1 E1_H01W0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C70:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: B3 E1_H02W0101 +arc: C2 N1_V02S0401 +arc: C3 V02N0401 +arc: D3 N1_V01S0000 +arc: F2 F5B_SLICE +arc: M2 H02E0601 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R29C71:PLC2 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 E1_H02W0301 +arc: C3 N1_V02S0401 +arc: C5 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F0 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R29C72:PLC2 +arc: E1_H02E0501 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 V02N0501 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B7 V02N0701 +arc: C1 S1_V02N0401 +arc: C2 F4 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 F7 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F5 +arc: V01S0100 Q7 +arc: W1_H02W0501 F5 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C73:PLC2 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 + +.tile R29C74:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C75:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: C0 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F5 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C76:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V00B0100 +arc: C0 E1_H02W0401 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D5 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C77:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 S1_V02N0501 +arc: A1 V02N0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: A0 F7 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 E1_H02W0501 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: D0 S1_V02N0001 +arc: D1 N1_V02S0001 +arc: D2 H00R0000 +arc: D3 F0 +arc: D5 N1_V02S0601 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F3 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0100110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C79:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 W1_H02E0501 +arc: B0 V02N0301 +arc: C0 W1_H02E0401 +arc: D0 H02W0001 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C80:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00L0100 +arc: A1 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B5 F1 +arc: B6 H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C6 H02W0601 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A7 V00T0100 +arc: B7 W1_H02E0101 +arc: C7 V00T0000 +arc: D7 V02S0601 +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C82:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: A5 V02S0101 +arc: B0 V02S0301 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C83:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A3 V00T0000 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C84:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 1000001011000011 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 V06N0303 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0100 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C87:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 F5 +arc: A3 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 F6 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C88:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B0 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1111010100000000 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEB.K0.INIT 0011010111111111 +word: SLICEB.K1.INIT 0011010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: B0 H00R0100 +arc: B2 H02W0301 +arc: C0 S1_V02N0601 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R29C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B1 V00T0000 +arc: B3 H02W0301 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 W1_H02E0401 +arc: D0 E1_H02W0201 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0101001101010011 +word: SLICED.K0.INIT 0101010111111111 +word: SLICED.K1.INIT 0000111101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R29C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICED.K0.INIT 1000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: B4 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R29C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A2 H02W0501 +arc: B0 V00B0000 +arc: B2 H00R0100 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C6 H02E0401 +arc: D0 E1_H02W0001 +arc: D2 V02S0201 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 H01E0001 +arc: A1 H00R0000 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A7 H02W0701 +arc: B1 W1_H02E0301 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 F1 +arc: B7 V00B0100 +arc: C1 H02W0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C7 V02S0201 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0303 F5 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V00B0100 F5 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 H02E0401 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 H01E0101 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D5 E1_H01W0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C97:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B4 H02E0101 +arc: B6 N1_V02S0701 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C98:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B2 N1_V02S0301 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 F4 +arc: D0 V02S0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F7 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C99:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A2 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 W1_H02E0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 H02W0401 +arc: C2 H00L0000 +arc: C4 F6 +arc: C5 W1_H02E0401 +arc: C6 N1_V02S0201 +arc: C7 V01N0101 +arc: D0 W1_H02E0201 +arc: D2 H02E0201 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 F1 +arc: B1 V02N0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C101:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H01E0001 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 V01N0001 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06N0303 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: B0 F1 +arc: B1 H00R0100 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 N1_V02S0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: D0 H02E0201 +arc: D1 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: W3_H06W0003 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A2 V02S0501 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C104:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A7 N1_V02S0301 +arc: B0 F3 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B5 N1_V02S0701 +arc: B7 F1 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C105:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 E1_H02W0401 +arc: C7 V02S0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 F2 +arc: D6 H02E0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S3_V06S0203 F4 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C106:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B6 F1 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEC.K0.INIT 0010001100000011 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C107:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 H01E0001 +arc: N1_V01N0101 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 S1_V02N0701 +arc: A3 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 H00L0000 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02S0401 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0011001000010000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1010100000100000 +word: SLICED.K0.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C109:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H02E0701 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0401 +arc: C7 H01E0001 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V00B0000 F6 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEA.K1.INIT 1010101100000000 +word: SLICEB.K1.INIT 1010000010001000 +word: SLICED.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C110:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02W0001 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C111:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06W0303 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 F5 +arc: A2 H00L0100 +arc: A5 V02S0301 +arc: A6 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 H00L0000 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 V00T0100 +arc: D5 H02W0001 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F0 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C112:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H01E0001 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 N1_V02S0501 +arc: C2 F4 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0101000001011111 +word: SLICED.K0.INIT 0000010100000011 +word: SLICED.K1.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C113:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F5 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEB.K0.INIT 1011100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C114:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C115:PLC2 +arc: H00L0000 H02W0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F7 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICED.K0.INIT 1111001100000000 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C116:PLC2 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06E0103 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R30C118:PLC2 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0303 E1_H01W0100 + +.tile R30C119:PLC2 +arc: H01W0100 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C120:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R30C13:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0203 S1_V02N0401 + +.tile R30C14:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: B0 V02S0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C15:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010000000100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C16:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 H02W0301 +arc: B4 V02S0501 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1010111000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C17:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00R0000 +arc: A2 E1_H01E0001 +arc: B0 H01W0100 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: C0 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C18:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 V01N0101 +arc: W3_H06W0103 E1_H01W0100 + +.tile R30C19:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: F0 F5A_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C20:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0000 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100000011100010 +word: SLICEA.K1.INIT 1100110011111010 +word: SLICEB.K0.INIT 1010101011111100 +word: SLICEB.K1.INIT 1010000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C21:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 S1_V02N0501 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C22:PLC2 +arc: E1_H02E0201 V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C23:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0501 V06S0303 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B1 V02S0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C24:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0701 F5 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1011100010111000 +word: SLICEC.K1.INIT 0000000000110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C25:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V00B0000 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C26:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06N0203 +arc: A0 V02N0701 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S3_V06S0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C27:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C28:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 W1_H02E0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C29:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06N0103 +arc: N1_V02N0101 H02E0101 +arc: V00T0100 S1_V02N0501 +arc: B0 H01W0100 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C30:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W3_H06E0303 +arc: A0 H02E0701 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C31:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0103 +arc: A3 H02E0701 +arc: B0 E1_H01W0100 +arc: B2 F3 +arc: B3 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: A4 S1_V02N0301 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +word: SLICEC.K1.INIT 0001001100000010 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0011000000110001 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C33:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 F7 +arc: A4 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 H02E0101 +arc: B2 H02W0101 +arc: B4 H02W0101 +arc: B5 F1 +arc: B6 V01S0000 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02S0201 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1100010010000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 F7 +arc: A7 H00R0000 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 N1_V02S0201 +arc: C6 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C35:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C36:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile R30C37:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C38:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 F4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICEB.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C39:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F5 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K0.INIT 0001001100010000 +word: SLICEA.K1.INIT 0001001100010000 +word: SLICEB.K0.INIT 0000011100000100 +word: SLICEC.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C40:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H01E0001 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C41:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 N1_V02S0101 +arc: B1 H02E0101 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 F4 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010001010000000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000010100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C4 H02W0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C43:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 W1_H02E0501 +arc: A4 V00B0000 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B1 V02N0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C1 H02E0601 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D4 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C44:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B3 H00L0000 +arc: B5 F3 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 E1_H02W0001 +arc: D2 W1_H02E0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: V01S0000 F5 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100001100000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R30C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 E1_H02W0001 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C46:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: A7 H00R0000 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q6 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 E1_H01W0100 +arc: B4 F1 +arc: B5 H01E0101 +arc: B6 V00B0100 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEA.K0.INIT 0000001100001010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C48:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: B0 F3 +arc: B1 H00R0100 +arc: B3 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F1 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R30C49:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 N1_V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 S1_V02N0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0100 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F0 +arc: V00B0000 Q6 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F5 +arc: A3 H01E0001 +arc: A4 F5 +arc: A5 V02S0301 +arc: B3 W1_H02E0101 +arc: B4 W1_H02E0101 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: M0 H02E0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: V00B0100 Q5 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 N1_V01S0100 +arc: B1 H02E0301 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: C1 H00L0000 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02S0401 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R30C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C53:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 F5 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0701 +arc: C1 H00R0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q5 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1110010011111111 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 N1_V01N0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0501 F5 +arc: V01S0000 F5 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEC.K1.INIT 0000000001011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R30C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V00T0000 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: C0 F6 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 F2 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C56:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A1 H02E0501 +arc: A3 V02N0701 +arc: A6 V02N0101 +arc: B0 F1 +arc: B1 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: M2 W1_H02E0601 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010001010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R30C57:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 E3_H06W0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 V00T0000 +arc: N1_V02N0001 F0 +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C58:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A4 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D3 H02W0201 +arc: D4 N1_V02S0401 +arc: D6 V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 F1 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1101100011110000 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C59:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A3 V02N0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B5 F1 +arc: B6 F1 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C60:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02W0701 +arc: A4 V02N0101 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B4 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D4 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 H00L0000 +arc: M3 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q3 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C61:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H02W0701 +arc: A5 H02W0501 +arc: B1 H02W0101 +arc: B3 S1_V02N0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q3 +arc: V01S0100 F0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C62:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B5 V02S0501 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 N1_V01N0001 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000001011111 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C63:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 H01E0001 +arc: A5 S1_V02N0101 +arc: B1 H02W0101 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 F4 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0101010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: B0 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C3 N1_V02S0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R30C65:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V01N0001 +arc: H00L0000 V02N0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: C1 S1_V02N0401 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R30C66:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A5 H02E0701 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 H00R0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C5 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 Q3 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 V02S0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0001101100001010 +word: SLICEB.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 1011111110001111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C68:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A3 H02W0501 +arc: A5 V02N0101 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: C1 V02N0401 +arc: C3 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C69:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: B2 H02W0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V00T0100 +arc: D2 W1_H02E0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0001 F2 +arc: N1_V02N0201 F2 +arc: N3_V06N0003 F3 +word: SLICEB.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C71:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 H02W0501 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C3 S1_V02N0601 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C72:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B7 E1_H02W0101 +arc: C2 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C7 H02W0601 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000101000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C73:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B7 S1_V02N0701 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C7 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1001110010010011 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 + +.tile R30C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S1_V02N0201 + +.tile R30C76:PLC2 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 E1_H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C77:PLC2 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A2 V00B0000 +arc: B2 V01N0001 +arc: C0 V02N0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000100000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H02W0701 +arc: A4 V02S0301 +arc: B1 V02S0101 +arc: B4 H02W0101 +arc: C1 E1_H02W0401 +arc: C4 H02W0401 +arc: D1 V00B0100 +arc: D4 H02W0201 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C79:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 N1_V01S0100 +arc: A4 F7 +arc: A7 H02W0701 +arc: B4 N1_V01S0000 +arc: B7 V01S0000 +arc: C4 S1_V02N0201 +arc: C7 H02E0401 +arc: D4 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C80:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02N0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B4 H02W0301 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C4 V02N0201 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C82:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: B0 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q4 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C86:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0501 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 H02W0301 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0201 +arc: C5 W1_H02E0601 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010110010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C87:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0701 +arc: A3 S1_V02N0501 +arc: A6 H00L0000 +arc: B0 V02N0301 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D3 H02W0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEA.K0.INIT 1101100001010000 +word: SLICEB.K1.INIT 1010111100000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C88:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 H02E0701 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C89:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C3 N1_V02S0401 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0001 +arc: D5 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0701 F5 +arc: V01S0000 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C90:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V06N0203 +arc: A0 N1_V02S0501 +arc: A1 V02S0501 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0301 +arc: A7 H02W0501 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 N1_V02S0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 N1_V02S0601 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: S3_V06S0203 F7 +word: SLICEC.K1.INIT 1101000001010000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICED.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R30C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B5 H00L0000 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: M4 V00T0100 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 0001010100000000 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000000001010 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R30C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0701 +arc: A1 F7 +arc: A3 H02E0701 +arc: A4 S1_V02N0301 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1000000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 V06S0203 +arc: A0 S1_V02N0701 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 H01E0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A6 V00T0100 +arc: B2 W1_H02E0101 +arc: B6 H02W0301 +arc: C2 H00L0100 +arc: C6 V01N0101 +arc: D2 H02W0001 +arc: D6 E1_H01W0100 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C3 F6 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 F0 +arc: D5 V00B0000 +arc: D6 N1_V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C0 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D0 H02W0001 +arc: D1 F0 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1001100100000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V01N0101 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 F0 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +arc: S1_V02S0501 F7 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00R0000 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 H01E0001 +arc: D0 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 W1_H02E0601 +arc: M4 V00B0100 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C99:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 N1_V02S0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 W1_H02E0701 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 H00R0100 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F7 +arc: N1_V02N0101 F3 +arc: S3_V06S0003 F0 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 0100010001000100 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C100:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 F3 +arc: B6 F1 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0201 +arc: D0 V02S0001 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 F0 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C101:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: W1_H02W0101 F1 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 V02S0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 F0 +arc: D6 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: V00T0100 F3 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C103:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02W0201 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H00L0000 +arc: A5 H02W0701 +arc: B1 V00T0000 +arc: B5 V00B0100 +arc: C1 N1_V02S0401 +arc: C5 V00T0100 +arc: D1 N1_V02S0201 +arc: D5 E1_H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: V01S0000 F1 +arc: V01S0100 F5 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0401 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: D0 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 N1_V02S0401 +arc: D5 H00L0100 +arc: D6 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C105:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: A2 E1_H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 H02W0101 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 F5 +arc: A3 V00T0000 +arc: A5 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 H00L0000 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: C7 V00T0100 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 V02S0001 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C107:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 V02S0301 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F7 +arc: S1_V02S0301 F3 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0011001000000010 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 1010100000001000 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R31C108:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H02W0501 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q2 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C109:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 H02E0201 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A1 H02E0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C4 V02N0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C110:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 F4 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100100000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C111:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H01E0001 +arc: A5 V02S0301 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 F3 +arc: S3_V06S0103 F2 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100000011110000 +word: SLICEC.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICED.K1.INIT 0101010100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R31C112:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q6 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R31C113:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02N0701 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEA.K0.INIT 1010000010110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C114:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H02W0201 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C115:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V06S0303 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V00B0000 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B7 H02E0301 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V02S0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V01S0100 F2 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICEB.K1.INIT 1010100000100000 +word: SLICEB.K0.INIT 1111000000010000 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICED.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R31C116:PLC2 +arc: N1_V02N0001 H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile R31C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C118:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R31C119:PLC2 +arc: W3_H06W0003 E1_H01W0000 + +.tile R31C120:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R31C13:PLC2 +arc: E3_H06E0103 V01N0101 + +.tile R31C14:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0201 +arc: A4 V00T0000 +arc: B2 V01N0001 +arc: B4 V02N0501 +arc: B7 V00B0000 +arc: C4 V02N0001 +arc: C7 V01N0101 +arc: D2 V02N0201 +arc: D4 F2 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +word: SLICEC.K0.INIT 0101111100010011 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEB.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R31C15:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 H02W0401 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0100 V02N0501 +arc: A1 H00R0000 +arc: A3 H01E0001 +arc: A5 H02E0501 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B5 H01E0101 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C5 V01N0101 +arc: D1 V00T0100 +arc: D5 V01N0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 0000111100001000 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEC.K1.INIT 0000000100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C16:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 N1_V01S0000 +arc: A2 V01N0101 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 F4 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEA.K0.INIT 0011000000000000 +word: SLICED.K0.INIT 1100000011000000 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 0111011100000111 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R31C17:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V02N0401 +arc: A0 H02E0701 +arc: A2 V00T0000 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F7 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0111000001110111 +word: SLICED.K0.INIT 0000000000000010 +word: SLICEA.K0.INIT 0101000111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C18:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 0011111100010101 +word: SLICEB.K0.INIT 0100110011000100 +word: SLICED.K1.INIT 0011111100010101 +word: SLICED.K0.INIT 0011000111110101 +word: SLICEC.K0.INIT 0011000111110101 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0000000000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C19:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0601 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R31C20:PLC2 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A5 V00T0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0101 +arc: B5 V01S0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D5 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C21:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0701 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: E1_H01E0001 F6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R31C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q3 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R31C23:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 V02N0501 +arc: A3 F7 +arc: A5 V02N0301 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B4 H02E0301 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000000100110001 +word: SLICEB.K1.INIT 1111000010100000 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R31C24:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F4 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C25:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C26:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: B2 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C27:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: B0 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C28:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: V00T0000 V02S0601 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C30:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 H02E0101 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C31:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B2 F3 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 W1_H02E0201 +arc: D3 V02S0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C32:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: S3_V06S0203 F7 +arc: V00T0100 F3 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C33:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A1 H00L0100 +arc: A3 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A7 W1_H02E0501 +arc: B0 E1_H01W0100 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000010101000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 H02W0501 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D2 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +word: SLICED.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEA.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C35:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 H01E0001 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: B1 H02E0301 +arc: B3 H02E0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H00L0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 F3 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C37:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: B1 V00B0000 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: C1 H02E0601 +arc: C4 V02N0001 +arc: C5 F6 +arc: D1 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1000100010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C39:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A3 W1_H02E0501 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 H02E0501 +arc: B0 N1_V02S0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: B7 H02E0101 +arc: C0 V02S0601 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 H01E0001 +arc: C7 S1_V02N0001 +arc: D0 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 V01S0100 +arc: D4 F0 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101000001011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C40:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B6 F1 +arc: B7 V02N0501 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D6 F2 +arc: D7 V02S0401 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F4 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICED.K1.INIT 0000011100000100 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0101000001010001 +word: SLICEC.K0.INIT 0011000000110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 N1_V02S0501 +arc: A2 V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V02S0301 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: B0 F3 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 N1_V02S0001 +arc: D4 F2 +arc: D6 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: V01S0100 F4 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010010000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1110010011100100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 + +.tile R31C42:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B6 F3 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C43:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C44:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 V02S0501 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00B0100 +arc: D0 S1_V02N0001 +arc: D1 H01E0101 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F7 +arc: V01S0000 F5 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C45:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0701 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B1 E1_H02W0101 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C1 N1_V01S0100 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H01W0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C46:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F7 +arc: N3_V06N0103 F1 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1001000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C47:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 F1 +arc: B4 N1_V02S0501 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0001 F2 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C7 V00T0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 F0 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 F5 +arc: A1 H02E0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C50:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V00T0000 +arc: B0 V00T0000 +arc: C0 E1_H01W0000 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R31C52:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0100 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: B0 V01N0001 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: C0 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C53:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: B0 V02N0101 +arc: B4 H02W0101 +arc: C0 E1_H01W0000 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: V00B0100 Q5 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010100000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 V01N0001 +arc: A1 W1_H02E0501 +arc: A2 V01N0101 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 N1_V01N0101 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1001100100001001 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1101111111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 H02W0701 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C56:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 N1_V02S0501 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1100101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C58:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111011111010101 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R31C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 H01W0100 +arc: B2 H02E0101 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0001000010111010 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C60:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: C0 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 1011111110110011 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R31C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B2 H02W0101 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D2 W1_H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 V01N0101 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N3_V06N0103 F2 +arc: V01S0100 Q7 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000111100100010 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B4 S1_V02N0501 +arc: B6 V02S0701 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C64:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: B0 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: D0 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1110000000100000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C65:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 N1_V01S0000 +arc: A5 S1_V02N0301 +arc: A7 H02W0501 +arc: B0 E1_H02W0301 +arc: B3 V02S0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D7 V01N0001 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 F2 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0501 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 W1_H02E0101 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: S1_V02S0201 F2 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R31C67:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 H02W0701 +arc: A5 W1_H02E0701 +arc: A6 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 W1_H02E0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001000101010101 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R31C68:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A3 V02S0501 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B5 H02W0301 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C69:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A5 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B3 V02N0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 N1_V02S0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C70:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F4 +arc: V00T0000 F0 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R31C71:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06N0303 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: B0 H02W0301 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 0011000001010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101010000010000 +word: SLICEB.K0.INIT 0010001000001010 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C72:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V00B0100 F5 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000001000001 +word: SLICED.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0101000000110000 +word: SLICEA.K1.INIT 0000001000000001 +word: SLICED.K1.INIT 0101000001000100 +word: SLICEC.K1.INIT 0000101000100010 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C73:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A2 S1_V02N0701 +arc: A3 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D6 F0 +arc: D7 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010010111000011 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1101100000100111 +word: SLICEA.K1.INIT 1101100000100111 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C74:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0301 + +.tile R31C75:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 + +.tile R31C76:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: A2 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: C0 H02W0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H00R0000 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C77:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B6 V00B0100 +arc: C0 H00R0100 +arc: C6 V02S0201 +arc: D0 N1_V02S0201 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0111000011110000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C78:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A6 V02N0301 +arc: B0 V02N0101 +arc: C0 F6 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02S0601 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C79:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 N1_V01S0100 +arc: A3 E1_H02W0501 +arc: B3 V02N0301 +arc: C3 H00L0000 +arc: D3 H02W0201 +arc: F3 F3_SLICE +arc: N1_V01N0001 F3 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C80:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A5 V00T0100 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 Q5 +arc: V01S0100 F6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +word: SLICEC.K0.INIT 1101100001010000 +word: SLICEC.K1.INIT 1110010001000100 +word: SLICED.K0.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010110010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C82:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 V06N0303 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A6 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B5 V02S0501 +arc: C0 S1_V02N0401 +arc: C2 H02W0601 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICED.K0.INIT 1111000001010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +word: SLICEB.K0.INIT 1100110000001100 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C84:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 S1_V02N0101 +arc: A5 N1_V01S0100 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C86:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 W1_H02E0301 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0201 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1101110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C87:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 E1_H02W0101 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1110010011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C88:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A6 F7 +arc: A7 V02S0301 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B4 H02E0101 +arc: B6 F1 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C4 V02N0001 +arc: C6 F4 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C89:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02E0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 V00B0000 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C3 H02W0401 +arc: C5 F6 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 F7 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 F3 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0601 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 W1_H02E0701 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B3 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R31C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00L0000 +arc: A5 N1_V02S0301 +arc: B5 H00R0000 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C5 V00T0100 +arc: D0 H02E0201 +arc: D1 N1_V02S0201 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R31C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A3 W1_H02E0501 +arc: A6 H00R0000 +arc: B1 H02W0301 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C6 V00T0100 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: N1_V02N0601 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C94:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 V06N0203 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 F1 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 F4 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N3_V06N0203 F7 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1101000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 V02S0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 F3 +arc: B3 N1_V02S0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: D0 V00T0100 +arc: D1 N1_V02S0001 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 W1_H02E0501 +arc: A2 V02S0501 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A5 F7 +arc: A7 H02W0701 +arc: B0 H02E0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 N1_V01S0000 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H01W0000 +arc: E1_H02E0001 F0 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0401 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0601 F4 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1101110100001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A2 H02W0501 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 W1_H02E0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B2 W1_H02E0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 N1_V02S0501 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +arc: V00T0000 F2 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: B0 F3 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C102:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 W1_H02E0201 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A5 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 S1_V02N0501 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C5 N1_V02S0001 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D5 H00L0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0100 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1000100001000100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C104:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 S1_V02N0501 +arc: A1 F7 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B1 F3 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V02N0401 F4 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R32C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 H02E0701 +arc: A5 V02S0101 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 H00L0000 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 H02E0601 +arc: D0 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C106:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C4 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D4 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R32C107:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 H02W0301 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 F6 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V02N0201 F0 +arc: S1_V02S0001 F2 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C108:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 F7 +arc: A4 H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0101 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0203 F4 +arc: V01S0000 F6 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 1010101000000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C110:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V01N0101 +arc: A3 H02W0701 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 H00R0000 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V02S0701 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C111:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02E0201 +arc: D4 N1_V02S0401 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F7 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000111101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 E1_H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: A1 E1_H02W0501 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000111100110011 +word: SLICED.K1.INIT 0011001000010000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011000000111111 +word: SLICED.K0.INIT 0000000100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C113:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V06S0303 +arc: A1 N1_V02S0701 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 N1_V01S0100 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0000000000001010 +word: SLICEB.K1.INIT 1000100010001100 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 1010000010100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C114:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 F5 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0000000011100010 +word: SLICEB.K0.INIT 1111000100000000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 0000010100000011 +word: SLICEA.K0.INIT 0000001100000000 +word: SLICEA.K1.INIT 1100010011000000 +word: SLICEB.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C115:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01S0100 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 0000000000110000 +word: SLICEC.K1.INIT 1000110010001000 +word: SLICEB.K0.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C116:PLC2 +arc: N3_V06N0003 W3_H06E0003 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 V06N0203 + +.tile R32C117:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 + +.tile R32C118:PLC2 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 + +.tile R32C13:PLC2 +arc: S1_V02S0201 H06W0103 +arc: B5 H02W0301 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 0011001100000011 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R32C14:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 E1_H02W0201 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 F7 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 0000010100000000 +word: SLICEC.K1.INIT 0000010100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 0101011100100000 +word: SLICEA.K1.INIT 0000001111001100 +word: SLICEB.K0.INIT 0101011100100000 +word: SLICEB.K1.INIT 0100011001001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C15:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: M2 V00T0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F1 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 0000000011101100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 0000000000010000 +word: SLICEA.K0.INIT 0100010100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0000011100000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000100110011 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C16:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 W1_H02E0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 F3 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H01E0101 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010000011101100 +word: SLICEB.K1.INIT 0000000001110000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICEB.K0.INIT 1111111110100000 +word: SLICED.K0.INIT 1111100011111010 +word: SLICED.K1.INIT 0000100000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C17:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: A1 H02E0501 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H00R0100 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0601 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 F5 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F4 +arc: V00B0100 Q5 +arc: V01S0000 Q7 +arc: V01S0100 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111111111001100 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 0000110010101100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111110100000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R32C18:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 V06N0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +arc: S1_V02S0101 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0011101000001010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 0111010000110000 +word: SLICEC.K0.INIT 1111101011111010 +word: SLICEC.K1.INIT 0101110000001100 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 0000110010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A1 H02E0701 +arc: B1 V02N0101 +arc: C1 V02N0401 +arc: D1 V02N0001 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C20:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: B1 Q1 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D3 V02N0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0101101000001010 +word: SLICEA.K1.INIT 1010110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C21:PLC2 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C5 V00T0100 +arc: C6 H01E0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000000001000111 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000011101111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R32C22:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 N1_V02S0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: S3_V06S0003 Q3 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R32C23:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 V00B0000 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B7 F1 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000100110001 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K1.INIT 0000000000100111 +word: SLICED.K1.INIT 1111000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C24:PLC2 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: B1 H02E0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 W1_H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 F3 +arc: V01S0000 F5 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0100000001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C25:PLC2 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: A7 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1111110010101100 +word: SLICEB.K0.INIT 1011001110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C26:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 V01N0101 +arc: A2 F7 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C2 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0100011100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001000010110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C27:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 V02S0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C28:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000111000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C29:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R32C30:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: A5 Q5 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C31:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: B0 S1_V02N0301 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C32:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0301 V06N0003 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 F1 +arc: B7 F3 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 F0 +arc: D6 V02S0601 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0101000001010001 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 0101000001010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C33:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B4 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D4 H02W0201 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000101011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 E1_H02W0701 +arc: A3 V02S0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0101110001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C35:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 H02E0501 +arc: A5 V02S0301 +arc: A7 F5 +arc: B0 V01N0001 +arc: B1 H02W0301 +arc: B2 N1_V02S0301 +arc: B3 H00L0000 +arc: B5 V00B0100 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V02S0201 +arc: D5 S1_V02N0401 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F2 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 F0 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 N1_V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICED.K1.INIT 0000000000101110 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C37:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B0 V02N0101 +arc: B2 W1_H02E0301 +arc: B3 H01W0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 F3 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 V02S0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: V00B0100 F5 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010010100000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V02N0501 +arc: A2 W1_H02E0701 +arc: A5 S1_V02N0301 +arc: A6 N1_V01S0100 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 F1 +arc: B5 H00L0000 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C2 V02S0401 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0000010000001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C39:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A5 H02W0701 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 V02S0301 +arc: B5 V02N0701 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: D0 N1_V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D5 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F5 +arc: V00T0100 F3 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000001111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R32C40:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V01N0101 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0100 F2 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0000111100000001 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEC.K1.INIT 0000101000001011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 S1_V02N0501 +arc: A3 V02S0501 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 F4 +arc: C7 N1_V02S0001 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 H02E0201 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0101 F1 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICEA.K0.INIT 0001001100000010 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1011000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C42:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000000001110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R32C43:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A3 H00L0100 +arc: A5 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B3 H02E0301 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 V02S0401 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: D0 V01S0100 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000011110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 F7 +arc: A2 V02S0501 +arc: A4 V00T0100 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 F1 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +arc: V00T0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 F1 +arc: B5 H00R0000 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEB.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEC.K0.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C47:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: B0 H02E0101 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M1 H00L0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010001010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C49:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02N0501 +arc: A5 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B5 V02N0501 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 H00R0000 +arc: D5 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C50:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B5 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02W0601 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C51:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A5 H02E0701 +arc: B0 V02N0101 +arc: B1 N1_V02S0301 +arc: B5 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C52:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 V02N0501 +arc: A5 H02W0701 +arc: B1 V02N0101 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: C1 V02S0401 +arc: C3 H02E0401 +arc: C5 V00B0100 +arc: D1 H02W0201 +arc: D3 V02S0201 +arc: D5 V01N0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V02N0101 F1 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000011111110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C53:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: N1_V01N0101 F2 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C54:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 E1_H02W0501 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 F1 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C55:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q7 +arc: M0 H02E0601 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V02N0401 F4 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011101000111010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1010000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C56:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02W0501 +arc: A4 N1_V01N0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B5 W1_H02E0301 +arc: B7 V02N0701 +arc: C3 H00L0100 +arc: C5 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0100 Q5 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C57:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 0100011101110111 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1011100011111111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A5 E1_H02W0701 +arc: B2 V01N0001 +arc: B5 H02W0101 +arc: C2 H02E0601 +arc: C5 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D5 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C59:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B0 V01N0001 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0301 F1 +arc: S1_V02S0601 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1111011110110011 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C60:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06N0203 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0501 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 Q6 +arc: W1_H02W0601 F4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C61:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B2 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F0 +arc: V00B0000 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A3 F7 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B4 H00L0000 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: C0 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1010000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C63:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 H02W0301 +arc: C2 V02S0601 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C64:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C65:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: B0 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q4 +arc: W1_H02W0601 F6 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C66:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: A1 V02N0501 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 V00T0100 +arc: B0 V02S0301 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 Q5 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1110000000100000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C67:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B5 E1_H02W0101 +arc: B6 H01E0101 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R32C68:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A3 H02E0501 +arc: A5 S1_V02N0301 +arc: B3 H00R0100 +arc: B5 S1_V02N0501 +arc: C3 S1_V02N0401 +arc: C5 V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H02E0701 +arc: A3 V00T0000 +arc: A7 N1_V01N0101 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: B5 H02E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICED.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C70:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H00R0000 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 F4 +arc: M1 H00L0000 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 F7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000010100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 V02S0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V01S0100 Q6 +arc: W1_H02W0401 F4 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000000000100001 +word: SLICEC.K1.INIT 0011011011000110 +word: SLICED.K0.INIT 0100000000000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C72:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 V00B0100 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02W0601 +arc: N1_V01N0101 F0 +arc: V00T0100 F3 +arc: W1_H02W0501 F7 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000001000001 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 0011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R32C73:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 V02S0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D3 V02N0001 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 W1_H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0100 F3 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 1001110010010011 +word: SLICEA.K0.INIT 1010100101011001 +word: SLICED.K1.INIT 1011010010000111 +word: SLICEC.K1.INIT 1100101000110101 +word: SLICED.K0.INIT 1001101010010101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 H01E0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D4 H02W0001 +arc: D5 F2 +arc: D6 H02E0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1110001000011101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C75:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A4 H02W0501 +arc: A7 H00R0000 +arc: B1 V02N0301 +arc: B2 H02W0301 +arc: B7 F1 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C7 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D4 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0100010000001100 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICED.K1.INIT 0011000100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R32C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 N1_V02S0701 +arc: A5 N1_V02S0101 +arc: B1 H02E0301 +arc: B5 S1_V02N0501 +arc: C1 N1_V01S0100 +arc: C5 V02S0201 +arc: D1 V00B0100 +arc: D5 H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C77:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H02W0501 +arc: A4 N1_V02S0101 +arc: B1 H02W0101 +arc: B4 N1_V02S0701 +arc: C1 H02E0401 +arc: C4 V02N0001 +arc: D1 V00B0100 +arc: D4 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C78:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: B1 H02W0301 +arc: C1 H02E0401 +arc: D1 S1_V02N0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R32C79:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C80:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 + +.tile R32C81:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02S0501 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: B1 V02N0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0601 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R32C82:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02S0501 +arc: A1 N1_V02S0701 +arc: A3 W1_H02E0501 +arc: B1 H02E0101 +arc: B3 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C83:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R32C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06S0203 +arc: A0 H00R0000 +arc: A5 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B5 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C85:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V02N0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 W1_H02E0201 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C86:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B3 H00R0100 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V00T0000 F2 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1111000000110000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F6 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0100 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 H00L0100 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B4 V00B0100 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R32C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 F1 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 N1_V02S0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V01S0100 +arc: D2 H02W0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R32C91:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06S0203 +arc: A0 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H01W0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 1101000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C92:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 H01E0101 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 V02S0601 +arc: C4 H02W0601 +arc: C5 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: N1_V01N0101 F2 +arc: V01S0000 F5 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R32C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B1 H01W0100 +arc: B5 H02E0101 +arc: C1 V02S0601 +arc: C5 S1_V02N0001 +arc: C7 V00B0100 +arc: D1 E1_H02W0201 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V00B0100 F5 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000001010000 +word: SLICEA.K1.INIT 1000101011001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C4 W1_H02E0401 +arc: C5 S1_V02N0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: S1_V02S0201 F0 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1000101000001010 +word: SLICEC.K0.INIT 1000000011110000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R32C95:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: C0 H02W0601 +arc: C2 W1_H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 H02W0301 +arc: B2 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 W1_H02E0601 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0101 F0 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 F5 +word: SLICED.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0011001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R32C97:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 F7 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 N1_V02S0101 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0201 +arc: D0 V02N0001 +arc: D2 H02W0001 +arc: D3 V02S0201 +arc: D4 W1_H02E0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0701 F5 +arc: V01S0000 F2 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 V01N0101 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 H01W0100 +arc: B2 F3 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 W1_H02E0701 +arc: A2 N1_V02S0501 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0601 F4 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 F1 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 F6 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F0 +arc: S1_V02S0501 F5 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A2 F7 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 F0 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F5 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C102:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 W1_H02E0101 +arc: C0 N1_V02S0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00L0000 +arc: A2 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 H02W0501 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C1 V02S0401 +arc: C2 F4 +arc: C4 V00T0000 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: S1_V02S0301 F1 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICEA.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C104:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 W1_H02E0501 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 E1_H02W0501 +arc: B0 F3 +arc: B1 H02E0301 +arc: B2 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 F7 +arc: S1_V02S0401 F6 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C106:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 E1_H02W0101 +arc: B7 V00B0000 +arc: C1 H00L0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D1 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C107:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00R0000 +arc: A3 F5 +arc: A4 N1_V01S0100 +arc: A5 E1_H02W0501 +arc: A6 F7 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 V02S0401 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEB.K1.INIT 1111000100000000 +word: SLICEA.K1.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C108:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F5 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F4 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C109:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0101 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 V00B0100 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 W1_H02E0601 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C110:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02N0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0601 +arc: D1 W1_H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N3_V06N0203 F4 +arc: V00B0100 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1010001010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C111:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 F7 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000100000100010 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICED.K0.INIT 1010101000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C112:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0701 +arc: A1 W1_H02E0501 +arc: A2 V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000000101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C113:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1100111111001010 +word: SLICEC.K1.INIT 1111111111101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R33C114:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 F7 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C115:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEC.K1.INIT 0000000000000101 +word: SLICEB.K0.INIT 1010101000000010 +word: SLICEC.K0.INIT 1000110010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C116:PLC2 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N1_V01S0000 +arc: A6 S1_V02N0301 +arc: B6 E1_H02W0101 +arc: D6 V02N0401 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: N1_V02N0601 F6 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1011101100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R33C117:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 S1_V02N0501 + +.tile R33C118:PLC2 +arc: W1_H02W0101 S1_V02N0101 + +.tile R33C13:PLC2 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0601 H02W0601 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 F7 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0001 +arc: D1 H01E0101 +arc: D3 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 0000111100001101 +word: SLICEA.K1.INIT 0000101000001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111100100010 +word: SLICED.K1.INIT 0000000000000101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000011111110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C15:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C5 H02E0401 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111111111111100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000010001 +word: SLICEC.K1.INIT 0000000000010011 +word: SLICEA.K0.INIT 1111100011110000 +word: SLICED.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 1111010111111101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C16:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 S1_V02N0301 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B1 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02E0201 +arc: D7 N1_V02S0401 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0000000011010000 +word: SLICEB.K1.INIT 0111000001110000 +word: SLICEA.K1.INIT 1011111100000000 +word: SLICEC.K0.INIT 0001010100000000 +word: SLICEC.K1.INIT 0011111100000000 +word: SLICED.K0.INIT 0000000001010001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0011000100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C17:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 0000110000000100 +word: SLICEB.K1.INIT 0100010011001100 +word: SLICEC.K0.INIT 0011000100000000 +word: SLICEC.K1.INIT 0101111100000000 +word: SLICED.K1.INIT 0100110001011111 +word: SLICEA.K0.INIT 1100111011001100 +word: SLICED.K0.INIT 1000100010001000 +word: SLICEA.K1.INIT 1111001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R33C18:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 V06N0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0100010100000000 +word: SLICEA.K1.INIT 0011111100000000 +word: SLICEB.K0.INIT 1010000010100000 +word: SLICEB.K1.INIT 1110110011101110 +word: SLICEC.K0.INIT 0000100000001100 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICED.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 0000000010110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C19:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0101 +arc: A1 F5 +arc: A5 V00T0100 +arc: B5 E1_H02W0301 +arc: C1 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 V02S0001 +arc: D5 E1_H02W0001 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: W1_H02W0101 F1 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C20:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 V02N0501 +arc: A6 E1_H01W0000 +arc: B0 F3 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 0101110110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C21:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 H01E0001 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1111001000100010 +word: SLICEC.K1.INIT 1111001000100010 +word: SLICED.K0.INIT 1111010001000100 +word: SLICED.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C22:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02W0301 +arc: M2 E1_H02W0601 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000111100001101 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000111100001011 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0101010101010001 +word: SLICED.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R33C23:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 V02N0501 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R33C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: A2 H02E0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 W1_H02E0101 +arc: B3 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 F2 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 0000000101000101 +word: SLICEC.K1.INIT 1111000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R33C25:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02W0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A6 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C26:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 V06S0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 F7 +arc: N3_V06N0203 Q4 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C27:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C28:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 W1_H02E0101 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F1 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0100011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C29:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C2:PLC2 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 S1_V02N0201 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R33C30:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q3 +arc: S3_V06S0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C32:PLC2 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 F3 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D6 E1_H02W0201 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0303 F6 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C33:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 F7 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C34:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 H01E0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F7 +arc: V00T0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEA.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 F5 +arc: A2 V01N0101 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01S0100 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 0000000011001101 +word: SLICEB.K0.INIT 0000010101000100 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEA.K1.INIT 0000110000001101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0001 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F7 +arc: V00B0000 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1000100011000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C37:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 V06N0203 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100010010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C38:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +arc: W1_H02W0201 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C2 F4 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C7 E1_H02W0601 +arc: D0 N1_V02S0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C3:PLC2 +arc: W1_H02W0701 S1_V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C40:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0501 +arc: A4 V02N0301 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C41:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A3 V02S0701 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V01S0000 +arc: D3 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000001000110010 +word: SLICED.K1.INIT 0001010100010000 +word: SLICED.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F4 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1010000010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V02N0301 F3 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C45:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0201 +arc: D0 E1_H02W0001 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M4 V00T0100 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000001011000011 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A7 N1_V01N0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 W1_H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: M0 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0000 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1100000000110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C47:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A6 F7 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0100 F6 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C48:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 H02W0701 +arc: A6 H02E0501 +arc: B1 S1_V02N0101 +arc: B6 V02N0501 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0000 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q4 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A3 H02W0501 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0201 Q0 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C4:PLC2 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A3 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B1 H01W0100 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D5 F0 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F1 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICED.K0.INIT 1100100001000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C52:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A7 V02N0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 H02W0101 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B7 V02S0501 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: M2 N1_V01N0001 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V00T0000 Q2 +arc: V01S0000 F2 +arc: V01S0100 Q2 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 F3 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1110110001001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0000 +arc: A5 V02S0301 +arc: B3 V02S0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B3 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C4 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q4 +arc: V00B0000 F4 +arc: V01S0000 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C56:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A3 V02N0701 +arc: A5 V02S0101 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B6 F1 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02S0501 +arc: A3 E1_H02W0701 +arc: A4 V02S0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 0001110100111111 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C4 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D7 S1_V02N0401 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0701 F7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A6 H00R0000 +arc: B0 E1_H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R33C5:PLC2 +arc: B0 V00T0000 +arc: B1 Q1 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R33C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 H02W0701 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C61:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 S1_V02N0301 +arc: B0 H02W0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: C0 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: C5 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: D7 V00B0000 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C62:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q3 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0401 F6 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 V02S0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 F3 +arc: V00T0100 F1 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1011000010000000 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 1111111110111000 +word: SLICEB.K0.INIT 1111000011101110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02S0701 +arc: A4 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0401 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A5 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B3 V02S0301 +arc: B5 H00L0000 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 Q6 +arc: S1_V02S0701 Q7 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0100 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100010010000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C66:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0701 +arc: A5 N1_V02S0101 +arc: A7 N1_V01N0101 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B2 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C1 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: M0 H02E0601 +arc: M4 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C68:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R33C69:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02N0101 +arc: B0 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D5 W1_H02E0001 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C70:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 V02N0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: A1 H02W0501 +arc: A2 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 V02N0301 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C1 N1_V02S0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K0.INIT 0010001100100000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C71:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A3 F5 +arc: A4 H02W0701 +arc: A6 V02N0101 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 0000000000110001 +word: SLICEA.K1.INIT 0011000100000000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001000000000001 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C72:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H02W0501 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V01S0000 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C73:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V01N0101 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 H02W0501 +arc: B0 H00R0100 +arc: B1 H01W0100 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K0.INIT 0000001010100010 +word: SLICEA.K1.INIT 0000001000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0000000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R33C74:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B3 H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F6 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0011000000100010 +word: SLICEC.K1.INIT 0000000000100001 +word: SLICEA.K1.INIT 0000101000100010 +word: SLICEA.K0.INIT 0000010000000001 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A2 V02N0701 +arc: A4 F7 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B7 V00B0100 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 N1_V02S0001 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: H01W0100 Q7 +arc: M0 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0100 F3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000101000100010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C76:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02E0701 +arc: A1 E1_H02W0501 +arc: A3 V02S0501 +arc: A4 N1_V02S0301 +arc: A6 V02S0301 +arc: B2 H02E0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R33C77:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F7 +arc: A2 F5 +arc: A4 H02E0501 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 H00R0100 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H00L0100 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D2 H02E0201 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0100010001000100 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B1 H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0301 +arc: B7 V02N0501 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F0 +arc: S1_V02S0601 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1010010111000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C79:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V06S0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: A3 V00B0000 +arc: A5 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1001000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C80:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H02W0701 +arc: B1 E1_H02W0101 +arc: C1 H02W0401 +arc: D1 V00B0100 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0101 +arc: B1 F3 +arc: B2 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C82:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 N1_V02S0701 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F5 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R33C83:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C84:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02W0501 +arc: A2 V02S0701 +arc: A5 S1_V02N0301 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 Q4 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 F7 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEC.K1.INIT 1011101100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 V02S0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010010100000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0203 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V00B0000 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C88:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A5 H02E0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0303 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 S1_V02N0701 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 V00T0000 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0401 F4 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100001100000000 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000100000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A5 V02N0101 +arc: A6 N1_V02S0301 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B2 F3 +arc: B3 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C5 V02S0001 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: D0 V01S0100 +arc: D1 V02S0201 +arc: D2 F0 +arc: D3 N1_V01S0000 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 H02W0401 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: V01S0000 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R33C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 W1_H02E0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0501 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: N1_V02N0601 F6 +arc: V01S0000 F7 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0001101100011011 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 1101111111001100 +word: SLICED.K1.INIT 0001000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 N1_V02S0501 +arc: A6 H00R0000 +arc: A7 N1_V01S0100 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: N1_V01N0101 F0 +arc: V01S0000 F2 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000001111110011 +word: SLICED.K0.INIT 0100110001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R33C94:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 V02N0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0401 +arc: D0 H02E0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F0 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A4 S1_V02N0301 +arc: A5 N1_V02S0301 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 V02S0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 0111011101110111 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 S1_V02N0501 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 E1_H01E0001 +arc: A4 H02W0701 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 F6 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +arc: V00T0000 F0 +arc: V01S0000 F2 +arc: W1_H02W0301 F1 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H02W0701 +arc: A1 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 H02W0501 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 V02S0501 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F7 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C98:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 S1_V02N0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 F1 +arc: B7 W1_H02E0101 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010010000100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C99:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A1 H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F7 +arc: N1_V01N0001 F3 +arc: S1_V02S0301 F1 +arc: V00B0000 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D2 W1_H02E0001 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 F7 +arc: A3 N1_V02S0501 +arc: A4 N1_V01N0101 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 N1_V02S0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C1 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F4 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000100001000100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C103:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 F1 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: C7 V01N0101 +arc: D0 V02S0201 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: S3_V06S0203 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C104:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A5 N1_V01S0100 +arc: A7 F5 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B7 F3 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C7 E1_H01E0101 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D7 H01W0000 +arc: E1_H01E0101 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 W1_H02E0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 F6 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C106:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 V02S0201 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 H02W0701 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B2 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C2 V02S0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: D0 H02E0001 +arc: D2 V00B0100 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: S1_V02S0401 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C107:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H01W0000 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 1010001010000000 +word: SLICEB.K0.INIT 1100110100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 N1_V02S0701 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICEC.K0.INIT 1100110100000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C109:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 V02S0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 F0 +arc: D3 N1_V02S0201 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F2 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 0000000000000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R35C110:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V02S0601 +arc: C1 H00R0100 +arc: C2 F4 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C111:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0501 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 W1_H02E0101 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 H02W0601 +arc: D0 N1_V02S0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F5 +word: SLICEA.K0.INIT 1110000000100000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B4 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q6 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C113:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H00L0100 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 F6 +arc: C3 W1_H02E0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0701 F5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C114:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C115:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A3 F5 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C5 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D5 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C116:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A0 H02W0501 +arc: B0 H02E0101 +arc: B2 H02E0101 +arc: C0 S1_V02N0601 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F2 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R35C117:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C118:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile R35C14:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: A1 N1_V02S0501 +arc: B1 E1_H01W0100 +arc: C1 E1_H02W0601 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 1101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C15:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 F6 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 0000000000100010 +word: SLICEC.K1.INIT 1100110011001110 +word: SLICEB.K0.INIT 0000000000000111 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K1.INIT 0000001100010011 +word: SLICEA.K0.INIT 1010101110101010 +word: SLICED.K0.INIT 0000000000101010 +word: SLICEA.K1.INIT 1111100011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C16:PLC2 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 W1_H02E0201 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000011110011 +word: SLICEA.K1.INIT 0000000000111011 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICED.K1.INIT 0011000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R35C17:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 W1_H02E0301 +arc: C1 V02S0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: D0 W1_H02E0201 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +word: SLICEB.K0.INIT 0111011100000000 +word: SLICEB.K1.INIT 0000110100000000 +word: SLICEA.K0.INIT 0000000001010101 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1111111100111111 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R35C18:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 H00L0100 +arc: A5 S1_V02N0301 +arc: A6 N1_V02S0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02S0601 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 F4 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1100110011001010 +word: SLICEC.K1.INIT 0000101100000000 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICED.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEB.K1.INIT 0000000000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C19:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: A7 H00L0000 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0701 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 0000111100001000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C20:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 V01N0101 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1011101000110000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1011101000110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111001000100010 +word: SLICEB.K1.INIT 1011101000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C21:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A2 W1_H02E0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B2 H02W0101 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: V01S0000 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 0000000011111011 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R35C22:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 E1_H01E0001 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A6 V02N0101 +arc: B2 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02N0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F1 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0401 F6 +arc: N3_V06N0103 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000111100001011 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R35C23:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 F5 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C24:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00R0000 +arc: A4 S1_V02N0101 +arc: B0 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 N1_V02S0401 +arc: C3 F4 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 F3 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEC.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R35C25:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 N1_V02S0101 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F7 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1000111110001000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111001000100010 +word: SLICEC.K1.INIT 1011101000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C26:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0501 +arc: B6 H02E0301 +arc: B7 H01E0101 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 Q0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 F1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R35C27:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 F3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C28:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 H02E0701 +arc: A1 V02N0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C29:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 H00R0000 +arc: A3 V02N0501 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q6 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C2:PLC2 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R35C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A3 V02N0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 V02N0701 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 V02N0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C31:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: A2 W1_H02E0701 +arc: A5 Q5 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C32:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A4 V00B0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B4 H02E0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q1 +arc: S3_V06S0203 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C33:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0401 W3_H06E0203 +arc: A2 S1_V02N0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 F5 +arc: B2 N1_V02S0101 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C2 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0401 +arc: C6 N1_V02S0001 +arc: C7 F6 +arc: D2 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F4 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0001000000110010 +word: SLICEB.K0.INIT 0000010101000100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 F1 +arc: B3 F1 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 V02S0601 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 N1_V02S0401 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C35:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B3 V01N0001 +arc: B4 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F7 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A7 F5 +arc: B1 H02W0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0001010100010101 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C37:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 N1_V02S0201 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F2 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 W1_H02E0201 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: A7 W1_H02E0701 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 W1_H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C3:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R35C40:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 N1_V02S0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F0 +arc: V00T0100 F1 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000100001000100 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C41:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 F3 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 F0 +arc: D7 H02W0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S3_V06S0103 F2 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C42:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 H02E0701 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0101 +arc: A7 H02W0701 +arc: B0 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: C6 F4 +arc: C7 S1_V02N0201 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 W1_H02E0201 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: V01S0100 F0 +arc: W1_H02W0501 F7 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0701 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B7 V02N0501 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C7 V02S0001 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: V01S0100 F5 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F0 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: V00B0100 F5 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C46:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V00T0100 F1 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A1 H02W0501 +arc: A3 N1_V02S0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 V02N0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 F4 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 Q3 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C48:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B3 V02S0301 +arc: B5 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 W1_H02E0201 +arc: D3 V00T0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 1111101000111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C49:PLC2 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02N0701 +arc: A5 V00B0000 +arc: A7 S1_V02N0101 +arc: B4 V01S0000 +arc: B6 V01S0000 +arc: B7 S1_V02N0701 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C50:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A3 H00L0100 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B3 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C3 V02S0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +word: SLICED.K1.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 0011001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 V02N0501 +arc: B0 N1_V02S0301 +arc: B5 H02W0301 +arc: B7 V02S0501 +arc: C0 V02S0601 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D4 H01W0000 +arc: D5 H02W0201 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0501 Q7 +arc: V00T0000 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C52:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 S1_V02N0301 +arc: A6 V02S0101 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B6 V02N0701 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F4 +arc: V00T0100 Q3 +arc: V01S0100 F2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C53:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011111110110011 +word: SLICEA.K0.INIT 1011100011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C54:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 H02W0001 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0601 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0303 Q6 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q3 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C56:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00L0100 +arc: A5 V02S0301 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1101111110000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C57:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02N0701 +arc: A3 F7 +arc: A4 F7 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C58:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A3 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 Q1 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C59:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 V02S0301 +arc: B0 V02N0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C60:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A5 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B7 H02W0101 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q5 +arc: V00B0000 F4 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 0000111101110111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C61:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A3 H02W0701 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H00R0100 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 H02W0101 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V01S0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010100000100000 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R35C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 F3 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011000011111100 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEB.K0.INIT 0000000001011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C63:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 W1_H02E0301 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000100011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A2 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B5 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0501 +arc: A7 E1_H02W0701 +arc: B1 E1_H02W0301 +arc: B3 H02W0101 +arc: B5 W1_H02E0301 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q3 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 F6 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00L0100 +arc: A6 H02E0501 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: C0 V02S0601 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 F0 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 Q5 +arc: V00T0000 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C67:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00L0000 +arc: A3 V02N0501 +arc: B0 H02E0101 +arc: B5 H00R0000 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D5 H02W0201 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C68:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 W1_H02E0501 +arc: A6 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: D0 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: N1_V01N0001 F0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEC.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C69:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B4 W1_H02E0101 +arc: B6 V02N0701 +arc: C1 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 Q5 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEC.K0.INIT 1010010100100001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001100100001001 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C70:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 H00R0000 +arc: A4 F7 +arc: A7 S1_V02N0301 +arc: B1 V02S0101 +arc: B3 N1_V02S0301 +arc: B5 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C1 V02S0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 N1_V02S0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: E1_H02E0501 F5 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: V00B0100 F5 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0100010101000000 +word: SLICEC.K0.INIT 0000000000001010 +word: SLICED.K1.INIT 1101001010000111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C71:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M6 H02W0401 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 Q6 +arc: S1_V02S0701 F5 +arc: V01S0100 F7 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V01N0101 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 V00B0100 +arc: B7 H02E0301 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C7 N1_V02S0201 +arc: D2 V02N0001 +arc: D4 F2 +arc: D5 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101100011011000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 + +.tile R35C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: A1 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B3 E1_H02W0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C5 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 F0 +arc: V00T0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C74:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A1 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B6 V02N0701 +arc: C1 W1_H02E0401 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F0 +arc: S1_V02S0701 F7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C75:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 W1_H02E0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B7 H02W0301 +arc: C1 N1_V02S0601 +arc: C2 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 V02N0001 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: N1_V01N0101 F7 +arc: N1_V02N0701 F5 +arc: S1_V02S0201 F2 +arc: V01S0100 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000100001 +word: SLICEC.K1.INIT 0011001000000010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000010011000100 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R35C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02N0701 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B1 V02S0301 +arc: B2 S1_V02N0101 +arc: B5 V02S0701 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 V02S0601 +arc: C7 N1_V02S0001 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 N1_V02S0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0301 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R35C77:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: A2 W1_H02E0701 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: B0 V00T0000 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 V02N0501 +arc: C0 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: D0 F2 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100001110011001 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R35C78:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H01E0001 +arc: A3 S1_V02N0701 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000000000011 +word: SLICEB.K1.INIT 0000100000000010 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C79:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A7 F5 +arc: B0 F3 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B4 F1 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C80:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 E1_H02W0301 + +.tile R35C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 N1_V02S0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C82:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A5 V00T0100 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0601 F4 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C84:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B6 V02N0501 +arc: B7 H01E0101 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 N1_V02S0201 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010000000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R35C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02S0501 +arc: A2 F7 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0501 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 H01E0001 +arc: A4 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 W1_H02E0501 +arc: A7 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0501 +arc: A2 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 N1_V02S0301 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B5 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0501 F5 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 W1_H02E0501 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 H01E0001 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A4 S1_V02N0101 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: B7 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 W1_H02E0601 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: A2 V00T0000 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 N1_V02S0401 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R35C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B3 N1_V02S0101 +arc: B4 V02S0501 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICEA.K0.INIT 1000101000001010 +word: SLICEB.K1.INIT 1010001000100010 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R35C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 F6 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0001001100000000 +word: SLICEB.K1.INIT 1011111110101010 +word: SLICEC.K1.INIT 0011011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 H02E0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 F6 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 H02W0001 +arc: D1 N1_V02S0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H02W0201 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F4 +arc: N1_V02N0201 F0 +arc: V01S0000 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 H02W0501 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F0 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C96:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 V01N0101 +arc: A2 H02W0701 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: D0 W1_H02E0001 +arc: D1 F0 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 N1_V02S0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 S1_V02N0501 +arc: A4 F7 +arc: A5 N1_V02S0301 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: V01S0100 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 F5 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0401 F4 +arc: V00T0100 F1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0501 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 N1_V02S0601 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 W1_H02E0001 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V01S0000 F6 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0000101000001010 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C102:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B4 V02S0501 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V02N0001 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 F3 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C103:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02W0001 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 F5 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 H02W0301 +arc: B7 V02S0501 +arc: C1 H00R0100 +arc: C2 F6 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0401 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C104:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 S1_V02N0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A3 F7 +arc: A4 H02W0501 +arc: A7 H00L0000 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B7 H02E0101 +arc: C3 F4 +arc: C4 V00B0100 +arc: C7 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C105:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 V02S0501 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 F1 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 F0 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C106:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 V02S0501 +arc: A5 E1_H02W0701 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B5 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 V01N0101 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R36C107:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 F4 +arc: C2 N1_V01N0001 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C108:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 E1_H02W0101 +arc: B3 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1100100001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C109:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0301 +arc: B1 H02E0101 +arc: B2 N1_V02S0101 +arc: B3 E1_H01W0100 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V01N0101 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H01E0001 +arc: D0 H01E0101 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 F3 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C110:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0201 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEB.K1.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R36C111:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 F3 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 0010001000110010 +word: SLICED.K1.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C112:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A2 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0303 F5 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F6 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0011001101010101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0000101001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R36C113:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V02S0501 +arc: A4 N1_V02S0101 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C114:PLC2 +arc: E1_H02E0101 H01E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 E1_H02W0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010100000000 +word: SLICED.K1.INIT 1111000000100000 +word: SLICED.K0.INIT 0000111000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C115:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A5 V02S0301 +arc: B5 N1_V02S0501 +arc: C5 W1_H02E0601 +arc: D5 S1_V02N0401 +arc: F5 F5_SLICE +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C116:PLC2 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: A0 H02W0501 +arc: B0 V02S0301 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R36C117:PLC2 +arc: N1_V02N0501 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 + +.tile R36C118:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R36C14:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0101 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R36C15:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 + +.tile R36C16:PLC2 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: A0 V02N0501 +arc: B0 E1_H01W0100 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0011101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C17:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 F5 +arc: A6 H02W0501 +arc: A7 F5 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 1111010100000000 +word: SLICED.K0.INIT 0001000101010001 +word: SLICEA.K0.INIT 0000000011000000 +word: SLICEA.K1.INIT 1010101011101010 +word: SLICEC.K0.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R36C18:PLC2 +arc: E1_H02E0401 V02N0401 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 H01E0001 +arc: A0 H02E0701 +arc: A1 F5 +arc: A3 V02S0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 F6 +arc: C1 F4 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 N1_V02S0401 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0010000000100000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K0.INIT 0000000000001011 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 1101010101010101 +word: SLICEC.K0.INIT 0000000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R36C19:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: S3_V06S0303 H01E0101 +arc: A6 V02N0101 +arc: B3 V02N0101 +arc: C1 E1_H02W0601 +arc: C6 V02N0001 +arc: D1 V01S0100 +arc: D3 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 0000000000110011 +word: SLICED.K0.INIT 0101000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R36C20:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0501 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A7 F5 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 H00L0000 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICEC.K0.INIT 1011101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R36C21:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 0000000010101000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1000111110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C22:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B6 H01E0101 +arc: C1 V02S0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C23:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: H00L0000 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0701 +arc: A2 V00T0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 V02S0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0101010100000000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R36C24:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010111000001100 +word: SLICED.K0.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C25:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H00R0000 +arc: A2 V02N0501 +arc: A5 N1_V01S0100 +arc: A7 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R36C26:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1101010111000000 +word: SLICED.K0.INIT 1101110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C27:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 V06S0303 +arc: A1 S1_V02N0701 +arc: A3 V01N0101 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0100 F5 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C28:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: A0 H02E0501 +arc: A3 F5 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R36C29:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02S0001 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: C0 S1_V02N0401 +arc: C1 F6 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0301 Q3 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C30:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: A0 H02W0701 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C31:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 V02N0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C32:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 W3_H06E0303 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C33:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 F4 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02S0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F6 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 0000111100000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 S1_V02N0701 +arc: A4 F7 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F2 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0001000100110011 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C35:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0501 +arc: A1 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C7 V02S0201 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D4 F0 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0100 F7 +arc: N1_V01N0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R36C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A0 V02S0701 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C37:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0601 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D7 H02E0201 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: N1_V01N0001 F2 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 F7 +arc: A3 S1_V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0000101000001011 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICEB.K0.INIT 0000000000111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B3 N1_V02S0301 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V01S0000 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 F6 +arc: D1 V02S0201 +arc: D2 W1_H02E0001 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0001 F2 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C42:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 H02W0601 +arc: C1 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: N1_V01N0001 F7 +arc: S1_V02S0601 F4 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C44:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0301 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 V02S0501 +arc: C0 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0001 +arc: D5 E1_H02W0201 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0000 F3 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 0000001000110010 +word: SLICEB.K1.INIT 0000001000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 H00L0100 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C46:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 H00R0100 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: D0 V02N0001 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F0 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C47:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B2 V02N0101 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 0000010101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R36C48:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0501 +arc: B3 V01N0001 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0001 +arc: F3 F3_SLICE +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 0011001101011111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C49:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B5 H02W0101 +arc: C1 S1_V02N0601 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 N1_V01N0001 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111110000110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C50:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A7 H00R0000 +arc: B2 V01N0001 +arc: B5 H02W0301 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C5 V00T0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 Q7 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0201 Q2 +arc: N3_V06N0203 Q7 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C51:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A5 H02E0701 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B5 V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010100000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B1 H02W0101 +arc: B2 H02W0301 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R36C53:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 E1_H02W0501 +arc: A6 S1_V02N0101 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B3 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C3 H02E0401 +arc: C6 N1_V02S0001 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0101010100001100 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R36C54:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 S1_V02N0501 +arc: A4 V02N0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 W1_H02E0201 +arc: D4 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 F3 +arc: V00B0100 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C55:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0701 +arc: A5 N1_V02S0301 +arc: A6 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B6 H01E0101 +arc: C3 H02W0601 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 F0 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N3_V06N0303 F6 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1110010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C56:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: B2 V01N0001 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C57:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 F1 +arc: B5 V01S0000 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 F4 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0011001000000010 +word: SLICEB.K1.INIT 1111111011001110 +word: SLICEC.K1.INIT 1100111111001010 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 1111000011101110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C58:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: E1_H02E0401 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V02N0301 F3 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1010000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C59:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0701 +arc: A2 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 V02S0101 +arc: C0 H02E0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C60:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0401 F6 +arc: V01S0100 F6 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C61:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q7 +arc: M0 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 H02E0701 +arc: A4 N1_V02S0101 +arc: A5 E1_H02W0501 +arc: A6 V02S0101 +arc: B0 V02S0301 +arc: B1 V01N0001 +arc: B3 H02W0301 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 S1_V02N0501 +arc: C0 F6 +arc: C1 V02N0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K1.INIT 1101111111010000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R36C63:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V01N0101 +arc: A1 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR0 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C64:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 W1_H02E0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V02S0501 +arc: C1 H02E0401 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V02S0401 +arc: E1_H01E0101 Q7 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 W1_H02E0401 +arc: M5 H02E0001 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F6 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1111000011101110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C65:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile R36C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 H06W0103 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 H02W0701 +arc: B1 H02E0301 +arc: B3 V02N0101 +arc: C1 W1_H02E0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0201 +arc: D3 S1_V02N0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0100010001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C67:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 V02N0301 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 N1_V02S0001 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 F2 +arc: V00B0000 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 0000001010100010 +word: SLICEB.K0.INIT 0000000001000001 +word: SLICED.K1.INIT 0101010000000100 +word: SLICEC.K1.INIT 0000101000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B4 V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C4 S1_V02N0001 +arc: C5 V02S0001 +arc: C6 H01E0001 +arc: C7 V01N0101 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: N1_V01N0101 F1 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K0.INIT 0000000000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0010000000101010 +word: SLICEC.K1.INIT 0000000001000001 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0100000001110000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R36C69:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02W0701 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: B3 H00R0100 +arc: B5 H02E0101 +arc: C1 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0701 F5 +arc: N3_V06N0003 F3 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C70:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B5 N1_V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0501 +arc: C0 V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V02N0001 F0 +arc: N3_V06N0303 F5 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 0100000001001100 +word: SLICEB.K0.INIT 1100101000110101 +word: SLICED.K0.INIT 0100011100000000 +word: SLICED.K1.INIT 0011010100000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C71:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: A4 N1_V01S0100 +arc: A5 W1_H02E0501 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V02N0501 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 F4 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A2 F7 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: C0 H00R0100 +arc: C2 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0501 F7 +arc: V01S0000 F5 +arc: V01S0100 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0011000001010000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C73:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000000000100011 +word: SLICEB.K1.INIT 0000000010001100 +word: SLICEC.K1.INIT 0101000001000100 +word: SLICEC.K0.INIT 0011000000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C74:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 H00L0100 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICEB.K1.INIT 0000110001000100 +word: SLICED.K1.INIT 0001000000000001 +word: SLICEA.K0.INIT 0010000001110000 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000110000001111 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R36C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 F5 +arc: A1 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 0010001000110000 +word: SLICEC.K1.INIT 0101010100010001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0011000000100010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C76:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 V02S0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0701 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 H02W0301 +arc: B4 N1_V02S0501 +arc: B5 H02W0101 +arc: B7 V02S0501 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D2 H01E0101 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0011000000100010 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R36C77:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 N1_V02S0701 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0401 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 H02W0001 +arc: D3 F2 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V00T0100 F1 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEB.K0.INIT 0011001000010000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEB.K1.INIT 0000000001000001 +word: SLICED.K0.INIT 0001000000000001 +word: SLICEA.K1.INIT 0010011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A4 H02W0701 +arc: A5 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 H02E0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0101000000110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C79:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: B5 H02E0101 +arc: C5 H02W0401 +arc: D5 V02N0401 +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R36C80:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile R36C81:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: V01S0000 N3_V06S0103 + +.tile R36C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 F5 +arc: A7 H02E0501 +arc: B3 N1_V02S0301 +arc: B4 H00L0000 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 E1_H02W0001 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 V06N0003 +arc: A2 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C84:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A2 V00B0000 +arc: A3 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V01N0001 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C86:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: A1 E1_H02W0501 +arc: A4 V00T0100 +arc: A6 V02S0301 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B6 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C87:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: A1 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 N1_V02S0301 +arc: B4 V00B0100 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 H01E0101 +arc: C0 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C5 F4 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C88:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 N1_V02S0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C89:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0701 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 W1_H02E0601 +arc: C5 V02S0001 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0103 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 V02N0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D0 H02E0001 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F6 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V01N0101 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 V00B0100 +arc: B5 H01E0101 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 F4 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 N1_V02S0401 +arc: D6 V02N0401 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: M0 H02W0601 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F0 +arc: V00T0000 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000101010 +word: SLICEA.K1.INIT 1011111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 E1_H02W0501 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: D0 E1_H02W0201 +arc: D1 V02S0001 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: D4 N1_V02S0601 +arc: D5 W1_H02E0001 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: A1 N1_V02S0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V02N0201 F2 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R36C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 S1_V02N0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010001000100 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R36C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 V01N0101 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 N1_V02S0601 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 F0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C96:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 H01E0101 +arc: A0 V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R36C97:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 V06N0203 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C2 F4 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 H01E0001 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: D0 V00B0100 +arc: D2 F0 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0101 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C100:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V01N0101 +arc: A0 N1_V02S0501 +arc: A1 V02S0701 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C101:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0501 +arc: A2 V02N0501 +arc: A3 V01N0101 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0301 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 F1 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C103:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0501 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 S1_V02N0101 +arc: A5 H02E0701 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B7 H02W0301 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C7 V00T0000 +arc: D1 F2 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 H02E0601 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C104:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 F5 +arc: A5 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B5 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C5 V00T0100 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0701 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C106:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H00L0000 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0601 +arc: C6 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C107:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B4 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D4 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C108:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 F2 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C110:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEC.K1.INIT 0000010100010001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000101100001010 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C111:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A2 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B1 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 V02S0701 +arc: B7 H01E0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F5 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEC.K1.INIT 0000000011110100 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 1010101100000000 +word: SLICEA.K0.INIT 0000101001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R37C112:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 N1_V02S0101 +arc: B1 V01N0001 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0101010100110011 +word: SLICEC.K0.INIT 0000010100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C113:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V01N0001 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C114:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 V00B0000 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 H02E0101 +arc: B7 F1 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICEC.K0.INIT 1100000011001000 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICED.K1.INIT 1010101000000010 +word: SLICEB.K0.INIT 1011101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C115:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0501 +arc: B0 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: C0 H00L0100 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R37C116:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0501 F7 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R37C117:PLC2 +arc: N1_V02N0601 H01E0001 + +.tile R37C119:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R37C120:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R37C14:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: V00T0100 N1_V02S0701 +arc: A0 H02W0701 +arc: B0 V02S0301 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0111010100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C15:PLC2 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 V02S0701 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R37C16:PLC2 +arc: N1_V02N0501 H02E0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02W0301 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 0100010001100110 +word: SLICEB.K1.INIT 0111001001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R37C17:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 V02S0701 + +.tile R37C18:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0201 N3_V06S0103 +arc: V00T0100 V02S0701 +arc: A0 H02W0701 +arc: B0 H02E0301 +arc: C0 E1_H01W0000 +arc: D0 V02N0201 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111111111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C19:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: S1_V02S0101 H06E0103 +arc: W1_H02W0701 N1_V02S0701 +arc: B2 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C5 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: LSR1 E1_H02W0301 +arc: M5 H02E0001 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C20:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 V02N0301 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C21:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 W1_H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 V02S0501 +arc: A3 H01E0001 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 H02E0301 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0100 F2 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R37C23:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B0 H02W0101 +arc: B3 V01N0001 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 F3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1010000010100000 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C24:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: A3 S1_V02N0701 +arc: A5 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 W1_H02E0301 +arc: B6 H02W0301 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R37C25:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: A0 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 V02S0301 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R37C26:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0401 N1_V01S0000 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02S0501 +arc: A4 H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0701 Q5 +arc: V00T0000 Q2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R37C27:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C4 V00B0100 +arc: C5 H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F6 +arc: V01S0100 F4 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R37C28:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F5 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R37C29:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H02E0701 +arc: B0 F3 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C30:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H02E0501 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: E1_H02E0101 Q3 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C31:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C32:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C33:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 E1_H02W0101 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 V01S0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02S0401 +arc: C4 V00T0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEC.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C34:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 H01E0101 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 0001010100010000 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000000011110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C36:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 S1_V02N0301 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000001001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C37:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 H02E0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H00R0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V02S0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0001 +arc: D3 W1_H02E0201 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0201 F2 +arc: V01S0100 Q0 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C38:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 F6 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0701 F5 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A5 H02E0701 +arc: A7 H02E0701 +arc: B1 H02E0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V00B0100 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F0 +arc: V01S0100 F5 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A4 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B4 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C4 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F0 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C41:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0501 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02W0401 +arc: C6 F4 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C42:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A1 H00R0000 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 N1_V02S0101 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C1 E1_H02W0601 +arc: C2 F6 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02S0001 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: V00B0100 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C43:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A4 V02S0101 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B0 N1_V02S0101 +arc: B1 H01W0100 +arc: B2 W1_H02E0301 +arc: B3 H01W0100 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: B7 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: C7 V02N0001 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0701 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001010000010 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C44:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 N1_V02S0101 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: S3_V06S0303 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEA.K0.INIT 0101000001010001 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F5 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C46:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V01N0101 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0001 F3 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C47:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B6 F1 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q0 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H02W0501 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0701 Q7 +arc: V00T0100 Q3 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0701 +arc: B2 E1_H02W0101 +arc: C2 H02W0601 +arc: D2 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +word: SLICEB.K0.INIT 1000110010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C50:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02S0101 +arc: B1 H02E0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B7 S1_V02N0701 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R37C51:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 S1_V02N0301 +arc: B1 H02W0301 +arc: B4 V02N0501 +arc: C1 H00L0100 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C52:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 H02W0501 +arc: B0 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 H02W0301 +arc: B7 V00B0100 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 V02S0201 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q1 +arc: V00B0100 Q5 +arc: V00T0000 F0 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W1_H02W0401 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 E1_H02W0701 +arc: B0 H02E0101 +arc: B3 E1_H02W0301 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C3 H02E0601 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 F0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001000011011100 +word: SLICED.K1.INIT 0011000011111100 +word: SLICEA.K0.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R37C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 S1_V02N0501 +arc: A6 V02S0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C1 H02W0601 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010101000101010 +word: SLICEB.K0.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R37C55:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E1_H01W0100 +arc: H00L0100 H02W0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02S0701 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 V02N0101 +arc: B5 E1_H02W0301 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00L0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 E1_H02W0701 +arc: A7 V02S0301 +arc: B7 H02E0301 +arc: C4 H01E0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D7 H02W0201 +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M1 H00L0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F7 +arc: V01S0000 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q6 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A2 V00B0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: B0 W1_H02E0101 +arc: B1 V01N0001 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V00T0100 F1 +arc: V01S0000 Q7 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0000000010101100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C59:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: B0 V02S0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F0 +arc: V01S0100 F4 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEA.K0.INIT 0000111101110111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C60:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B6 S1_V02N0701 +arc: B7 F1 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F7 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C62:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A6 H00R0000 +arc: B1 H02E0101 +arc: B6 V02S0501 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D6 F2 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 Q4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q6 +arc: V00B0000 Q6 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1110000001000000 +word: SLICED.K0.INIT 0000011111110111 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 V00B0000 +arc: A5 E1_H02W0701 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B4 H02W0301 +arc: B7 F1 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0601 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C64:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 V00B0100 +arc: D5 V02S0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 W1_H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0203 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C65:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0301 +arc: B3 V02N0301 +arc: B5 H02W0301 +arc: C1 V02S0601 +arc: C3 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q3 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C66:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B7 S1_V02N0501 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C7 W1_H02E0601 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +word: SLICEB.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R37C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: A3 V02N0701 +arc: A4 F5 +arc: A5 H02E0701 +arc: A6 N1_V01N0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 N1_V02S0701 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D0 V00T0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F4 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEC.K0.INIT 0001000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H00L0000 +arc: A2 H02E0701 +arc: A3 E1_H01E0001 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: A7 F5 +arc: B2 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 W1_H02E0601 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000001000000001 +word: SLICED.K0.INIT 0000000011100100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0010011100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C69:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A0 N1_V02S0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B3 H00L0000 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 V02S0201 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0100000001001100 +word: SLICEB.K1.INIT 0000000001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C70:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A5 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: C1 V02S0601 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00L0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R37C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0701 +arc: A2 H02W0701 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 F5 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0101011010100110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0100010001010000 +word: SLICED.K1.INIT 0010000100000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 0101000000110000 +word: SLICEB.K1.INIT 0100011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C72:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F6 +arc: V00T0000 F0 +word: SLICED.K1.INIT 0000001000000001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0101000001000100 +word: SLICEA.K1.INIT 0000001010100010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101010000000100 +word: SLICEC.K0.INIT 0011010100000000 +word: SLICED.K0.INIT 0000010000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A3 H02W0701 +arc: A5 H02E0701 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F5 +arc: V01S0100 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000010011000100 +word: SLICEA.K0.INIT 0011000000000011 +word: SLICEA.K1.INIT 0100000100000000 +word: SLICEC.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A2 N1_V02S0701 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: B0 H02E0301 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 0011000000100010 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 N1_V02S0501 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 0000111000000100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000110001000100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C76:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A3 V02S0701 +arc: A4 N1_V02S0101 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B4 V00B0100 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 S1_V02N0401 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D0 F2 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0001110100000000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C77:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A2 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C1 V02S0401 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1010000001010000 +word: SLICED.K0.INIT 0000000001000001 +word: SLICEB.K0.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C78:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A2 F7 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 F6 +arc: C2 F6 +arc: C3 F6 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000100001001100 +word: SLICEB.K0.INIT 0101000000000101 +word: SLICEB.K1.INIT 0100000100000000 +word: SLICEC.K1.INIT 0000100000101010 +word: SLICEC.K0.INIT 0011000100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C79:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02E0701 +arc: A4 N1_V02S0101 +arc: A6 V02S0101 +arc: B2 H02W0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V01S0000 +arc: C2 V02N0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D2 E1_H02W0201 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: S1_V02S0501 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111000000100 +word: SLICED.K0.INIT 0000101000100010 +word: SLICEC.K0.INIT 0000000000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C80:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 H00L0000 +arc: A1 F5 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 F6 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 F0 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C81:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 V02S0101 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H01E0001 +arc: A6 H00L0000 +arc: B0 V02S0301 +arc: B3 E1_H02W0301 +arc: B6 V02S0501 +arc: C0 H02E0601 +arc: C3 N1_V01S0100 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00T0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A4 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 N1_V02S0101 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C84:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V01N0001 +arc: A0 H02W0701 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C85:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 V01S0000 +arc: B5 F3 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1000100000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C87:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C88:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 F7 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010110010101100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0701 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C90:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V06N0303 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0401 +arc: C2 F4 +arc: C3 E1_H02W0401 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0701 F7 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R37C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A2 H02W0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: D1 E1_H02W0001 +arc: D2 V00T0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0000001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R37C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: B1 W1_H02E0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 F3 +arc: C0 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0101 F5 +arc: S1_V02S0001 F0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0001000110111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R37C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H02E0501 +arc: A4 V00T0100 +arc: A6 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B4 H00R0000 +arc: B6 V00T0000 +arc: C1 V02N0401 +arc: C4 V01N0101 +arc: C6 H02E0601 +arc: D1 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: V00T0100 F1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: B4 H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C4 V00T0100 +arc: D1 E1_H02W0201 +arc: D4 V02S0601 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0000 +arc: S1_V02S0201 F0 +arc: S3_V06S0203 F4 +word: SLICEC.K0.INIT 0000000011110011 +word: SLICEA.K1.INIT 0000101001011111 +word: SLICEA.K0.INIT 0101111101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R37C95:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0003 V06N0003 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 V02S0101 +arc: B4 F3 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0201 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00T0000 F0 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02S0201 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: A7 H02W0701 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 F0 +arc: V00T0100 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V00B0100 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 F6 +arc: C3 W1_H02E0401 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: D0 H02W0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C99:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 E1_H02W0201 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F2 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 V02N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 F0 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 H02E0401 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C103:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 N1_V02S0701 +arc: A1 H01E0001 +arc: A2 F5 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 F3 +arc: B2 F1 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 H00L0100 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1101110100001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C104:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R38C105:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A7 H00L0000 +arc: B1 V02S0301 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C7 S1_V02N0201 +arc: D1 V00T0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C106:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 H02E0101 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0101 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F6 +arc: V00T0000 F2 +arc: V01S0000 F3 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C107:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 V02S0701 +arc: A6 H00L0000 +arc: B0 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B6 F3 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C6 V00T0000 +arc: D0 V00T0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D6 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C108:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 F7 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H00R0100 +arc: B2 H02E0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 W1_H02E0101 +arc: C0 V02S0601 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 F6 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R38C109:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 F0 +arc: S1_V02S0701 F5 +word: SLICEB.K0.INIT 0000010111110101 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C110:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000101001000101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000011111101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C111:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 H02E0501 +arc: A4 F5 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0501 +arc: B0 V02S0101 +arc: B1 N1_V02S0101 +arc: B2 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: S3_V06S0003 F0 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 0000111000001111 +word: SLICED.K1.INIT 0000111000001111 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEC.K0.INIT 0011000000110010 +word: SLICEA.K0.INIT 0000111000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R38C112:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A1 V02S0501 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V00B0000 F6 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000000010101100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000011000100 +word: SLICEA.K1.INIT 0001000000010000 +word: SLICED.K1.INIT 1010101000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C113:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C114:PLC2 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 + +.tile R38C115:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02S0501 +arc: A4 V00B0000 +arc: B0 V02N0301 +arc: C0 V02N0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D4 S1_V02N0401 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K0.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R38C116:PLC2 +arc: N3_V06N0303 S1_V02N0601 +arc: A0 H00L0000 +arc: B0 H02E0301 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C117:PLC2 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0601 V06N0303 + +.tile R38C118:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R38C14:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 V06N0203 + +.tile R38C15:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R38C16:PLC2 +arc: H00R0100 H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B6 H02W0301 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +word: SLICED.K0.INIT 0011000010101010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C17:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: C3 H00L0000 +arc: C6 H01E0001 +arc: D3 H01E0101 +arc: D6 H02E0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V01S0100 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R38C18:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0401 V01N0001 + +.tile R38C19:PLC2 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R38C20:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: A0 H00R0000 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100000011000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C21:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 H01E0101 +arc: A0 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 V02S0501 +arc: A7 V02N0301 +arc: B1 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0203 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R38C23:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: A1 W1_H02E0701 +arc: B0 V00T0000 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: B6 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0101000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R38C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 F5 +arc: A5 V02S0101 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: C0 N1_V01N0001 +arc: C3 F4 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEC.K1.INIT 0000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C25:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 H00L0000 +arc: A6 V02N0301 +arc: B1 E1_H01W0100 +arc: B4 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R38C26:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A2 V00B0000 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000001010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C27:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A5 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B5 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F4 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R38C28:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A6 H02W0701 +arc: A7 E1_H02W0501 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R38C29:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02S0601 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010000011101100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C30:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V01N0101 +arc: B0 H02E0101 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C31:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 S1_V02N0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C32:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 V06N0003 + +.tile R38C33:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: A0 F5 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 W1_H02E0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C34:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B5 H02W0301 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D5 F0 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: B1 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F1 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00L0000 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 F3 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100001010 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEB.K1.INIT 0000000011001101 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0100010001000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B4 F1 +arc: B5 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B1 V00T0000 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C3 V02S0401 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F0 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C39:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: D0 N1_V02S0201 +arc: D5 N1_V02S0601 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0601 F6 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C40:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B4 V01S0000 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 0000000001110010 +word: SLICED.K0.INIT 0000000011001101 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 0000010000001110 +word: SLICEC.K1.INIT 0000000011001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C41:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A2 H01E0001 +arc: A3 V02N0701 +arc: A6 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 F2 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R38C42:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A4 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B1 H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 F1 +arc: C1 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010001010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: D0 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C44:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N3_V06N0203 F4 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 F7 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 V01N0101 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C46:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0203 F7 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICED.K1.INIT 1110001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C47:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 E1_H02W0701 +arc: B3 E1_H02W0101 +arc: C3 N1_V01N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: E1_H01E0001 F7 +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 F2 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R38C49:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: B0 V00B0000 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1011111110110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 E1_H02W0501 +arc: A2 E1_H01E0001 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B5 F3 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: M0 V00T0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R38C51:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 H00R0100 +arc: B3 F1 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 F0 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 F0 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C52:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0701 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B5 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H00R0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEA.K1.INIT 1110010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C53:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A3 F7 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B5 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C54:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H02W0701 +arc: A4 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C6 V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B4 V02N0701 +arc: B6 H01E0101 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 Q7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0001101100001010 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 0100110001001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R38C56:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0501 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: B3 H02W0101 +arc: C0 H02E0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 H02E0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C58:PLC2 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 V01N0101 +arc: A5 V02S0101 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C3 H00L0100 +arc: C5 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0203 F7 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1100101011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C60:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111011111010101 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICED.K1.INIT 1111111111001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C61:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V00B0000 +arc: B5 V01S0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F5 +arc: F5 F5_SLICE +arc: H01W0000 Q3 +arc: M3 H02E0201 +arc: M5 H02W0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010000011000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C62:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: B0 H02E0301 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C63:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: C2 W1_H02E0601 +arc: C4 V01N0101 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00T0000 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C64:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06S0203 +arc: B1 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C1 V02N0401 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C65:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 V06N0103 +arc: A0 F7 +arc: A7 V02N0301 +arc: B1 H02W0101 +arc: B4 H02W0101 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0601 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M3 H00R0000 +arc: MUXCLK1 CLK0 +arc: V00B0000 F4 +arc: V01S0000 Q3 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C66:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 S3_V06N0003 +arc: B3 V02N0301 +arc: C3 S1_V02N0601 +arc: D3 V00T0100 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R38C67:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0501 +arc: A2 F5 +arc: A4 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000101000100010 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICED.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R38C68:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEA.K1.INIT 0010000001110000 +word: SLICED.K1.INIT 0001000000000001 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R38C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B5 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 E1_H01E0101 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F1 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0100000001001100 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000100000101010 +word: SLICED.K0.INIT 0101000101000000 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C70:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 F5 +arc: A6 H00L0000 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 F4 +arc: C4 V01N0101 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 F1 +arc: V00B0000 F6 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 0010001000110000 +word: SLICEC.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0010011100000000 +word: SLICEB.K0.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C71:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A3 V02S0501 +arc: A5 S1_V02N0101 +arc: A6 F7 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 V02S0201 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F0 +arc: S1_V02S0401 F6 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000010100101 +word: SLICEA.K1.INIT 0000000010000100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A4 N1_V02S0101 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 N1_V02S0501 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 F4 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICED.K0.INIT 0000000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C73:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0501 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0010001000110000 +word: SLICEA.K0.INIT 0001110100000000 +word: SLICEC.K1.INIT 0000000001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C74:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 F0 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010110001010011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110010000011011 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B2 E1_H01W0100 +arc: B5 N1_V01S0000 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 W1_H02E0401 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R38C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V01N0101 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: N1_V01N0001 F4 +arc: V00T0000 F0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C77:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0501 +arc: A1 F5 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A6 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: C0 F6 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D3 H02W0201 +arc: D4 F0 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: V00T0100 F1 +arc: V01S0000 F3 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C78:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00R0000 +arc: A4 E1_H02W0701 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: B0 H02E0301 +arc: B2 N1_V02S0101 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: D0 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F2 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 0000110001000100 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C79:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A7 E1_H02W0701 +arc: B3 S1_V02N0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C3 V02N0601 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: D3 H02E0201 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F6 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C80:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A2 H02W0501 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H02E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: S1_V02S0201 F2 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 1100000011110000 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 H00R0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 S1_V02N0501 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C83:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 H00L0100 +arc: A4 V00B0000 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 H02W0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C84:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02E0701 +arc: A4 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C4 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C85:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A3 E1_H01E0001 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B1 H02E0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 E1_H01W0000 +arc: C4 N1_V02S0001 +arc: C5 F4 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C87:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 N1_V02S0301 +arc: B2 H02W0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0501 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A4 H02W0501 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C2 S1_V02N0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 V06S0103 +arc: A0 V02N0501 +arc: A5 Q5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C90:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A6 H00R0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B6 F1 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D6 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A0 W1_H02E0501 +arc: A1 H02W0701 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 F6 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C92:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 F7 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B6 H02W0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S3_V06S0103 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00L0100 +arc: A4 W1_H02E0701 +arc: B1 E1_H02W0101 +arc: B4 V00B0100 +arc: C1 N1_V01N0001 +arc: C4 V00T0100 +arc: D1 H00R0000 +arc: D4 S1_V02N0601 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 + +.tile R38C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A1 F5 +arc: A3 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 F3 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0401 F4 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C96:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 N1_V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F1 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B7 V00B0000 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 S1_V02N0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V02N0201 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R38C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 F0 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H01E0001 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 F7 +arc: A7 V02S0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C101:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 H02W0301 +arc: B4 F1 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 F2 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 F1 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V02S0001 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R39C103:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A5 W1_H02E0701 +arc: A6 E1_H01W0000 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B5 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C104:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 F5 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 N1_V02S0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 V02N0501 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: C0 H02E0401 +arc: C2 V02N0401 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: D0 V02S0001 +arc: D2 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 F0 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C106:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 V01N0101 +arc: A2 N1_V02S0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F2 +arc: V00T0100 F1 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C107:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0000 H02W0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A1 V02S0501 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 F3 +arc: B3 H02E0101 +arc: B4 V02N0501 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V01S0000 F4 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C108:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H01E0001 +arc: A3 V00T0000 +arc: A4 F7 +arc: A7 H00L0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B7 S1_V02N0501 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C7 H02W0401 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 0000010100000000 +word: SLICEB.K1.INIT 0010001000110010 +word: SLICEB.K0.INIT 0000111000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C109:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 F3 +arc: B5 E1_H02W0301 +arc: B6 W1_H02E0301 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 F6 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICED.K1.INIT 0000101001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R39C110:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A4 H02E0701 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 N1_V02S0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 0101000001010100 +word: SLICEC.K0.INIT 0000111000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C111:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A2 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: D0 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 F0 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +word: SLICEA.K0.INIT 0100010001110111 +word: SLICEC.K1.INIT 0000000100001011 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R39C112:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A1 H02W0701 +arc: A3 N1_V02S0701 +arc: B1 V02S0301 +arc: B3 H02W0301 +arc: B5 F3 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C5 E1_H01E0101 +arc: D1 E1_H02W0201 +arc: D3 V02S0201 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R39C113:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C0 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +arc: V01S0100 F2 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R39C114:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C115:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C116:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 + +.tile R39C117:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R39C15:PLC2 +arc: N1_V02N0101 S1_V02N0101 + +.tile R39C16:PLC2 +arc: E1_H02E0401 N1_V01S0000 + +.tile R39C17:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 + +.tile R39C18:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F0 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0100010111001100 +word: SLICEA.K1.INIT 0100000011001100 +word: SLICEB.K0.INIT 0100010111001100 +word: SLICEB.K1.INIT 0100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C19:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: V01S0000 N3_V06S0103 +arc: A2 F5 +arc: A3 W1_H02E0501 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C3 V02S0401 +arc: C5 W1_H02E0401 +arc: D1 W1_H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K1.INIT 0000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R39C20:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 H01E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: B1 V02N0101 +arc: C0 H02E0401 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: S3_V06S0003 F0 +arc: V00B0000 F4 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R39C21:PLC2 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: A2 V00B0000 +arc: A3 F7 +arc: A6 E1_H01W0000 +arc: A7 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 0011001000010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C22:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 H01E0001 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C23:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 0000010100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R39C24:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: A1 V02N0501 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010111000001100 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 1000100011111000 +word: SLICEC.K1.INIT 1010111000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C25:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 V01N0101 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 H01E0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H01W0100 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R39C26:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 V02S0601 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 V02S0301 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q6 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICEB.K0.INIT 1011001110100000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1011001110100000 +word: SLICEC.K1.INIT 1111001000100010 +word: SLICED.K0.INIT 1111001000100010 +word: SLICED.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C27:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 W3_H06E0103 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B1 Q1 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R39C28:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0501 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 1011101111110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1011100010111000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R39C29:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A4 F7 +arc: A5 Q5 +arc: A6 H02W0701 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V02N0501 +arc: B6 H01E0101 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1101110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C30:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C31:PLC2 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C32:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A6 N1_V02S0301 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C33:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: A1 N1_V02S0501 +arc: A4 E1_H01W0000 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 F1 +arc: B1 H01W0100 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C1 F4 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEC.K0.INIT 0001000100110000 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C34:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06N0303 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 H01E0001 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: B1 W1_H02E0101 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 H02W0401 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001010100010000 +word: SLICEC.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000000010101011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F7 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A4 V00T0100 +arc: A6 H02E0501 +arc: B0 N1_V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V00T0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEC.K0.INIT 0000000001001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C37:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H00L0000 +arc: A1 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 V02N0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: B0 V01N0001 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICEB.K0.INIT 0000000010101011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A4 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0100010001000101 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 1011100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C39:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H02E0301 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: S1_V02S0501 F7 +arc: V00B0000 F4 +arc: V01S0000 F0 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001000100110011 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 E3_H06W0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A5 V00B0000 +arc: B1 V01N0001 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C1 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: D1 H02W0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N3_V06N0103 F1 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H02W0501 +arc: B0 F3 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: S1_V02S0601 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: A0 V02N0501 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A3 W1_H02E0501 +arc: A4 H02E0501 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 N1_V02S0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C43:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: D0 V00T0100 +arc: D1 N1_V02S0001 +arc: D3 H02W0201 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1010100000100000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 N1_V02S0701 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B6 F1 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 F4 +arc: D0 F2 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: V00B0100 F5 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000000001110111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0000010000001110 +word: SLICEA.K1.INIT 0000010000001110 +word: SLICED.K0.INIT 0101000001010001 +word: SLICED.K1.INIT 0000110000001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C45:PLC2 +arc: E1_H02E0101 V06S0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A0 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 E1_H02W0701 +arc: A6 H02W0501 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B4 V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: C0 H00L0100 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 0000101000001010 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C46:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 E1_H01E0001 +arc: A7 N1_V01N0101 +arc: B3 N1_V02S0301 +arc: B5 F3 +arc: B7 H02E0101 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 V00T0100 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M4 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0101001101011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 N3_V06S0303 +arc: A6 H02W0501 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B6 H02W0301 +arc: C1 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0601 F6 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C48:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 E1_H01E0001 +arc: A6 V00T0100 +arc: B1 V02S0301 +arc: C1 V02S0601 +arc: C3 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 Q4 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R39C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 V02N0301 +arc: B6 V00B0100 +arc: C6 H02W0401 +arc: D6 H00R0100 +arc: F6 F6_SLICE +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C50:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0701 +arc: A3 H02W0501 +arc: B4 N1_V02S0701 +arc: B5 V02N0501 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C51:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1101111110001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C52:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0501 +arc: A5 E1_H01W0000 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R39C53:PLC2 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: A6 V02N0101 +arc: B0 V00B0000 +arc: C0 H02W0401 +arc: C6 V00T0100 +arc: D0 V00B0100 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C54:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 N1_V01N0101 +arc: B6 W1_H02E0101 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q1 +arc: F6 F6_SLICE +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 1010000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C55:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 H02W0301 +arc: B7 H02W0101 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0001101101011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R39C56:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C57:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A4 F7 +arc: A7 V02S0301 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: V00T0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0010101000101010 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C58:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A6 V00T0100 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 H01E0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0201 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0303 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R39C59:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R39C60:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: C1 H02W0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 F2 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 1111101100111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: A3 V02N0701 +arc: B3 H00L0000 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 S1_V02N0001 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 F3 +arc: F3 F3_SLICE +arc: M2 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q6 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEB.K1.INIT 1101000010000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C62:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A5 W1_H02E0701 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 H01E0101 +arc: C0 S1_V02N0601 +arc: C3 H02E0601 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0000011111110111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C63:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C3 H00L0100 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0301 Q3 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEB.K0.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R39C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 V06N0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0701 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 Q3 +arc: F2 F5B_SLICE +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C65:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1011100010111000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R39C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 W1_H02E0701 +arc: B2 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: V00B0100 F7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0010001000110000 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICED.K0.INIT 0000101000100010 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R39C67:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 V02S0501 +arc: A2 V01N0101 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H01E0001 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F2 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001001 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C68:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 F1 +arc: B6 N1_V02S0701 +arc: B7 H02E0301 +arc: C1 S1_V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 0100010000001100 +word: SLICEA.K1.INIT 0101000001000100 +word: SLICEC.K1.INIT 0000000000100000 +word: SLICED.K1.INIT 1110010000011011 +word: SLICEB.K1.INIT 1100000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R39C69:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 F1 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: D0 V02S0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K1.INIT 0000010011000100 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 0101000101000000 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICED.K0.INIT 0000000001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C70:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 F5 +arc: A3 N1_V02S0701 +arc: A7 V00T0100 +arc: B0 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000011100010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEA.K1.INIT 0000101000000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R39C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 H01E0101 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: C0 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0100010101000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C72:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02N0501 +arc: A4 F7 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F2 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 0000000000001001 +word: SLICED.K1.INIT 0010011111011000 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C73:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 H02W0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0001 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0501 F7 +arc: V00T0100 F3 +arc: V01S0000 F1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100101000110101 +word: SLICED.K0.INIT 1101100000100111 +word: SLICEB.K1.INIT 1001101010010101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001101010010101 +word: SLICEA.K1.INIT 0000000011001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 N1_V02S0501 +arc: A2 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 F7 +arc: A5 V02S0301 +arc: A7 V02N0101 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 N1_V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0001 F2 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 0101000001000100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 V02S0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 E1_H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 F3 +arc: V01S0000 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C76:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A6 V02S0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F1 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 0100110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C77:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B4 V00B0100 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C3 V02S0601 +arc: C4 H02W0601 +arc: C7 V00T0100 +arc: D0 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 F4 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0011000100100000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C78:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0001 +arc: C6 H02W0601 +arc: D0 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D6 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F4 +arc: V01S0000 F6 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0101000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: B0 V02S0301 +arc: C0 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: V00T0000 F2 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R39C80:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A6 H02E0701 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B6 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D6 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1110010001000100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C81:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B0 V01N0001 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R39C82:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C83:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 S3_V06N0103 + +.tile R39C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0203 V06N0203 +arc: A1 V02N0701 +arc: B1 E1_H01W0100 +arc: C1 H02W0401 +arc: D1 H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0100 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A4 H02E0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B7 V02S0701 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D4 V00B0000 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F4 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1000100011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C87:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V01N0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 1000111110000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 F1 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 F4 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0601 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C90:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A4 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0401 F4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1011001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: C0 H02W0601 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1101010100000000 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEB.K1.INIT 0000110001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A3 S1_V02N0701 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 + +.tile R39C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEA.K0.INIT 0001010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 F5 +arc: A1 S1_V02N0501 +arc: A2 V00B0000 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 W1_H02E0401 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B2 H00L0000 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 W1_H02E0601 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 F5 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 F5 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 S1_V02N0301 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: V01S0000 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 F5 +arc: A2 H01E0001 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 W1_H02E0101 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 H01E0101 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: N1_V01N0001 F2 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R3C43:PLC2 +arc: V00B0000 E1_H02W0401 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F5A_SLICE +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C44:PLC2 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0301 S1_V02N0301 + +.tile R3C45:PLC2 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 + +.tile R3C46:PLC2 +arc: H00L0000 V02N0201 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: A0 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C47:PLC2 +arc: S1_V02S0001 H02W0001 +arc: W1_H02W0401 S1_V02N0401 + +.tile R3C48:PLC2 +arc: W1_H02W0001 V06N0003 + +.tile R40C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0501 +arc: A1 H02E0501 +arc: A4 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B4 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 F4 +arc: C4 S1_V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A2 V00B0000 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A7 F5 +arc: B0 V01N0001 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B7 H02E0301 +arc: C0 F4 +arc: C2 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: D0 F2 +arc: D2 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000100000100010 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A3 N1_V02S0701 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 W1_H02E0601 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 W1_H02E0201 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R40C103:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 F1 +arc: B4 H01E0101 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A2 V02S0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V02S0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: S1_V02S0301 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C105:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02E0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H01E0001 +arc: A3 S1_V02N0501 +arc: A6 V00T0100 +arc: B2 F3 +arc: B3 H02W0101 +arc: B6 V02S0501 +arc: C2 F6 +arc: C3 V02N0401 +arc: C6 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D6 H00L0100 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C106:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 N1_V02S0701 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0701 F7 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R40C107:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C6 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 F0 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F2 +arc: W3_H06W0103 F1 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0001000111011101 +word: SLICEA.K0.INIT 0011000000111111 +word: SLICEB.K1.INIT 0000000100100011 +word: SLICED.K0.INIT 0101010100000100 +word: SLICEA.K1.INIT 1110111011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C108:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00R0000 +arc: A2 E1_H02W0501 +arc: A4 F7 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B4 F1 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 F6 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D4 F2 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C109:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A7 N1_V02S0301 +arc: B0 W1_H02E0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C4 Q4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0000010110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R40C110:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C4 V00B0100 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V00B0100 F5 +arc: V00T0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEC.K1.INIT 0011001101010101 +word: SLICEC.K0.INIT 0000001100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C111:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0501 +arc: A5 F7 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0101 +arc: B5 H01E0101 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F5 +arc: N3_V06N0203 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0011010100110101 +word: SLICEC.K1.INIT 0000010100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C112:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D7 V00B0000 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R40C113:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 F5 +arc: V01S0100 F3 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C114:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02W0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: B0 V01N0001 +arc: B4 H02W0101 +arc: C0 H00L0000 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D4 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEC.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R40C115:PLC2 +arc: N1_V02N0401 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q2 +arc: V00T0000 Q2 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C116:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 + +.tile R40C17:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 E1_H01W0100 + +.tile R40C18:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: V01S0000 F2 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0000101110101010 +word: SLICEA.K1.INIT 0000100010101010 +word: SLICEB.K0.INIT 0101000111110000 +word: SLICEB.K1.INIT 0100000011110000 +word: SLICEC.K0.INIT 0000101010111010 +word: SLICEC.K1.INIT 0000101010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C19:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q7 +arc: N3_V06N0003 F3 +arc: V01S0000 F0 +arc: V01S0100 Q7 +word: SLICED.K0.INIT 0010001110101010 +word: SLICED.K1.INIT 0010001010100010 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R40C20:PLC2 +arc: E1_H02E0001 V01N0001 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: A0 V02S0701 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 H02E0701 +arc: A6 W1_H02E0501 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0201 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 F1 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0011110010101010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C21:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A3 F5 +arc: A6 F7 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 F3 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R40C22:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: A3 V02N0701 +arc: A5 N1_V02S0301 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 N1_V02S0201 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: S1_V02S0201 F2 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000001010011 +word: SLICED.K1.INIT 0011001100100010 +word: SLICED.K0.INIT 0001000000010101 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R40C23:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02E0501 +arc: A2 F7 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 H01W0100 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0001 +arc: D3 H01E0101 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 F5 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C24:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: A1 V02N0501 +arc: A2 H01E0001 +arc: A3 N1_V02S0501 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0100000000000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001000100010 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C25:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 N1_V01S0100 +arc: A7 Q7 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010000011101100 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1000100011111000 +word: SLICED.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C26:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A4 V02S0101 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C27:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 H02W0701 +arc: A5 V02S0101 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B7 F3 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R40C28:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: B1 Q1 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 W1_H02E0601 +arc: C4 V02S0001 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R40C29:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A6 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B6 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: V01S0000 F1 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C30:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 H06E0303 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0501 H06E0303 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C32:PLC2 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: A0 W1_H02E0701 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C33:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: A0 H02W0701 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 F7 +arc: A2 F7 +arc: A3 H01E0001 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B5 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: S3_V06S0303 F5 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000000011001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C35:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0701 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C36:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B5 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C5 E1_H01E0101 +arc: D0 H00R0000 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 0000000001001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C37:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V02S0501 +arc: A5 V02N0101 +arc: B5 F3 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: D3 V00T0100 +arc: D5 V02S0601 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010000010001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C38:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 F6 +arc: C3 H02W0601 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0001 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 F2 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000000111010 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 0000000010101011 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0010001000100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C39:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B1 H02E0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 F2 +arc: D7 H02W0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 0001000101010101 +word: SLICEA.K1.INIT 0000001000001110 +word: SLICED.K0.INIT 0000001000110010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEB.K1.INIT 0000000011110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C40:PLC2 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A2 F5 +arc: A3 F7 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C2 F4 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 F0 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 F0 +arc: D2 H01E0101 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: V01S0000 F3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C42:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 N1_V02S0301 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 V02S0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1000100010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C43:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 F7 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D0 H02W0201 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A5 H02E0701 +arc: A7 V00T0100 +arc: B5 H02E0301 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V00T0100 F1 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C45:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 V02N0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02E0501 +arc: A4 H02E0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C1 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: H01W0100 Q6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0501 Q5 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: V00T0000 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C46:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A6 H02E0701 +arc: B1 E1_H02W0101 +arc: B6 H01E0101 +arc: C1 S1_V02N0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S1_V02S0601 F6 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C47:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: C1 H02W0601 +arc: C3 H00R0100 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B6 H01E0101 +arc: C1 N1_V02S0601 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 S1_V02N0001 +arc: D6 H02W0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0401 F6 +arc: V00T0000 F2 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C49:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B5 F1 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 H00L0100 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 W1_H02E0001 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0401 F6 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 W1_H02E0301 +arc: B4 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C3 H00R0100 +arc: C4 H02E0401 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R40C51:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B3 V01N0001 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C52:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0501 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C1 N1_V02S0401 +arc: C3 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 F6 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000101001001110 +word: SLICED.K1.INIT 0100010011101110 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R40C53:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A4 V00B0000 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q3 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R40C54:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V02S0101 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F5 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C55:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A6 V02N0301 +arc: B1 S1_V02N0301 +arc: B6 H01E0101 +arc: C1 H02W0601 +arc: C2 F6 +arc: C3 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D6 H00R0100 +arc: E1_H02E0401 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F0 +arc: W1_H02W0201 F2 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C56:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02E0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0701 +arc: A3 V02S0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: S3_V06S0003 Q3 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100100001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C57:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02N0501 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C58:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: B0 F1 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B6 V02N0701 +arc: C0 H00L0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F3 +arc: V01S0000 Q0 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C59:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: C0 S1_V02N0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 V01N0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 0001001111011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C60:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C61:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B3 S1_V02N0301 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C62:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E3_H06W0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 H02E0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C65:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 E1_H01E0001 +arc: A4 H02E0701 +arc: A6 E1_H02W0501 +arc: B4 S1_V02N0501 +arc: C1 H02E0401 +arc: C4 V02S0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D4 V00B0000 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C66:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A7 H00R0000 +arc: B1 H02W0101 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C4 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D4 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101000001000100 +word: SLICEA.K1.INIT 0000110001000100 +word: SLICED.K1.INIT 0000000000100001 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R40C67:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A1 F7 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 V01N0001 +arc: B5 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H02E0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICED.K1.INIT 0101001100000000 +word: SLICEA.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R40C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A7 V00T0100 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C69:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A6 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R40C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 W1_H02E0501 +arc: A3 F7 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 H00L0000 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C3 F6 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000011100100 +word: SLICED.K1.INIT 0001000010110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R40C72:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 V00T0000 +arc: B2 F3 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 W1_H02E0601 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V02N0101 F1 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C73:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 V02S0101 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 W1_H02E0601 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F4 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0000101000100010 +word: SLICEA.K1.INIT 0000000001000001 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICEC.K1.INIT 0001000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C74:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 H02E0301 +arc: B4 H01E0101 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 F6 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 F2 +arc: D1 W1_H02E0001 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0100 F7 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K0.INIT 0000000000001001 +word: SLICED.K0.INIT 0100010001010000 +word: SLICEB.K1.INIT 0011000001010000 +word: SLICED.K1.INIT 0011000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R40C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 V02N0501 +arc: A4 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B4 V01S0000 +arc: B6 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F1 +word: SLICEC.K0.INIT 0101000101000000 +word: SLICED.K0.INIT 0000100000101010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C76:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D2 H02W0201 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1110010000011011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C77:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B2 V01N0001 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C2 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D2 N1_V02S0001 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEC.K1.INIT 0000000000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C78:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B0 V02N0301 +arc: B2 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V02S0601 +arc: C2 N1_V01S0100 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: V00T0000 F0 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICED.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0000000000001001 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C79:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile R40C80:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 F0 +arc: D3 V02N0201 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: C0 V02S0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F7 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R40C82:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H01E0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0701 +arc: A5 Q5 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06N0303 + +.tile R40C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: B0 H02E0101 +arc: C0 H00L0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1101110100001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C85:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 H00L0100 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C86:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V02S0401 +arc: A1 N1_V02S0501 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 F7 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H00R0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 F6 +arc: C5 V02S0201 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02E0701 +arc: A2 E1_H02W0501 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D5 E1_H02W0001 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C88:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V02N0701 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 F1 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C89:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 W1_H02E0701 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 F3 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W1_H02W0001 Q2 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111000000110000 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C90:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A5 V02S0101 +arc: B0 E1_H02W0101 +arc: B2 H00L0000 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101011100000000 +word: SLICEB.K0.INIT 1010101010100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C91:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 H02W0701 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 F3 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001000001010000 +word: SLICEC.K1.INIT 1011101011111010 +word: SLICEB.K1.INIT 0001000100010011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C92:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A2 H02W0501 +arc: B2 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 H00R0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 W1_H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00R0000 +arc: A3 H02W0701 +arc: B0 V00B0000 +arc: B3 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C3 S1_V02N0401 +arc: C7 V01N0101 +arc: D0 S1_V02N0201 +arc: D3 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1000000010101010 +word: SLICEB.K1.INIT 0101001100000000 +word: SLICED.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R40C94:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 V06S0203 +arc: B3 N1_V02S0101 +arc: C3 W1_H02E0601 +arc: D3 V00B0100 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0011000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 F3 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A0 S1_V02N0501 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C97:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 F5 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 H01E0001 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D2 V02N0201 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B6 F3 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C6 F4 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C99:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 E1_H01W0000 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 H01E0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: N3_V06N0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R41C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 H02E0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C101:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 F6 +arc: C6 V00B0100 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 H01E0101 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0501 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 E1_H01W0000 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D5 V02S0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C103:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0501 +arc: A2 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 F1 +arc: B4 H02E0101 +arc: B5 H01E0101 +arc: B6 E1_H02W0301 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V00B0100 +arc: C6 E1_H02W0601 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00L0100 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C104:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A2 V02N0701 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: V00B0000 F6 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: B0 S1_V02N0301 +arc: C0 H02W0401 +arc: D0 N1_V01S0000 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C106:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02W0501 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A5 W1_H02E0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 F3 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C107:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 F5 +arc: A1 H00L0000 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 V02N0701 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F4 +arc: N1_V02N0201 F0 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C108:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 +arc: A5 V00T0100 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C3 H00L0100 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D3 E1_H02W0201 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +word: SLICED.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000001111110011 +word: SLICEC.K1.INIT 0000010100000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C109:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C110:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 S1_V02N0101 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C111:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 Q5 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 N1_V02S0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C113:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V06S0103 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C114:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: B0 S1_V02N0301 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C115:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile R41C116:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R41C117:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R41C118:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 + +.tile R41C14:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R41C15:PLC2 +arc: N1_V02N0101 S3_V06N0103 + +.tile R41C16:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E3_H06E0103 V06S0103 + +.tile R41C17:PLC2 +arc: N1_V02N0101 H02E0101 + +.tile R41C18:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N3_V06S0303 + +.tile R41C19:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0201 H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A5 H02E0701 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0601 Q6 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 Q6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1000101011001110 +word: SLICEA.K1.INIT 1000000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0100010100000001 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R41C20:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 H02E0101 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 0011110010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R41C21:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0101110010101100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1111001110111011 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R41C22:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0501 +arc: A1 W1_H02E0501 +arc: B1 H02E0101 +arc: B2 V01N0001 +arc: B4 H02W0101 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0601 F4 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R41C23:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: B0 V01N0001 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 N1_V02S0001 +arc: D3 F2 +arc: D4 F2 +arc: D5 W1_H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R41C24:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 F7 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 W1_H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010000011101100 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R41C25:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0501 F7 +arc: S1_V02S0601 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R41C26:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B4 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000101000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C27:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 W1_H02E0301 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C6 N1_V02S0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0401 Q6 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C28:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N1_V01S0100 +arc: V00B0000 H02E0601 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 N1_V02S0501 +arc: A7 V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 N1_V01S0000 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C29:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0701 +arc: B1 V02N0101 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C30:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C31:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: A2 V00B0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C32:PLC2 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C33:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A6 V02S0301 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 F4 +arc: C4 V01N0101 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0010001000100011 +word: SLICEB.K1.INIT 0100010001000101 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C34:PLC2 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02N0701 +arc: A0 F7 +arc: A1 V02S0501 +arc: A2 F5 +arc: A5 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H02W0201 +arc: D5 H02W0001 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICEC.K1.INIT 0000000001110100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C35:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: A1 F5 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: B2 H02W0101 +arc: B4 V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 V02N0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00B0000 F4 +arc: W1_H02W0301 F1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C36:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A7 H00R0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C2 N1_V02S0601 +arc: C3 V02N0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D6 W1_H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C37:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0601 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 H02E0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B5 E1_H02W0301 +arc: B6 H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: S3_V06S0103 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C38:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D4 H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: V01S0100 F1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0000110000001101 +word: SLICEA.K1.INIT 0001010100000100 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C39:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1010001010000000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000110010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R41C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 H02E0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K1.INIT 1010100000100000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICED.K0.INIT 0001000101010000 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C41:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 E1_H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 V02S0501 +arc: A3 H02W0501 +arc: A6 E1_H02W0701 +arc: B1 V02N0101 +arc: B3 F1 +arc: C1 H00L0000 +arc: C6 V01N0101 +arc: D1 N1_V01S0000 +arc: D3 E1_H02W0201 +arc: D6 V01N0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +arc: W1_H02W0101 F3 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R41C43:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A2 H02E0501 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 H01W0100 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K1.INIT 0000000001110010 +word: SLICEB.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B7 F3 +arc: C0 H02E0601 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 F0 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +word: SLICED.K1.INIT 0000101000001011 +word: SLICEB.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02W0701 +arc: A5 F7 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1010000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C46:PLC2 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: A3 H02E0501 +arc: A7 H00R0000 +arc: B3 H00R0100 +arc: B7 H02E0101 +arc: C3 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D3 H01E0101 +arc: D7 H02W0001 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C47:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A5 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q5 +arc: H01W0100 F1 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1011111110001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A4 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 H01E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 F7 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C51:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: B1 V01N0001 +arc: C1 V02S0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C52:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 H02W0101 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 F7 +arc: S3_V06S0303 Q5 +arc: V00T0000 F0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R41C53:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 N1_V02S0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 F5 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: W1_H02W0001 F2 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E1_H02W0601 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 V02S0301 +arc: B3 V02N0101 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0601 F4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R41C55:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02W0501 +arc: A2 V02S0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H02W0501 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B4 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000010011110100 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02E0401 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICEA.K1.INIT 1110000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C58:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A3 V02N0701 +arc: B3 N1_V02S0101 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK3 CLK0 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R41C59:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A6 H02E0701 +arc: B0 H02E0301 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: C0 H00L0000 +arc: C5 F6 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0201 F2 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A3 H02W0501 +arc: A4 H02E0501 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C61:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02E0101 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 S1_V02N0501 +arc: A3 H02E0501 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 S1_V02N0301 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q2 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V02N0001 Q2 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1010000011000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C62:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0000 +arc: A3 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 E1_H01W0100 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: B7 V02N0701 +arc: C1 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: V00B0000 F4 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R41C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: B1 V02S0101 +arc: B3 V02N0101 +arc: B7 H01E0101 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F0 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R41C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 F6 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R41C65:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 E1_H02W0601 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 H02W0501 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R41C68:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 V02S0101 +arc: B0 W1_H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEA.K1.INIT 0000101000100010 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C69:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A6 F5 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C70:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 N1_V02S0501 +arc: A3 W1_H02E0701 +arc: A6 N1_V01S0100 +arc: B0 S1_V02N0301 +arc: B2 V02S0101 +arc: B3 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D6 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H01E0001 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F6 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0101000000110000 +word: SLICED.K0.INIT 0000000000001001 +word: SLICEB.K1.INIT 0011111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R41C72:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 V00B0000 +arc: B1 V00T0000 +arc: B5 H02W0301 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C5 H02E0601 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D5 E1_H01W0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: N1_V01N0001 F1 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 0100011110111000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R41C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H02W0701 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R41C74:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 F5 +arc: A3 V02N0501 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 W1_H02E0401 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICEC.K1.INIT 0000110000001010 +word: SLICEC.K0.INIT 0011110001011010 +word: SLICEB.K0.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A4 V02S0301 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D4 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 0000001010001010 +word: SLICEA.K0.INIT 0000000011000011 +word: SLICEA.K1.INIT 0000000010000010 +word: SLICED.K1.INIT 0000101000001100 +word: SLICEC.K0.INIT 0001000010110000 +word: SLICED.K0.INIT 0001000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H01E0001 +arc: A4 N1_V02S0101 +arc: B4 H00L0000 +arc: C0 N1_V02S0401 +arc: C4 H02E0601 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 H02E0601 +arc: N1_V02N0001 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0010000000101010 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0101010110101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R41C77:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00R0000 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 F2 +arc: D6 V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: V01S0000 F6 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 0000101000100010 +word: SLICED.K1.INIT 0000110000001010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000101100001000 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000000000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 H01E0001 +arc: A5 S1_V02N0301 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B5 H00R0000 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C79:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V01N0101 +arc: A2 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0100 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C80:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 V01N0101 +arc: B0 N1_V02S0101 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C81:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1010000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R41C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0401 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: V00T0100 F3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C83:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0701 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 V02N0701 +arc: B7 H02E0301 +arc: C2 H02W0601 +arc: C3 F4 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: W1_H02W0301 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 F1 +arc: B1 V02S0301 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 V00B0000 +arc: B3 H02E0101 +arc: C3 H02E0401 +arc: D3 H02E0001 +arc: F3 F3_SLICE +arc: H01W0000 F3 +word: SLICEB.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile R41C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V00T0000 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A7 F5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 F2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C88:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 V01N0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B6 H02W0301 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D6 H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: V00B0000 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110100000000 +word: SLICEC.K0.INIT 0000000000000011 +word: SLICEB.K1.INIT 0101011100000000 +word: SLICEB.K0.INIT 0000110001001100 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 + +.tile R41C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A5 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C5 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F7 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1010100010101010 +word: SLICEA.K1.INIT 0100010001001100 +word: SLICEC.K1.INIT 0101000001110000 +word: SLICEB.K0.INIT 0000000000010001 +word: SLICED.K1.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R41C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0601 +arc: D1 S1_V02N0201 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F6 +word: SLICED.K1.INIT 1000000010101010 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000010110101111 +word: SLICED.K0.INIT 1011001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0100 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 V02N0301 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 F3 +arc: C0 H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H00L0000 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 F4 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C96:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V01N0101 +arc: A0 H00L0100 +arc: A2 S1_V02N0501 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 F4 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C99:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 W1_H02E0301 +arc: B2 F1 +arc: B3 W1_H02E0101 +arc: B4 N1_V02S0701 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: C7 W1_H02E0401 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B1 V02S0301 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V01S0000 +arc: C1 N1_V02S0601 +arc: C2 V02S0601 +arc: C3 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 V02N0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F1 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C101:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A2 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 V02N0301 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 F3 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: V01S0000 F1 +arc: V01S0100 F5 +arc: W1_H02W0201 F2 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1101000001010000 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D1 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C103:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C104:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 V02S0601 +arc: C2 F6 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: M0 H01E0001 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C105:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C4 F6 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: V00B0100 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C106:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02W0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: C0 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: D0 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F5 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C107:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A3 F5 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: N3_V06N0003 F3 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C108:PLC2 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B1 H02E0101 +arc: B4 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C4 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V02S0001 +arc: D1 V00B0100 +arc: D4 H02E0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C109:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06N0303 +arc: A0 E1_H02W0501 +arc: B0 H01W0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C110:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N3_V06N0003 Q0 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C111:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N1_V01S0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C112:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile R42C113:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 N1_V02S0701 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C114:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: W3_H06W0303 N3_V06S0303 + +.tile R42C115:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R42C18:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R42C19:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 + +.tile R42C20:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: A0 F7 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1010000011101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C21:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 E1_H02W0701 +arc: A1 V01N0101 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R42C22:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B4 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F6 +arc: V01S0000 Q2 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R42C23:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C3 W1_H02E0401 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICED.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C24:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F4 +arc: N3_V06N0303 F5 +arc: V00T0000 Q2 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011001110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C25:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00L0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C26:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 V02S0501 +arc: A3 H02W0501 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H01W0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R42C27:PLC2 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0401 Q6 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1101010111000000 +word: SLICEC.K0.INIT 1010000011101100 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1111001000100010 +word: SLICED.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C28:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02S0601 +arc: A2 H02E0501 +arc: A4 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V02S0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C29:PLC2 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 F7 +arc: A5 Q5 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C30:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: B0 V02N0101 +arc: C0 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0401 V02S0401 +arc: A1 N1_V02S0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C32:PLC2 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H02E0001 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: B0 V02S0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C33:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: B0 S1_V02N0101 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C34:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: A0 H00L0000 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H02W0401 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C35:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0601 E1_H02W0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEC.K1.INIT 0000000001011100 +word: SLICEB.K1.INIT 0001001100010000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 N1_V02S0501 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 F1 +arc: B5 N1_V02S0501 +arc: B6 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A6 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 V00B0000 +arc: B4 V02N0701 +arc: B6 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C6 F4 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D4 F0 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICED.K0.INIT 0000000000101110 +word: SLICEA.K1.INIT 0000011100000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C5 V00B0100 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R42C40:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A7 H02W0501 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C7 V01N0101 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 F0 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 0001000101010000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICEB.K0.INIT 0011000000110001 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C41:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 N1_V02S0501 +arc: A1 V01N0101 +arc: A2 H02E0701 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 H02E0701 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V02N0201 +arc: D1 F0 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F1 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A6 H02W0701 +arc: B0 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 H00L0100 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C43:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0601 V06S0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A1 H02W0501 +arc: A2 H02E0501 +arc: A4 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0101 F1 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1011101100001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A3 E1_H01E0001 +arc: B3 V02S0101 +arc: C3 H02E0601 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: S1_V02S0301 F3 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C45:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 F7 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 F3 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V02N0701 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N3_V06N0203 F4 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C46:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02E0701 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R42C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A5 H02W0501 +arc: B5 S1_V02N0701 +arc: C5 V00B0100 +arc: D5 H00R0100 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1110010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N3_V06S0203 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: B1 V00B0000 +arc: B5 V02S0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R42C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A6 W1_H02E0501 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: C0 N1_V01N0001 +arc: C2 H00R0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0000010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R42C50:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A6 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B6 V02S0501 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C3 H00L0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C51:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 E1_H02W0501 +arc: A4 V02S0101 +arc: B4 H02E0101 +arc: C1 H02W0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C52:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K0.INIT 1000110010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C53:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V02S0301 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B3 H01W0100 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 F2 +arc: V00B0100 F7 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R42C54:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C55:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B5 F1 +arc: C0 H02W0601 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C5 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C56:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: B0 H00R0100 +arc: B1 H02E0301 +arc: B2 F1 +arc: B4 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D4 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0010011101110111 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R42C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 S1_V02N0501 +arc: A4 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 0000111101000100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C58:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A6 N1_V01S0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B6 V02N0701 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 S1_V02N0601 +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEB.K1.INIT 1111011111010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C59:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A6 E1_H01W0000 +arc: B0 H00R0100 +arc: B6 V02S0501 +arc: C0 F6 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C60:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C5 V01N0101 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R42C61:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H00L0100 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C2 V02N0401 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 H02E0201 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100100000001000 +word: SLICED.K1.INIT 1111101100111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 F0 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q5 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 F4 +arc: S3_V06S0203 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R42C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B7 H01E0101 +arc: C0 F4 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B3 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V01S0100 +arc: D3 F0 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R42C65:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A3 H02E0701 +arc: A6 V02N0301 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B3 W1_H02E0101 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C66:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 H02E0701 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 V00B0000 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 F0 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0000111100100010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0010001010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R42C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H01E0101 +arc: D3 S1_V02N0201 +arc: D6 S1_V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R42C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 F5 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1011100001000111 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R42C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B3 S1_V02N0301 +arc: B6 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D3 H00R0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H02W0601 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEA.K0.INIT 0101111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R42C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: B0 H01W0100 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B5 H02E0301 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: D0 N1_V02S0001 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +word: SLICEC.K1.INIT 0010001000001010 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEC.K0.INIT 0100011100000000 +word: SLICEA.K1.INIT 0100010001010000 +word: SLICEA.K0.INIT 0000001010001010 +word: SLICED.K0.INIT 0000000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 H01E0101 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 F0 +arc: D4 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1100000000000000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000010000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0110011000111100 +word: SLICEC.K1.INIT 0000000011011000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C73:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 H02W0501 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: V01S0000 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C74:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A7 H00R0000 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 F3 +arc: B7 H02W0301 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 H01E0001 +arc: C7 H02E0401 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F0 +arc: N1_V02N0701 F5 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 0110011000111100 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C75:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A7 H02E0701 +arc: B0 V02N0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 H00R0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1100111110101111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0010011111011000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C76:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R42C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A6 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C6 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000010101100 +word: SLICEA.K0.INIT 0000000000100011 +word: SLICEA.K1.INIT 0010001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C78:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C79:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C80:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B5 W1_H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 F6 +arc: C3 F6 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C81:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V02S0701 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q5 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C82:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A4 W1_H02E0701 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 V02N0301 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C1 H00R0100 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 0010101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C83:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q4 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 F7 +arc: A6 V02S0301 +arc: A7 E1_H02W0501 +arc: B0 V01N0001 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C6 V02S0201 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0201 F0 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R42C85:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 H00R0000 +arc: B1 H02E0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 + +.tile R42C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B6 V00B0100 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0100011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0100 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02S0601 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0011010111111111 +word: SLICEA.K1.INIT 0011010100000000 +word: SLICED.K0.INIT 0011000001110000 +word: SLICEB.K0.INIT 0011000001110000 +word: SLICED.K1.INIT 1010101010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C90:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A7 H00L0000 +arc: B7 H02W0301 +arc: C7 H02E0401 +arc: D7 V01N0001 +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICED.K1.INIT 1000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: A1 V02N0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B6 F1 +arc: B7 V02N0501 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 1101000001010000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICED.K0.INIT 1100100011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A4 V02S0101 +arc: A6 H00R0000 +arc: B4 V02N0501 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0001 +arc: D4 V01N0001 +arc: D6 F0 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000101001011111 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R42C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A4 E1_H02W0501 +arc: B1 H02E0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0001 +arc: D4 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0001000110111011 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R42C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 N1_V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 N1_V02S0501 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 W1_H02E0201 +arc: D1 N1_V02S0201 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0201 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: W1_H02W0101 F1 +word: SLICED.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K1.INIT 0011000001110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 V01N0101 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0001 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 N1_V01N0001 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 V02N0701 +arc: A4 F7 +arc: A5 V00B0000 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 V02S0001 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C99:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: N1_V01N0101 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B6 V00B0100 +arc: B7 N1_V02S0501 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: V00T0100 F3 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICEA.K0.INIT 0111011101110111 +word: SLICEA.K1.INIT 0000101001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C101:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 H02E0701 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 F3 +arc: B5 W1_H02E0101 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +arc: V00T0000 F0 +arc: V01S0100 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C102:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000010111110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A2 V00B0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B2 H02E0301 +arc: B4 V01S0000 +arc: B5 W1_H02E0301 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C2 V02S0601 +arc: C4 V01N0101 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V00T0100 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C104:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 H02E0601 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 F0 +arc: D6 H01W0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 N1_V02S0201 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0001 F0 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C106:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C107:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A6 H00R0000 +arc: B0 V01N0001 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B6 F3 +arc: C0 H02E0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C6 H01E0001 +arc: D0 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C108:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H01W0100 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C109:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H06W0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C110:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 V01N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C111:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E1_H01W0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 + +.tile R43C112:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: A7 N1_V02S0101 +arc: C7 S1_V02N0001 +arc: D7 V00B0000 +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0000 F7 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1010111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C113:PLC2 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0103 +arc: A0 H02W0501 +arc: A1 V01N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C114:PLC2 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 + +.tile R43C115:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 + +.tile R43C20:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: V00B0100 V02S0101 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: C0 V02N0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C21:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: A1 E1_H01E0001 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 H02E0401 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: LSR0 V00T0100 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: V00B0100 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1101110001010000 +word: SLICEC.K1.INIT 1100111000001010 +word: SLICED.K0.INIT 1100000011101010 +word: SLICED.K1.INIT 1010111000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C22:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: A2 H02W0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B3 E1_H01W0100 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 Q6 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C23:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 V01N0101 +arc: A0 V02S0501 +arc: A4 W1_H02E0501 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F6 +arc: W1_H02W0101 Q3 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000001000111 +word: SLICEC.K1.INIT 0000000011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: C0 H02E0601 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 F2 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C25:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: W1_H02W0601 V06N0303 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C26:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 F6 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C27:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: S1_V02S0001 H02E0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: A0 H02W0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C3 H00L0100 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: V01S0000 Q0 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C28:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: A5 V02N0101 +arc: B0 V00T0000 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C29:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0001 V02N0001 +arc: A1 N1_V02S0701 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C30:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: B0 H02E0101 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C31:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 V02N0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C32:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N3_V06S0303 +arc: A4 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C4 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D4 V02N0401 +arc: D7 V00B0000 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C33:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 V02S0701 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: B6 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C34:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: A7 H02E0701 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000011100000010 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C35:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A3 V00T0000 +arc: A6 S1_V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F0 +arc: D3 W1_H02E0201 +arc: D6 H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1010001010000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 0001000000110010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C4 V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D4 H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEA.K0.INIT 0101000011111010 +word: SLICEA.K1.INIT 0100010011101110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C37:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S3_V06S0103 F1 +arc: V00T0000 Q0 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B4 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C4 W1_H02E0601 +arc: C7 V02N0001 +arc: D0 F2 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D4 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F0 +arc: V00T0100 F1 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100001100000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000001011100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C39:PLC2 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0701 +arc: A2 N1_V02S0701 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A5 N1_V01S0100 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 F4 +arc: C7 V02S0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEC.K0.INIT 0001001100010011 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000000101110 +word: SLICEC.K1.INIT 0100010001000101 +word: SLICED.K1.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C40:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000001000110010 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H01E0001 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B4 V02N0501 +arc: B6 V00B0100 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: D0 V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: V00T0000 F0 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R43C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H02W0501 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F1 +arc: V00B0000 F6 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: A1 S1_V02N0701 +arc: A3 N1_V02S0701 +arc: A6 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0100 +arc: B6 V02N0501 +arc: C1 F6 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C6 H02E0401 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D6 H00L0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C44:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: C1 F6 +arc: C2 N1_V02S0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: D1 F2 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N3_V06N0103 F1 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C45:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A5 E1_H01W0000 +arc: A6 N1_V02S0101 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: N3_V06N0003 F3 +arc: S3_V06S0303 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 S1_V02N0501 +arc: A3 S1_V02N0701 +arc: B1 V02S0101 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0501 Q7 +arc: S3_V06S0203 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C47:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 S1_V02N0701 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D5 H02W0201 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: S3_V06S0303 Q5 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 F1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R43C49:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02W0701 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: C1 V02N0601 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C51:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V01N0001 + +.tile R43C52:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B5 F1 +arc: C0 V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 1011101110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R43C53:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 S1_V02N0501 +arc: A7 V00T0100 +arc: B0 F3 +arc: B3 H02W0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C3 H00R0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1010000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 H02W0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0501 +arc: A4 E1_H01W0000 +arc: A6 W1_H02E0501 +arc: B1 V02S0101 +arc: B4 V02S0501 +arc: B6 V00T0000 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C4 V00T0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D4 E1_H01W0100 +arc: D6 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0000000100010001 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F1 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 1101000001010000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C56:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 E1_H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 H02E0501 +arc: A2 H02W0501 +arc: A3 V00B0000 +arc: A5 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 H02W0101 +arc: B6 V01S0000 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: M4 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R43C58:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B3 H00R0000 +arc: B7 N1_V02S0501 +arc: C0 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C59:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A6 V00T0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B3 V02S0101 +arc: B6 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 W1_H02E0601 +arc: C3 H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D6 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0101001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: B4 S1_V02N0501 +arc: C1 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: M0 V00B0100 +arc: M3 H02W0201 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C62:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 F7 +arc: A3 H02E0701 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICED.K1.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C63:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B5 E1_H02W0301 +arc: C5 H02E0401 +arc: D5 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C64:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A2 V02S0501 +arc: A4 H02E0501 +arc: A6 W1_H02E0701 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 V01S0000 +arc: C1 E1_H02W0601 +arc: C2 F4 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C65:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V01N0101 +arc: A5 H02W0701 +arc: B0 H02W0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C5 V02N0001 +arc: D0 H00R0000 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F0 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0011001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 F7 +arc: A7 H02W0501 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000001011111 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A4 H02W0501 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00B0100 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C68:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A4 H02W0701 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 F1 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0001000010111010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 F2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R43C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 V02N0101 +arc: B3 F1 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: D0 N1_V02S0201 +arc: D1 V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F3 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0001000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 H02E0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 F0 +arc: D3 V02N0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F7 +word: SLICEA.K1.INIT 0000000000000010 +word: SLICEB.K1.INIT 0011000001010000 +word: SLICEA.K0.INIT 0000000010101100 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R43C73:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C4 E1_H02W0601 +arc: C6 H02W0401 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0100010000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0301 +arc: C0 E1_H01W0000 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111001111110101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C75:PLC2 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B5 S1_V02N0701 +arc: C2 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: S1_V02S0001 F2 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C76:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R43C77:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 + +.tile R43C78:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 + +.tile R43C79:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0101 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C80:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A5 V00B0000 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02S0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K1.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C82:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V01N0101 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B1 H01W0100 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 H02E0101 +arc: C1 W1_H02E0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D1 W1_H02E0001 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 F3 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B1 E1_H01W0100 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 F3 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C85:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C86:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R43C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A6 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R43C88:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H01E0001 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B3 H00R0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 E1_H02W0001 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 0100010001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C89:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: B2 V02N0101 +arc: C2 S1_V02N0601 +arc: D2 V00B0100 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R43C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A6 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 H00R0000 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C6 V02N0001 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D6 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +word: SLICED.K0.INIT 0001000100010011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R43C91:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 V02S0501 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0301 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICEC.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1000000011110000 +word: SLICED.K1.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C93:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000011100000000 +word: SLICEA.K1.INIT 1011111110101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D0 H02E0001 +arc: D1 W1_H02E0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F1 +arc: S1_V02S0101 F3 +arc: V00T0000 F2 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: M0 V00T0100 +arc: V00B0100 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011000000111111 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R43C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: A1 V01N0101 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H02W0701 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 H01E0101 +arc: A1 H02E0501 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B1 V02N0101 +arc: B3 F1 +arc: B4 V01S0000 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C1 H02E0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C98:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H02E0101 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: D0 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 H02E0701 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02W0501 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: S1_V02S0301 F3 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R44C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: D0 V02N0201 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02W0601 +arc: M2 V00T0100 +arc: N1_V02N0001 F0 +arc: W1_H02W0001 F2 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R44C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0100 +arc: A7 V02N0301 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 F4 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V01N0101 F7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101000001011111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A1 H00R0000 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 N1_V02S0701 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 F4 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 F0 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0101 F1 +arc: V01S0100 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C103:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 V00B0100 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V02S0201 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F1 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C105:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V01N0101 +arc: A3 E1_H02W0701 +arc: B3 H00R0100 +arc: C3 S1_V02N0401 +arc: D3 E1_H02W0201 +arc: F3 F3_SLICE +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C106:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F7 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C107:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C108:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 H02E0101 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0201 +arc: D4 F0 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C109:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A5 Q5 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C110:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 V06N0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q6 +arc: N1_V02N0701 Q7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C111:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 N3_V06S0003 +arc: B4 E1_H02W0101 +arc: C4 H02W0401 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: F4 F4_SLICE +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1100000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R44C112:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A6 E1_H01W0000 +arc: C6 V02N0001 +arc: D6 S1_V02N0401 +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R44C113:PLC2 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: W1_H02W0101 N1_V01S0100 +arc: A0 H00L0000 +arc: B0 H02E0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 V06N0003 + +.tile R44C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R44C17:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R44C19:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 + +.tile R44C20:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: A0 F5 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 V00B0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C21:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: A6 W1_H02E0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R44C22:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06S0303 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A4 F7 +arc: A7 N1_V02S0101 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B6 E1_H02W0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0000000100110001 +word: SLICED.K0.INIT 0000111100001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0001000100000011 +word: SLICEC.K0.INIT 0000111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R44C23:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A4 N1_V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C24:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 F7 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D7 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 Q3 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000100011111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C25:PLC2 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 E1_H02W0401 +arc: A6 S1_V02N0101 +arc: B0 V00B0000 +arc: B6 V02N0701 +arc: C0 E1_H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0101001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C26:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R44C27:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A6 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0010000000101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C28:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: A2 N1_V02S0701 +arc: A4 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D4 V01N0001 +arc: D5 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0100000001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: B0 S1_V02N0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C30:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 W1_H02E0701 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02N0401 +arc: B0 S1_V02N0301 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C32:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 V06N0303 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 H01E0001 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 H02W0301 +arc: B2 F1 +arc: B3 H00L0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 N1_V01S0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICED.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C33:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A1 F7 +arc: A5 N1_V02S0301 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A3 F7 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0101 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0601 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0001001100010000 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 0101000001010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 V02S0501 +arc: C0 N1_V02S0601 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: D0 V02N0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C36:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02S0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: A5 V02S0301 +arc: A6 W1_H02E0501 +arc: B0 W1_H02E0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000000001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C37:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A2 H02E0501 +arc: B0 S1_V02N0101 +arc: B2 V02N0101 +arc: B5 E1_H02W0301 +arc: C0 V02N0401 +arc: C2 S1_V02N0401 +arc: C5 H02E0601 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: S1_V02S0201 F2 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEB.K0.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C38:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00T0100 H02W0101 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 E1_H02W0701 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 N1_V02S0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K1.INIT 0100010001000101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C39:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K1.INIT 0000000000111010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 1010001010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C40:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: D2 V02S0201 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V00T0000 F0 +arc: V01S0000 F1 +word: SLICEC.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1101000010000000 +word: SLICEB.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0000010101000100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0010001000100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C41:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C2 E1_H02W0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: D0 V02S0001 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F3 +arc: S3_V06S0203 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICEA.K0.INIT 0000000000111010 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C42:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 F3 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1110010000000000 +word: SLICEC.K0.INIT 0101000001010001 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 F5 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F5 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000010101000100 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0203 V06S0203 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 F5 +arc: A4 E1_H01W0000 +arc: A5 E1_H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M0 V00B0000 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V01N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A7 Q7 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: C1 H02W0601 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 V02N0301 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0100 +arc: C6 H01E0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100010010000000 +word: SLICED.K0.INIT 0000111101110111 +word: SLICED.K1.INIT 1010001010000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 W1_H02E0501 +arc: A7 H00R0000 +arc: B1 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R44C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 V06N0203 +arc: A2 H02E0501 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B5 V02N0701 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C6 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0011001101010000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R44C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C50:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0501 +arc: A5 H02E0701 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02E0101 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 F6 +arc: C3 N1_V02S0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C51:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q3 +arc: M3 H00R0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q7 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0001001111011111 +word: SLICEA.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C52:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 H02W0101 +arc: C1 H02W0401 +arc: C3 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q6 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 N1_V01N0101 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 Q1 +arc: S3_V06S0303 Q6 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0001101101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0001 +arc: D3 V01S0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1110010011101110 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100100001000000 +word: SLICED.K1.INIT 1111101101110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0101 +arc: C0 F6 +arc: C1 F6 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 0001000011011100 +word: SLICEA.K1.INIT 0101000011111010 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C55:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 F5 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 H02E0401 +arc: C4 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: B0 V00T0000 +arc: B4 E1_H02W0301 +arc: C0 H02W0401 +arc: C2 H00R0100 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02N0201 +arc: D4 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R44C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 E1_H02W0701 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C1 V02S0401 +arc: C2 V02S0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D4 F2 +arc: D5 V02S0601 +arc: D6 H02E0001 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V01S0000 F0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R44C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A6 V02N0101 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A6 N1_V02S0301 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C1 H02E0401 +arc: C3 S1_V02N0601 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D6 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 F7 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0001 F2 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1011000010000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R44C60:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: B0 V01N0001 +arc: B2 S1_V02N0101 +arc: B4 H01E0101 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 0001001100010011 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0000 +arc: A3 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: B0 F3 +arc: B1 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B6 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 H00R0100 +arc: C5 H02W0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 V02N0201 +arc: D5 N1_V02S0401 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R44C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: B1 V02S0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0203 F4 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C63:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0701 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1101100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 V06N0203 +arc: A0 E1_H02W0701 +arc: A1 H02E0701 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 F1 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V00T0000 F2 +arc: W3_H06W0303 Q6 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R44C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A6 N1_V02S0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B6 H02W0101 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D6 H00R0100 +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 V00B0100 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0100 +arc: B3 E1_H02W0101 +arc: B5 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A5 V02S0101 +arc: A7 H02E0501 +arc: B5 H00R0000 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C5 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K1.INIT 1000100011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 V00B0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D5 H00R0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: V01S0000 F1 +word: SLICEC.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R44C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1111101100111011 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 1011111110110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 V00T0000 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000101001011111 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 1111101101110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C71:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 N1_V02S0501 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101111111010101 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 0101010000010000 +word: SLICEB.K0.INIT 0101010000010000 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 V06N0303 +arc: A0 F5 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B2 N1_V02S0301 +arc: B4 W1_H02E0101 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C73:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 S1_V02N0701 +arc: A3 F5 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0101 +arc: B3 F1 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F6 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100001110011001 +word: SLICEA.K0.INIT 0110011000111100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C74:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V01N0101 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 N1_V02S0501 +arc: A5 S1_V02N0101 +arc: A6 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 F4 +arc: C6 V02N0201 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R44C75:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 F5 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: B0 V00T0000 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: D0 V02S0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000000010100101 +word: SLICEB.K1.INIT 0000100000000100 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C76:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R44C77:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 S3_V06N0303 + +.tile R44C78:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile R44C79:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C80:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 H02W0501 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0100 F7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C81:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V01N0001 +arc: B2 V02N0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C82:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00B0100 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: S1_V02S0401 Q6 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C83:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 F5 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: C0 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 H02E0601 +arc: N1_V01N0001 F3 +arc: V01S0000 F7 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000001010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R44C84:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02E0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: A0 H02W0701 +arc: A4 V00T0100 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B4 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C4 H02W0401 +arc: C7 H02W0601 +arc: D0 E1_H02W0201 +arc: D4 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0001 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V01N0001 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 W1_H02E0101 +arc: B2 F1 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 F4 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0100 +arc: A7 V02S0101 +arc: B0 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D6 F0 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1100001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R44C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C88:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: C2 E1_H02W0601 +arc: C4 H02W0401 +arc: D2 V02N0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000110001001100 +word: SLICEB.K0.INIT 1010100010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0401 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C4 V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: N1_V01N0101 F0 +arc: V01S0000 F6 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 0001010100000000 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0001000110111011 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R44C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 H02W0701 +arc: A3 H02E0501 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001101010101 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 1101111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0701 +arc: A4 F5 +arc: A5 F7 +arc: A7 H02W0501 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B7 H02W0101 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V01N0101 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1100010001000100 +word: SLICEC.K1.INIT 0000000000010001 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEC.K0.INIT 0101000001110000 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R44C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A4 V00T0100 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 V00T0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICED.K1.INIT 0111011100000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000010110101111 +word: SLICED.K0.INIT 1000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 H02W0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R44C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0501 +arc: A2 V02N0501 +arc: A3 F5 +arc: A5 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D1 H01E0101 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0101000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R44C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: V00B0100 F5 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000110000111111 +word: SLICEC.K1.INIT 0011000011110000 +word: SLICEB.K0.INIT 0000010001000100 +word: SLICEB.K1.INIT 1010111011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 F2 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C98:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A4 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C7 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 V02N0601 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F7 +arc: S3_V06S0203 F4 +arc: W3_H06W0003 F0 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R44C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 V01N0101 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 F4 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D3 N1_V02S0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: S3_V06S0103 F2 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0000110000111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B1 H02W0101 +arc: B2 H00R0100 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V02N0001 F0 +arc: S1_V02S0601 F6 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 H02E0501 +arc: A4 N1_V02S0101 +arc: A6 F5 +arc: A7 H02W0501 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 F1 +arc: B7 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100000000110000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 S1_V02N0701 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 H01W0100 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C103:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D5 E1_H01W0100 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C104:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A3 V00B0000 +arc: A6 S1_V02N0301 +arc: B3 H02E0101 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C3 W1_H02E0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 V00T0100 +arc: D6 H00R0100 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C105:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 W1_H02E0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C106:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C107:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C108:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V00T0000 +arc: A5 Q5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C109:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C110:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A5 Q5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: V00B0000 Q6 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C111:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 + +.tile R45C112:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 + +.tile R45C113:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 N3_V06S0003 + +.tile R45C114:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 + +.tile R45C20:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 + +.tile R45C21:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 + +.tile R45C22:PLC2 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02W0401 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 H02W0101 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 E1_H01W0100 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 F7 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C23:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N3_V06S0203 +arc: A6 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 N1_V02S0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R45C24:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 V02N0501 +arc: B0 V00B0000 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C25:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H01E0001 +arc: A0 V02S0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C26:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: C2 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C27:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0601 V02S0601 +arc: B0 V00B0000 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C28:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 V06N0303 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D5 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R45C29:PLC2 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: B0 V02N0101 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C30:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 V02N0301 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C31:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: V00B0000 H02W0401 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 V02N0101 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0100 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 V02N0601 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICED.K0.INIT 0100010001000101 +word: SLICEA.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C33:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 F7 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000111100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: A1 H01E0001 +arc: A4 S1_V02N0301 +arc: A5 V02S0101 +arc: A6 V02N0301 +arc: B0 H02E0301 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 F4 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C35:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V02S0501 +arc: B6 V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C36:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 N1_V01S0100 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: S1_V02S0001 F2 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C37:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: A0 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A5 F7 +arc: A7 H02W0501 +arc: B1 H02W0301 +arc: B2 F1 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C2 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 0001001100000010 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C38:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: A0 N1_V02S0501 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A7 V02N0301 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C7 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F4 +arc: S1_V02S0001 F2 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0001001100000010 +word: SLICEA.K0.INIT 0000001100001010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEB.K0.INIT 0000000011001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C39:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A1 S1_V02N0501 +arc: A4 F5 +arc: A6 N1_V02S0301 +arc: B0 H02W0301 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: D5 V02S0601 +arc: D6 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V01S0100 F1 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEA.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R45C40:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 V02S0501 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 F4 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0100 F3 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000000101110 +word: SLICEB.K1.INIT 0000010101000100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 0011000000110001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C41:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICEC.K1.INIT 0000000011110001 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C42:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A1 F5 +arc: A2 V00B0000 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0101 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H00L0000 +arc: A3 V02N0501 +arc: A5 N1_V02S0301 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: D1 V00T0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 F3 +arc: V01S0000 F1 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C45:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 S1_V02N0101 +arc: A7 N1_V02S0101 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C5 E1_H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D5 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 F7 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M1 H02W0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICED.K1.INIT 1110010000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C46:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICED.K1.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 E1_H02W0501 +arc: A4 F7 +arc: A5 F7 +arc: A6 H02W0701 +arc: B0 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B7 E1_H02W0101 +arc: C1 V02S0601 +arc: C3 N1_V01S0100 +arc: C4 F6 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q5 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000111100100010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R45C48:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C3 H02E0401 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 Q3 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C49:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0401 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101010100111111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C50:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C5 N1_V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F6 +arc: V01S0100 Q7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C51:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A4 V02S0101 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C5 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1110001011101110 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C52:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0601 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: V00B0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 1110001011101110 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C53:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B3 F1 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 F4 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R45C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 F1 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C55:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 W1_H02E0101 +arc: B3 H02E0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 H00L0100 +arc: C3 H02E0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0201 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C56:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F7 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B1 E1_H02W0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C57:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0100 +arc: B2 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: C2 V02N0601 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M2 H02W0601 +arc: N1_V01N0001 F4 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1010000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 E1_H02W0501 +arc: A5 V02N0301 +arc: B0 V02S0301 +arc: B7 V02S0501 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C60:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 N1_V02S0301 +arc: A7 E1_H02W0701 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B7 H02W0301 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1110111101001111 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0011001101011111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C61:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A3 V00B0000 +arc: A6 V00T0100 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: C1 H02W0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 W1_H02E0701 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B5 H02E0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 V02N0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0011111100001100 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: A6 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 E1_H01W0100 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0303 F6 +arc: V01S0100 Q7 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0011001101010000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000001100001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C65:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C66:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A6 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 V02S0101 +arc: C0 F6 +arc: C3 H00L0100 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 1010000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R45C67:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: B0 H02E0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02S0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: B0 W1_H02E0101 +arc: B2 H02E0301 +arc: C0 E1_H02W0601 +arc: C2 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: D0 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F3 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000101001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 S1_V02N0701 +arc: A3 H01E0001 +arc: A4 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0000111101010101 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0010001000110000 +word: SLICEB.K1.INIT 0000001000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C71:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 W1_H02E0601 +arc: M2 V00T0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 0000000000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C72:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 F5 +arc: A4 H02E0701 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 F3 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: S1_V02S0201 F0 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010010110011001 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R45C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0401 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: D0 F2 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 0110011000111100 +word: SLICEA.K0.INIT 0000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 F5 +arc: B0 V02S0301 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B5 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 F6 +arc: C6 V02S0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C75:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H00L0100 +arc: A6 E1_H01W0000 +arc: B1 H02E0101 +arc: B3 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: C1 W1_H02E0401 +arc: C3 H02W0601 +arc: C6 S1_V02N0201 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D6 H02W0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A5 H02W0501 +arc: A6 E1_H01W0000 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 V00B0100 +arc: D1 V00T0100 +arc: D2 F0 +arc: D5 W1_H02E0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000100000000000 +word: SLICEB.K0.INIT 0111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: S1_V02S0001 F0 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C78:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: B2 H00R0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C79:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 N1_V02S0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C80:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: C0 H02W0601 +arc: C1 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1110010001000100 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C81:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C82:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 F3 +arc: B2 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H01W0100 +arc: B3 F1 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 H00L0100 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 S1_V02N0001 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00T0000 F2 +arc: W1_H02W0301 F3 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 V02N0501 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02W0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 + +.tile R45C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C3 F4 +arc: C4 H02E0601 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D3 F0 +arc: D4 H00L0100 +arc: D6 V02S0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06N0303 +arc: A0 H01E0001 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F0 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 + +.tile R45C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 W1_H02E0301 +arc: A1 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: V01S0100 F4 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C92:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 W1_H02E0601 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 0101111100000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEB.K0.INIT 0000001000001010 +word: SLICEB.K1.INIT 1111001011111010 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0011001101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R45C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 H01E0001 +arc: A2 S1_V02N0701 +arc: A3 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 W1_H02E0701 +arc: B1 E1_H02W0101 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B5 F3 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 F6 +arc: C6 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 F2 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C94:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 F4 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 S3_V06N0303 +arc: A5 V00B0000 +arc: B0 E1_H01W0100 +arc: B3 H00R0000 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R45C96:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 F1 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 H00L0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 F6 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V02N0601 F4 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A5 E1_H02W0701 +arc: A7 V02N0101 +arc: B2 V02S0101 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: S1_V02S0001 F2 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 N1_V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 W1_H02E0601 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 H02E0201 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C101:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 F3 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S3_V06S0203 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C102:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R47C103:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 F3 +arc: B3 H02W0101 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C1 H02E0601 +arc: C2 F6 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00T0000 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F7 +arc: S3_V06S0103 Q1 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1110010011100100 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000001110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R47C105:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A4 E1_H02W0501 +arc: A5 Q5 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F6 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C106:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B4 F1 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 F2 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F7 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C107:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V01S0000 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q4 +arc: V01S0000 F7 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000010010000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R47C108:PLC2 +arc: E1_H02E0001 V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B6 H02W0301 +arc: C0 F6 +arc: C1 V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R47C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C110:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: B0 N1_V02S0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B5 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: S3_V06S0003 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R47C111:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 + +.tile R47C112:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R47C113:PLC2 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R47C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R47C116:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C117:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C118:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C14:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R47C15:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C20:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R47C21:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C23:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C24:PLC2 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 V02N0401 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C25:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C26:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C27:PLC2 +arc: E1_H02E0401 V06S0203 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: A3 H01E0001 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 H00L0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V00T0100 Q1 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R47C28:PLC2 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: B0 V02N0301 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C29:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: W1_H02W0401 E1_H01W0000 + +.tile R47C30:PLC2 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 N1_V02S0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C31:PLC2 +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 + +.tile R47C32:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 E1_H01W0100 +arc: A0 V02N0701 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C33:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICEB.K1.INIT 0000010000001110 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 F5 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 F1 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 V02S0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 F2 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V00T0100 F3 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000000001001110 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICED.K0.INIT 0000101000001011 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C35:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 V02S0501 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 F6 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C36:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: A0 H02W0701 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C37:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 V02S0401 +arc: A0 H01E0001 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 N1_V02S0001 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 F0 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 0000110000001101 +word: SLICED.K0.INIT 0000000011001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C38:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H02E0701 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: V01S0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0001010100010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C39:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 N3_V06S0203 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R47C40:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 V06S0103 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: D4 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V01S0100 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 0000001000001110 +word: SLICEB.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 0010001000100011 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K0.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 V06S0103 +arc: A1 S1_V02N0501 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D6 H02W0201 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000101000001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C42:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A3 N1_V02S0501 +arc: A6 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F4 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0101110001011100 +word: SLICEB.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C43:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A3 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 F1 +arc: B1 H00R0100 +arc: B3 V02N0101 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 F6 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V02N0501 Q5 +arc: S1_V02S0601 Q6 +arc: V00T0000 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 0000000001001110 +word: SLICEA.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A6 E1_H01W0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F5 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0100011101110111 +word: SLICEA.K1.INIT 1010111111001100 +word: SLICEC.K0.INIT 1010110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C45:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 Q1 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICED.K1.INIT 1110010000000000 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C46:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: A3 V00B0000 +arc: A5 E1_H02W0501 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: C1 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C47:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 H02W0301 +arc: B3 V02S0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R47C48:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H01E0001 +arc: A4 H02E0501 +arc: A6 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 V01N0001 +arc: B5 H01E0101 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C3 V02N0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0001000010111010 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F5 +arc: A5 V00T0100 +arc: A7 W1_H02E0701 +arc: B1 S1_V02N0101 +arc: B4 W1_H02E0301 +arc: B7 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0701 F5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R47C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0701 +arc: A3 S1_V02N0501 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V00B0000 F4 +arc: V01S0100 Q2 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1011100010111000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A3 N1_V02S0501 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C3 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C52:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 V01N0101 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 F1 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 V02S0401 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111010111011101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C53:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A3 V02N0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B5 N1_V02S0501 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 H02E0601 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000111101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 V02S0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 V01N0101 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 Q4 +arc: V01S0100 F4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B3 H02E0301 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R47C58:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: B0 E1_H02W0301 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R47C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V00B0000 +arc: A5 W1_H02E0501 +arc: A7 Q7 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: M2 E1_H02W0601 +arc: M4 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEB.K1.INIT 1111011111010101 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICED.K1.INIT 1110001011100010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C60:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1110110001001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R47C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C6 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D6 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1110001011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00T0000 +arc: A5 H02W0701 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 W1_H02E0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: V00T0000 F0 +arc: V01S0000 Q7 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C63:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R47C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A3 W1_H02E0501 +arc: A5 F7 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C5 V02S0201 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +arc: V01S0100 Q1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R47C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H00L0100 +arc: A6 H02W0501 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H02W0601 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C66:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 N1_V02S0401 +arc: C2 H02E0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 H01E0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 F5 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B4 V02S0501 +arc: B5 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F4 +arc: C4 V02S0001 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C69:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: N1_V02N0201 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 1110111100101111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B7 H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 F0 +arc: D5 F2 +arc: D6 H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: N1_V01N0001 F7 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 0101000001011111 +word: SLICED.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 0101000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R47C71:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F5 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0011000001010000 +word: SLICEA.K0.INIT 0001000010110000 +word: SLICEC.K1.INIT 0000000001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 S1_V02N0301 +arc: B5 H00L0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D5 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R47C73:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C7 H01E0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 0001000000010011 +word: SLICEA.K1.INIT 1111010011110111 +word: SLICEB.K0.INIT 0000010000000111 +word: SLICEB.K1.INIT 1101110011011111 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R47C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: N3_V06N0103 F2 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEB.K0.INIT 0000010100000011 +word: SLICEB.K1.INIT 1111010111110011 +word: SLICEC.K0.INIT 0000001000000111 +word: SLICEC.K1.INIT 1111001011110111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C75:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 0010001000010001 +word: SLICED.K1.INIT 0010000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R47C76:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R47C77:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 E1_H02W0501 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: D2 N1_V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R47C78:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R47C79:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: F0 F0_SLICE +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R47C80:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 Q6 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: B6 V02N0701 +arc: C0 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C82:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B4 N1_V02S0701 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 W1_H02E0401 +arc: C4 V00B0100 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D6 E1_H01W0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 N1_V02S0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C84:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F7 +arc: A1 N1_V02S0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B7 N1_V02S0701 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 F7 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C86:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R47C87:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A3 H02E0701 +arc: A4 F7 +arc: A6 W1_H02E0701 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 F3 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C6 N1_V02S0001 +arc: C7 W1_H02E0401 +arc: D0 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 F0 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 H00R0100 +arc: B4 W1_H02E0101 +arc: B6 V00T0000 +arc: B7 F3 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C89:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 V01N0001 +arc: A2 V02S0701 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B2 H00R0100 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 H02E0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: D2 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C90:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A3 F5 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: B0 V02S0101 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: C0 H00L0100 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V02S0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 H01E0001 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 0000100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R47C92:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02E0701 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C7 W1_H02E0401 +arc: D1 V02N0001 +arc: D7 E1_H01W0100 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 0111011100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R47C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: V00T0000 Q2 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A2 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 N1_V02S0301 +arc: A5 Q5 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B7 E1_H02W0301 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C5 N1_V02S0001 +arc: C6 Q6 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F7 +arc: V01S0100 Q1 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C95:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V00B0000 F6 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 S1_V02N0301 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: A7 F5 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02S0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 S1_V02N0501 +arc: A3 F7 +arc: A4 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 V02S0401 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D6 H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B5 H02E0301 +arc: B7 N1_V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0601 +arc: C3 N1_V01S0100 +arc: C5 V02S0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F5 +arc: W1_H02W0001 Q0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R47C99:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 E1_H02W0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 H01E0101 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q5 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 V02S0301 +arc: A7 F5 +arc: B0 H02W0301 +arc: B2 V02S0301 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C2 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 H01E0001 +arc: D0 V02N0001 +arc: D2 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1101000000001101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 H02W0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: B1 E1_H02W0101 +arc: B3 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C1 F4 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: D1 W1_H02E0001 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: V00T0100 F3 +arc: W3_H06W0003 F0 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: V00B0000 V02S0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 W1_H02E0101 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C103:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H02W0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0401 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C104:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A2 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C105:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A5 H02W0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C106:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C107:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02W0101 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C108:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0501 +arc: A6 V02S0301 +arc: B0 E1_H01W0100 +arc: C0 N1_V01S0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICED.K0.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R48C109:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 V00T0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C5 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D5 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R48C110:PLC2 +arc: N1_V02N0301 H01E0101 + +.tile R48C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R48C112:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 + +.tile R48C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R48C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R48C24:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 + +.tile R48C25:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R48C26:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 + +.tile R48C27:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0601 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 + +.tile R48C28:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 + +.tile R48C30:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 + +.tile R48C31:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: V01S0100 S3_V06N0303 +arc: A1 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C32:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0501 V06S0303 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: B1 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C33:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 N1_V01S0100 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 N1_V02S0601 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0011000000110001 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0010001000100011 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C34:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A1 W1_H02E0501 +arc: A5 H02E0501 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0001000101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R48C35:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A5 V00B0000 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B5 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 F2 +arc: D5 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C37:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02S0301 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 Q0 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEB.K1.INIT 0000000000101110 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C38:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H02E0701 +arc: A4 V02N0301 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 F5 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C39:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H00L0000 +arc: A2 F7 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEC.K0.INIT 0010001000100011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C40:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: C0 W1_H02E0401 +arc: C1 F4 +arc: C2 E1_H02W0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C6 E1_H01E0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00B0000 F4 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000000001001110 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000000001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R48C41:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 0000010001010100 +word: SLICED.K1.INIT 0000001000110010 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A1 F7 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 H00R0100 +arc: C4 F6 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C43:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C4 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D4 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 0011010100111111 +word: SLICEA.K0.INIT 1110001011101110 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R48C44:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B6 H02W0301 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 N1_V01S0100 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111111000001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: A3 H02W0501 +arc: B0 S1_V02N0301 +arc: B4 H00L0000 +arc: C0 H02E0601 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M5 H02W0001 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: V00T0000 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1100010010000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C46:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 F7 +arc: A4 F7 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B4 F1 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R48C47:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0501 +arc: A3 S1_V02N0501 +arc: A6 V02S0301 +arc: C0 H02W0601 +arc: C3 V02N0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0201 +arc: D3 V01S0100 +arc: D6 V02S0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C48:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 F5 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C50:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: A2 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 F1 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 H01E0001 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000011100010 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICEC.K0.INIT 0000000011100010 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 1111111000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R48C51:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: A0 V02N0701 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111011110010 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R48C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0501 +arc: A2 H02W0701 +arc: A3 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H01W0000 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 Q2 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 H01W0100 +arc: B4 W1_H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C54:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A5 V02S0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B3 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A3 F7 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: C0 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C56:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A1 S1_V02N0501 +arc: A3 F7 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: B2 H02E0101 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C3 V02S0601 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M1 H00L0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C57:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 H02W0101 +arc: C0 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C58:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V02S0301 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M2 N1_V01N0001 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R48C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F2 +arc: N3_V06N0203 Q7 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C62:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A4 F5 +arc: A5 H02W0701 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A4 H02E0501 +arc: A5 S1_V02N0101 +arc: B0 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: C0 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V01S0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1101000011010000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B6 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A7 S1_V02N0101 +arc: B2 V02N0301 +arc: C0 V02N0601 +arc: C2 H00L0000 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R48C68:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101000000000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R48C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N3_V06N0103 Q2 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A5 H02E0701 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 V02S0001 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V02S0001 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F6 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C71:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +word: SLICEA.K0.INIT 1011000010000000 +word: SLICEA.K1.INIT 1011111110001111 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1110111101001111 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B7 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C7 H01E0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C73:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: N1_V02N0001 F0 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 H02W0101 +arc: B4 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 W1_H02E0401 +arc: C7 H02W0601 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 0010000000100010 +word: SLICED.K1.INIT 0000000000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: N1_V01N0101 F0 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C76:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: B1 H02E0101 +arc: B4 V02S0701 +arc: C1 H02E0601 +arc: C2 E1_H02W0401 +arc: C4 V02S0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D4 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A5 H02W0701 +arc: C5 S1_V02N0201 +arc: D5 E1_H02W0001 +arc: F5 F5_SLICE +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R48C78:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 H02W0101 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R48C79:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: F0 F0_SLICE +arc: H01W0100 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B4 H02E0301 +arc: C0 V02S0601 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R48C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0100 H02E0301 +arc: B2 H01W0100 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: W1_H02W0201 F0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: A5 V02N0101 +arc: A7 S1_V02N0101 +arc: B7 H02E0301 +arc: C7 V00T0100 +arc: D5 W1_H02E0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R48C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: A0 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C2 W1_H02E0401 +arc: C3 F6 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D2 F0 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 F7 +arc: A6 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0101 +arc: B2 N1_V02S0301 +arc: B3 H01W0100 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D0 H02W0001 +arc: D2 H01E0101 +arc: D3 F0 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 V02S0501 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C0 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: V01S0000 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C87:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 N1_V02S0501 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 V02S0401 +arc: C4 F6 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: D4 F2 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C88:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: A0 H00L0100 +arc: A1 E1_H02W0501 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A7 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 F1 +arc: B4 N1_V02S0701 +arc: B7 V02N0501 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 W1_H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F3 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 F4 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 N1_V02S0601 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000100001000100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R48C90:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0501 +arc: A2 F5 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 H00R0100 +arc: B5 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 V02S0601 +arc: C2 H02E0401 +arc: C5 W1_H02E0601 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D2 W1_H02E0201 +arc: D5 F0 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R48C91:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A0 W1_H02E0701 +arc: A3 H02E0701 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C7 H02W0401 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D3 F0 +arc: D4 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0010000010100000 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K1.INIT 0000000000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 V01N0101 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 F5 +arc: B1 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C93:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02E0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A7 E1_H02W0501 +arc: B1 V02S0101 +arc: B4 W1_H02E0301 +arc: B7 V02S0701 +arc: C1 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C7 V02N0201 +arc: D1 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 N1_V01S0000 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: S3_V06S0003 F3 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: H00L0000 V02S0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C96:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C97:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: B0 H02W0301 +arc: B1 H02E0101 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C98:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A4 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B1 V02S0301 +arc: B4 E1_H02W0301 +arc: B6 F1 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C4 V02S0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C99:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 H01E0101 +arc: C0 W1_H02E0401 +arc: C1 V02N0401 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F2 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1101110100000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C100:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: A6 V02S0101 +arc: B1 H01W0100 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: C1 F6 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A6 S1_V02N0101 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B6 E1_H02W0101 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C6 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C102:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V06S0203 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A3 F7 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B3 F1 +arc: B7 V02N0701 +arc: C1 H00L0000 +arc: C3 E1_H01W0000 +arc: C7 H02E0401 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 V02N0601 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C103:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0701 +arc: A3 F7 +arc: A4 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 V02S0201 +arc: D4 N1_V02S0401 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: LSR1 H02W0301 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V00T0100 F1 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C104:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0501 +arc: A2 S1_V02N0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C105:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 S1_V02N0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C106:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C107:PLC2 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 S1_V02N0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C108:PLC2 +arc: E1_H02E0101 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: A2 V01N0101 +arc: B2 N1_V02S0301 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1011101100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R49C109:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C110:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R49C113:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R49C114:PLC2 +arc: N3_V06N0303 S1_V02N0601 + +.tile R49C29:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R49C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R49C31:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: A0 V02N0501 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R49C32:PLC2 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C33:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 V02N0501 +arc: B1 N1_V02S0301 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C34:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0701 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C35:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C36:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 S1_V02N0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 E1_H01W0000 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C37:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B1 F3 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C5 V00T0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 F7 +arc: S3_V06S0003 Q0 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEB.K1.INIT 0001001100000010 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICED.K1.INIT 0011000000110001 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 S1_V02N0701 +arc: C0 F4 +arc: C2 E1_H02W0401 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000011110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C39:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 W1_H02E0701 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 V02S0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 0000011100000100 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0100010001000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C40:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0000110000001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C41:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: B0 H02W0101 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C3 H02E0401 +arc: D0 V02N0001 +arc: D3 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R49C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06S0203 +arc: A1 H02E0701 +arc: B1 N1_V02S0301 +arc: B4 F1 +arc: C1 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R49C43:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 F7 +arc: A6 N1_V01N0101 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C3 N1_V01N0001 +arc: C6 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D3 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0301 F3 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0303 F6 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000111000000100 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100110011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 F7 +arc: A6 W1_H02E0701 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 W1_H02E0401 +arc: C1 F6 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 1010111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C46:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A3 E1_H02W0501 +arc: A5 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: N3_V06N0203 F7 +arc: S1_V02S0401 F6 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C47:PLC2 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0201 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000001110111 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A5 E1_H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011100011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 E1_H01E0001 +arc: A2 F7 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C50:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: A0 H02E0701 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 V02N0401 +arc: C4 V02S0201 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 0000000011001010 +word: SLICED.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICEA.K1.INIT 0000000000110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R49C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V06S0203 +arc: A0 W1_H02E0501 +arc: A1 V02S0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 Q0 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000000011100100 +word: SLICEB.K1.INIT 1111111111100100 +word: SLICED.K0.INIT 1100111111001010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C52:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: A3 V00B0000 +arc: B0 W1_H02E0301 +arc: B3 H02E0101 +arc: C0 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 S1_V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000100011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C53:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V00T0100 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: V01S0000 Q5 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R49C54:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F7 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C6 N1_V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: V01S0000 F1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 0000001011001110 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C55:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: F0 F5A_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101111111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C56:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 V02S0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000110000101110 +word: SLICEC.K1.INIT 0010111000101110 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A4 V00B0000 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: C0 V02S0601 +arc: C3 F6 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00B0000 F6 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C58:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C59:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A4 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B4 V01S0000 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C4 V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 1100100011001100 +word: SLICEA.K0.INIT 0101010100110000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R49C60:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 F1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R49C61:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 E1_H02W0501 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 V02S0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B3 H02W0301 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C0 F4 +arc: C1 F4 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0001000010111010 +word: SLICEA.K1.INIT 0101000011111010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R49C63:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 N1_V02S0501 +arc: A1 H02W0701 +arc: A2 V00B0000 +arc: A4 V02N0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B4 V02N0501 +arc: B6 V02S0701 +arc: B7 F1 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V00T0100 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C64:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B2 N1_V02S0301 +arc: B5 H02E0101 +arc: CLK0 G_HPBX0000 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0701 Q5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 W1_H02E0701 +arc: A1 N1_V02S0501 +arc: A3 V00T0000 +arc: A5 H02W0501 +arc: B2 H02W0301 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C67:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: A3 V00B0000 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0301 +arc: B4 H00L0000 +arc: B6 V02S0701 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C68:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02E0701 +arc: B0 V02S0101 +arc: B4 S1_V02N0501 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D4 H02W0001 +arc: E1_H02E0401 Q4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0201 F2 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R49C69:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C70:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02S0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C71:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H00L0100 +arc: A7 H00L0000 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B7 H02W0301 +arc: C1 W1_H02E0601 +arc: C3 V02N0401 +arc: C7 V00T0000 +arc: D1 H02E0201 +arc: D3 H02W0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: V01S0100 F3 +arc: W1_H02W0001 F0 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 + +.tile R49C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 V02N0701 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0000010000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0010001000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V06N0203 + +.tile R49C75:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02N0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D2 F0 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 F1 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: C7 V01N0101 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C77:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 0000010000000111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 + +.tile R49C79:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: A2 W1_H02E0701 +arc: B2 V02S0101 +arc: C2 E1_H02W0601 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEB.K0.INIT 1111111000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 + +.tile R49C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0601 S1_V02N0601 + +.tile R49C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H02E0701 + +.tile R49C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 S3_V06N0303 + +.tile R49C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A5 H02E0701 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B7 F1 +arc: C1 H00R0100 +arc: C2 E1_H02W0401 +arc: C5 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D5 F2 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C85:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02S0501 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A6 S1_V02N0301 +arc: A7 H02W0701 +arc: B2 H00R0100 +arc: B6 N1_V02S0701 +arc: B7 F3 +arc: C2 H00L0100 +arc: C3 F6 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D6 V00B0000 +arc: D7 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0100 F7 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C2 H00L0100 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 H02E0001 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 + +.tile R49C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B3 H00R0000 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00B0000 F4 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R49C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A4 V02S0301 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: D0 V02N0201 +arc: D2 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R49C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0101 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C2 F6 +arc: C4 V02N0201 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D2 F0 +arc: D4 H00L0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C91:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0100 +arc: A2 W1_H02E0501 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C6 V00T0000 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D6 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 W1_H02E0601 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000000000010 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1100001101000001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R49C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0201 V02N0201 +arc: A1 H02W0501 +arc: B1 S1_V02N0301 +arc: C1 H02E0401 +arc: D1 V02S0001 +arc: F1 F1_SLICE +arc: N1_V01N0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 F5 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 F1 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 F6 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F4 +arc: S3_V06S0003 F0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 E3_H06W0303 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H02W0001 +arc: A0 E1_H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 E1_H02W0701 +arc: A5 H02E0701 +arc: A6 H02W0501 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 H00R0000 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: S1_V02S0401 F4 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R49C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 N1_V02S0501 +arc: A1 V02N0701 +arc: A3 V02N0501 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C96:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q5 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C97:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0501 +arc: A4 N1_V02S0101 +arc: A5 Q5 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 Q3 +arc: B6 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C98:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A2 E1_H02W0701 +arc: A3 H00L0100 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B5 F3 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D5 F2 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C99:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 F5 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C4 V02S0201 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F6 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R4C3:PLC2 +arc: W1_H02W0301 V02N0301 + +.tile R4C41:PLC2 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: B0 V02N0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: E1_H01E0001 Q2 +arc: F0 F5A_SLICE +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F0 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C42:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H01E0001 +arc: A0 V02N0701 +arc: A2 E1_H02W0701 +arc: B0 V02N0301 +arc: B2 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C43:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 H02E0301 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A4 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V02N0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R4C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C45:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H00L0100 +arc: A2 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B4 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1110010011100100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C47:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 H02W0001 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B4 V02N0501 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 V02N0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C50:PLC2 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 V02N0701 +arc: A2 V01N0101 +arc: B0 V01N0001 +arc: C0 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111000001000100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C51:PLC2 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 V01N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V01N0001 + +.tile R4C7:PLC2 +arc: S3_V06S0103 W3_H06E0103 + +.tile R50C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0103 + +.tile R50C101:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 S3_V06N0103 + +.tile R50C102:PLC2 +arc: E1_H02E0001 V02N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H02W0501 + +.tile R50C103:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A5 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H00R0100 +arc: B5 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C3 F6 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00T0100 F1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C104:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 N1_V02S0601 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C105:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C6 S1_V02N0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D6 H00L0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C106:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A5 Q5 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0501 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R50C107:PLC2 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H01E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A4 V02N0101 +arc: B2 V02N0101 +arc: C2 E1_H01W0000 +arc: C4 V02N0201 +arc: D2 V02N0201 +arc: D4 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEC.K0.INIT 1111000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R50C108:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C109:PLC2 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R50C110:PLC2 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 N3_V06S0003 + +.tile R50C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R50C112:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R50C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R50C115:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R50C17:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R50C24:PLC2 +arc: E3_H06E0103 N3_V06S0103 + +.tile R50C29:PLC2 +arc: E1_H02E0201 E3_H06W0103 + +.tile R50C30:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 S3_V06N0203 + +.tile R50C31:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0100 S3_V06N0303 + +.tile R50C32:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0701 H06W0203 +arc: V00T0100 V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0003 Q0 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C33:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 + +.tile R50C34:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 V02N0701 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C35:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 F0 +arc: D4 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 F3 +word: SLICEA.K1.INIT 0010101000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C36:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H02W0701 +arc: A4 E1_H01W0000 +arc: B1 V00B0000 +arc: B4 N1_V01S0000 +arc: C1 S1_V02N0401 +arc: C4 V02N0201 +arc: D1 E1_H02W0001 +arc: D4 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A3 H02W0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C4 E1_H02W0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 0011001110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C38:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 E1_H02W0501 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0101010111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C39:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F7 +arc: A2 V02S0501 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 H02W0601 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0010001000100011 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000001100100010 +word: SLICEB.K0.INIT 1010100000001000 +word: SLICEB.K1.INIT 0010001000100011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B2 V02N0101 +arc: B3 F1 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 0100010001000101 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 0101000001010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C41:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H01E0001 +arc: B0 V02S0301 +arc: B4 H02W0101 +arc: C0 V02S0401 +arc: C4 H01E0001 +arc: D0 H02E0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R50C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICEB.K0.INIT 0011000000110001 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C43:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 S1_V02N0101 +arc: B1 V02S0301 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: V01S0000 F3 +arc: V01S0100 Q4 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000010100001111 +word: SLICED.K0.INIT 1100010010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C44:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000101100001000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C45:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: B4 V00B0100 +arc: B5 V02N0701 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C46:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 N1_V02S0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 F1 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F6 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEB.K1.INIT 1111111111100010 +word: SLICEA.K1.INIT 0000000010111000 +word: SLICED.K0.INIT 1111111001010100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 0100010101000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A4 N1_V02S0301 +arc: B1 Q1 +arc: B4 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V02S0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C48:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A2 H00L0100 +arc: A4 H02W0701 +arc: A5 V02N0301 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 V00B0100 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0201 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: S1_V02S0101 F1 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R50C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A3 V02N0501 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C50:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V01N0101 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B4 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001010110111111 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0501 +arc: A4 V00B0000 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 Q6 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000111000000100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: B0 H02E0101 +arc: B3 F1 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: D0 H02W0001 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R50C53:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00R0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: B0 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0701 +arc: C0 H02W0601 +arc: C3 W1_H02E0401 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R50C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0100010101000000 +word: SLICED.K1.INIT 1010101011111100 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C55:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02W0101 +arc: C0 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEB.K1.INIT 1111111111100010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C56:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1110001011100010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1111111000110010 +word: SLICEA.K1.INIT 0000101000001100 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 1100110011111010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C58:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: B0 H02W0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C60:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0701 +arc: B0 V01N0001 +arc: C0 H00R0100 +arc: D0 H00R0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C61:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A6 H02E0701 +arc: B6 V01S0000 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: M0 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: V01S0000 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R50C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 V00T0100 +arc: A6 F5 +arc: B0 H02E0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0401 +arc: C6 F4 +arc: D0 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 S1_V02N0301 +arc: A7 F5 +arc: B0 V01N0001 +arc: B2 S1_V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C2 V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D4 V01N0001 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 + +.tile R50C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B3 H02W0301 +arc: B5 H02E0301 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A3 V02N0501 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B1 V02S0301 +arc: B3 H02E0301 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C1 V02N0401 +arc: C3 V02S0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D1 N1_V02S0201 +arc: D3 V02S0001 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F6 +arc: V01S0000 F1 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010010100000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 E1_H01W0000 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 F1 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: C7 N1_V02S0001 +arc: D0 V01S0100 +arc: D1 H01E0101 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: C1 F6 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: D1 H01E0101 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R50C69:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A6 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B6 S1_V02N0701 +arc: C1 H02W0401 +arc: C3 W1_H02E0401 +arc: C6 S1_V02N0001 +arc: D1 W1_H02E0001 +arc: D3 V02S0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +arc: V00T0100 F3 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: A7 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B6 V00T0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 +arc: B7 H02W0301 +arc: C7 N1_V02S0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R50C73:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A7 V00T0100 +arc: B0 H02W0301 +arc: B2 N1_V02S0101 +arc: B3 V02N0301 +arc: B6 E1_H02W0301 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F7 +arc: V00T0100 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000100000001100 +word: SLICED.K1.INIT 0111111100000000 +word: SLICEA.K0.INIT 1000000010100000 +word: SLICED.K0.INIT 0011000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R50C74:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 N1_V02S0501 +arc: D2 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: N1_V01N0101 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R50C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 E1_H01W0000 + +.tile R50C76:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 N1_V02S0701 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V01N0101 +arc: B1 V01N0001 +arc: D0 S1_V02N0201 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R50C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 N3_V06S0003 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: V01S0000 Q3 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q6 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A3 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A7 H00R0000 +arc: B1 F3 +arc: B3 H00R0100 +arc: B5 H02E0101 +arc: B7 H02E0301 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C5 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D5 H02W0001 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A6 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C3 E1_H01W0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: V00T0000 F2 +arc: V01S0100 Q6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0103 V06N0103 +arc: A2 W1_H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: E1_H01E0101 F6 +arc: E3_H06E0203 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0003 +arc: W3_H06W0303 E3_H06W0303 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R50C84:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 V02S0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R50C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 E1_H02W0401 +arc: A1 H00L0100 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B7 S1_V02N0501 +arc: C1 W1_H02E0601 +arc: C7 H02E0401 +arc: D1 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C86:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C2 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D2 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: V00B0000 F6 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 + +.tile R50C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 F3 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V02S0001 +arc: C7 V00B0100 +arc: D0 N1_V02S0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R50C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H00L0000 +arc: B5 F3 +arc: B6 F1 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H02E0601 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R50C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A2 F5 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B2 H00L0000 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C0 H02E0601 +arc: C2 F4 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: D0 H00R0000 +arc: D2 F0 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R50C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 H00R0100 +arc: B3 F1 +arc: B4 V02N0701 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 W1_H02E0201 +arc: D5 V02S0601 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 N1_V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C93:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 + +.tile R50C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V06N0303 +arc: A0 F5 +arc: A1 V02S0501 +arc: A3 E1_H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0101 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000100000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C95:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A4 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 V02S0601 +arc: C4 V02N0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D4 V02S0401 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A2 F5 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C97:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02W0701 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C98:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: B1 N1_V02S0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C99:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 H02W0301 +arc: B1 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C100:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: A1 N1_V02S0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: C0 H02W0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile R51C102:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 W1_H02E0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C103:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C104:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q6 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C105:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A5 Q5 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C106:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: A6 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C6 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 F3 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R51C107:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C108:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 + +.tile R51C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: W1_H02W0501 S1_V02N0501 + +.tile R51C110:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C111:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C113:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C114:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 + +.tile R51C26:PLC2 +arc: E3_H06E0103 N3_V06S0103 + +.tile R51C28:PLC2 +arc: V00B0000 V02N0201 +arc: CLK0 G_HPBX0000 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C29:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0001 Q2 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C30:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: V00B0000 V02S0001 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B3 H00R0000 +arc: B5 V02N0701 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C7 V02S0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C31:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 W1_H02E0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C32:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B4 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEA.K0.INIT 1111110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C33:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 0101000001010101 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000000001001110 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICED.K1.INIT 0100010001000101 +word: SLICEA.K1.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 F7 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F0 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICEB.K0.INIT 0010001100100010 +word: SLICEA.K0.INIT 0000110000001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R51C35:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 V02S0601 +arc: D0 W1_H02E0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C36:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C37:PLC2 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 N1_V02S0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C38:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 S1_V02N0101 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C39:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: A0 V02N0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C40:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000001001110 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 F7 +arc: A4 F5 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B2 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 N1_V02S0501 +arc: B7 V02N0701 +arc: C0 F4 +arc: C2 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +word: SLICED.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R51C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02N0501 +arc: A2 H01E0001 +arc: A3 F5 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B5 H01E0101 +arc: B6 V00T0000 +arc: C0 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C43:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0501 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEC.K0.INIT 0010001000100011 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0501 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0101 +arc: B2 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R51C45:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 N1_V02S0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 F7 +arc: A1 F5 +arc: A2 W1_H02E0501 +arc: A5 V02N0101 +arc: A6 H02W0501 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B5 V02N0501 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 V02S0401 +arc: C5 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B6 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02W0701 +arc: A3 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 N1_V01S0100 +arc: B1 E1_H02W0301 +arc: B5 H00R0000 +arc: B7 V02N0501 +arc: C1 H00L0100 +arc: C3 W1_H02E0601 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: S1_V02S0501 F7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R51C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: B7 S1_V02N0701 +arc: C1 E1_H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F7 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R51C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A3 F7 +arc: A7 V02N0301 +arc: B1 H02E0101 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q4 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 Q4 +arc: V01S0000 F2 +arc: V01S0100 Q6 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C51:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00R0000 +arc: B1 H02E0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: D1 V02N0201 +arc: D3 E1_H02W0001 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R51C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A5 F7 +arc: B0 V02S0301 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 F1 +arc: B5 H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C54:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A6 V00T0100 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 S1_V02N0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V00B0000 F6 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H01E0001 +arc: A2 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 V02S0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 H00L0100 +arc: A4 V00T0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F4 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C57:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICEC.K0.INIT 0100010101000000 +word: SLICEC.K1.INIT 1110111111101100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C58:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B3 V01N0001 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V00B0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C59:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 F5 +arc: A3 F5 +arc: A5 N1_V01N0101 +arc: B1 H02E0101 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010000010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R51C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B1 H02W0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C61:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R51C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: B0 F3 +arc: B1 W1_H02E0101 +arc: B3 F1 +arc: B4 V02S0501 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R51C63:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E3_H06W0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 W1_H02E0701 +arc: B0 H02E0101 +arc: B4 H02W0101 +arc: C0 V02N0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 E1_H01W0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0001001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 V00B0000 +arc: A6 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B6 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C66:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 F7 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B6 F3 +arc: C0 H02E0601 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0601 +arc: C6 V00T0000 +arc: D0 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F2 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111001100000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C68:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R51C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: V00T0100 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R51C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0501 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00T0000 Q2 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C71:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 H02W0501 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 N1_V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C5 F6 +arc: C6 V00T0100 +arc: D0 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H02E0701 +arc: A3 V02S0701 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: C0 H00L0100 +arc: C1 N1_V01N0001 +arc: C3 H00R0100 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0100 F3 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B3 S1_V02N0301 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111111111111100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000010110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C74:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R51C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0601 + +.tile R51C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: A4 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R51C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 W1_H02E0501 +arc: A3 H02W0701 +arc: A5 W1_H02E0501 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H02W0101 +arc: B6 V01S0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q7 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: V00B0000 F4 +arc: V01S0000 Q6 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V01N0101 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B4 F1 +arc: C4 V02S0201 +arc: D0 V00B0100 +arc: D4 E1_H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 0000111100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R51C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A4 F7 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B4 F3 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C1 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: S1_V02S0001 F0 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: S1_V02S0501 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C83:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile R51C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0203 E3_H06W0203 + +.tile R51C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 F5 +arc: A5 V00B0000 +arc: B0 V02S0101 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H02E0101 +arc: C0 H02E0601 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: D0 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 F0 +arc: D5 H00L0100 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A2 H02E0501 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B1 F3 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H02E0501 +arc: A3 H01E0001 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: D0 H02W0001 +arc: D3 V02N0001 +arc: D5 F0 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 H02E0701 +arc: A4 V02N0101 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H00R0100 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: D0 V02S0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000001000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 V00B0000 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 F1 +arc: C1 H02W0401 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D4 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 H02E0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A2 F5 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: C2 F6 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000111111110000 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0010000000000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 F7 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B4 V00B0100 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C2 V02N0601 +arc: C4 H02E0401 +arc: C6 F4 +arc: C7 V00T0000 +arc: D2 H02E0201 +arc: D4 E1_H01W0100 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 V01N0001 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C93:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F5 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1001000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R51C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 V02S0701 +arc: B3 W1_H02E0301 +arc: C3 E1_H02W0601 +arc: D3 H02W0201 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C95:PLC2 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A3 H00L0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C96:PLC2 +arc: H00L0000 V02N0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B7 E1_H02W0301 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 V01N0001 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F1 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R51C97:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C98:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: A2 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C99:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 N1_V02S0701 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 N1_V02S0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C101:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 V06N0103 +arc: A1 H02E0501 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A5 Q5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C2 N1_V01N0001 +arc: C4 Q4 +arc: C5 N1_V02S0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C102:PLC2 +arc: N1_V02N0701 H02W0701 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E1_H01W0100 + +.tile R52C103:PLC2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C104:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 V01N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C105:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: B1 H02W0101 +arc: C1 E1_H01W0000 +arc: D1 H02W0001 +arc: F1 F1_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: N1_V01N0001 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R52C106:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02N0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C107:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 + +.tile R52C108:PLC2 +arc: N1_V02N0101 V01N0101 + +.tile R52C109:PLC2 +arc: N1_V02N0401 S1_V02N0101 + +.tile R52C110:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R52C113:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R52C116:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R52C22:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R52C23:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R52C25:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R52C26:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R52C28:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 H02W0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B3 H00L0000 +arc: B6 E1_H02W0101 +arc: C0 F6 +arc: C3 F6 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C29:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: A0 F5 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: A7 V02N0101 +arc: B1 H02W0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C30:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 F5 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 F7 +arc: B0 W1_H02E0101 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0101 +arc: B5 F1 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 1111111011001110 +word: SLICEB.K1.INIT 0011001000000010 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C31:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A7 V00T0100 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 1110110011101100 +word: SLICEC.K1.INIT 1111111111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010001010000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R52C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: A2 H01E0001 +arc: A5 F7 +arc: A7 W1_H02E0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B5 H01E0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02E0401 +arc: M5 H02W0001 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q0 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K1.INIT 1110111010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R52C33:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A6 H02E0701 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R52C34:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 F6 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R52C35:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 N1_V02S0501 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B2 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D2 H02E0201 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C36:PLC2 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R52C37:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 + +.tile R52C38:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: A5 N1_V02S0301 +arc: B0 H02E0301 +arc: B5 S1_V02N0701 +arc: C0 H02W0601 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C39:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C40:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C41:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C42:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02W0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q1 +arc: M1 H02W0001 +arc: MUXCLK0 CLK0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H02E0501 +arc: A2 H01E0001 +arc: A3 F7 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C3 V02N0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C45:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06N0103 +arc: A1 V02N0501 +arc: A3 F7 +arc: A7 V02N0301 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F7 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C46:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: B0 E1_H01W0100 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1000100010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C47:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 F7 +arc: A3 F7 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 F6 +arc: C2 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K1.INIT 1011101110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R52C48:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 F7 +arc: A5 V02S0301 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C3 V02S0601 +arc: C4 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001000100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R52C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 F7 +arc: A4 V02N0301 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B4 H00R0000 +arc: B7 V00T0000 +arc: C0 F4 +arc: C4 V02S0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0001001111011111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C0 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C51:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A2 V01N0101 +arc: A4 H02E0701 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F7 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1100100000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 V02N0301 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q1 +arc: LSR1 H02W0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICEC.K1.INIT 1100100001000000 +word: SLICED.K1.INIT 0001110100111111 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C53:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A7 Q7 +arc: B4 H02W0101 +arc: C1 H00R0100 +arc: C4 H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D4 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C54:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: C1 V02N0401 +arc: C2 W1_H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D5 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A1 E1_H01E0001 +arc: B1 H02W0301 +arc: B2 W1_H02E0101 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R52C56:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 0101001101010000 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C57:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 F7 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C4 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: S1_V02S0301 F3 +arc: V00T0100 F3 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000111100100010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 H02W0501 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: C0 H00L0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R52C60:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 + +.tile R52C61:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: V00T0100 V02N0501 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: B0 N1_V02S0101 +arc: B2 F3 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: C0 H02E0401 +arc: C2 F4 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: D0 H02W0001 +arc: D2 F0 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C62:PLC2 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H02W0301 + +.tile R52C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 + +.tile R52C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B4 H02E0101 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 N1_V02S0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R52C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q4 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q2 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1011101100000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: A2 H02E0701 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C68:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06N0303 +arc: A4 V02S0301 +arc: B4 V02N0501 +arc: C4 H02E0601 +arc: D4 S1_V02N0401 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A3 V02S0501 +arc: B1 E1_H02W0301 +arc: B3 H00R0000 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR0 H02W0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 Q0 +arc: V00T0100 F1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C71:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 + +.tile R52C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V02S0501 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: B2 H02E0101 +arc: B3 W1_H02E0101 +arc: B4 H01E0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 V01N0001 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 F6 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C74:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A0 F5 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: B0 F3 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: C0 F6 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: D0 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C75:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 V01N0001 + +.tile R52C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: A1 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 N1_V01S0100 + +.tile R52C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: A5 V02S0101 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C79:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A3 V02N0501 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F4 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 F3 +arc: V01S0100 Q5 +word: SLICEB.K1.INIT 0001000100000101 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00R0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: C1 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V00B0000 Q6 +word: SLICEC.K0.INIT 1000001010000010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1101110100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R52C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A3 V02S0701 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 F2 +arc: V01S0000 Q4 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 E1_H02W0301 +arc: A4 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 E1_H02W0701 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 H02W0301 +arc: C0 V02S0601 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K1.INIT 0000000011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: B0 H02E0301 +arc: C5 N1_V02S0001 +arc: D1 V00B0100 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A4 V00T0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C1 V02S0401 +arc: C4 H02W0601 +arc: D0 H02W0001 +arc: D1 N1_V01S0000 +arc: D4 F0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C85:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A4 H02E0501 +arc: A7 V02N0101 +arc: B4 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C4 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 0000000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R52C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: B7 W1_H02E0301 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 F2 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: C0 V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C6 V02S0201 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R52C88:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 + +.tile R52C89:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: B1 V02S0301 +arc: B2 H01W0100 +arc: B3 F1 +arc: B5 W1_H02E0301 +arc: B6 H02W0301 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C90:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A6 V02N0101 +arc: B1 V01N0001 +arc: B2 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B6 V02N0501 +arc: C1 H02E0401 +arc: C2 F4 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0100000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 W1_H02E0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 H00R0100 +arc: B4 N1_V02S0501 +arc: B5 H00R0000 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C92:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 H01E0101 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F0 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 0010000000000010 +word: SLICEC.K0.INIT 0011000100110011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C93:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: B0 H02W0301 +arc: C0 H02E0601 +arc: C5 S1_V02N0201 +arc: D0 N1_V02S0001 +arc: D5 H02E0201 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C94:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 E1_H02W0701 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C3 H00L0100 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: D0 H02W0201 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 H02W0601 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C95:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C96:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 V06N0203 +arc: A2 V00T0000 +arc: A6 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C97:PLC2 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 N1_V02S0701 +arc: A3 H02W0501 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C98:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C99:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 Q5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C100:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C101:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0701 +arc: B0 H02E0301 +arc: B1 Q1 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C102:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 E1_H02W0401 + +.tile R53C103:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 V02S0301 +arc: W3_H06W0003 N3_V06S0003 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B7 V00B0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0011001100000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C104:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0401 N1_V01S0000 + +.tile R53C105:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0501 V06N0303 + +.tile R53C106:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C107:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C108:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 S3_V06N0203 + +.tile R53C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C110:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C112:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C113:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C114:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C115:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C116:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C117:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C14:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C15:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R53C20:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C21:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C23:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C27:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: V00T0000 H02W0001 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0401 Q4 +arc: LSR0 E1_H02W0301 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C28:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 H02W0701 +arc: V00T0100 V02N0701 +arc: A0 H00L0000 +arc: A4 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 H00L0000 +arc: C0 F4 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 F6 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C30:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 F7 +arc: A1 E1_H02W0501 +arc: A3 F7 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R53C31:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 F7 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: A7 V02N0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M3 H00L0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1101100011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1101100011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C32:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06N0203 +arc: A1 H02E0501 +arc: A3 H02E0701 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B5 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C3 H00R0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C33:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q7 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000001001100 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0100000011000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V01S0000 F6 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R53C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1111100001110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1101100011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C36:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0100 F7 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R53C37:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 V06N0303 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: C3 N1_V01S0100 +arc: C4 H02E0401 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C38:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 E1_H01E0001 +arc: A5 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B5 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C39:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 F1 +arc: B4 F1 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEB.K0.INIT 0100010101000100 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K0.INIT 0000000011110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R53C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C40:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06N0303 + +.tile R53C41:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 N1_V02S0701 +arc: A2 S1_V02N0701 +arc: A3 E1_H01E0001 +arc: A5 N1_V01S0100 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 F1 +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010000010001000 +word: SLICEC.K1.INIT 0000110000001101 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0001000101010000 +word: SLICEB.K0.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C42:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 V02S0501 +arc: A2 F5 +arc: A7 F5 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B5 F1 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 V02N0401 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 0000000001110100 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C43:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C44:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C45:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 V00T0000 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B3 W1_H02E0301 +arc: B5 H00R0000 +arc: B7 V02N0701 +arc: C0 S1_V02N0401 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 W1_H02E0201 +arc: D5 E1_H01W0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 F1 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: C0 H02W0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 0011001100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R53C48:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02W0501 +arc: B3 N1_V02S0301 +arc: C3 N1_V02S0401 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C49:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00R0000 +arc: A3 F5 +arc: B5 H02E0301 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q5 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q1 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H02W0701 +arc: A3 V00T0000 +arc: B3 H00R0100 +arc: C1 H02E0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D3 V00B0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02E0701 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: C0 F6 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V02S0701 +arc: A3 F7 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 H00L0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001101010000 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R53C54:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A7 V00T0100 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C55:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 V01N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R53C56:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R53C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: B1 V02S0301 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C58:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R53C59:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile R53C60:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H02W0501 +arc: A5 H02W0501 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 Q4 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0601 Q6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C61:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 E1_H01W0000 +arc: B5 S1_V02N0501 +arc: D5 V02N0601 +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1011101100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R53C62:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 E1_H02W0301 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C64:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 S1_V02N0301 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C65:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: B0 H02E0101 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 H00L0100 +arc: C4 V01N0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R53C66:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A3 H02W0501 +arc: B3 V02S0101 +arc: C0 H02W0601 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C5 W1_H02E0401 +arc: C6 V00T0100 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000100000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R53C68:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C69:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 H02E0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 V00B0100 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 N1_V02S0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C71:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B1 H00R0100 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R53C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02S0501 +arc: A7 H02W0701 +arc: B2 H00R0100 +arc: B7 N1_V02S0701 +arc: C2 H02E0601 +arc: C7 V02S0201 +arc: D2 V02N0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F6 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000100000001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0100000001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R53C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile R53C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: A5 V02S0101 +arc: C0 N1_V01S0100 +arc: D1 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C77:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: S3_V06S0203 F7 +arc: V00B0000 Q6 +arc: V01S0000 F4 +arc: V01S0100 Q6 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111100000101 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: C0 H02E0601 +arc: C5 H01E0001 +arc: D1 H01E0101 +arc: D4 V02S0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 E1_H02W0601 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICED.K1.INIT 0000000011111110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: C1 E1_H01W0000 +arc: C4 V02S0001 +arc: C6 V02S0001 +arc: D0 V02S0001 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D5 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R53C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: C0 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q5 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C82:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B4 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q6 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 F4 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H01E0001 +arc: C4 V02N0201 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: D0 V02N0201 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C84:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 V00T0000 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 H02W0501 +arc: B0 H02E0301 +arc: B2 V02S0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0100 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0001 +arc: D2 V02N0001 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0101 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEB.K0.INIT 1011000010111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C5 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A2 V01N0101 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B2 V02S0101 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C5 E1_H02W0601 +arc: D0 H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D5 N1_V02S0401 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0100 +arc: N1_V02N0001 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0100000100000000 +word: SLICEC.K1.INIT 0111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile R53C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 F5 +arc: A5 H02E0501 +arc: A7 H02W0701 +arc: B2 V01N0001 +arc: B5 H00L0000 +arc: B7 S1_V02N0501 +arc: C2 V02N0401 +arc: C5 W1_H02E0601 +arc: C7 V00T0100 +arc: D2 V00B0100 +arc: D5 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 F7 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: V00T0000 F0 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0010000000000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0101010100000101 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEC.K1.INIT 0101010100000101 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 1100000010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A3 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: C4 W1_H02E0601 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 N1_V02S0201 +arc: D2 H01E0101 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: V00T0100 F1 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F5 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010100000000000 +word: SLICEA.K0.INIT 1000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: A3 E1_H01E0001 +arc: A7 V02S0101 +arc: B2 V02N0101 +arc: B3 N1_V02S0101 +arc: B7 H02W0301 +arc: C3 H02E0401 +arc: C7 E1_H02W0401 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0701 F7 +arc: S1_V02S0201 F2 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICEB.K0.INIT 0011001111001100 +word: SLICED.K1.INIT 0000000011011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C93:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A2 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B0 H02W0101 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C1 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: V00T0000 F2 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: B0 E1_H02W0301 +arc: C0 V02N0401 +arc: D0 E1_H02W0201 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C95:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02W0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B3 N1_V02S0101 +arc: B5 V02N0501 +arc: C0 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0601 +arc: C5 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: D0 N1_V01S0000 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D5 F2 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R53C96:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 E1_H02W0501 +arc: B0 N1_V02S0301 +arc: C0 E1_H02W0401 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C97:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 N1_V02S0001 +arc: D4 H00L0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C98:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 V00T0000 +arc: A5 F7 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 N1_V02S0101 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C5 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D5 V02N0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C99:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: A5 Q5 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 1010000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C100:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile R54C101:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0103 S1_V02N0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 W3_H06E0303 + +.tile R54C102:PLC2 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C103:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06S0303 + +.tile R54C104:PLC2 +arc: H01W0000 W3_H06E0103 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 + +.tile R54C105:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 + +.tile R54C106:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C108:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C109:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R54C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R54C20:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R54C25:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R54C26:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R54C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: B0 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C29:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICED.K0.INIT 1100010010000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1101100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 F1 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICED.K1.INIT 0000110100001100 +word: SLICEC.K1.INIT 0000000011110001 +word: SLICEA.K0.INIT 1101111110000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C31:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H01E0001 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A5 S1_V02N0101 +arc: B2 V01N0001 +arc: B6 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: D6 F2 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C32:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1110101000101010 +word: SLICED.K1.INIT 0000110011111100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R54C33:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B3 E1_H02W0101 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: V00B0100 F5 +word: SLICEB.K1.INIT 0111010001110100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0111011100001111 +word: SLICEA.K0.INIT 0111111100001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C34:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0010111010101010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V06S0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02W0501 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEC.K1.INIT 0011001111110011 +word: SLICEC.K0.INIT 0011001111111010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R54C36:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 V06N0303 +arc: A2 V02N0701 +arc: A7 V00T0100 +arc: B2 H00L0000 +arc: B7 W1_H02E0101 +arc: C2 V02N0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D7 V02N0601 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F7 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R54C37:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B6 W1_H02E0101 +arc: C0 F6 +arc: C3 V02N0601 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H00R0000 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +word: SLICEB.K1.INIT 1111111111000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C4 V00T0000 +arc: C6 H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0101000101010000 +word: SLICEA.K0.INIT 1110111011100010 +word: SLICEC.K0.INIT 0000101000001011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R54C39:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 N1_V02S0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 V02S0501 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 E1_H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F2 +arc: S1_V02S0001 Q0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1111111011110010 +word: SLICEB.K1.INIT 0000111000000010 +word: SLICED.K1.INIT 0100000011000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C40:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B1 V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 F6 +arc: C4 V00T0100 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0100 Q0 +arc: W1_H02W0101 F1 +word: SLICEC.K0.INIT 1110101000101010 +word: SLICED.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C41:PLC2 +arc: E1_H02E0501 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A2 S1_V02N0501 +arc: A4 V02N0301 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B2 H00R0000 +arc: B4 W1_H02E0101 +arc: B6 H02W0301 +arc: C0 E1_H02W0601 +arc: C2 F6 +arc: C4 S1_V02N0201 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D4 V02N0401 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C42:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0601 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00L0000 H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C45:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S3_V06S0103 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C46:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 V02N0701 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B3 V01N0001 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1101110100000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C47:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02S0401 +arc: A0 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H01E0101 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: V00B0000 Q4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C48:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 + +.tile R54C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 V00T0000 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00L0000 +arc: C0 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C50:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R54C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0501 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: B2 W1_H02E0301 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V02N0001 F2 +arc: V00T0100 Q3 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R54C52:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R54C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: B1 V00B0000 +arc: B4 V01S0000 +arc: C0 H02E0401 +arc: C1 F4 +arc: C4 H02E0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C54:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: C3 H02W0401 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 0101010101010101 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R54C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 V02N0301 +arc: B4 E1_H02W0101 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D3 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0101010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R54C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0303 E3_H06W0203 +arc: C1 V02N0601 +arc: D3 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F5 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 0000111100001111 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R54C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R54C58:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 H02W0701 +arc: C3 N1_V01N0001 +arc: D3 V02N0201 +arc: F3 F3_SLICE +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1010000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R54C59:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 V02S0501 +arc: A3 V02N0701 +arc: A5 V00T0100 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 V02N0101 +arc: B3 W1_H02E0301 +arc: B5 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H00R0100 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C5 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D5 V02S0401 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: V01S0100 F1 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C60:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 E1_H02W0101 +arc: B6 V00B0100 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q3 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R54C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEB.K1.INIT 1100111100000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C62:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEC.K0.INIT 1010000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R54C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C64:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011100000110000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B0 F3 +arc: B2 V02S0101 +arc: B3 V02N0101 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 F2 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D6 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0003 F0 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 + +.tile R54C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: A0 V01N0101 +arc: A2 V02S0501 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 H00L0000 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C71:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 H02E0301 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C72:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0701 F7 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R54C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 V00B0000 +arc: B0 N1_V02S0301 +arc: B2 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C74:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: C6 E1_H02W0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F0 +arc: V01S0100 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000111100001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R54C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0401 V01N0001 + +.tile R54C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 + +.tile R54C77:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A2 N1_V02S0701 +arc: A5 E1_H02W0701 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 V02N0001 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0003 F0 +arc: S1_V02S0701 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C78:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R54C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 + +.tile R54C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B6 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 W1_H02E0201 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 0000000011001111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 F4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 F5 +arc: B0 H01W0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D3 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010110010101100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R54C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: A2 S1_V02N0501 +arc: B0 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 Q4 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A7 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 F3 +arc: B7 V00B0000 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C7 V01N0101 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000110000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A5 V00T0100 +arc: B5 V00B0100 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: D3 W1_H02E0001 +arc: D5 E1_H02W0201 +arc: E1_H01E0101 F5 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F3 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R54C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 N1_V02S0701 +arc: A2 H02W0501 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0010000000010000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R54C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 H01E0001 +arc: A3 F7 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 V02S0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 0010000110000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 F1 +arc: B4 F3 +arc: B5 V00B0100 +arc: B6 S1_V02N0701 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110000110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 W1_H02E0701 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 W1_H02E0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R54C91:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00R0000 +arc: A1 V01N0101 +arc: A2 V02N0701 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 F3 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R54C92:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0501 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C93:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 V02N0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: C3 V02S0601 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: D0 V02S0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R54C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 H00L0000 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 F0 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F7 +arc: S1_V02S0401 F4 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C96:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: B1 N1_V02S0301 +arc: C1 H00L0000 +arc: C5 V02N0201 +arc: D1 V02N0001 +arc: D5 V00B0000 +arc: E1_H02E0501 F5 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F1 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R54C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: D0 N1_V02S0001 +arc: D2 F0 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F7 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C98:PLC2 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: M0 H01E0001 +arc: N1_V01N0001 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 W1_H02E0601 +arc: C4 H01E0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0101 Q3 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C100:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 S3_V06N0103 + +.tile R55C101:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 + +.tile R55C102:PLC2 +arc: N1_V02N0301 S1_V02N0201 + +.tile R55C103:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R55C104:PLC2 +arc: N1_V02N0401 S1_V02N0401 + +.tile R55C28:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 V02S0401 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B4 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 E1_H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C29:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 F7 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B4 H02W0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D4 N1_V02S0601 +arc: D6 H02E0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R55C30:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 H01W0100 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M3 H02E0201 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q3 +arc: V01S0000 F2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICEC.K1.INIT 0100010101000100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R55C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A6 H02E0501 +arc: A7 N1_V01S0100 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 1100101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C32:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 W1_H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0010001111101111 +word: SLICEB.K1.INIT 0000111110101111 +word: SLICEC.K0.INIT 0011001111110101 +word: SLICEC.K1.INIT 0000111111001111 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C33:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V02N0701 +arc: C0 W1_H02E0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: LSR0 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 F7 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R55C34:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06N0203 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C35:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: V00B0100 Q7 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R55C36:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B4 H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: V00B0100 F5 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C37:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B5 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D5 V00B0000 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: LSR1 E1_H02W0501 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0301 Q1 +arc: V00B0000 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1110110001001100 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000000101110 +word: SLICEA.K0.INIT 1111111111100010 +word: SLICEA.K1.INIT 0101010000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C39:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 E1_H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C40:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 F7 +arc: A3 V02S0701 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C41:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0701 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 H02E0501 +arc: A4 V00T0100 +arc: A6 H02W0501 +arc: A7 E1_H02W0501 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C42:PLC2 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: A1 V02S0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S1_V02S0501 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 F1 +arc: W1_H02W0501 Q7 +word: SLICEA.K1.INIT 1010101000001010 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0501 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: B1 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C4 V01N0101 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q0 +arc: V00T0100 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 0001001100000010 +word: SLICEC.K1.INIT 0000000011001101 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C45:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: B0 S1_V02N0101 +arc: C0 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: N1_V02N0601 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEB.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R55C46:PLC2 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C47:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C48:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A3 V02S0501 +arc: B0 H02E0101 +arc: B3 E1_H01W0100 +arc: C0 E1_H02W0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 H02E0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R55C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B3 Q3 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F7 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R55C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0601 V01N0001 +arc: B2 E1_H02W0101 +arc: C2 V02N0401 +arc: D2 V00B0100 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R55C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R55C52:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 V06S0103 +arc: D0 H02E0201 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: H01W0100 F5 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R55C53:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: A0 N1_V02S0501 +arc: A2 H02W0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A3 S1_V02N0501 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C55:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C57:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A1 F5 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R55C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A6 V02N0301 +arc: B1 V02N0101 +arc: B3 V01N0001 +arc: B6 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C6 V00T0000 +arc: D1 H02E0001 +arc: D3 V02S0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEA.K1.INIT 0000001000001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R55C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00T0000 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C61:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C62:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C63:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 H01E0001 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B2 V02N0101 +arc: C0 N1_V02S0401 +arc: C2 H00L0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICED.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R55C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 + +.tile R55C67:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0501 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B2 H00R0100 +arc: B3 H00L0000 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C70:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 H02W0301 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R55C73:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0601 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R55C74:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06W0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0103 N1_V01S0100 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R55C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 + +.tile R55C76:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: A1 H02W0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B4 F1 +arc: B6 V02S0501 +arc: B7 E1_H02W0101 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R55C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 H02W0401 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F7 +arc: N1_V01N0101 F4 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0501 +arc: A2 V01N0101 +arc: A5 V00T0000 +arc: A6 S1_V02N0101 +arc: B0 H02E0301 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D0 V02S0001 +arc: D2 V00B0100 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: M0 H02W0601 +arc: V00T0000 F2 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile R55C80:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A4 F7 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000110001000100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: B0 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 0000001100000101 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 W1_H02E0701 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 N1_V02S0001 + +.tile R55C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A6 N1_V01S0100 +arc: B0 H02E0301 +arc: B3 W1_H02E0101 +arc: B4 H01E0101 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: D0 S1_V02N0001 +arc: D2 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1001000010010000 +word: SLICEB.K0.INIT 0000111111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R55C86:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 H02E0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 F6 +arc: C1 V02S0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: B0 H00R0100 +arc: B1 E1_H02W0301 +arc: B2 V01N0001 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F3 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R55C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: B0 H02W0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B6 V00T0000 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H02W0401 +arc: C6 H02W0601 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0101010110101010 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 0011001111001100 +word: SLICED.K0.INIT 0100000100000000 +word: SLICEB.K1.INIT 0100000100000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C89:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B4 V02N0501 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 S1_V02N0001 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F2 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICEC.K0.INIT 0100000100000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C91:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B5 V02N0701 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0101101001011010 +word: SLICEB.K0.INIT 0000000011000011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C92:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 F7 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 W1_H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 W1_H02E0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F3 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C93:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N3_V06N0103 F1 +arc: S1_V02S0301 F3 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R55C94:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0101 +arc: B1 H00R0100 +arc: B2 V01N0001 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C1 W1_H02E0401 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R55C95:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0501 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0401 +arc: C2 H00R0100 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H02W0701 +arc: A5 H02W0701 +arc: B1 H02W0301 +arc: B5 H02W0301 +arc: C1 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: D1 V00B0100 +arc: D5 V02N0401 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C97:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02N0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A3 V02S0501 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: B0 V02N0301 +arc: B1 N1_V02S0301 +arc: B3 V02S0301 +arc: B5 F3 +arc: B6 N1_V02S0501 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C98:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 H02W0001 +arc: D5 F2 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: V01S0100 F1 +arc: W1_H02W0201 F0 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C99:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C100:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: B0 H01W0100 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 S1_V02N0401 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R56C101:PLC2 +arc: N3_V06N0203 V01N0001 +arc: V00B0100 V02N0301 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C102:PLC2 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 + +.tile R56C103:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C105:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R56C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R56C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R56C109:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R56C111:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C112:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R56C114:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C115:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R56C17:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R56C28:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 N1_V02S0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02N0301 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 H02W0201 +arc: D5 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C29:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 V02N0201 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 F1 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 F3 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C3 N1_V01S0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q6 +arc: LSR0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F6 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000010100001100 +word: SLICED.K1.INIT 0010001000100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C30:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 V01N0101 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F6 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 0000000000111010 +word: SLICEB.K1.INIT 1110101000101010 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111111110101100 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C31:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H01E0001 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111011110000000 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R56C32:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V01N0001 +arc: A0 W1_H02E0501 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 F1 +arc: B6 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C3 H02E0401 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000110111111101 +word: SLICED.K1.INIT 0000111110101111 +word: SLICEA.K1.INIT 1011101100001011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C33:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 H02E0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110101 +word: SLICEA.K1.INIT 0011001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R56C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C35:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 W1_H02E0701 +arc: B3 W1_H02E0101 +arc: C3 V02N0401 +arc: D3 H00R0000 +arc: F3 F3_SLICE +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C36:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: C0 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M5 H00L0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F6 +arc: V00B0100 Q5 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001110101111 +word: SLICEA.K1.INIT 0011001110111011 +word: SLICEB.K1.INIT 0000011101110111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1110101000101010 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: B0 H02E0301 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B4 V00B0100 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0000110111111101 +word: SLICEC.K1.INIT 0000101011111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C39:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A1 H02W0701 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 Q1 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C40:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 F5 +arc: B1 H02E0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C41:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B4 V00B0100 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011000111111101 +word: SLICEC.K1.INIT 0101000011111111 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R56C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C43:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A4 S1_V02N0301 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110001010101010 +word: SLICEC.K0.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C44:PLC2 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100100001000000 +word: SLICED.K1.INIT 0101010100000100 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C45:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B4 W1_H02E0101 +arc: C0 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEC.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C46:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C47:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 N1_V02S0401 +arc: C2 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C49:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: A0 W1_H02E0701 +arc: A5 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C50:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0701 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 F2 +arc: H01W0000 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K1.INIT 0101101000111100 +word: SLICEB.K0.INIT 1111111111110011 +word: SLICEB.K1.INIT 1010101010100010 +word: SLICED.K0.INIT 1010010111000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C52:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 H02E0701 +arc: A3 V01N0101 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C53:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A6 S1_V02N0101 +arc: B6 N1_V01S0000 +arc: C6 V00T0000 +arc: D0 V00T0100 +arc: D4 H02E0001 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F4 +arc: V01S0100 F0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R56C54:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A5 V02N0301 +arc: B5 H02E0301 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0201 +arc: D2 V02S0001 +arc: D5 H02E0201 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R56C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0001 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R56C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D5 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R56C57:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B4 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D4 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R56C58:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A3 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V02S0101 +arc: B3 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C59:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R56C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: E1_H02E0501 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0000001000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 F7 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02S0301 +arc: B4 N1_V02S0501 +arc: C4 V02N0201 +arc: D4 E1_H02W0001 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 0001010000101000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C63:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 N1_V02S0701 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: B0 H02E0301 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000001000100000 +word: SLICEA.K1.INIT 0000000011110101 +word: SLICED.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R56C64:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 F7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R56C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q7 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C68:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H02E0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C70:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R56C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06N0103 +arc: A0 V02N0701 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C73:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 N1_V02S0101 +arc: B3 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C74:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C75:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R56C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0701 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C2 F6 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S3_V06S0103 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06N0303 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C78:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 V00B0000 +arc: A5 F7 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: B7 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H00R0000 +arc: D5 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V00T0100 F1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C80:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A2 S1_V02N0501 +arc: A3 V02N0501 +arc: A5 V00T0100 +arc: A7 W1_H02E0501 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 W1_H02E0101 +arc: B7 H02W0301 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C5 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: C4 N1_V02S0201 +arc: D1 V00B0100 +arc: D5 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C82:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 H02E0101 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C2 H02E0401 +arc: D1 N1_V01S0000 +arc: D3 V00T0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: C0 N1_V02S0601 +arc: C5 N1_V02S0201 +arc: D1 N1_V02S0001 +arc: D4 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: A1 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 F4 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: S3_V06S0103 F1 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 0101000001010101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000110000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B5 N1_V02S0501 +arc: B6 F1 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 F4 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 F0 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0601 F6 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C86:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 F0 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000010000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0000000010000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C87:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 H00R0000 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 V02S0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C88:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H02W0301 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 F4 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 H01W0100 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 V01S0000 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C1 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 S1_V02N0201 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 0100000000000100 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C90:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 V01N0101 +arc: A1 H00R0000 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 W1_H02E0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H02W0301 +arc: B5 F3 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 N1_V02S0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 0100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: V00T0000 F0 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C93:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 V02N0001 +arc: C7 F4 +arc: D1 H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R56C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B1 V02S0301 +arc: B2 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 V02S0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 F0 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 0010000000000010 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C96:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R56C97:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0401 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D4 F0 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C98:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00T0100 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C99:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B3 E1_H01W0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1101000011010000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C100:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C101:PLC2 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C102:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V01S0100 + +.tile R57C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C104:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C106:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C107:PLC2 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C108:PLC2 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C109:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R57C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R57C111:PLC2 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C113:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R57C114:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R57C26:PLC2 +arc: E1_H02E0201 E3_H06W0103 + +.tile R57C27:PLC2 +arc: H00R0000 H02W0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q5 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 E1_H02W0601 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C28:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: C0 F6 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 1111110011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C29:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06N0203 +arc: A0 F5 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 N1_V02S0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1010100000001000 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1111101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C2:PLC2 +arc: V01S0100 S3_V06N0303 + +.tile R57C30:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A3 E1_H01E0001 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICED.K1.INIT 0000000011001110 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICED.K0.INIT 1110010011001100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C31:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: A0 F5 +arc: A4 N1_V01S0100 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: N3_V06N0203 Q4 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 1111111110111000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1110010011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C32:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H01E0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 N1_V01S0100 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: S1_V02S0401 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C33:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B5 V02S0701 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: V00B0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R57C34:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A3 H02W0501 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C35:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 H02W0701 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 V02S0701 +arc: B7 F3 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 E1_H02W0601 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0601 F4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 0001010100000100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000000011110001 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R57C36:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 H02E0701 +arc: B0 F1 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0301 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K1.INIT 0000000010111010 +word: SLICEA.K0.INIT 1111101011001010 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011110001 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C38:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B4 F1 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111011110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V01N0101 +arc: A2 V00B0000 +arc: A4 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C2 F4 +arc: C4 V02N0001 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D4 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q2 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C40:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 E1_H02W0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0011111100000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C41:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0010000010100000 +word: SLICEA.K1.INIT 0100000011000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0010101000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C42:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A5 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 H01E0101 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M3 H02W0201 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 1100100001000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C43:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06N0303 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02W0601 +arc: C1 H02E0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011000011111100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011000011111100 +word: SLICEB.K0.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R57C44:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111101111111000 +word: SLICEB.K1.INIT 0000101100001000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111111001010 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 0100010011101110 +word: SLICED.K0.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R57C45:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C46:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A2 V02N0701 +arc: A5 H02E0701 +arc: A7 F5 +arc: B0 H02E0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0011001111110101 +word: SLICEB.K1.INIT 0011001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R57C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C48:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: B0 S1_V02N0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1011100000110000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C51:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C52:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 N1_V02S0301 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C54:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 0110010101101010 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0101011010100110 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 H01E0101 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 0011011011000110 +word: SLICEA.K0.INIT 0011110001100110 +word: SLICEB.K1.INIT 0001111011010010 +word: SLICEC.K1.INIT 0110010101101010 +word: SLICEA.K1.INIT 0110011000111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 H02W0701 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: E1_H02E0601 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C57:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H01E0101 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 W1_H02E0701 +arc: A2 H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02W0701 +arc: A5 V02S0101 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B5 S1_V02N0501 +arc: B7 V02S0701 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: D5 W1_H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M4 V00B0100 +arc: S1_V02S0101 F1 +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C61:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 W1_H02E0701 +arc: A6 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: B1 F3 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 W1_H02E0001 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R57C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C63:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H02W0701 +arc: B1 N1_V02S0101 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V02N0701 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 V00T0100 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02N0401 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0000011001100000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R57C64:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V01N0101 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 W1_H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q3 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010000101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C65:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0701 Q5 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1011100010111000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C66:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 H02W0701 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B4 V02N0701 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000000000100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C67:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0501 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0301 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R57C68:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: F2 F2_SLICE +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 V02S0501 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C70:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C72:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0100 +arc: A1 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B5 E1_H02W0101 +arc: C5 W1_H02E0401 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M4 V00B0100 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011001100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C73:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0701 +arc: A3 F7 +arc: A7 V02S0301 +arc: B1 V02N0101 +arc: B3 E1_H01W0100 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C7 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: V00T0100 F1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C74:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 F7 +arc: A5 V00T0100 +arc: A6 W1_H02E0501 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V02N0401 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEA.K0.INIT 0000001000001000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEB.K0.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C75:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 F1 +arc: B4 V02N0701 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0100 F3 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R57C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A4 V00T0100 +arc: B0 V00B0000 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1010111100000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R57C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 V00T0000 +arc: C2 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B3 W1_H02E0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C3 V02N0401 +arc: C5 F4 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F0 +arc: V01S0000 F5 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000100001000100 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C81:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: B0 V00T0000 +arc: B3 S1_V02N0101 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: D0 V02N0001 +arc: D3 V00B0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R57C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A2 F7 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 F3 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 F6 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V02S0001 +arc: D2 F0 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R57C83:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 F3 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 W1_H02E0201 +arc: D4 F0 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: V00B0000 F6 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R57C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A1 W1_H02E0701 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R57C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 H02W0501 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 F1 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C7 F4 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0001 F2 +arc: V00T0100 F3 +arc: V01S0100 F7 +word: SLICED.K0.INIT 0110011001100110 +word: SLICEA.K0.INIT 0100000100000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C88:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F0 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R57C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C1 V02S0401 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R57C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A2 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A7 S1_V02N0301 +arc: B5 H00L0000 +arc: B6 W1_H02E0301 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C92:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 W1_H02E0501 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F5 +arc: V01S0100 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B5 H02E0301 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: N1_V02N0201 F0 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C94:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 S1_V02N0301 +arc: B2 H02E0301 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0301 F1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F6 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F5 +arc: V01S0100 F0 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C95:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: A6 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C4 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 W1_H02E0601 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W3_H06W0003 F0 +word: SLICED.K0.INIT 0000100000000100 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C96:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A6 W1_H02E0701 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B3 V02N0301 +arc: B6 F3 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C6 V02N0201 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D3 H02E0201 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: S1_V02S0201 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R57C97:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: B5 W1_H02E0301 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R57C98:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 E1_H02W0701 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 Q3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C99:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: C0 W1_H02E0401 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C100:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A0 H02E0701 +arc: A2 H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1011100010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C101:PLC2 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: B0 H02E0301 +arc: B3 V01N0001 +arc: C0 W1_H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 F3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R59C102:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0201 H01E0001 + +.tile R59C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R59C104:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R59C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C107:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: C6 V02S0001 +arc: D6 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: N3_V06N0303 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R59C108:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C109:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C110:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 + +.tile R59C111:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C113:PLC2 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C115:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C116:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C117:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C14:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C15:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R59C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C21:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C23:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C26:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C28:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02N0701 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C3 F6 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R59C29:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEC.K1.INIT 0000001100100010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEB.K1.INIT 1110111010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C30:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEC.K1.INIT 1010110011001100 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C31:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A5 H02W0501 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B7 V02N0701 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C32:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: A0 W1_H02E0701 +arc: A1 H02W0701 +arc: A2 H01E0001 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0501 +arc: A7 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 H01E0101 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0103 Q2 +arc: V00T0100 F3 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0111010001110111 +word: SLICEC.K1.INIT 0111010101110101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 + +.tile R59C33:PLC2 +arc: E1_H02E0301 V02S0301 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 H01E0001 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A6 V02N0101 +arc: B0 V02N0301 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F5 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0011001111110101 +word: SLICED.K1.INIT 0011001111110011 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R59C34:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0501 F7 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111110011111010 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICED.K0.INIT 0011001100010000 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEC.K0.INIT 0101010111110011 +word: SLICEC.K1.INIT 0101010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R59C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0301 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +arc: N3_V06N0203 F4 +arc: V00T0000 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110101 +word: SLICEA.K1.INIT 0011001111110011 +word: SLICEC.K0.INIT 0000110000001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R59C36:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 V06N0303 +arc: A1 H02E0501 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 F1 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C37:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 0000000000111010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R59C38:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000001100100010 +word: SLICEB.K0.INIT 1111111010101110 +word: SLICEB.K1.INIT 0101010000000100 +word: SLICEA.K1.INIT 0100010101000100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICED.K1.INIT 1011111110000000 +word: SLICED.K0.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C39:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 W1_H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1111111110111000 +word: SLICEC.K1.INIT 0000000010111000 +word: SLICED.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111011110000000 +word: SLICEB.K1.INIT 1110010011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C40:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 V02S0701 +arc: A5 V00B0000 +arc: A7 W1_H02E0501 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 H02W0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C5 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0100 F0 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C41:PLC2 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 H02E0101 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 N1_V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1000000010101010 +word: SLICEC.K0.INIT 0100010100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R59C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C3 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEC.K1.INIT 1111111110100000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111101010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A2 V01N0101 +arc: A5 H02E0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0101 +arc: B3 Q3 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101011001010 +word: SLICED.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 E1_H02W0301 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0303 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F6 +arc: V00B0000 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111111110101100 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0011001111110000 +word: SLICEC.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C45:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 1101100011110000 +word: SLICEB.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C46:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C47:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V00T0000 +arc: A6 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B3 E1_H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 Q0 +arc: V01S0100 F2 +arc: W1_H02W0001 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEB.K0.INIT 1010000011110000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R59C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H01E0001 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B6 H02E0101 +arc: C0 F6 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D6 N1_V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R59C50:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A5 V00T0100 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0301 F3 +arc: V01S0000 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111001111111111 +word: SLICEC.K1.INIT 0101000101010101 +word: SLICED.K0.INIT 1111111100111111 +word: SLICED.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C51:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B1 H02E0301 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0101101000111100 +word: SLICEB.K0.INIT 1111111101011111 +word: SLICEB.K1.INIT 0000000011011111 +word: SLICEC.K0.INIT 1111111101011111 +word: SLICEC.K1.INIT 0000000011011111 +word: SLICEA.K1.INIT 1001100111000011 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R59C52:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B1 V02S0101 +arc: B3 H00R0100 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 N1_V02S0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111101011111 +word: SLICEA.K1.INIT 0011001100010011 +word: SLICEB.K0.INIT 1111111101011111 +word: SLICEB.K1.INIT 0011001100010011 +word: SLICEC.K0.INIT 1111111101011111 +word: SLICEC.K1.INIT 0000000011011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C53:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 F6 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0203 F7 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 0000100000000100 +word: SLICED.K0.INIT 0011110001011010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C54:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A7 H00R0000 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 H01E0101 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0010000000000010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C55:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000000010000 +word: SLICED.K0.INIT 0000100100000000 +word: SLICEA.K1.INIT 0101011010011010 +word: SLICEC.K1.INIT 0000000011000011 +word: SLICEB.K1.INIT 0011110001011010 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEB.K0.INIT 0011000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R59C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: V00B0100 H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 V02N0501 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C57:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V01S0000 F7 +arc: V01S0100 F1 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C58:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +arc: V01S0100 F0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C59:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F6 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B6 H01E0101 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: V01S0000 F1 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100101011001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 W1_H02E0101 +arc: B5 F3 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 F6 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C65:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEB.K0.INIT 0010000010000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: C1 H02E0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: N1_V01N0101 F1 +word: SLICEA.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R59C67:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00T0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C68:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 V00T0000 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 H02E0101 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000111100001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C71:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 V02S0501 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0101 F7 +arc: N3_V06N0103 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C73:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +arc: V01S0100 F0 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C74:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: B0 E1_H02W0301 +arc: B1 V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0301 F1 +arc: V01S0100 F0 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A5 H02W0501 +arc: A7 V02N0101 +arc: B1 V00B0000 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C1 H00R0100 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: D1 V00B0100 +arc: D5 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C76:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C77:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 N1_V02S0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: C0 H00R0100 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C78:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C79:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A2 V02N0701 +arc: B0 S1_V02N0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 F1 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R59C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: B0 V02S0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: V01S0000 Q6 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R59C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A4 V00T0100 +arc: A7 V02S0301 +arc: B0 H02W0301 +arc: B1 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0003 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000000010100011 +word: SLICEA.K1.INIT 0000000011001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R59C82:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 V01N0101 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R59C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A5 V00T0000 +arc: B0 H02W0101 +arc: B2 H00L0000 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C2 H00R0100 +arc: C5 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D0 H02E0201 +arc: D2 N1_V02S0201 +arc: D5 W1_H02E0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A6 N1_V02S0301 +arc: B6 W1_H02E0301 +arc: C6 S1_V02N0201 +arc: D6 V02N0401 +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 0100000000000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0701 +arc: A5 V00T0000 +arc: B4 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: E1_H01E0001 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F6 +arc: S3_V06S0003 F3 +arc: V01S0000 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H02W0501 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F0 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C87:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A3 W1_H02E0701 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B4 E1_H02W0301 +arc: B7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +arc: N3_V06N0003 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: E1_H01E0101 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C89:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 V02N0101 +arc: B4 V00B0100 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D4 V00B0000 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02N0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 N1_V02S0501 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 V02S0601 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: D0 H02W0001 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 N1_V02S0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C3 F4 +arc: C4 E1_H02W0601 +arc: C5 H01E0001 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 W1_H02E0001 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICED.K1.INIT 0000000011000011 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R59C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 N1_V02S0501 +arc: A2 F7 +arc: A3 W1_H02E0701 +arc: A4 N1_V02S0101 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02S0401 +arc: C1 H00R0100 +arc: C2 F4 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D0 N1_V02S0001 +arc: D1 V02S0001 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 F1 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V02S0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R59C94:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: B1 Q1 +arc: B4 V02S0701 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000110000100011 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0000111111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R59C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A3 W1_H02E0501 +arc: A4 V02S0101 +arc: A6 H02W0701 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 V00T0000 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: B5 N1_V02S0501 +arc: C0 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D5 V02N0401 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: C0 H02E0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R59C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q5 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q5 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C3:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 + +.tile R5C40:PLC2 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: B0 H02W0301 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: F0 F5A_SLICE +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C42:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1000101110111000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C43:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 V00T0100 +arc: B0 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q6 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A5 Q5 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00L0000 +arc: B4 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C45:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B4 S1_V02N0501 +arc: B6 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1110010011100100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C46:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 V02N0501 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C47:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C48:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A4 V02S0101 +arc: B0 E1_H01W0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C49:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C50:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 E1_H01W0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: C0 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q5 +arc: V01S0000 F4 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C51:PLC2 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0401 E1_H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C53:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 + +.tile R60C100:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 W1_H02E0601 +arc: V01S0000 S3_V06N0103 +arc: C7 V02S0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00R0100 +arc: M2 W1_H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R60C101:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R60C102:PLC2 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 + +.tile R60C103:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R60C105:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R60C106:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R60C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R60C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C115:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R60C20:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C25:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R60C26:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R60C27:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q3 +arc: LSR1 E1_H02W0301 +arc: M3 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C28:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B3 H00L0000 +arc: B6 E1_H02W0101 +arc: C0 F6 +arc: C3 F6 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R60C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D7 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K1.INIT 0000101100001010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V01N0001 +arc: A2 H02W0501 +arc: A3 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0101 +arc: B5 F3 +arc: B6 H01E0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C4 V01N0101 +arc: C5 H02E0401 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0601 F6 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEC.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110110001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 W1_H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1110001010101010 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C32:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02N0101 +arc: A6 F7 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000111111101 +word: SLICEB.K1.INIT 0011111100001111 +word: SLICEA.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C33:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 F3 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0201 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C3 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1011111110000000 +word: SLICEA.K1.INIT 1110101000101010 +word: SLICEC.K1.INIT 0101111101010000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1110101000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C35:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 H02E0701 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V02S0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q5 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R60C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A2 H02W0701 +arc: A5 S1_V02N0101 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: LSR0 H02E0501 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V01S0000 F5 +arc: V01S0100 Q6 +word: SLICEA.K1.INIT 0111011101000100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 0011001111110101 +word: SLICEB.K1.INIT 0011001111110011 +word: SLICEC.K1.INIT 1011000010111011 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C37:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 F6 +arc: C3 F6 +arc: C4 V02N0001 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C38:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0000 +arc: A3 V02N0701 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0101 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 W1_H02E0201 +arc: D3 F2 +arc: D5 E1_H02W0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 Q4 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C39:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 H02E0701 +arc: A5 E1_H02W0501 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 E1_H01W0100 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D3 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1111100001110000 +word: SLICED.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C40:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0501 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: V01S0000 F2 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111110111011 +word: SLICEA.K1.INIT 0000111110101111 +word: SLICEB.K0.INIT 0010001111101111 +word: SLICEB.K1.INIT 0101111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R60C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B3 H00L0000 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D1 H02W0201 +arc: D3 V00T0100 +arc: D6 E1_H02W0001 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F6 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R60C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B4 V02N0501 +arc: B5 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +arc: S1_V02S0501 F5 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C43:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 N1_V02S0501 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +word: SLICEB.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICED.K1.INIT 0011001100000010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C44:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B1 S1_V02N0101 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001010100000100 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEC.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C45:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 0001001100010011 +word: SLICED.K1.INIT 1010100000100000 +word: SLICEC.K0.INIT 0000111111011101 +word: SLICEC.K1.INIT 0101010111011101 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICEB.K0.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C46:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 E3_H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A2 V01N0101 +arc: A7 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D7 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0101110001011111 +word: SLICEB.K1.INIT 0011111100110011 +word: SLICED.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C47:PLC2 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 S1_V02N0501 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEB.K0.INIT 0011101000111111 +word: SLICEB.K1.INIT 0011111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R60C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H01E0001 +arc: A2 H02W0701 +arc: A3 H01E0001 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 F3 +arc: V01S0100 F3 +arc: W1_H02W0201 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEB.K1.INIT 1010111100000000 +word: SLICEB.K0.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R60C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 W1_H02E0401 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00T0000 F2 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100001110011001 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICED.K1.INIT 0100101101111000 +word: SLICEB.K1.INIT 0001111011010010 +word: SLICEB.K0.INIT 1100001110100101 +word: SLICED.K0.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R60C51:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: V00B0100 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1111111101011111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 0100101101111000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C52:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B1 E1_H01W0100 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C1 V02N0601 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00B0000 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 0000000010000010 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C53:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 N1_V02S0401 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1010110001010011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C54:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A4 F7 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0100000000000100 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0101101000111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C55:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 N1_V02S0701 +arc: A1 V02N0701 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 F7 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0101 +arc: B3 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0011010111001010 +word: SLICEB.K1.INIT 1100001110100101 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K1.INIT 0011010111001010 +word: SLICEA.K1.INIT 0011110001011010 +word: SLICEC.K0.INIT 1010110001010011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R60C56:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 + +.tile R60C57:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V01S0000 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C58:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H01E0101 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D6 H02W0201 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q3 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C59:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H00L0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 N1_V01S0100 +arc: B1 Q1 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R60C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 N1_V02S0701 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C64:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02S0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R60C66:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V01N0101 +arc: A4 V02S0301 +arc: A6 E1_H02W0501 +arc: B2 V02S0101 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 H02E0001 +arc: D4 V02S0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C67:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R60C68:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06W0003 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: B1 Q1 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C69:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A7 H02E0701 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C71:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C72:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 H00R0100 +arc: C5 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V00T0100 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000011001100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C74:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 V02N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V00B0000 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C75:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile R60C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: B6 H02W0101 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D5 V01N0001 +arc: D6 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R60C77:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 H01E0101 +arc: V00B0000 V02S0201 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 V02S0701 +arc: A3 F7 +arc: A4 V02S0301 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C3 F6 +arc: C4 H02W0601 +arc: C6 N1_V02S0001 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D3 F0 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R60C78:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H02W0501 +arc: A4 V02S0301 +arc: B0 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V02S0401 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C79:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B3 H01W0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q7 +arc: S1_V02S0701 Q7 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A5 W1_H02E0501 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 W1_H02E0601 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 Q5 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C81:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02E0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 W1_H02E0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 Q6 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B5 V01S0000 +arc: B7 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 V02S0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M5 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100000011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H01E0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: C0 V02N0401 +arc: C2 E1_H01W0000 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C84:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R60C85:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A2 F5 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B2 H01W0100 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICED.K1.INIT 0100000000010000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 F5 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B1 F3 +arc: B3 H00R0100 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 F4 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C87:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: D1 V02S0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C88:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A2 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B2 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: V00T0100 F3 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 H01E0101 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0001 +arc: D6 F0 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F3 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: B0 H00R0100 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0401 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: D0 V02S0201 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: V01S0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 H01W0100 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R60C92:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: B1 N1_V02S0301 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000001100000101 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C94:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: B0 V02N0301 +arc: B4 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C95:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B3 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F4 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C96:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A7 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 Q4 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C97:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 N1_V02S0501 +arc: A2 V00T0000 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0103 Q1 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C98:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 V06N0103 +arc: A0 H02W0501 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: C0 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 W1_H02E0201 +arc: M4 H02E0401 +arc: M5 H00R0100 +arc: M6 H02E0401 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R61C100:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C101:PLC2 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R61C107:PLC2 +arc: N1_V02N0601 S1_V02N0601 + +.tile R61C28:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 H02W0701 +arc: B1 E1_H01W0100 +arc: C1 V02N0401 +arc: D1 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R61C29:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICED.K0.INIT 0000000001001110 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K1.INIT 0000101100001010 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C30:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: B0 V01N0001 +arc: B2 V02N0101 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C31:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: A1 W1_H02E0501 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F6 +arc: V00T0100 F1 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0010111000101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0010111000101110 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0101010111110011 +word: SLICED.K1.INIT 0101010111110101 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C32:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 V00B0000 +arc: M1 W1_H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R61C33:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 H02W0701 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C1 F4 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 E1_H01W0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1000100010100000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEA.K1.INIT 0011000000110010 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C34:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 N1_V02S0701 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 F3 +arc: V01S0000 Q1 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111111110101100 +word: SLICEC.K1.INIT 0011000000100010 +word: SLICED.K1.INIT 0010001011101110 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1011111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 W1_H02E0101 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0000110111111101 +word: SLICEC.K1.INIT 0011111100110011 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C36:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V01N0001 +arc: A1 H01E0001 +arc: A4 N1_V01S0100 +arc: B1 E1_H02W0301 +arc: B4 V02S0501 +arc: C1 N1_V01S0100 +arc: C4 V02N0201 +arc: D1 S1_V02N0001 +arc: D4 H02E0001 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0011000100010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C37:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M1 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F7 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0100110000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0111000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R61C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 V02N0701 +arc: A6 S1_V02N0301 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 F6 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0010001100000011 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C40:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0201 E3_H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V01N0001 +arc: A0 V01N0101 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 V02N0301 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 H02W0101 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F6 +arc: V00T0000 F0 +arc: V01S0000 F7 +arc: W1_H02W0601 F6 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02W0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B1 V01N0001 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 H01E0001 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000010000000 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C42:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V01S0000 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R61C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 F5 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C6 V01N0101 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F7 +arc: V01S0000 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q4 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111101011111100 +word: SLICEB.K1.INIT 0000101000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1011100011110000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: A7 H00L0000 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C4 F6 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0011001110101111 +word: SLICEB.K1.INIT 0011001110111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R61C46:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1111111111100010 +word: SLICEC.K1.INIT 0000000011100010 +word: SLICED.K1.INIT 0000000011011100 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICED.K0.INIT 1110101000101010 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: B0 H02E0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: D0 V01S0100 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: N3_V06N0203 F4 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K0.INIT 0100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C48:PLC2 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 S1_V02N0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A2 H02W0501 +arc: A5 N1_V01S0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R61C49:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile R61C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0201 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1100001110100101 +word: SLICED.K0.INIT 0001111011010010 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICEC.K0.INIT 1111111100111111 +word: SLICEC.K1.INIT 0000101100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C51:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06N0203 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 W1_H02E0201 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 0101101000111100 +word: SLICEC.K0.INIT 0000000000000100 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0100010101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R61C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 1100001110100101 +word: SLICED.K0.INIT 0011110001100110 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010111111111111 +word: SLICEA.K1.INIT 0010001100110011 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICEC.K1.INIT 1100001110011001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C53:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: A1 S1_V02N0701 +arc: B1 H00R0100 +arc: B2 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: V01S0000 F2 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010111111111 +word: SLICEA.K1.INIT 0101000101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C54:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A2 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B2 V02S0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C2 H00L0000 +arc: C4 V02S0201 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0701 F7 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C55:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: B0 V00T0000 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R61C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: B0 V02S0301 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0101000001011111 +word: SLICEC.K1.INIT 0000000001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C57:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 E1_H02W0301 +arc: B4 F3 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q2 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEA.K0.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C58:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 W1_H02E0501 +arc: A5 Q5 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0303 Q5 +arc: V00T0000 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C59:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A7 N1_V01S0100 +arc: B0 N1_V02S0101 +arc: C0 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 W1_H02E0501 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B6 H01E0101 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D6 H02E0201 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C61:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0201 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C2 W1_H02E0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C63:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0701 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q4 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A5 V00T0100 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C66:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A6 N1_V01S0100 +arc: B1 V01N0001 +arc: B6 H01E0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C68:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C69:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0501 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C70:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A3 H02E0501 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C71:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A1 V02S0701 +arc: A2 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 E1_H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C72:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A5 E1_H01W0000 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C4 N1_V02S0201 +arc: C5 V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 F7 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 Q4 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001110100111111 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R61C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06E0203 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C74:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C75:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 + +.tile R61C76:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R61C77:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 N1_V02S0701 + +.tile R61C78:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 + +.tile R61C79:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: B1 Q1 +arc: B4 V02S0701 +arc: B5 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C80:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B5 H02W0301 +arc: C0 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C81:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: B1 Q1 +arc: B5 V02S0501 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q7 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06S0203 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: A3 H02W0501 +arc: A4 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 W1_H02E0101 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B5 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C85:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 N1_V02S0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q4 +arc: V00B0000 Q4 +arc: V01S0000 F5 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 F5 +arc: B2 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q3 +arc: V00B0000 F4 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C87:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02W0001 +arc: H00L0100 W1_H02E0301 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 H00L0100 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 E1_H01W0100 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D3 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: V00T0100 F3 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A5 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000001100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C89:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A6 H02W0701 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B5 H01E0101 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D6 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q5 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0011000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 E1_H01W0100 +arc: B5 V02N0701 +arc: C1 E1_H01W0000 +arc: C5 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 V00B0000 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: S3_V06S0103 F1 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R61C91:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 H02E0701 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q3 +arc: V01S0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R61C92:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 + +.tile R61C93:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: F0 F5A_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R61C94:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C95:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B3 V02N0101 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R61C96:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02S0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R61C97:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: B0 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 V01S0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C98:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V02N0201 +arc: D4 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C99:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 E1_H01W0000 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C100:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C101:PLC2 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 + +.tile R62C102:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R62C105:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C106:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R62C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C109:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R62C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R62C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R62C114:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R62C115:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R62C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R62C28:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B6 V02S0701 +arc: C0 F6 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C29:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: B0 V01N0001 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1111111010101110 +word: SLICEC.K1.INIT 0011001000000010 +word: SLICED.K0.INIT 0010001000110010 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 H02W0501 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 H01E0101 +arc: B6 W1_H02E0101 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F7 +word: SLICEC.K0.INIT 1110010011001100 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000001000001110 +word: SLICEC.K1.INIT 0000000010101011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C31:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A3 V01N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B1 H02E0301 +arc: B3 H00L0000 +arc: B5 F1 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 Q7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111110011001100 +word: SLICED.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C32:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 H01E0101 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A6 N1_V01S0100 +arc: A7 H02E0501 +arc: B1 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: S1_V02S0701 F7 +word: SLICED.K0.INIT 0010000010100000 +word: SLICEB.K0.INIT 0000110111111101 +word: SLICEB.K1.INIT 0000110011111111 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C33:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R62C34:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 F5 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: LSR0 H02W0301 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F3 +arc: S1_V02S0001 F2 +arc: V01S0000 F7 +arc: V01S0100 Q5 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R62C35:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02W0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A7 V02N0301 +arc: B3 V01N0001 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: D7 H00L0100 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F3 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 1110010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C36:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B4 N1_V01S0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: LSR0 H02E0501 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0010000010100000 +word: SLICED.K1.INIT 1000101000001010 +word: SLICEC.K0.INIT 1111110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R62C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 S1_V02N0501 +arc: A4 E1_H02W0501 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 Q6 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 0000000011001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R62C38:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0701 +arc: A1 F7 +arc: A3 H02W0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q3 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1010110011001100 +word: SLICEC.K1.INIT 0010001011101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R62C39:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F5 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1010001000100010 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C40:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B2 E1_H02W0101 +arc: B4 V02N0701 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F1 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C41:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 V02S0701 +arc: A4 E1_H02W0701 +arc: A6 H02E0701 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B5 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: D0 S1_V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100110011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R62C42:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N3_V06N0103 F1 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000000010001111 +word: SLICEC.K0.INIT 0100110000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R62C43:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 V02N0601 +arc: C3 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D3 N1_V02S0001 +arc: D5 V00B0000 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0501 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: V01S0100 F6 +arc: W1_H02W0401 F6 +word: SLICEC.K1.INIT 1110001010101010 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1110010011001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0011001110101111 +word: SLICEC.K1.INIT 0011001110111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R62C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q3 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 0011111100011101 +word: SLICED.K1.INIT 0011111100001111 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 0101110001011100 +word: SLICEC.K0.INIT 1110010011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C47:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V02S0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 Q7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R62C48:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0501 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 V02N0401 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R62C49:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00B0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 F3 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R62C50:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 + +.tile R62C51:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: C1 S1_V02N0401 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F5A_SLICE +arc: M0 H02E0601 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1111111101110111 +word: SLICEA.K1.INIT 0000111100000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C52:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: B2 S1_V02N0101 +arc: C2 H02W0401 +arc: D2 S1_V02N0201 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: V01S0100 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C53:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C54:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A4 V02S0301 +arc: C0 V02N0401 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R62C55:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B2 V02S0101 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B6 E1_H02W0101 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C57:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00L0000 +arc: B5 H00R0000 +arc: B6 V02N0701 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C58:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 +arc: A3 H02W0501 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C59:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02W0701 +arc: A4 H02W0501 +arc: B0 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C60:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C4 W1_H02E0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 Q5 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C61:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 H02E0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 V02N0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 N1_V02S0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0011000000111111 +word: SLICED.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C65:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C67:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C68:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 N1_V02S0301 +arc: B0 H02E0101 +arc: B1 E1_H02W0301 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: A2 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: B5 S1_V02N0701 +arc: B7 H02W0101 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 V06S0303 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 F6 +arc: V00B0000 Q4 +arc: V00B0100 F7 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000001010011 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C73:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V00T0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C75:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C77:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: S1_V02S0201 F0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C78:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R62C79:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 F5 +arc: A3 H02W0501 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B1 H00R0100 +arc: B3 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C1 F6 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D1 V01S0100 +arc: D3 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C80:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +word: SLICEA.K0.INIT 1111000001110000 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICEB.K0.INIT 1100000001000000 +word: SLICEB.K1.INIT 0000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: B1 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C1 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: D1 H02E0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011010111111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011010100000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R62C82:PLC2 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 E1_H01W0000 +arc: B5 H02W0301 +arc: D4 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R62C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A6 V02S0301 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000001100000101 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H02W0501 +arc: A2 H00L0100 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B6 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V02S0601 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C86:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R62C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0501 +arc: A5 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +word: SLICEA.K1.INIT 1000100011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R62C89:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B1 H01W0100 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V00T0100 Q3 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0011000001010000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 F5 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R62C91:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A4 N1_V01N0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000011101111 +word: SLICEA.K1.INIT 0000000011100000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C93:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q7 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V00B0000 F4 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C94:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: B6 H02E0301 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D3 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C95:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: A0 V02S0501 +arc: A2 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B1 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C96:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: A0 H02E0501 +arc: A1 W1_H02E0501 +arc: A2 V00B0000 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F2 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C97:PLC2 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C98:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 V06N0003 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C99:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C100:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 V02S0401 +arc: A4 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02E0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R63C101:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: B1 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C2 E1_H02W0401 +arc: D0 H02E0001 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R63C102:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R63C103:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R63C104:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R63C106:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R63C107:PLC2 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 + +.tile R63C108:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R63C109:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R63C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R63C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R63C114:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R63C27:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 + +.tile R63C28:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: A0 F7 +arc: A4 E1_H01W0000 +arc: A7 H00L0000 +arc: B3 H02E0301 +arc: B5 H00L0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 N1_V01S0100 +arc: C5 E1_H01E0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 N1_V01S0000 +arc: D5 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R63C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06N0203 +arc: A0 V02N0701 +arc: A3 V01N0101 +arc: A5 F7 +arc: B0 V01N0001 +arc: B3 W1_H02E0301 +arc: B5 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 F0 +arc: D5 E1_H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H01E0001 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q6 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111111110001000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1110010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C2:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R63C30:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A6 H02E0701 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 F6 +arc: C3 F6 +arc: C4 H02E0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D6 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R63C31:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: A1 H00R0000 +arc: A3 H02E0501 +arc: A4 H02E0501 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C3 F4 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0101 F1 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000100010001000 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R63C32:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 V02S0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B1 V02S0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C3 F6 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111100001110000 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0011000111111101 +word: SLICED.K1.INIT 0111011101010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R63C33:PLC2 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 F4 +arc: C1 H02W0601 +arc: C3 F4 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M2 W1_H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0101111101010011 +word: SLICEC.K1.INIT 0011111100001111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C34:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B1 V01N0001 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M3 E1_H02W0201 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q4 +arc: V01S0000 F2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R63C35:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 H00L0100 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B3 H00L0000 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C3 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0101010111001111 +word: SLICED.K1.INIT 0101010111011101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B3 H01W0100 +arc: B5 H02E0301 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C3 F6 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0100010100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C37:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C4 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D4 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F2 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 0100010001000101 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C38:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H01E0001 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1110010000000000 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K0.INIT 0000101100001010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R63C39:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A6 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B6 H02W0301 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 H00R0000 +arc: D6 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R63C40:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0001 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: N3_V06N0303 F5 +arc: V01S0000 F0 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K0.INIT 0010001111101111 +word: SLICEA.K1.INIT 0000101011111111 +word: SLICEB.K0.INIT 0000101111111011 +word: SLICEB.K1.INIT 0000101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R63C41:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F5 +arc: A2 H00L0100 +arc: A7 S1_V02N0301 +arc: B1 E1_H01W0100 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 H02W0101 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D5 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0303 F5 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C42:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B1 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: C1 H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 H02W0601 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0401 Q6 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICEA.K1.INIT 1111111111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R63C43:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H02W0701 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F7 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEC.K0.INIT 1111101011111100 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICED.K0.INIT 0000000011011100 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C45:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 F3 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0010001000110010 +word: SLICEC.K0.INIT 0000010000001110 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 1110010011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C46:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A4 F7 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 E1_H01W0100 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 V02S0001 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 N1_V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N3_V06N0103 F2 +arc: V00B0000 F4 +arc: V01S0000 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111110101100 +word: SLICEA.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R63C47:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0701 +arc: A3 V02N0701 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 N1_V01S0000 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F2 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0501 +arc: A6 V02N0301 +arc: B6 H02W0101 +arc: C0 S1_V02N0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R63C49:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: A4 E1_H02W0501 +arc: B0 V00T0000 +arc: B3 V02N0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R63C50:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: B3 S1_V02N0101 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R63C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H00L0100 +arc: A7 V02S0301 +arc: B2 V02S0301 +arc: B5 N1_V02S0701 +arc: B7 E1_H02W0101 +arc: C1 N1_V01S0100 +arc: C2 H02E0601 +arc: C5 W1_H02E0401 +arc: C7 H02E0601 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D5 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F1 +arc: N3_V06N0103 F1 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000111100001110 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R63C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A3 V01N0101 +arc: B0 E1_H01W0100 +arc: B3 V02S0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000100000000000 +word: SLICEA.K0.INIT 1111110110101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C53:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0501 +arc: B2 H02E0101 +arc: C2 N1_V02S0401 +arc: D2 V02S0001 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 0000111000000010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R63C54:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: W3_H06W0103 E3_H06W0003 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C55:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A7 H02E0501 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V02S0501 +arc: A4 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 N1_V02S0501 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: V00B0100 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 0001111100010000 +word: SLICEA.K1.INIT 0000110001011100 +word: SLICEB.K0.INIT 0001111100010000 +word: SLICEB.K1.INIT 0100010001001110 +word: SLICEC.K0.INIT 0001000111110000 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 0000001110101010 +word: SLICED.K1.INIT 0000001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C57:PLC2 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 E1_H01W0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEC.K0.INIT 0000001100001010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C58:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A7 V02S0101 +arc: B1 V02S0101 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 H00R0000 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C59:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B5 N1_V01S0000 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D5 V00B0000 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C60:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B5 H02E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C7 V00B0100 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F0 +arc: V01S0000 F7 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000101000001100 +word: SLICEB.K0.INIT 0011000000111111 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 0011000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R63C62:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 0011000000111111 +word: SLICEC.K1.INIT 0000000001011100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C63:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 E3_H06W0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C64:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V00T0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 N1_V01S0100 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B1 S1_V02N0301 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C66:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V00T0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C67:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 S1_V02N0701 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0701 Q5 +arc: S1_V02S0201 Q2 +arc: S3_V06S0203 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 N1_V02S0701 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011111110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C72:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B5 H02E0101 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D5 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C73:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 H02W0201 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C74:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 N1_V02S0701 +arc: A5 V00B0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 W1_H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C75:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A5 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C3 H02E0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D3 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 W1_H02E0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001110100111111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C77:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C78:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B7 F3 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C7 E1_H01E0101 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0701 +arc: A4 V02N0101 +arc: B1 W1_H02E0301 +arc: B4 H02E0301 +arc: C1 V02N0601 +arc: C4 E1_H02W0601 +arc: D1 H00R0000 +arc: D4 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: M0 V00B0000 +arc: N3_V06N0003 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R63C80:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R63C81:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02E0001 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 W1_H02E0001 +arc: M6 V00B0100 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1111000001110000 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICEB.K0.INIT 1100000001000000 +word: SLICEB.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 1011000011110000 +word: SLICEC.K1.INIT 0001111100000000 +word: SLICED.K0.INIT 1000000011000000 +word: SLICED.K1.INIT 0000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C82:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S1_V02S0501 F5 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1011111100000000 +word: SLICEC.K1.INIT 0001111100000000 +word: SLICED.K0.INIT 1011000000000000 +word: SLICED.K1.INIT 0001000000000000 +word: SLICEA.K0.INIT 0000110000001111 +word: SLICEA.K1.INIT 0000101000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R63C83:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A4 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C85:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B1 E1_H01W0100 +arc: B3 H02W0101 +arc: C0 V02N0601 +arc: D2 H02W0001 +arc: D4 V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R63C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B4 N1_V02S0501 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000001100000101 +word: SLICED.K1.INIT 1111000011100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R63C88:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C89:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 N1_V02S0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0501 +arc: B0 V02S0101 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C5 H01E0001 +arc: D0 W1_H02E0001 +arc: D4 H00L0100 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: S1_V02S0701 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEA.K0.INIT 0000000000101111 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R63C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A6 E1_H02W0701 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: S1_V02S0001 Q0 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V01S0100 +arc: A7 V02S0101 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D6 W1_H02E0201 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C94:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A5 N1_V02S0101 +arc: C0 V02N0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C95:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: W1_H02W0401 W3_H06E0203 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C96:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C97:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C98:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C99:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C100:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 V02N0401 +arc: A6 N1_V02S0301 +arc: C7 H02E0601 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 W1_H02E0201 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C101:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0101 V02N0101 + +.tile R64C107:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R64C110:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 + +.tile R64C113:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R64C116:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R64C23:PLC2 +arc: N3_V06N0003 E3_H06W0003 + +.tile R64C26:PLC2 +arc: N3_V06N0003 H06W0003 + +.tile R64C28:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 + +.tile R64C29:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C30:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: A0 F7 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICED.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 V02S0401 +arc: A0 N1_V02S0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEB.K0.INIT 1111111010101110 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C32:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A3 H02W0501 +arc: A4 S1_V02N0301 +arc: A7 H02E0501 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1110110001001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0100000011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R64C33:PLC2 +arc: E1_H02E0201 V02S0201 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: A1 F7 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B6 N1_V02S0701 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C6 H01E0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M3 H00L0000 +arc: M5 H00R0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q7 +arc: S1_V02S0501 Q7 +arc: V01S0000 F7 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0100000011000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 H02E0501 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C5 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D5 H02E0201 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q2 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1010110011001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110101000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C35:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000000010000000 +word: SLICEA.K0.INIT 1100101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C36:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A5 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111100011110000 +word: SLICEB.K0.INIT 0000111110111011 +word: SLICEB.K1.INIT 0000111110101111 +word: SLICEC.K1.INIT 0100000011000000 +word: SLICEA.K1.INIT 1100010001000100 +word: SLICED.K0.INIT 1111110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R64C37:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0011001111111100 +word: SLICEA.K1.INIT 1001100111111010 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C38:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: A3 N1_V02S0701 +arc: A6 V02N0101 +arc: B0 H01W0100 +arc: B3 E1_H02W0301 +arc: B6 H02W0301 +arc: C0 S1_V02N0401 +arc: C3 H02W0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D3 H02E0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C39:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A5 H02E0501 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B5 H00L0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1110110001001100 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110110001001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C40:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A6 V02N0101 +arc: D6 E1_H02W0201 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: N3_V06N0303 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000001010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R64C41:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 F5 +arc: A1 V02N0501 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: C3 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: V00T0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C42:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 V00T0000 +arc: A6 N1_V02S0301 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 F6 +arc: C2 N1_V01S0100 +arc: C3 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R64C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A6 E1_H02W0501 +arc: B1 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C6 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 N1_V02S0601 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEB.K0.INIT 0010000000000000 +word: SLICEA.K1.INIT 1110110000000000 +word: SLICEB.K1.INIT 0010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: A3 V00T0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 V00T0000 +arc: B3 V02S0301 +arc: B5 F1 +arc: B7 N1_V01S0000 +arc: C1 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02E0401 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R64C45:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 + +.tile R64C46:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V02N0101 +arc: B5 H02W0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R64C47:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: A3 N1_V02S0701 +arc: B3 H00L0000 +arc: C0 H00L0000 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C48:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C49:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: B4 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 N1_V02S0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0203 F4 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R64C50:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0701 N1_V02S0701 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 H02W0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E1_H02W0301 +arc: A7 S1_V02N0301 +arc: C6 E1_H01E0101 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0303 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0303 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R64C51:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A5 H02E0701 +arc: C7 V02S0201 +arc: D5 V02S0401 +arc: D7 V02S0601 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: S3_V06S0303 F5 +arc: V01S0100 F7 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R64C52:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02N0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: M0 H02E0601 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1011101110110001 +word: SLICEA.K1.INIT 1010101010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R64C53:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: B1 H00R0100 +arc: B3 E1_H01W0100 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111101000110011 +word: SLICEA.K1.INIT 1110111000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R64C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 E1_H02W0501 +arc: A3 V02S0501 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000111111011 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 E1_H01W0100 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: A1 V02S0501 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C57:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: A2 H02W0501 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B3 V02S0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C58:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0501 +arc: A4 E1_H01W0000 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R64C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: A2 N1_V02S0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 N1_V02S0701 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: V00B0000 Q4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 0011011100000100 +word: SLICEA.K1.INIT 0001000111110000 +word: SLICEB.K0.INIT 0101011100000010 +word: SLICEB.K1.INIT 0000001110101010 +word: SLICEC.K0.INIT 0000001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C61:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A4 V02S0101 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R64C62:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 F5 +arc: A3 V02S0501 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D5 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000011100000100 +word: SLICEC.K1.INIT 0000010110101111 +word: SLICEA.K1.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R64C63:PLC2 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: B0 H01W0100 +arc: B2 V02S0301 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R64C64:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V06S0303 + +.tile R64C65:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V01N0001 + +.tile R64C66:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 Q5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C67:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0601 +arc: W3_H06W0103 E1_H02W0101 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0501 F5 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C68:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C69:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V00B0000 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C70:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B4 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C71:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00R0000 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A7 Q7 +arc: B0 V02S0301 +arc: B6 V01S0000 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q6 +arc: V00B0000 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q6 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R64C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V01N0001 +arc: A0 H01E0001 +arc: A3 E1_H02W0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V00T0000 +arc: A5 H02E0701 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D5 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M4 W1_H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010110111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C74:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A5 N1_V01S0100 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 F5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C76:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0701 V02S0701 +arc: A4 V02N0101 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C77:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C78:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C79:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0201 H01E0001 +arc: A0 H00L0000 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C3 H00L0000 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0011001100110011 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C80:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R64C81:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R64C82:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 + +.tile R64C83:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: A3 E1_H02W0501 +arc: A5 V02N0101 +arc: A7 E1_H02W0701 +arc: B3 N1_V02S0101 +arc: B5 V02S0701 +arc: B7 V02S0501 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 V02N0201 +arc: D3 S1_V02N0001 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001111110111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011101011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C84:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: B1 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: D0 V02S0001 +arc: D5 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C85:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R64C86:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C87:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R64C88:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V00B0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R64C89:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 V02N0501 +arc: B6 W1_H02E0301 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q7 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0303 F5 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0010111101111111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0100000001110000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1101110110001000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C90:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0203 H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0303 E3_H06W0203 + +.tile R64C91:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: V00B0000 H02W0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 N1_V02S0701 +arc: C6 V02S0201 +arc: D3 V00T0100 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R64C92:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: D0 V02N0001 +arc: D2 V02N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0011010111111111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011010100000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R64C93:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A6 W1_H02E0501 +arc: B0 V02S0301 +arc: B2 S1_V02N0101 +arc: B4 V02S0501 +arc: B6 W1_H02E0301 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0011010111111111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101001100000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100101011001010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1011101110001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C94:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: B1 H02W0101 +arc: B5 H02W0101 +arc: B7 H02W0101 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: S1_V02S0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C95:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: C7 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C96:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C97:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B4 H01E0101 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N3_V06N0003 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R64C98:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: C3 N1_V02S0401 +arc: D2 V00T0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R64C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C100:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V02N0101 + +.tile R65C101:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R65C102:PLC2 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R65C103:PLC2 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 + +.tile R65C104:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 + +.tile R65C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C107:PLC2 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C108:PLC2 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C110:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: C3 H02E0601 +arc: D3 H02E0001 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R65C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C113:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C114:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C115:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C116:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C117:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C14:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C15:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R65C20:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C21:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C23:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C26:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C29:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 + +.tile R65C30:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H02W0101 +arc: A3 H00L0100 +arc: B1 F3 +arc: B3 E1_H01W0100 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: D1 S1_V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 F1 +arc: E1_H02E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1010110000000000 +word: SLICEA.K1.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R65C31:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0100 H02E0101 +arc: A0 F7 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K1.INIT 0100010001010100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C32:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C1 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEB.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C33:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C34:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 F5 +arc: A5 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B1 H02W0301 +arc: B2 H02E0101 +arc: B5 H01E0101 +arc: B7 H02W0101 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 F3 +arc: V01S0000 Q2 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C35:PLC2 +arc: E1_H02E0501 V06S0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 F4 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F6 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEB.K0.INIT 0000110000001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C36:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00B0000 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C37:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111111110001000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010101011111100 +word: SLICEA.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R65C38:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0103 N3_V06S0103 +arc: A2 V00T0000 +arc: A4 H02W0701 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C39:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E1_H01W0000 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 F4 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K1.INIT 0101000101010000 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEC.K1.INIT 0100010001000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R65C3:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C40:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A3 H02W0701 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B3 E1_H01W0100 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V02S0601 +arc: C5 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: V00B0000 Q4 +arc: V00B0100 F5 +arc: V01S0000 F2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110101011101010 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R65C41:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A3 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V02S0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C42:PLC2 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 E1_H02W0301 +arc: C0 F6 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C43:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 + +.tile R65C44:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile R65C45:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: C7 V01N0101 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R65C46:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0701 +arc: A4 F5 +arc: A5 V02N0301 +arc: A7 H02W0701 +arc: B5 S1_V02N0501 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K0.INIT 1111101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R65C47:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: A5 V02N0301 +arc: C5 H02E0601 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0000010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R65C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 V06S0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 W1_H02E0601 +arc: A2 V02S0701 +arc: A4 H02E0501 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 H02W0201 +arc: D4 N1_V02S0601 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 F0 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0101000101010101 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R65C49:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H02W0501 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H02W0101 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 V02S0201 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 1010000010101010 +word: SLICEA.K0.INIT 0000111000001100 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1101000011010101 +word: SLICEC.K1.INIT 1100111000000000 +word: SLICED.K1.INIT 0000000010001111 +word: SLICED.K0.INIT 1010001010101010 +word: SLICEC.K0.INIT 0000000010101011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C50:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 E1_H01W0000 +arc: A6 V02N0301 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B4 H02W0301 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0101001101010000 +word: SLICEB.K0.INIT 1101000001010000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000010100001101 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0011000100000001 +word: SLICED.K1.INIT 0011001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R65C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A2 H02E0501 +arc: A4 F7 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 F6 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F7 +arc: V00B0100 F5 +arc: V01S0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1000101010001000 +word: SLICEA.K0.INIT 0100000011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0010000000100010 +word: SLICED.K0.INIT 1010101010001010 +word: SLICEB.K0.INIT 0001000001010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C52:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0203 E3_H06W0203 +arc: C1 E1_H02W0401 +arc: C6 V01N0101 +arc: D1 V00B0100 +arc: D6 H02E0001 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +arc: S3_V06S0103 F1 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R65C53:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 V02S0701 +arc: B0 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0101011100000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C54:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101000001111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C55:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02W0701 +arc: A2 N1_V02S0701 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111001111110101 +word: SLICEA.K1.INIT 0001000001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R65C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A6 N1_V01S0100 +arc: A7 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000110001000100 +word: SLICED.K0.INIT 0000100001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C57:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 0011000010100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K1.INIT 0100000001110000 +word: SLICEC.K0.INIT 0101000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C58:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 N3_V06S0203 +arc: A2 S1_V02N0701 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 0011000001010000 +word: SLICED.K0.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C59:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A5 N1_V01S0100 +arc: B2 V02N0301 +arc: B5 H00L0000 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C5 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEB.K0.INIT 0011010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C60:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0001000010110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K1.INIT 0001000010110000 +word: SLICED.K0.INIT 0010000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C61:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: A1 H02E0501 +arc: A4 V00B0000 +arc: B4 V00B0100 +arc: C1 H02W0601 +arc: C4 H02W0401 +arc: D1 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C62:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: B7 N1_V01S0000 +arc: C7 V00T0000 +arc: D7 S1_V02N0601 +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R65C63:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile R65C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E1_H02W0201 + +.tile R65C65:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R65C66:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: A4 N1_V02S0101 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D4 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C67:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 V02N0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0000 F4 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0601 Q6 +arc: S1_V02S0001 Q0 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q2 +arc: V01S0000 Q4 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C70:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 N1_V02S0501 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 W1_H02E0501 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0100011101110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R65C71:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A5 H02W0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C72:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06N0203 +arc: A1 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: A7 F5 +arc: B1 W1_H02E0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0100011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C73:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0701 +arc: B7 V00B0100 +arc: C0 V02S0401 +arc: C1 S1_V02N0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F1 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C74:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0201 +arc: D5 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R65C75:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0501 +arc: A5 S1_V02N0101 +arc: A7 N1_V01S0100 +arc: B0 V00T0000 +arc: B2 N1_V02S0101 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C2 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C76:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C77:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R65C78:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C79:PLC2 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C80:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010110011111111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C81:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R65C82:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0003 + +.tile R65C83:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 + +.tile R65C84:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 N3_V06S0303 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 1111010011110111 +word: SLICEB.K1.INIT 0011010000110111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C85:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R65C86:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 N1_V01S0100 +arc: B5 N1_V01S0000 +arc: C4 N1_V02S0201 +arc: C6 N1_V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C87:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 H02E0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: M2 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C88:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00L0100 +arc: M2 W1_H02E0601 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R65C89:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B6 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0100 F0 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000000001110100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R65C90:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 N1_V02S0701 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A7 Q7 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0301 +arc: B6 V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 F4 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000111110000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R65C91:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B2 H02E0301 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D3 H02E0001 +arc: E1_H02E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: N1_V01N0101 F1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R65C92:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 N1_V02S0101 +arc: C5 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C93:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C4 V02S0001 +arc: C6 V02S0001 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 W1_H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C94:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06W0203 +arc: W3_H06W0003 V06N0003 + +.tile R65C95:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: B2 H02W0301 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D3 V02S0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 N1_V01N0001 +arc: M3 E1_H02W0201 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C96:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 + +.tile R65C97:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00B0000 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C98:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: A1 H00L0100 +arc: A5 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: E1_H01E0101 Q5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C99:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: B0 V00B0000 +arc: B6 H02W0101 +arc: C0 H02E0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1100000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C100:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0701 V06N0203 + +.tile R66C103:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C105:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R66C106:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C108:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C109:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R66C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R66C112:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C20:PLC2 +arc: N3_V06N0303 E3_H06W0303 + +.tile R66C25:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R66C26:PLC2 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R66C28:PLC2 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R66C29:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0401 H06W0203 + +.tile R66C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02S0101 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 V02N0001 +arc: D5 V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C31:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B6 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 F6 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R66C32:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 V01N0001 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C1 F6 +arc: C2 H00L0100 +arc: C3 F4 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 E1_H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 F7 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0601 Q4 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R66C33:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 E1_H01W0000 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0301 Q1 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C34:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 F7 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A7 H00L0000 +arc: B4 H02E0101 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 F4 +arc: C4 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C35:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: A7 N1_V01S0100 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 H01E0101 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0100 F7 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1011101111111111 +word: SLICEA.K0.INIT 1111111111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R66C36:PLC2 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0103 H06E0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 N1_V02S0501 +arc: A5 V02S0101 +arc: B0 V02N0301 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B6 N1_V01S0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: LSR0 H02E0501 +arc: M3 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C37:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0303 +arc: B3 E1_H01W0100 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0201 +arc: E1_H01E0101 Q7 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R66C38:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A1 E1_H02W0501 +arc: A3 S1_V02N0701 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F1 +arc: V00T0000 Q0 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 0101111111001100 +word: SLICEA.K1.INIT 1100101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R66C39:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: A0 H01E0001 +arc: A6 N1_V01N0101 +arc: B6 H02E0101 +arc: C0 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 0101110000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C40:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02N0301 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 V00B0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R66C41:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: A6 V02N0301 +arc: B6 E1_H02W0101 +arc: C6 V02N0001 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R66C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02S0301 +arc: W3_H06W0303 E3_H06W0303 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0001 F2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B5 E1_H02W0101 +arc: C2 H02W0401 +arc: C5 E1_H02W0401 +arc: D2 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R66C44:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: A0 H00L0000 +arc: A3 F7 +arc: A4 F5 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0001010101010101 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1100000011101010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R66C45:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H02W0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A6 H00R0000 +arc: B0 H02E0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1000100000001000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000100010001000 +word: SLICED.K0.INIT 0010001000101010 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEC.K1.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R66C46:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 F5 +arc: B1 V02S0101 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F0 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R66C47:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 S1_V02N0701 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D1 H02W0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F3 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0001000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000001000000010 +word: SLICEC.K1.INIT 0000010100000101 +word: SLICEB.K0.INIT 0011000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R66C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 V06N0303 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: S1_V02S0001 F0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 0101000001010101 +word: SLICED.K0.INIT 0000110000001000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 0001001100110011 +word: SLICEB.K0.INIT 0011000001110000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000110100000000 +word: SLICEC.K0.INIT 1101010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R66C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: A0 H02E0701 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B4 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 H01E0101 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 H01E0001 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0100000000000000 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICED.K1.INIT 0011001100100000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICED.K0.INIT 1100100010001000 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R66C50:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0501 +arc: A1 F5 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B3 V02N0101 +arc: B6 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 S1_V02N0601 +arc: C3 F6 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F3 +arc: V00B0100 F7 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0001001100010001 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0011000100110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R66C51:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V06S0303 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V02S0501 +arc: A4 H02W0701 +arc: A5 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 W1_H02E0301 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 H02W0601 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0011001000110000 +word: SLICEB.K0.INIT 0000101000001111 +word: SLICEC.K0.INIT 1010000010110000 +word: SLICEB.K1.INIT 0000100010101010 +word: SLICED.K1.INIT 0101010101010100 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R66C52:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A4 S1_V02N0101 +arc: A6 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D4 H02W0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0011011100000000 +word: SLICEB.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010000011100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R66C53:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 F5 +arc: A1 F5 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: C1 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C7 F4 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 0011001011111010 +word: SLICEB.K0.INIT 0111000000000000 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K1.INIT 0000010100000000 +word: SLICEB.K1.INIT 0010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R66C54:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: B0 V02S0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K1.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R66C55:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: A3 V02S0501 +arc: B0 N1_V02S0101 +arc: B3 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C56:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: B0 H00R0100 +arc: B2 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C2 S1_V02N0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 0101011100000010 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A5 E1_H01W0000 +arc: B0 V00B0000 +arc: B3 S1_V02N0101 +arc: B5 V02S0501 +arc: C0 H02W0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F3 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R66C58:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02W0701 +arc: A6 V02N0101 +arc: B0 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: V01S0000 Q6 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C59:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: A3 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F3 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C60:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: A5 Q5 +arc: B0 E1_H02W0301 +arc: B4 H02W0101 +arc: C4 Q4 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 Q5 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C61:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: A2 V02N0701 +arc: B0 V00T0000 +arc: B3 V02N0101 +arc: B7 E1_H02W0301 +arc: C7 E1_H01E0101 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: V01S0000 F3 +word: SLICED.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R66C62:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 W1_H02E0701 +arc: B1 Q1 +arc: B6 S1_V02N0501 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C63:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V02S0501 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C64:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R66C65:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: B0 H01W0100 +arc: B6 H02W0101 +arc: C0 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R66C66:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: B3 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F3 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R66C67:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C7 V00B0100 +arc: D0 V02N0001 +arc: D2 N1_V02S0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0003 F0 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C68:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 V06S0003 +arc: A1 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 W1_H02E0101 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 V02N0101 +arc: A7 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C1 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D1 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D5 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M2 W1_H02E0601 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R66C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001110100111111 +word: SLICED.K0.INIT 0011001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C71:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0101 +arc: A7 V02S0101 +arc: B1 V00B0000 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C3 V02N0601 +arc: C5 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D5 W1_H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C72:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06S0303 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 N1_V01S0000 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R66C73:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A5 N1_V02S0101 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V02S0501 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C74:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A6 V02S0301 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B2 V02S0101 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C75:PLC2 +arc: E1_H02E0101 V01N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B7 N1_V02S0701 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C76:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0000 H02E0001 +arc: A0 V02S0501 +arc: A5 Q5 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B1 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: C4 V00T0000 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C78:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B4 W1_H02E0101 +arc: B5 V01S0000 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 0000010111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R66C79:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 N1_V02S0401 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0701 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B6 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C80:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: B1 V02S0101 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000001111110011 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C81:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 N1_V02S0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R66C82:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1101000011110000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0001000000000000 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 1101000011110000 +word: SLICED.K1.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R66C83:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 N1_V02S0601 + +.tile R66C84:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H06W0203 +arc: W1_H02W0401 S1_V02N0401 + +.tile R66C85:PLC2 +arc: E3_H06E0003 V06N0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0303 V06N0303 +arc: A3 V00T0000 +arc: B3 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R66C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 V06N0003 + +.tile R66C87:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0301 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C3 N1_V01S0100 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C88:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R66C89:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V06S0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R66C90:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: A2 H00L0100 +arc: A5 Q5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 H06W0003 + +.tile R66C92:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: V00B0100 H02W0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: B0 W1_H02E0101 +arc: B1 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C93:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000001101011111 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 1111001101011111 +word: SLICED.K1.INIT 1111000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R66C94:PLC2 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A5 W1_H02E0501 +arc: C0 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 S1_V02N0601 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C95:PLC2 +arc: H00R0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A4 H02E0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H02E0301 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C96:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 + +.tile R66C97:PLC2 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 + +.tile R66C98:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0103 H06E0103 + +.tile R66C99:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile R67C100:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R67C101:PLC2 +arc: W1_H02W0001 N3_V06S0003 + +.tile R67C103:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R67C28:PLC2 +arc: S1_V02S0701 H02W0701 + +.tile R67C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0701 E3_H06W0203 + +.tile R67C30:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile R67C31:PLC2 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 W1_H02E0401 + +.tile R67C32:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C33:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: B1 E1_H01W0100 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: F0 F5A_SLICE +arc: LSR0 E1_H02W0501 +arc: M0 E1_H02W0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K1.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R67C34:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 H02W0101 +arc: C0 F6 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C35:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 + +.tile R67C36:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0401 N3_V06S0203 + +.tile R67C37:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: A7 N1_V01N0101 +arc: B7 N1_V02S0501 +arc: C7 S1_V02N0001 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 0101110000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C38:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B3 V02S0101 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C39:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H01E0001 +arc: B0 H01W0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C40:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 + +.tile R67C41:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0003 +arc: C1 H00L0000 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F1 +arc: N3_V06N0103 F1 +arc: S3_V06S0103 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R67C42:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: A0 H00L0000 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 F3 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: V01S0000 F3 +arc: W1_H02W0101 F3 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000011111010 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R67C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 H00L0100 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0701 F7 +arc: V00T0100 F1 +arc: V01S0000 F7 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010101010101 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEA.K0.INIT 1100111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C44:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 V06N0003 +arc: A2 V01N0101 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0100000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000001000001010 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R67C45:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 S1_V02N0501 +arc: A5 H02W0501 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 V00B0100 +arc: C7 E1_H02W0601 +arc: D0 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: N1_V02N0201 F2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0100000000000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEB.K0.INIT 0011001100111111 +word: SLICEB.K1.INIT 0001000100010011 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111111000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C46:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0701 +arc: A3 H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: N1_V01N0001 F6 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0100 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEC.K1.INIT 0000000010100000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICED.K0.INIT 1010101000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000010001000 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R67C47:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 V01N0001 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B2 F3 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: C1 V02S0401 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 0000000000000101 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R67C48:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F7 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C6 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D6 E1_H02W0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F0 +arc: S3_V06S0303 F6 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0100010001000100 +word: SLICED.K0.INIT 0000000010101011 +word: SLICEA.K0.INIT 0000100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R67C49:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A7 H02E0701 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N3_V06N0303 F6 +arc: V01S0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R67C50:PLC2 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: N3_V06N0103 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R67C51:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 F7 +arc: A3 H01E0001 +arc: A5 N1_V02S0301 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 F3 +arc: C0 H00L0000 +arc: C3 V02N0401 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: W1_H02W0001 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K1.INIT 0000101000001011 +word: SLICED.K0.INIT 1111111001010100 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 0111000011110000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S3_V06S0303 H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: C0 E1_H02W0401 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 F0 +arc: W1_H02W0001 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R67C53:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: A0 H02W0501 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A7 H02W0501 +arc: B1 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C4 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R67C54:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B1 N1_V02S0101 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: H00R0000 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C55:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 V02S0501 +arc: B0 V00B0000 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: C0 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R67C56:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 F5 +arc: A2 V01N0101 +arc: A3 F5 +arc: A5 H02W0701 +arc: B1 H02W0101 +arc: B3 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 V01S0100 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 F2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1011101110001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R67C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A5 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: C1 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R67C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: B3 H00L0000 +arc: B5 E1_H02W0301 +arc: C0 H02E0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R67C59:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0301 +arc: B0 F1 +arc: B5 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 H02E0501 +arc: B2 V02N0101 +arc: B6 S1_V02N0501 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M0 H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000111100110011 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C61:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02E0201 +arc: E1_H01E0101 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C62:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: B0 V00T0000 +arc: B3 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F6 +arc: W1_H02W0401 F4 +word: SLICED.K0.INIT 0011000000111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R67C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A5 N1_V02S0301 +arc: B3 H01W0100 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R67C64:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R67C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0100 N1_V02S0501 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C66:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C67:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R67C68:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: A2 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V02S0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R67C69:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 V00T0100 +arc: B0 V02S0301 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C5 V02N0201 +arc: D0 V02S0001 +arc: D5 V02N0601 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0011010100111111 +word: SLICEC.K1.INIT 0101000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R67C70:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 V00T0000 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B3 V02N0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 F3 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 1100010010000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C71:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 E1_H02W0101 +arc: B2 F3 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0601 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: D0 V02S0201 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0100011101110111 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C72:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B5 V02S0701 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0401 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F3 +arc: S3_V06S0303 F5 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R67C73:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A2 V02S0501 +arc: A4 H02E0701 +arc: A5 N1_V02S0101 +arc: A6 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C74:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 V06S0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R67C75:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 Q7 +arc: S3_V06S0103 Q2 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H00L0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100001101000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R67C77:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 N1_V02S0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A3 H01E0001 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0101 +arc: B6 H02E0101 +arc: C1 E1_H02W0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q2 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C78:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 H02E0501 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 H02E0601 +arc: C5 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R67C79:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A5 Q5 +arc: A6 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: V00B0100 Q5 +arc: V00T0000 F2 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R67C80:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 H01E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: E1_H02E0001 F0 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEA.K1.INIT 1111101100111011 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1111011110110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C81:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 N1_V02S0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1011000011110000 +word: SLICEB.K1.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C82:PLC2 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0100 H02E0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H02W0001 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 1101000011110000 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 1101000011110000 +word: SLICEA.K1.INIT 1011000011110000 +word: SLICEB.K0.INIT 0001000000000000 +word: SLICEB.K1.INIT 1011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C83:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V00T0000 +arc: B5 H00L0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R67C84:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C85:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 W3_H06E0303 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: C2 H00L0000 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C86:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0601 V02S0601 + +.tile R67C87:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0701 +arc: A5 H02W0701 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 V02S0301 +arc: B4 V02S0501 +arc: B6 H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R67C88:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H02E0701 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B5 H02W0301 +arc: C3 E1_H02W0601 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C89:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 E1_H02W0001 +arc: M2 W1_H02E0601 +arc: M3 H00R0100 +arc: M4 W1_H02E0401 +arc: M5 E1_H02W0001 +arc: M6 W1_H02E0401 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 1010011111110111 +word: SLICED.K1.INIT 0001010100011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C90:PLC2 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 V02S0701 +arc: A4 V02S0101 +arc: A5 N1_V01S0100 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: C1 N1_V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R67C91:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: B0 H01W0100 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R67C92:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: V00B0100 V02S0301 +arc: A0 H02E0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010110010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C93:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: W3_H06W0303 V06S0303 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICED.K0.INIT 1111001101011111 +word: SLICED.K1.INIT 0000001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C94:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 H06E0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: B0 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C95:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 V06S0003 +arc: A0 H02E0501 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C96:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0101 V02N0101 + +.tile R67C97:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 + +.tile R67C98:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S1_V02N0201 + +.tile R67C99:PLC2 +arc: N1_V02N0001 E1_H02W0001 + +.tile R68C100:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R68C102:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R68C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C106:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C109:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R68C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C112:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R68C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R68C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C28:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: B4 V02S0701 +arc: C0 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C29:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 H01E0001 +arc: S1_V02S0201 H01E0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 V02N0101 +arc: B2 V02N0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R68C30:PLC2 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 V02N0701 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C31:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0401 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C32:PLC2 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: V00T0000 V02S0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 0000001000000000 +word: SLICEC.K1.INIT 0101010100010101 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1101111110001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C33:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: A0 H01E0001 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: B0 V02S0101 +arc: B1 F3 +arc: B2 V01N0001 +arc: B3 V02S0101 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 W1_H02E0401 +arc: C4 H01E0001 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 0101010100010101 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICED.K0.INIT 0000000011110111 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEA.K1.INIT 0010001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C34:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 H01W0100 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0000000011011111 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICED.K0.INIT 0000000001000000 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K1.INIT 1011101111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C35:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E1_H01W0000 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 + +.tile R68C36:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 V02S0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D3 H02W0001 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1111101111111011 +word: SLICEB.K1.INIT 1100100011111011 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100000011110011 +word: SLICEA.K0.INIT 1111001111111111 +word: SLICEA.K1.INIT 1100010011110111 +word: SLICED.K1.INIT 0000000011000000 +word: SLICED.K0.INIT 0000111100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R68C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00L0000 V02N0201 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00R0100 Q7 +arc: M0 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V00T0000 F2 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 Q7 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111110111000 +word: SLICEA.K1.INIT 1100111110001000 +word: SLICEB.K0.INIT 0000000001010111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C38:PLC2 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0201 N1_V01S0000 + +.tile R68C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 + +.tile R68C40:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V01S0000 S3_V06N0103 +arc: A0 H02E0701 +arc: A4 F5 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F1 +arc: S1_V02S0201 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000101010001000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R68C41:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 V01N0001 +arc: A2 V01N0101 +arc: A7 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C7 H02W0601 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0301 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V01S0100 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R68C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 F7 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 F1 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H01E0001 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 H01E0101 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V00B0100 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICED.K1.INIT 0000001100000000 +word: SLICEC.K0.INIT 0000000100000101 +word: SLICEB.K0.INIT 1111111111111100 +word: SLICEB.K1.INIT 1111110111111100 +word: SLICEA.K0.INIT 1111111100001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R68C43:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A6 V02S0301 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000100000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0111111100000000 +word: SLICED.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R68C44:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 N1_V01S0000 +arc: A1 H02W0701 +arc: A2 E1_H02W0701 +arc: A5 V02N0101 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B1 V02S0301 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 V02N0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V01S0100 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000001110000 +word: SLICEC.K1.INIT 0000001000100010 +word: SLICEB.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 0111111100000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R68C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 V02S0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02E0701 +arc: A1 V02S0501 +arc: A3 V01N0101 +arc: A5 F7 +arc: B0 V01N0001 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: V01S0000 F1 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001111100111111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0011111111111111 +word: SLICEC.K1.INIT 0001010101010101 +word: SLICEA.K0.INIT 1111001111110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 H02W0501 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02S0001 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: W1_H02W0301 F1 +word: SLICED.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 0101000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R68C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H01E0001 +arc: A1 H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H01E0001 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 0001000001010000 +word: SLICED.K1.INIT 0000000011000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010000010100000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 0001001100110011 +word: SLICEA.K0.INIT 0010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R68C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A3 H02W0701 +arc: A6 F7 +arc: B0 H00R0100 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: C0 H02W0401 +arc: C2 F4 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: N1_V01N0001 F5 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R68C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H02W0501 +arc: B2 H02W0301 +arc: C2 S1_V02N0601 +arc: D2 V02N0201 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEB.K0.INIT 0000000000011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C50:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0301 N1_V02S0301 + +.tile R68C51:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E3_H06W0203 + +.tile R68C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 V06S0103 + +.tile R68C53:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 N1_V01S0100 +arc: B3 V02S0301 +arc: B5 N1_V01S0000 +arc: B7 V02S0501 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q1 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C54:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 V02N0301 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 V01N0001 +arc: B3 F1 +arc: B4 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +word: SLICEA.K1.INIT 0011000000111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R68C55:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R68C56:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02W0201 +arc: D5 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q7 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C57:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 V01N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C3 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M2 W1_H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0203 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R68C58:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 V02N0501 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R68C59:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 N1_V02S0101 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 H02E0301 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0101010100001111 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R68C60:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B6 V00B0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C61:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0011101000111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R68C62:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 V00B0000 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B6 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C3 H00R0100 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R68C63:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A4 V02N0301 +arc: A6 N1_V02S0101 +arc: B1 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0011001101010101 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEB.K1.INIT 0011001100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R68C64:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0701 +arc: B5 N1_V02S0501 +arc: C2 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D5 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 Q6 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 0101010100001111 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C65:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B2 V02S0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C2 V02N0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +arc: W3_H06W0303 F5 +word: SLICEB.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0100000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R68C66:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A2 V00T0000 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C2 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0103 F2 +arc: V01S0000 F7 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C68:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: V00B0100 W1_H02E0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C69:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C70:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C71:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: D0 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F2 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEC.K0.INIT 0000000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R68C72:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C4 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +arc: N1_V02N0301 F1 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0011000000000000 +word: SLICEA.K0.INIT 0000000000110000 +word: SLICEC.K0.INIT 0000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R68C73:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B5 V02N0701 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M7 E1_H01W0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0303 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 Q7 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 0000101000000000 +word: SLICEA.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 1100110011001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R68C74:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 V02S0101 +arc: B0 H00R0100 +arc: B1 V02S0301 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 F1 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1110110000000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C75:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A3 H00L0100 +arc: B0 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B4 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C76:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N1_V01S0000 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A4 N1_V01N0101 +arc: A5 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q1 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C78:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R68C79:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: B1 W1_H02E0301 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0011001100110011 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R68C80:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: V00B0100 H02W0701 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C81:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R68C82:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 V02N0101 +arc: B0 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B6 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C83:PLC2 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0101 H06W0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C84:PLC2 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C86:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 H01E0001 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: V01S0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R68C87:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R68C88:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00R0100 +arc: M2 W1_H02E0601 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C89:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: B0 V02N0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C90:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 V06N0103 +arc: A0 E1_H01E0001 +arc: A4 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q3 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1000100011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C91:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0201 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V06N0203 +arc: A0 H01E0001 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C92:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V06N0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: B0 N1_V02S0101 +arc: C2 N1_V01S0100 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D3 N1_V01S0000 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C93:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C94:PLC2 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C95:PLC2 +arc: N1_V02N0201 H02E0201 +arc: W1_H02W0101 V06N0103 + +.tile R68C96:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 S3_V06N0003 + +.tile R68C97:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 + +.tile R68C98:PLC2 +arc: N1_V02N0501 H02E0501 + +.tile R68C99:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R69C100:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R69C101:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R69C103:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R69C104:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C105:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R69C106:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R69C107:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C108:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R69C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R69C111:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R69C28:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C29:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: V00B0000 V02S0201 +arc: A2 V02N0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q7 +arc: H01W0000 Q6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C2:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C30:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N3_V06N0003 E3_H06W0003 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C31:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: A0 F5 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 N1_V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICEB.K0.INIT 0011001100010011 +word: SLICEC.K1.INIT 1000001000000000 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R69C32:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0100 H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 F3 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0011001100010011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1010111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C33:PLC2 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C1 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEB.K0.INIT 0101010100010101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0101000101010101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C34:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 N1_V01S0100 +arc: B4 N1_V01S0000 +arc: C4 E1_H02W0401 +arc: D4 V02S0401 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R69C35:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile R69C36:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0701 +arc: A2 H02E0701 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: C0 V02N0401 +arc: C2 V02S0601 +arc: C3 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +word: SLICEA.K0.INIT 1101110110000000 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1101100011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C37:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: A1 H01E0001 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B6 V02S0701 +arc: B7 H01E0101 +arc: C3 F6 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 F7 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0000110000000011 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110001010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C38:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0100 V02S0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: A1 H01E0001 +arc: A4 H02E0501 +arc: B1 V02S0101 +arc: B4 V02S0701 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D4 H00L0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0111011101000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C39:PLC2 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B2 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 F2 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R69C40:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 1111000011111010 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C41:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 H01E0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C4 V02S0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1111010111110000 +word: SLICEA.K1.INIT 1100110011111100 +word: SLICEB.K0.INIT 1111000011111100 +word: SLICEB.K1.INIT 0000000001000100 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C42:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 H00L0100 +arc: A3 H01E0001 +arc: A5 V02S0101 +arc: A6 F7 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C1 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K1.INIT 0011001100110001 +word: SLICEB.K0.INIT 0000000011001111 +word: SLICEC.K0.INIT 0000110000001111 +word: SLICEC.K1.INIT 1010101000000000 +word: SLICED.K1.INIT 0000000010001000 +word: SLICED.K0.INIT 0000010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R69C43:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 H01E0101 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 F3 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0000000000110000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0011000100110011 +word: SLICED.K0.INIT 1000100000001000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEA.K0.INIT 0111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C44:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0100 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A7 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: C0 F6 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D1 N1_V02S0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 0000000010100000 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 1010000010100000 +word: SLICEA.K0.INIT 0000000000000100 +word: SLICEC.K0.INIT 0000110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R69C45:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V00T0000 +arc: B1 H02E0301 +arc: B2 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: C0 V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 F0 +arc: D5 F2 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V00T0000 F0 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000010100000101 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0001000100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000101000000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R69C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B5 V02N0501 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F1 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F7 +arc: V01S0100 F3 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 0000001000000010 +word: SLICED.K1.INIT 0100000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEB.K0.INIT 0000001100000000 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R69C47:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0100 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D3 H01E0101 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V02N0501 F7 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V00B0100 F5 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 0011000000000000 +word: SLICED.K0.INIT 0100010000000000 +word: SLICEA.K0.INIT 0000000000000010 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R69C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H01E0001 +arc: A4 H02W0501 +arc: A7 E1_H01W0000 +arc: B1 V02S0101 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C1 N1_V01S0100 +arc: C4 N1_V02S0001 +arc: D1 H00R0000 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F4 +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F6 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0010000000110000 +word: SLICED.K1.INIT 1000100010001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R69C49:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 H01E0001 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A4 S1_V02N0101 +arc: A5 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 V00B0100 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: D1 H02E0001 +arc: D2 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F2 +arc: V01S0000 F0 +arc: V01S0100 F0 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1010000000100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEC.K0.INIT 0001000100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R69C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: H01W0000 E3_H06W0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R69C51:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R69C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: A4 H02W0701 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M5 H02W0001 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R69C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A7 E1_H01W0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R69C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 V06S0203 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B6 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 N1_V02S0601 +arc: D6 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M3 H00L0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0401 F4 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 F6 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B6 H02E0301 +arc: C1 H00L0100 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 F5 +arc: V00T0000 Q2 +arc: V01S0000 Q7 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0101000001011111 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R69C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 N1_V02S0701 +arc: A2 V02S0701 +arc: A5 V02N0301 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 Q7 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 0000000000010000 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R69C57:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q6 +arc: S1_V02S0401 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0301 Q3 +word: SLICED.K0.INIT 0011001000000010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R69C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D5 N1_V02S0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 Q6 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C59:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A5 V00T0000 +arc: B1 V02N0301 +arc: B3 S1_V02N0101 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 H01E0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0000110011111100 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R69C60:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C5 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R69C61:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: A1 E1_H02W0501 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q6 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 H02E0301 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: S3_V06S0303 Q5 +arc: V00T0000 Q0 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 0011001100001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C62:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0701 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +word: SLICED.K0.INIT 0000111100110011 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R69C63:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00B0000 +arc: A5 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0101010100001111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B6 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C3 V02S0601 +arc: C5 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R69C65:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0501 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R69C66:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: B0 F1 +arc: B3 V02S0301 +arc: B5 H02W0301 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F6 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R69C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000011100000 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C68:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02N0601 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R69C69:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 + +.tile R69C70:PLC2 +arc: E1_H02E0201 V02S0201 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 H00L0000 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C71:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: B0 V00T0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111000000001111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 1100110000001111 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R69C72:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06S0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C73:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile R69C74:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 V00T0000 +arc: B0 H00R0100 +arc: B2 F1 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V01S0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: N1_V02N0701 F5 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000010100000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C75:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A5 Q5 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: W1_H02W0401 Q6 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C76:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: V00B0000 H02W0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0103 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 H02E0401 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0011001100110011 +word: SLICED.K1.INIT 0011001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C77:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A3 F5 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: C0 H02E0601 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C6 V02S0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V02S0401 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1110010011111111 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C79:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: A6 H02E0501 +arc: B2 V02S0101 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C6 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D6 H02E0001 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000001000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C80:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C3 H02E0401 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 0101010101010101 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0101010101010101 +word: SLICED.K1.INIT 0011001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C81:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: B3 E1_H02W0301 +arc: B7 H01E0101 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H02E0701 F7 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0001000010110000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C82:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A6 V02S0101 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C6 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D6 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 H01E0001 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: V01S0100 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1011000011110000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 0101000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R69C83:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C7 V02N0201 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: N1_V02N0701 F7 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000011010000 +word: SLICEA.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R69C84:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1100110011000011 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C85:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R69C86:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: D0 H02E0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: N3_V06N0003 F0 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0110011000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R69C87:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W3_H06W0003 V06S0003 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: B0 E1_H02W0301 +arc: B2 V02N0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C88:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C89:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C90:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B5 W1_H02E0101 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 F2 +arc: N1_V02N0701 Q5 +arc: N3_V06N0303 Q6 +arc: S3_V06S0303 Q6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R69C92:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 S1_V02N0401 +arc: W1_H02W0301 S1_V02N0301 + +.tile R69C93:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 + +.tile R69C94:PLC2 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 H06E0103 + +.tile R69C95:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0101 S3_V06N0103 + +.tile R69C96:PLC2 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R69C97:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R69C98:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R69C99:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R6C40:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02W0401 +arc: A0 V02N0701 +arc: B0 V02N0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1101110000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C41:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C42:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: C0 N1_V02S0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C43:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A4 V02S0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 F4 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1100110001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C44:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02S0301 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H00R0100 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: C0 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0401 Q6 +arc: V00B0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C45:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 W1_H02E0701 +arc: B0 H00R0100 +arc: B2 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H00R0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F2 +arc: V01S0000 Q6 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C46:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C47:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A6 V02S0301 +arc: B0 H02E0101 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H02E0301 +arc: C0 E1_H01W0000 +arc: C2 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 Q3 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEB.K0.INIT 1100101011001010 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C48:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 V02N0401 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICED.K0.INIT 1110010011100100 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C49:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C50:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C51:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V02N0101 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: C0 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C52:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H02W0001 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R6C53:PLC2 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0401 V02N0401 + +.tile R6C54:PLC2 +arc: W1_H02W0001 W3_H06E0003 + +.tile R71C100:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C101:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R71C102:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R71C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C104:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C105:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C107:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R71C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C110:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C111:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R71C112:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C113:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C116:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C117:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R71C118:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C14:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C15:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R71C20:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C21:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C23:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C30:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 + +.tile R71C31:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0001 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0101010100010101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 1011101111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C32:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H01E0001 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B3 H02W0101 +arc: B4 F3 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICED.K0.INIT 0101010100010101 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 0010001100110011 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C33:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEB.K0.INIT 1011101111110000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICED.K0.INIT 0101010100010101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1010111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C34:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0501 +arc: A2 H01E0001 +arc: A3 V02N0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00R0100 +arc: C2 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: V00B0000 F4 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEA.K0.INIT 0011000100110011 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000101100001111 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K0.INIT 0011001100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C35:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0301 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C1 F4 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1010111111001100 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 1010111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C36:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C4 V00B0100 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: V01S0000 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEA.K0.INIT 0000000000100000 +word: SLICED.K0.INIT 0000000011011111 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 0010001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R71C37:PLC2 +arc: W1_H02W0701 V06S0203 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B6 V01S0000 +arc: C0 V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D6 H01W0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C38:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: A0 N1_V02S0701 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: A2 H01E0001 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B7 H02E0101 +arc: C2 H00L0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 V02S0201 +arc: D7 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R71C3:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C40:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: A0 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B2 F1 +arc: B3 F1 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 V01N0001 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +arc: V01S0100 F3 +word: SLICED.K1.INIT 0000111100000101 +word: SLICED.K0.INIT 0010001000101010 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0001010100000000 +word: SLICEB.K0.INIT 0011001100000011 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000000110011 +word: SLICEC.K0.INIT 1010101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R71C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 N1_V02S0201 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 0000000000001100 +word: SLICEC.K0.INIT 0000001000001010 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 0000001000110010 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEB.K1.INIT 0100111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C42:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V01N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: A4 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B3 H02E0101 +arc: B4 E1_H02W0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D0 H02E0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: N1_V02N0401 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0100110011001100 +word: SLICEC.K0.INIT 1110000000000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C43:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: A1 H02E0701 +arc: A3 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100000011111111 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0000001000000011 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 0111000000000000 +word: SLICED.K0.INIT 0000000000011111 +word: SLICEB.K0.INIT 1111110011001100 +word: SLICEB.K1.INIT 1111111111100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: A0 H01E0001 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B3 H02W0301 +arc: B5 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 0001000000110000 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R71C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A5 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 H02W0301 +arc: B5 H01E0101 +arc: C0 V02N0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: N1_V02N0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010100000000 +word: SLICEA.K1.INIT 1111110100000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 S3_V06N0003 +arc: A2 N1_V02S0701 +arc: A4 H02E0701 +arc: A7 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 H02E0601 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 N1_V02S0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02E0001 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0011000000000000 +word: SLICEC.K0.INIT 0111000011110000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000000110011 +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R71C47:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 S1_V02N0501 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B2 H02E0301 +arc: B6 F1 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 V02S0401 +arc: C2 V02N0401 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 W1_H02E0001 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEA.K0.INIT 1111111100000010 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000101000000000 +word: SLICEC.K0.INIT 0000000001010000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0111111111111111 +word: SLICEB.K0.INIT 0000000001000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R71C48:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: D0 V00T0100 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 F0 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1010101010001010 +word: SLICEA.K1.INIT 1010000011110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000101100000011 +word: SLICEC.K0.INIT 0010001000000010 +word: SLICEB.K0.INIT 0010001000000010 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R71C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: B2 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000010100000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 0111111111111111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0303 +arc: B6 W1_H02E0101 +arc: D6 H02E0001 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R71C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: A6 N1_V02S0301 +arc: B1 V02S0301 +arc: B6 F1 +arc: C1 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: D1 V01S0100 +arc: D6 S1_V02N0401 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A5 N1_V02S0301 +arc: B1 H02W0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: C1 N1_V02S0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R71C53:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 V02N0101 +arc: B3 Q3 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C5 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C54:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A5 V02S0101 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V01N0101 +arc: A2 V00B0000 +arc: A5 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 N1_V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0001 F2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R71C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 V02S0301 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0501 Q7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0000111000000010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 N1_V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R71C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0601 +arc: C5 V02S0001 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D3 V02S0001 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F6 +arc: V00B0000 F4 +arc: V01S0000 Q5 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0111000011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C59:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q1 +arc: V01S0000 F1 +arc: V01S0100 F6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R71C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A7 E1_H02W0701 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0501 Q5 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C61:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: B0 H02E0101 +arc: B2 H02E0301 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: CLK0 G_HPBX0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 V00T0000 +arc: M0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F4 +arc: V01S0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C62:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 V02N0701 +arc: A2 H02E0501 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B7 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C63:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B3 H02W0301 +arc: B4 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q3 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C64:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A6 V02N0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F1 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02W0601 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 F2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: B1 H02E0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B7 H02W0101 +arc: C4 H02E0601 +arc: C5 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: M6 V00T0100 +arc: MUXCLK2 CLK0 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0000 Q4 +word: SLICEC.K1.INIT 0000111100110011 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R71C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B3 V02S0301 +arc: B5 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 W1_H02E0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D3 N1_V02S0001 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R71C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A7 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C3 H02W0601 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0000111100110011 +word: SLICED.K1.INIT 0000101001011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1110010011100100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C68:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q5 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 0000010111110101 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C69:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 + +.tile R71C70:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 E1_H02W0701 +arc: A4 H02W0701 +arc: B0 H02E0101 +arc: B3 V02S0301 +arc: B4 N1_V02S0501 +arc: C0 H02W0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000100000101 +word: SLICEB.K1.INIT 0000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 E1_H01E0001 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R71C72:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0701 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C73:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 W1_H02E0701 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D4 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1100111100000000 +word: SLICEC.K0.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R71C74:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C75:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B0 H02W0301 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H01E0101 +arc: B6 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C76:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: B2 E1_H02W0101 +arc: C2 S1_V02N0401 +arc: D2 V02S0201 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R71C77:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0301 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: D0 V02N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R71C78:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: B1 E1_H02W0101 +arc: B7 H01E0101 +arc: C1 H02W0601 +arc: C7 V02N0001 +arc: D1 H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R71C79:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A2 H02W0501 +arc: B0 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C80:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A5 S1_V02N0301 +arc: A7 V02S0101 +arc: B1 H02E0101 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C81:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: B1 V02S0101 +arc: B6 V02S0501 +arc: C6 W1_H02E0601 +arc: D6 V01N0001 +arc: E3_H06E0303 F6 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0201 F2 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R71C82:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 + +.tile R71C83:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C84:PLC2 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R71C85:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: C2 V02N0601 +arc: D2 V02N0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 1111000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R71C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: A0 H02W0501 +arc: B0 H02E0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C87:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0501 S3_V06N0303 +arc: B5 H02W0301 +arc: C5 V02N0001 +arc: D5 H00R0100 +arc: F5 F5_SLICE +arc: N1_V02N0501 F5 +word: SLICEC.K1.INIT 1100001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R71C88:PLC2 +arc: E1_H02E0501 V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 V01N0101 + +.tile R71C89:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: A2 V02S0701 +arc: A4 H02E0501 +arc: B0 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C90:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0003 V06S0003 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R71C91:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C92:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C93:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R71C94:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: V01S0000 S3_V06N0103 + +.tile R71C95:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C96:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C97:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C98:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C99:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R72C100:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R72C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C105:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R72C106:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R72C108:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C109:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R72C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R72C112:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C115:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C28:PLC2 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 + +.tile R72C30:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R72C31:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEC.K0.INIT 0000000010111111 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000011110111 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C32:PLC2 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 V01N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K1.INIT 1100101011111010 +word: SLICEB.K0.INIT 1010110011111100 +word: SLICEB.K1.INIT 1101111111010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C33:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B2 F3 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0011000100110011 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 0010001100110011 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R72C34:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H02W0701 +arc: B3 V02S0301 +arc: C3 W1_H02E0601 +arc: D3 H02E0001 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C35:PLC2 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0701 H06W0203 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H01E0001 +arc: A1 V01N0101 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1110111000101110 +word: SLICEA.K1.INIT 1011101111110000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 0101010100010101 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1010111111001100 +word: SLICEB.K1.INIT 1111011110100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C36:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0103 H06W0103 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 H01E0101 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0501 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: V00B0000 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICEB.K1.INIT 0101000101010101 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0011001100010011 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R72C37:PLC2 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0003 E3_H06W0303 + +.tile R72C38:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: D0 V02S0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R72C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 E3_H06W0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A4 V00B0000 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B4 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C4 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 V02S0001 +arc: D4 V02N0601 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F2 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F2 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000100 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICEA.K0.INIT 0000000011110111 +word: SLICEB.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R72C40:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: A1 V02S0701 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C1 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: N1_V02N0601 F4 +arc: N3_V06N0203 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111011111111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011001100010000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R72C41:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: A1 H02E0701 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 V02N0301 +arc: B1 H00R0100 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0701 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V00B0100 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: D4 F2 +arc: D6 H01W0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011000000010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R72C42:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0701 +arc: A4 V02N0301 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 V02S0401 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F0 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1111000011010000 +word: SLICEB.K0.INIT 0011001100000011 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 F7 +arc: A1 F5 +arc: A2 F5 +arc: A6 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C3 F4 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N3_V06N0303 F6 +arc: V01S0100 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICED.K1.INIT 0000000000110011 +word: SLICEA.K0.INIT 0011000000100000 +word: SLICED.K0.INIT 0000010001000100 +word: SLICEC.K1.INIT 0000000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R72C44:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A2 V02S0701 +arc: A4 S1_V02N0101 +arc: A7 F5 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 V02S0601 +arc: C1 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0111111101001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111111110110011 +word: SLICEB.K1.INIT 1111001100110011 +word: SLICEC.K0.INIT 0101000001010000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0001000001010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C45:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: A7 H02W0501 +arc: B1 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B5 F1 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 W1_H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 Q4 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICEB.K1.INIT 0001000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICEC.K1.INIT 0101010000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1110000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A1 H00L0100 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0101 +arc: C0 W1_H02E0401 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 W1_H02E0501 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B3 H02W0101 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F2 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 0000101000000000 +word: SLICED.K0.INIT 1000100011001000 +word: SLICEB.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111000011100000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICED.K1.INIT 1010001000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C48:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 V02N0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 F6 +arc: C5 H02W0601 +arc: C7 V02S0201 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0001000011011100 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K0.INIT 1000110000001100 +word: SLICED.K1.INIT 0000010001000100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000010111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C49:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06S0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A3 W1_H02E0701 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 W1_H02E0301 +arc: B5 V02S0501 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: D0 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0011000000110011 +word: SLICEA.K0.INIT 0000110100000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEA.K1.INIT 1000000010000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R72C50:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: S3_V06S0003 H01E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: D0 H02E0201 +arc: D1 S1_V02N0201 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: M0 W1_H02E0601 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R72C51:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: D0 F2 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1100000010000000 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R72C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E3_H06W0103 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02S0701 +arc: A2 F5 +arc: A4 N1_V02S0301 +arc: A5 W1_H02E0701 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: B7 N1_V02S0701 +arc: C1 H00L0100 +arc: C2 N1_V01S0100 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D4 H02W0001 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: N1_V02N0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 F1 +arc: V00T0100 F1 +arc: V01S0000 F1 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0100000011000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 N1_V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C1 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0301 F1 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111111001100 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0501 +arc: A1 V02S0501 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R72C55:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 W1_H02E0101 +arc: C0 H00R0100 +arc: C2 F4 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q5 +arc: LSR1 H02W0301 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 V00B0000 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0701 +arc: C0 F6 +arc: C3 N1_V02S0601 +arc: C4 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V01S0100 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q7 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00B0000 F4 +arc: V01S0100 Q7 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A2 H02E0501 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: LSR0 H02E0301 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 Q2 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0103 Q2 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111111111100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R72C58:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00R0000 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C3 H00R0100 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q7 +arc: V01S0000 F0 +arc: V01S0100 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C59:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 N1_V02S0701 +arc: A7 E1_H01W0000 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: C1 H02E0401 +arc: C5 V00T0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C60:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 V02S0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A7 V02S0101 +arc: B1 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C5 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 H02E0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 W1_H02E0401 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q7 +arc: W1_H02W0501 Q7 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C62:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06N0203 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: B5 V02S0701 +arc: B7 N1_V02S0701 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q7 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H01E0001 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A7 V02N0301 +arc: B1 E1_H02W0301 +arc: B3 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C5 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0001110100011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R72C64:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A5 V02S0101 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C5 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R72C65:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B3 V02S0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C3 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02S0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 W1_H02E0001 +arc: M6 W1_H02E0401 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C66:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H00R0000 +arc: A3 W1_H02E0501 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R72C67:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 H02E0301 +arc: B7 N1_V02S0501 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 N1_V02S0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0101000101010101 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 0000111000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICED.K1.INIT 0000110000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C68:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 V00T0000 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1101100000000000 +word: SLICED.K0.INIT 0000111000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C69:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 + +.tile R72C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 H02W0501 +arc: B3 H02E0301 +arc: C3 H02E0401 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000000100010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C71:PLC2 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V00B0100 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEB.K1.INIT 1100110000001000 +word: SLICEB.K0.INIT 1100110010001000 +word: SLICEC.K1.INIT 1100000011001000 +word: SLICEA.K1.INIT 1100110000001000 +word: SLICEA.K0.INIT 1100110010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R72C72:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: A5 H02W0501 +arc: B0 V02N0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1110111011101110 +word: SLICEB.K1.INIT 1110111011101110 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C73:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: B0 H02W0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C74:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 V06S0003 + +.tile R72C75:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N3_V06N0103 S3_V06N0103 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: D3 S1_V02N0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N1_V02N0301 F3 +arc: N1_V02N0601 F6 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 0000111100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R72C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H02W0301 +arc: B2 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C77:PLC2 +arc: N1_V02N0001 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0301 V06S0003 +arc: A0 V02N0701 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C78:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 V02N0701 +arc: F0 F0_SLICE +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R72C79:PLC2 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N1_V01S0100 +arc: A2 V02S0501 +arc: A4 S1_V02N0301 +arc: B0 V02S0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C80:PLC2 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 S1_V02N0701 +arc: A2 V02S0701 +arc: A5 V02N0301 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B6 V00B0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C81:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: A0 V02N0701 +arc: B1 S1_V02N0101 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C82:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: B3 H02E0301 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R72C83:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 H01E0001 + +.tile R72C84:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: A3 V00B0000 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B2 S1_V02N0301 +arc: B4 W1_H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C85:PLC2 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: A6 H02W0501 +arc: B0 E1_H02W0101 +arc: C6 E1_H02W0601 +arc: D6 F0 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V02N0001 F0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010101010100101 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C86:PLC2 +arc: E1_H02E0701 W1_H02E0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C87:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C88:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A6 E1_H01W0000 +arc: B0 V02N0301 +arc: B7 V02N0501 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1010101010100101 +word: SLICED.K1.INIT 1100001111000000 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C89:PLC2 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: C3 H02W0601 +arc: D3 V00B0100 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +word: SLICEB.K1.INIT 1111000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C90:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 + +.tile R72C93:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R72C94:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 + +.tile R72C96:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R72C99:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R73C30:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 + +.tile R73C31:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 + +.tile R73C32:PLC2 +arc: H00L0100 V02S0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 N1_V01S0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 F3 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F1 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0000000001000000 +word: SLICEB.K0.INIT 0010001100110011 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 0101010100010101 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 0011001100010011 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C33:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 + +.tile R73C34:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: W1_H02W0601 E3_H06W0303 + +.tile R73C35:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A6 V02S0101 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B6 V01S0000 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C6 V00T0100 +arc: D1 N1_V01S0000 +arc: D3 V02N0001 +arc: D6 V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0000000000100000 +word: SLICEA.K1.INIT 0010001100110011 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C36:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 + +.tile R73C37:PLC2 +arc: S1_V02S0501 N3_V06S0303 + +.tile R73C39:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 V01N0101 +arc: C5 V02S0001 +arc: D5 V02S0401 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R73C40:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H02E0101 +arc: A0 H02E0501 +arc: A1 V01N0101 +arc: A4 H02W0501 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 F0 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N3_V06N0303 F5 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0011001000000000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K0.INIT 0001000100010001 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0000001100000001 +word: SLICEA.K1.INIT 0000000000101010 +word: SLICED.K1.INIT 0000000001110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R73C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V01N0101 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: B0 S1_V02N0101 +arc: B4 V02N0501 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 N1_V02S0001 +arc: C6 N1_V02S0001 +arc: C7 H01E0001 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011101000000000 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0011000000110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R73C42:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 H02E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A4 V00B0000 +arc: A7 H02E0701 +arc: B1 H01W0100 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0601 +arc: C2 F4 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 H02E0601 +arc: N1_V01N0101 F6 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R73C43:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 H00L0100 +arc: A2 V02N0701 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0101 +arc: B6 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0201 +arc: D0 H00R0000 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 0000000001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0111000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101000000000 +word: SLICEC.K0.INIT 0000000011101100 +word: SLICED.K0.INIT 0000000000001100 +word: SLICEC.K1.INIT 0000000011111101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C44:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 H01E0001 +arc: M2 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0100 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0101010101000000 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 0010000000110000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1100100010001000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C45:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C7 H02E0601 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F0 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000011110111 +word: SLICEB.K1.INIT 1010000010100000 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000100000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A6 V00T0100 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 V02N0501 +arc: C0 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: D3 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000010100000 +word: SLICEB.K1.INIT 0111111100000000 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K0.INIT 0111000011110000 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R73C47:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A6 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W1_H02W0301 F3 +word: SLICED.K0.INIT 1100010011001100 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111001100000011 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R73C48:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 N1_V02S0501 +arc: A2 V01N0101 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00L0000 +arc: B4 F1 +arc: B5 V02S0701 +arc: B6 F3 +arc: C0 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F1 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1000101000001010 +word: SLICEA.K1.INIT 1000100010001000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 1100010000000000 +word: SLICEB.K0.INIT 0111111100000000 +word: SLICEB.K1.INIT 0101110011111100 +word: SLICED.K0.INIT 0101000100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 F7 +arc: A5 V02S0301 +arc: B2 S1_V02N0101 +arc: B5 H01E0101 +arc: B7 V02N0501 +arc: C0 F4 +arc: C2 S1_V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 V02S0001 +arc: D0 H01E0101 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000110011 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R73C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 + +.tile R73C51:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A6 N1_V02S0301 +arc: B0 F3 +arc: B1 H02W0301 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0401 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N3_V06N0203 F4 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEA.K1.INIT 0000001100000010 +word: SLICEA.K0.INIT 0000000011111110 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICED.K1.INIT 0000000000001100 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R73C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 F5 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B5 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B2 V02S0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F2 +arc: V01S0000 F6 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 0000000010101000 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R73C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 V02S0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: A0 H00R0000 +arc: A2 F5 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R73C55:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: C7 F6 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000100010001 +word: SLICED.K0.INIT 1110111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000001000111 +word: SLICEA.K1.INIT 1100010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C56:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 V02S0301 +arc: B3 S1_V02N0301 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 V02S0201 +arc: D1 V00T0100 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V02N0001 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C57:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: N1_V01N0001 F2 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C58:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B6 W1_H02E0301 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C2 F6 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R73C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 E1_H01W0000 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V01S0000 +arc: B5 H01E0101 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEA.K1.INIT 1111101100111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1000100001000100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R73C60:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 N1_V02S0001 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D1 E1_H02W0201 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 V00B0000 +arc: D7 N1_V02S0401 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C62:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 H02W0501 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B2 N1_V02S0101 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 N1_V01N0001 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q7 +word: SLICEB.K1.INIT 0000111000001111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C63:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 N1_V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q6 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C64:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B5 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H02E0601 +arc: C3 N1_V02S0401 +arc: C5 V00B0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02S0001 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F1 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C65:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 H02W0501 +arc: A5 V02S0301 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B3 H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C3 H00R0100 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D5 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011101000111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C66:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A7 E1_H01W0000 +arc: B3 Q3 +arc: B5 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0501 Q5 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 F6 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 0011001000110011 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R73C67:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 V01N0101 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 H01E0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F4 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 0000000011110111 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R73C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 N1_V02S0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 W1_H02E0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 F4 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R73C69:PLC2 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 W3_H06E0303 +arc: C1 E1_H02W0401 +arc: D1 V00B0100 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: S3_V06S0103 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R73C70:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: V01S0100 N3_V06S0303 + +.tile R73C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 E1_H02W0101 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H00L0100 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000011000000 +word: SLICEA.K1.INIT 1010101000100000 +word: SLICEB.K0.INIT 1111000011000000 +word: SLICEB.K1.INIT 1010101000100000 +word: SLICEC.K0.INIT 1111000011000000 +word: SLICEC.K1.INIT 1111010000000000 +word: SLICED.K0.INIT 1111000011000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R73C72:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0701 H01E0101 + +.tile R73C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B4 E1_H02W0101 +arc: C0 H02W0601 +arc: C2 H02W0601 +arc: C4 V02N0201 +arc: C6 V00T0100 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S3_V06S0003 F3 +word: SLICED.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000010100000000 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0001000100000001 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0001000000010001 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0001000000010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R73C74:PLC2 +arc: E1_H02E0301 V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: B0 W1_H02E0301 +arc: B3 H02E0301 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C75:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R73C76:PLC2 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B5 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C5 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00T0000 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0100000000000100 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C77:PLC2 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: A2 S1_V02N0501 +arc: B0 V02S0301 +arc: B3 E1_H02W0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C79:PLC2 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0701 +arc: A5 H02W0701 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B5 V02N0501 +arc: B7 S1_V02N0701 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: D5 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M4 E1_H01E0101 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R73C80:PLC2 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V06N0203 + +.tile R73C81:PLC2 +arc: E1_H02E0101 V01N0101 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0101 V02N0101 + +.tile R73C82:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 + +.tile R73C83:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 N3_V06S0003 +arc: A3 V01N0101 +arc: B3 V01N0001 +arc: D3 V00B0100 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1010101000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R73C84:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0001 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: B3 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C85:PLC2 +arc: V00B0000 W1_H02E0401 +arc: A0 H02E0701 +arc: A2 V00B0000 +arc: A6 W1_H02E0501 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C86:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0101 N3_V06S0103 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: A1 W1_H02E0501 +arc: B0 V00B0000 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F7 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1111000000001111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R73C87:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 + +.tile R73C88:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B2 W1_H02E0101 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C89:PLC2 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F7 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B4 V02N0701 +arc: C4 N1_V02S0201 +arc: C7 N1_V02S0001 +arc: D4 V02N0401 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100001111000000 +word: SLICED.K1.INIT 1010101010100101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R73C90:PLC2 +arc: N1_V02N0101 V01N0101 +arc: V00B0100 S1_V02N0301 +arc: B0 V01N0001 +arc: B3 V02N0301 +arc: C3 V02N0401 +arc: D0 V00B0100 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F0 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F3 +word: SLICEB.K1.INIT 1100001111000000 +word: SLICEA.K0.INIT 1100110000110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R73C91:PLC2 +arc: N1_V02N0301 S1_V02N0301 + +.tile R73C92:PLC2 +arc: N3_V06N0003 S1_V02N0301 + +.tile R74C100:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R74C102:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R74C103:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R74C105:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C106:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R74C108:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C109:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R74C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C112:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R74C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R74C115:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R74C17:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R74C31:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R74C32:PLC2 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 + +.tile R74C33:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 + +.tile R74C35:PLC2 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 + +.tile R74C36:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0401 H02W0401 + +.tile R74C37:PLC2 +arc: H01W0100 E3_H06W0303 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 H01W0100 +arc: C0 H02E0601 +arc: D0 V02N0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0000110010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R74C38:PLC2 +arc: E1_H02E0601 V06N0303 + +.tile R74C39:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: A1 H00R0000 +arc: A4 V02N0301 +arc: A7 V02N0101 +arc: B1 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F1 +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000000100000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R74C40:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 N3_V06S0003 +arc: A0 E1_H01E0001 +arc: B0 H02W0101 +arc: B3 H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C7 F4 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000011110001 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A4 V00T0100 +arc: A6 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: C1 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 1010000010100000 +word: SLICEC.K0.INIT 1101000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R74C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A6 V02S0101 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B5 H02W0101 +arc: C0 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F3 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0001000100110001 +word: SLICEA.K1.INIT 0101010111011101 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R74C43:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 H02E0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C5 F4 +arc: C6 H02E0601 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N3_V06N0203 F7 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000010001010101 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0000000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R74C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: A0 V02N0501 +arc: A2 E1_H02W0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0401 +arc: C3 H00R0100 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: S1_V02S0101 F3 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +word: SLICEB.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 0100110000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K1.INIT 0010101000000000 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R74C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C7 V02S0201 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEB.K0.INIT 0001000100010101 +word: SLICED.K0.INIT 0100010011001100 +word: SLICED.K1.INIT 0000000000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C46:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 S1_V02N0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A7 H02W0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0401 +arc: C5 F4 +arc: C7 F6 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEB.K0.INIT 0000000000010001 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K1.INIT 1000110000001100 +word: SLICEA.K1.INIT 0000010100000001 +word: SLICEA.K0.INIT 1000101010101010 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R74C47:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0301 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V00B0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: M0 W1_H02E0601 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 F3 +arc: S1_V02S0701 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 0000000001000000 +word: SLICEC.K0.INIT 0000000001010001 +word: SLICEC.K1.INIT 0000000000010000 +word: SLICED.K1.INIT 1111101000000000 +word: SLICED.K0.INIT 0101000101000000 +word: SLICEA.K0.INIT 0001000101010101 +word: SLICEA.K1.INIT 0000000000010101 +word: SLICEB.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 F1 +arc: B4 H02E0301 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: N3_V06N0203 F7 +arc: V01S0000 Q0 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 0001010100000100 +word: SLICEA.K1.INIT 0101111100010011 +word: SLICEA.K0.INIT 0011011100000101 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1011101100011011 +word: SLICEC.K1.INIT 1010101000001010 +word: SLICEB.K0.INIT 0000010001000100 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C49:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V02S0201 +arc: D2 H02E0201 +arc: E1_H01E0001 Q7 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00L0000 F0 +arc: LSR0 H02W0301 +arc: M0 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 0001000100010011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000111100001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C50:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: B0 H01W0100 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0011011100000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C51:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A6 H02E0701 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 W1_H02E0301 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: C1 N1_V02S0401 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: N1_V02N0601 F6 +word: SLICEC.K1.INIT 0011000011110000 +word: SLICEB.K1.INIT 1000000011001100 +word: SLICED.K0.INIT 1000110000001100 +word: SLICEB.K0.INIT 0000111100001110 +word: SLICEA.K1.INIT 0000101000000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R74C52:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: A0 F7 +arc: A2 F5 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0101 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0101 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 V02S0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H01W0100 +arc: D5 V02S0401 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000000100000011 +word: SLICEC.K1.INIT 0000000000000010 +word: SLICEB.K0.INIT 1010111110100011 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 1100100011000000 +word: SLICEA.K0.INIT 0000001000001110 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C53:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V01S0100 +arc: A7 W1_H02E0501 +arc: B0 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: N1_V02N0601 F6 +arc: V01S0100 F1 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C54:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: V00B0000 F6 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C55:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A2 N1_V02S0701 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 W1_H02E0101 +arc: B5 N1_V02S0501 +arc: B6 N1_V02S0701 +arc: B7 F1 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R74C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R74C57:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 V02N0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1100100000000000 +word: SLICEA.K0.INIT 0111011101110010 +word: SLICEA.K1.INIT 1111111111111010 +word: SLICEB.K0.INIT 0000000000010101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000010000000 +word: SLICEC.K0.INIT 0101111101001110 +word: SLICEC.K1.INIT 1111111111101110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R74C58:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 F7 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 N1_V02S0001 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 0000100010001000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A1 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B1 N1_V02S0101 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEC.K1.INIT 0010000010100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 H02W0701 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 N1_V02S0501 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F3 +arc: LSR1 H02E0301 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F7 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C61:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V01N0101 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B1 E1_H02W0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0100 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F4 +arc: D1 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C62:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0100 V02N0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B7 H02W0301 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C5 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 H01E0101 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q7 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 N1_V01N0001 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: M6 V00T0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C63:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B3 V02S0301 +arc: B5 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 H01E0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +word: SLICEA.K1.INIT 0011001100100011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R74C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H01W0000 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 H00R0100 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0601 Q4 +arc: S1_V02S0701 Q7 +arc: V00B0000 F6 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q4 +word: SLICEB.K1.INIT 0011001100100011 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R74C65:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 S1_V02N0501 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 H02E0001 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q7 +arc: S1_V02S0601 F4 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C66:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 0101010101000101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C67:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 V01N0101 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A3 E1_H02W0501 +arc: B3 H00R0100 +arc: C0 E1_H01W0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICEB.K1.INIT 0101000101010101 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C68:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C69:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N3_V06N0203 H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 H00R0000 +arc: A3 V00T0000 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B1 H02W0101 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 E1_H02W0401 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111011100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111011100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111011100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R74C71:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A1 V02S0501 +arc: A3 V02S0501 +arc: A5 V02N0301 +arc: B1 V02N0301 +arc: B3 V02N0301 +arc: B5 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1101111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1101111100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1011000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R74C72:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B7 V00B0100 +arc: C1 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 1101111100000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 1100110001001100 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100010011001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100010011000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R74C73:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A4 V02S0101 +arc: B3 V02S0101 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: D3 E1_H02W0201 +arc: D4 H02E0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +word: SLICEC.K0.INIT 0000101000001111 +word: SLICEB.K1.INIT 0000110000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C74:PLC2 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile R74C75:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R74C76:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R74C77:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R74C78:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V01N0101 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: B2 E1_H02W0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C80:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0303 V01N0101 +arc: A1 S1_V02N0701 +arc: B0 V02N0301 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C81:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: A4 S1_V02N0301 +arc: B0 V02S0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: S1_V02S0701 F5 +arc: V01S0100 F6 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C82:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A5 W1_H02E0501 +arc: B1 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: A0 S1_V02N0701 +arc: B1 W1_H02E0101 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: V01S0100 F1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R74C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 H00L0000 +arc: A5 V00T0000 +arc: A7 H02E0501 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C85:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B6 E1_H02W0101 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C86:PLC2 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 V02S0001 +arc: A0 F5 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C5 H02E0601 +arc: C7 V02N0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: V01S0000 F0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1100110011000011 +word: SLICEC.K1.INIT 1100110000110000 +word: SLICEC.K0.INIT 1100110000110011 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C87:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 H01E0101 + +.tile R74C88:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 W3_H06E0303 + +.tile R74C89:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 W3_H06E0003 +arc: V00T0000 W1_H02E0001 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 W1_H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C90:PLC2 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00T0000 V02N0601 +arc: A1 V01N0101 +arc: A3 V00T0000 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B7 F3 +arc: C7 V02N0001 +arc: D7 S1_V02N0401 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +word: SLICED.K1.INIT 1111110000000011 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R74C91:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C93:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C96:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 + +.tile R74C97:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C99:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R75C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C101:PLC2 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 + +.tile R75C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C104:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R75C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R75C107:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R75C110:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R75C2:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R75C32:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R75C35:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R75C37:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 + +.tile R75C38:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V06S0003 + +.tile R75C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 H02E0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 N1_V01S0000 +arc: D4 F2 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1010101000100010 +word: SLICEA.K0.INIT 0000001100100011 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICEB.K0.INIT 1111010100000000 +word: SLICEC.K0.INIT 0000111100000100 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R75C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02S0601 +arc: A1 H00L0100 +arc: A5 H02E0501 +arc: B1 V00T0000 +arc: B5 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C5 H01E0001 +arc: C7 V02N0001 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0011101100000000 +word: SLICEC.K1.INIT 0000010000001111 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R75C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B4 H01E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0001010100010001 +word: SLICEC.K0.INIT 0100110001000100 +word: SLICED.K1.INIT 0000000100000101 +word: SLICEB.K1.INIT 0100000001010101 +word: SLICEA.K0.INIT 0100010001011111 +word: SLICEA.K1.INIT 0101011101011111 +word: SLICEB.K0.INIT 0100111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R75C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 W1_H02E0301 +arc: C1 V02N0401 +arc: C4 V00B0100 +arc: C7 V02S0201 +arc: D1 V02S0001 +arc: D2 W1_H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F2 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0010001010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R75C43:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 F5 +arc: A7 H02E0701 +arc: B3 H02E0301 +arc: B6 H02E0301 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C7 F6 +arc: D0 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: S1_V02S0201 F2 +arc: S3_V06S0103 F2 +arc: V01S0000 F7 +arc: V01S0100 F5 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R75C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0010001000000010 +word: SLICEA.K1.INIT 0100010000000000 +word: SLICEC.K0.INIT 1100110011000100 +word: SLICEB.K0.INIT 0000101110111011 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEC.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: A0 V02N0501 +arc: A2 N1_V02S0501 +arc: A3 F7 +arc: B0 E1_H02W0301 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 F1 +arc: B7 F1 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C6 V02N0001 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000010011 +word: SLICEA.K0.INIT 0101010100010000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000001110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R75C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A3 N1_V02S0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICED.K1.INIT 0011000100000001 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111111001010100 +word: SLICEA.K1.INIT 1111000011111111 +word: SLICED.K0.INIT 0000101100001000 +word: SLICEB.K1.INIT 0101010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R75C47:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 E1_H01E0101 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 0001000100000000 +word: SLICEB.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0100010100000000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K1.INIT 0000011100000011 +word: SLICED.K0.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R75C48:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A4 H02E0701 +arc: A5 N1_V01S0100 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C4 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: N1_V01N0101 F7 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 F3 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1010101011110011 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000000011001100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEC.K1.INIT 1010101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R75C49:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02N0701 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: B1 V00T0000 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 S1_V02N0701 +arc: C1 V02S0401 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1110000011000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1100100010001000 +word: SLICEC.K1.INIT 1010100010100000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A3 V00B0000 +arc: B3 N1_V02S0101 +arc: C0 V02S0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C51:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: B0 H02E0101 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: A1 V01N0101 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F5 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 1000000011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R75C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 N3_V06S0303 +arc: A1 E1_H02W0501 +arc: A2 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C2 F4 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0011110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0011111100000000 +word: SLICEC.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0001000000110010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R75C54:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F5 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0100000011000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 0111011101110100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R75C55:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0011001100000011 +word: SLICEC.K0.INIT 0011000100000001 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C56:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 H02W0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 0011010111110101 +word: SLICED.K1.INIT 0101111111111111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 E1_H01W0100 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 H02E0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001000111011101 +word: SLICED.K1.INIT 1111010111100100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000100110001 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100111111000101 +word: SLICED.K0.INIT 0000000100110001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C58:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A0 N1_V02S0701 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B0 H02E0301 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0100 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +word: SLICEB.K0.INIT 1000000011001100 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C59:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C60:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 F3 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: V01S0100 F6 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R75C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: A2 V01N0101 +arc: A5 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V02S0101 +arc: B2 V02N0101 +arc: B5 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 V02N0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0101 Q3 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: A1 V02N0701 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 F1 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100000000110000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C64:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 E1_H02W0701 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B4 H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F5 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q4 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEC.K0.INIT 0011001000110011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C65:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 V06N0003 +arc: CLK0 G_HPBX0000 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: W1_H02W0001 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C66:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C67:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02E0701 +arc: A6 F7 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C4 Q4 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1000100011000000 +word: SLICED.K0.INIT 0000111000001111 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C68:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 V02S0401 +arc: D0 V00B0100 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R75C69:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: C0 H02E0401 +arc: C5 V00T0000 +arc: D0 V00B0100 +arc: D5 H00R0100 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +word: SLICEA.K0.INIT 0101010100010101 +word: SLICEC.K1.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R75C70:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N1_V01S0100 + +.tile R75C71:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: A1 V02N0501 +arc: A3 S1_V02N0501 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 F3 +word: SLICEA.K1.INIT 0000000100001111 +word: SLICEB.K1.INIT 0000010100000111 +word: SLICEB.K0.INIT 0000000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R75C72:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 N1_V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A5 V00B0000 +arc: B1 H02E0101 +arc: B3 H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02S0201 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111011100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111011100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010101000101010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R75C73:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0601 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A3 H02E0501 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 N1_V02S0201 +arc: D2 V02N0001 +arc: D3 N1_V02S0201 +arc: D5 V02S0401 +arc: D7 H02W0001 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1011111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1011111100000000 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICEC.K1.INIT 1011000011110000 +word: SLICED.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1010000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R75C74:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: A3 W1_H02E0701 +arc: A5 V02N0301 +arc: B3 H02E0101 +arc: B5 S1_V02N0501 +arc: C3 N1_V02S0601 +arc: C5 V00T0000 +arc: D3 E1_H02W0001 +arc: D5 V02S0601 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +word: SLICEC.K1.INIT 0000111100001000 +word: SLICEB.K1.INIT 0000010100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R75C75:PLC2 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 + +.tile R75C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: W1_H02W0001 V06S0003 + +.tile R75C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B1 S1_V02N0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000101000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C78:PLC2 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: A1 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: D0 W1_H02E0001 +arc: D1 H02E0001 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C79:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R75C80:PLC2 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 S1_V02N0501 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C81:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06E0003 + +.tile R75C82:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 + +.tile R75C83:PLC2 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0501 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C84:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02S0401 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: A2 V00T0000 +arc: A5 E1_H01W0000 +arc: A7 H02W0501 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: E1_H01E0101 F7 +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C85:PLC2 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 V02S0701 +arc: B2 H00R0000 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 V02S0501 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEB.K0.INIT 1100110011000011 +word: SLICED.K1.INIT 1100001111000000 +word: SLICEB.K1.INIT 1010101010100101 +word: SLICEC.K1.INIT 1100110000110000 +word: SLICEC.K0.INIT 1100001111000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R75C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 + +.tile R75C87:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0501 W3_H06E0303 +arc: B4 V02N0501 +arc: B7 H02W0101 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C7 H02W0601 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1111110000000011 +word: SLICEC.K0.INIT 1100001111000000 +word: SLICEB.K1.INIT 1111000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R75C88:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 H01E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: A5 H02E0501 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B2 V02N0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C89:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0301 N1_V02S0301 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0101 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F4 +arc: F4 F4_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C90:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: V00B0000 V02S0201 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C2 H02E0601 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: D2 V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 1100110000110000 +word: SLICEC.K1.INIT 1111000011000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R75C91:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 + +.tile R75C92:PLC2 +arc: N1_V02N0301 S1_V02N0301 + +.tile R75C94:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C95:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R75C98:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R76C101:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R76C104:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R76C107:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R76C110:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R76C113:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R76C116:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R76C38:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E1_H01W0000 + +.tile R76C39:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: A0 F5 +arc: A4 F5 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEC.K1.INIT 0000000000110011 +word: SLICEB.K1.INIT 0000110000000000 +word: SLICED.K0.INIT 0000110011001100 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 0010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C40:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: B0 H00R0100 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010000011110000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 1010001010101010 +word: SLICEB.K0.INIT 0000000011110011 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R76C41:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: A1 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000100000000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R76C42:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V01S0000 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 E1_H02W0701 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101111101001100 +word: SLICEC.K1.INIT 0000100010101010 +word: SLICEA.K1.INIT 0000111000001010 +word: SLICEB.K0.INIT 0011001100010011 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0000101010001010 +word: SLICED.K1.INIT 1111010111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: A0 H00R0000 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 F4 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0111001011111010 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010101010111111 +word: SLICEA.K1.INIT 0011000000110011 +word: SLICED.K0.INIT 0010001010100010 +word: SLICED.K1.INIT 0101110011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A5 S1_V02N0101 +arc: B0 H02E0301 +arc: B3 F1 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F1 +arc: V01S0000 F3 +arc: V01S0100 F5 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 0101000001010000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 0011000000110000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R76C45:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A3 V02N0501 +arc: A5 W1_H02E0701 +arc: B0 F3 +arc: B1 F3 +arc: B5 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C5 N1_V02S0001 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 H02E0001 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N3_V06N0003 F3 +arc: V00B0100 F5 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 0101011101011111 +word: SLICEA.K1.INIT 0101011100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H01E0001 +arc: A5 S1_V02N0301 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 0000011100000011 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0000110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R76C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 H02W0501 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0101 Q1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1100110001001100 +word: SLICED.K0.INIT 0000110000001110 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000001110101010 +word: SLICEB.K0.INIT 1110111011110000 +word: SLICEB.K1.INIT 1111111111001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: A0 H02W0701 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B6 F3 +arc: C0 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N3_V06N0303 F6 +arc: W1_H02W0401 Q6 +word: SLICEB.K1.INIT 1011111100000000 +word: SLICED.K0.INIT 1000101000000000 +word: SLICEC.K0.INIT 1010111000000000 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C49:PLC2 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICED.K0.INIT 0000100000000000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C50:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: B3 V01N0001 +arc: D3 N1_V02S0001 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R76C51:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: A2 W1_H02E0701 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C52:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: A3 S1_V02N0501 +arc: A6 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 S1_V02N0101 +arc: B6 V02N0701 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H02E0201 +arc: D6 N1_V02S0601 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011001100000000 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R76C53:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 V02S0401 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F5 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R76C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: A3 V00T0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B2 N1_V02S0101 +arc: B4 E1_H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C55:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: B1 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B5 V02N0701 +arc: B7 V02S0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V01N0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B7 H02E0101 +arc: E1_H01E0101 F5 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C58:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 V02S0201 +arc: A1 V02N0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: LSR1 H02W0301 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 F0 +arc: V00B0000 F6 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C59:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H01E0001 +arc: A1 W1_H02E0701 +arc: A2 V01N0101 +arc: A3 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 W1_H02E0101 +arc: B7 F3 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 F4 +arc: D0 V02S0201 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0101 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R76C60:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 V02N0301 +arc: B4 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: C4 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: B1 V01N0001 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C62:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02S0501 +arc: B1 Q1 +arc: B3 N1_V02S0301 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C63:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R76C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 N1_V01S0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B3 Q3 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C65:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 E1_H01E0001 +arc: B1 H02W0101 +arc: C1 H02E0601 +arc: D1 H00R0000 +arc: F1 F1_SLICE +arc: S1_V02S0301 F1 +word: SLICEA.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C66:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H02W0501 +arc: A2 V02N0501 +arc: A4 E1_H02W0701 +arc: A7 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H02E0301 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C4 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C67:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: A1 V02S0501 +arc: A5 S1_V02N0301 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00B0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F7 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 0011110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0011001111001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R76C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C70:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1011111110110011 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1111101100111011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEB.K1.INIT 1111011110110011 +word: SLICEC.K0.INIT 1100100000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C71:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 V01N0101 +arc: A1 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q2 +arc: V01S0100 F6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1111001110111011 +word: SLICED.K0.INIT 1000100011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R76C72:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02N0501 +arc: B2 W1_H02E0301 +arc: C2 H02E0401 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 0000111100001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R76C73:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 N1_V02S0201 +arc: A0 F5 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 V02N0101 +arc: B0 H00R0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C2 H02E0601 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 0011001000110011 +word: SLICEC.K0.INIT 0011001100100000 +word: SLICEC.K1.INIT 0011001100100000 +word: SLICEA.K0.INIT 0011001100100011 +word: SLICEA.K1.INIT 0011001100100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C74:PLC2 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0701 +arc: A2 S1_V02N0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000000001010000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001000000010011 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICEC.K0.INIT 0000010100000100 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K0.INIT 0000010100010101 +word: SLICED.K1.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C75:PLC2 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 E1_H02W0601 + +.tile R76C76:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 + +.tile R76C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0701 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R76C78:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 0000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C79:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000101000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000010100000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1111111111110011 +word: SLICEA.K1.INIT 1111111111110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C80:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0101 V01N0101 +arc: A0 V02N0501 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000010100000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000000000100000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0100000000000000 +word: SLICEC.K0.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C81:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile R76C82:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 + +.tile R76C83:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0701 H06E0203 + +.tile R76C84:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: A4 N1_V02S0101 +arc: A5 H02E0701 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0301 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A4 N1_V01S0100 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B2 V02S0101 +arc: B3 N1_V02S0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C86:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 H01E0101 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1100110000110011 +word: SLICEC.K1.INIT 1100001111000000 +word: SLICEC.K0.INIT 1111000011000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R76C87:PLC2 +arc: E1_H02E0101 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B2 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B5 N1_V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C88:PLC2 +arc: N1_V02N0101 H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B2 H02W0301 +arc: B4 H02E0101 +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C89:PLC2 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0301 N1_V02S0301 + +.tile R76C90:PLC2 +arc: N1_V02N0401 N1_V01S0000 + +.tile R76C91:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R76C92:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R76C98:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R77C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C101:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R77C102:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C103:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R77C104:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C107:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 + +.tile R77C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C110:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R77C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C113:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 + +.tile R77C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C116:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R77C117:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C118:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C14:PLC2 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C15:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R77C21:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R77C23:PLC2 +arc: N3_V06N0303 H06W0303 + +.tile R77C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R77C32:PLC2 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 + +.tile R77C35:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R77C36:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R77C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C39:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 F5 +arc: A7 N1_V01S0100 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 F3 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: D0 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F7 +word: SLICEB.K1.INIT 0000000000010000 +word: SLICEB.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000001000100010 +word: SLICEA.K0.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R77C3:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R77C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 V02S0501 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 F0 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000010101000 +word: SLICEC.K1.INIT 1110101000000000 +word: SLICED.K1.INIT 0000111100001110 +word: SLICEB.K1.INIT 0100010001000000 +word: SLICEB.K0.INIT 1111101100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R77C41:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B7 V02S0501 +arc: C0 V02S0401 +arc: C1 F4 +arc: C3 W1_H02E0601 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEC.K0.INIT 0011001100110010 +word: SLICEB.K1.INIT 0000000011111110 +word: SLICEA.K1.INIT 0000001100000001 +word: SLICED.K0.INIT 0000101000001010 +word: SLICEC.K1.INIT 0000000100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C2 H02W0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02E0301 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F6 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEA.K1.INIT 1111111111001100 +word: SLICEB.K0.INIT 0101111111111111 +word: SLICEB.K1.INIT 0000011100001111 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 0100110011001100 +word: SLICEC.K0.INIT 0101111111111111 +word: SLICED.K0.INIT 0000010100000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R77C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A2 H00L0100 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR0 E1_H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 1111111100010101 +word: SLICEB.K1.INIT 0000110000001111 +word: SLICED.K1.INIT 0000100011001100 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K0.INIT 0011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R77C44:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C1 W1_H02E0601 +arc: C3 H00L0100 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1101000111110011 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011100001111 +word: SLICED.K1.INIT 0011000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C45:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V01N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 0011011101110111 +word: SLICEB.K1.INIT 0011000001110111 +word: SLICED.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0101011100000000 +word: SLICEC.K0.INIT 1111000010110000 +word: SLICEC.K1.INIT 1110000011000000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R77C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V06N0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V00B0100 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEA.K1.INIT 1100000011001100 +word: SLICEB.K0.INIT 1010000010110000 +word: SLICEC.K0.INIT 0011000000000000 +word: SLICED.K0.INIT 1010111110001101 +word: SLICED.K1.INIT 0000000000110010 +word: SLICEA.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C47:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A3 V02N0501 +arc: A4 H02W0501 +arc: A5 F7 +arc: A6 F5 +arc: B0 H02W0301 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C3 F4 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEC.K0.INIT 0001010101010101 +word: SLICEB.K1.INIT 0000101000101010 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0000000000010101 +word: SLICED.K0.INIT 0000000000011111 +word: SLICEA.K1.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R77C48:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H00R0100 F5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F1 +arc: V00B0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1100100011000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R77C49:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 F5 +arc: A1 F5 +arc: A5 E1_H01W0000 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D5 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +word: SLICEC.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0101010101111111 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R77C50:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B4 V00B0100 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 F4 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 H00L0100 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0111001101000000 +word: SLICED.K1.INIT 0000000011110011 +word: SLICEC.K0.INIT 0100010101010101 +word: SLICEA.K1.INIT 0000101011001100 +word: SLICED.K0.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R77C51:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0001 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 H06W0203 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0000 +arc: A3 S1_V02N0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B1 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 S1_V02N0001 +arc: D1 H02W0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C52:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 H02E0301 +arc: B4 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0100 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C53:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R77C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A5 E1_H02W0701 +arc: B0 V02N0301 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C5 N1_V02S0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0203 F7 +arc: S3_V06S0203 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000110000001100 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C55:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 V01N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 H02E0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 V02N0501 +arc: B6 V02S0701 +arc: C0 E1_H02W0401 +arc: C2 N1_V01S0100 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C56:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A4 V02S0101 +arc: A5 Q5 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B5 V02S0501 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 Q4 +arc: W1_H02W0601 Q4 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C57:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 N1_V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0011000011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R77C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: A4 H02E0701 +arc: A6 N1_V02S0301 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B4 V01S0000 +arc: B7 S1_V02N0501 +arc: C1 N1_V02S0401 +arc: C4 V00T0100 +arc: C6 F4 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D4 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R77C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A6 F5 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 F3 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R77C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 + +.tile R77C61:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 N1_V02S0301 +arc: A7 V02S0101 +arc: C0 N1_V01N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICED.K1.INIT 0000000010101111 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B6 V01S0000 +arc: C0 H02E0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 W1_H02E0001 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R77C63:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: V00T0100 H02E0101 +arc: A1 V01N0101 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011101100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R77C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 H01E0001 +arc: A5 F7 +arc: A7 V02S0101 +arc: B1 H02W0301 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 H02E0201 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R77C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A3 H02W0701 +arc: B0 W1_H02E0101 +arc: B3 V02S0301 +arc: C0 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: A0 E1_H01E0001 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 F7 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0001 +arc: D5 F0 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R77C67:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B7 S1_V02N0501 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 E3_H06W0303 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0701 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 H02E0401 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H00R0000 +arc: A3 V01N0101 +arc: A4 V02S0301 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C70:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V00T0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C71:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0501 +arc: A4 H02E0701 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H01W0100 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR1 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1101100011111111 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R77C72:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 E1_H02W0701 +arc: B1 H02E0101 +arc: C1 S1_V02N0601 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 0011001100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R77C73:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 H02W0401 +arc: C7 N1_V02S0001 +arc: D0 E1_H02W0001 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M4 V00T0000 +arc: M5 W1_H02E0001 +arc: M6 V00T0000 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1000110011001100 +word: SLICEC.K1.INIT 1011111100000000 +word: SLICED.K0.INIT 1000100011001000 +word: SLICED.K1.INIT 1101111100000000 +word: SLICEA.K0.INIT 0010111100000000 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEB.K1.INIT 0101010101000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C74:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 F5 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: S1_V02S0301 F3 +word: SLICEC.K0.INIT 0010001000110011 +word: SLICEB.K1.INIT 0101010001010101 +word: SLICEA.K0.INIT 0010101000100010 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEC.K1.INIT 0000111100001000 +word: SLICED.K0.INIT 0011001100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R77C75:PLC2 +arc: H00L0100 N1_V02S0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00T0000 +arc: V01S0000 F1 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010101000 +word: SLICEA.K0.INIT 1010101010101000 +word: SLICEA.K1.INIT 1010101010101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R77C76:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: C2 W1_H02E0401 +arc: D2 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R77C77:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 N1_V01S0100 +arc: A1 V02N0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: D0 H02W0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 0100010001010000 +word: SLICED.K0.INIT 0000000010101111 +word: SLICED.K1.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R77C78:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: A2 S1_V02N0501 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C79:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: A7 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C80:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0701 +arc: A5 H02W0701 +arc: A7 H02W0701 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C4 W1_H02E0601 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: V01S0100 F1 +arc: W1_H02W0601 F4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICED.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R77C81:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 + +.tile R77C82:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R77C83:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 + +.tile R77C84:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C85:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C87:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C88:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C89:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R77C90:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C91:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C92:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C93:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C94:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C95:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R77C96:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C97:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R77C98:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C99:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R78C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R78C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R78C105:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C106:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R78C108:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R78C109:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R78C112:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C115:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C38:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: A1 V01N0101 +arc: A5 V02N0101 +arc: B1 V01N0001 +arc: B5 H00L0000 +arc: C1 S1_V02N0601 +arc: C5 V01N0101 +arc: D1 V02N0001 +arc: D5 V01N0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0303 F5 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R78C39:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H01E0001 + +.tile R78C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: A0 F5 +arc: A1 F5 +arc: A3 V01N0101 +arc: A7 N1_V01S0100 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: N1_V02N0501 F7 +arc: N3_V06N0103 F2 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000011 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0000000100010001 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101011001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R78C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: B1 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 F2 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICEC.K1.INIT 0000100000000000 +word: SLICEA.K1.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R78C42:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0601 E1_H01W0000 +arc: A6 V02S0101 +arc: C6 W1_H02E0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +word: SLICED.K0.INIT 0000000011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R78C43:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 V06S0203 +arc: A2 H00L0100 +arc: A4 F5 +arc: A5 H02W0501 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B4 H01E0101 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V02S0001 +arc: C7 V02S0201 +arc: D0 E1_H02W0001 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N3_V06N0003 F0 +word: SLICEA.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 0001001100110011 +word: SLICED.K1.INIT 0000001010101010 +word: SLICEC.K1.INIT 0001010101010101 +word: SLICEC.K0.INIT 1100000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R78C44:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 N1_V02S0301 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 F2 +arc: V00T0100 F1 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111000011010000 +word: SLICEB.K1.INIT 1111000010000000 +word: SLICED.K1.INIT 0000111100000011 +word: SLICEC.K0.INIT 0000000000001011 +word: SLICEC.K1.INIT 0000000011001111 +word: SLICEA.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R78C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 F4 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 F3 +arc: V00T0100 Q1 +arc: V01S0000 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 0000000001110011 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 0101000101010101 +word: SLICED.K0.INIT 0100000011001100 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C46:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K1.INIT 0000011100000011 +word: SLICEC.K0.INIT 1111000010100000 +word: SLICEC.K1.INIT 1000101010101010 +word: SLICED.K0.INIT 0000000011110010 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 0100000001010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R78C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A4 F7 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: B0 E1_H02W0101 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B5 V01S0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: N3_V06N0203 F4 +arc: S1_V02S0601 F4 +arc: V01S0100 F1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1101100011111010 +word: SLICEB.K0.INIT 0010001000000000 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEA.K1.INIT 0000000000011111 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 0000101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R78C48:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 F1 +arc: C0 W1_H02E0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR1 E1_H02W0501 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111110010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0011011100111111 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 1010111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: A0 H00R0000 +arc: B0 H02E0301 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111101101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C50:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A6 E1_H01W0000 +arc: C2 N1_V02S0601 +arc: C6 V02N0201 +arc: D2 H02E0201 +arc: D6 H02E0001 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R78C51:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B4 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001000110110011 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C52:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 H01E0001 + +.tile R78C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V02N0401 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B4 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D4 E1_H02W0201 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N1_V01S0100 +arc: S3_V06S0103 H01E0101 +arc: A0 F7 +arc: A3 S1_V02N0501 +arc: A6 V02N0301 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: B6 W1_H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 H02W0201 +arc: D3 N1_V01S0000 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: V00B0000 F6 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010111010101 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 V02S0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C6 V02S0001 +arc: D0 W1_H02E0201 +arc: D1 H02E0201 +arc: D6 H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0101 F1 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R78C56:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C57:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: A1 H02W0701 +arc: A2 V02N0501 +arc: A7 V00T0100 +arc: B1 H01W0100 +arc: B2 W1_H02E0101 +arc: B7 V00B0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C7 H02W0401 +arc: D1 N1_V01S0000 +arc: D2 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R78C58:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V01N0101 +arc: A1 V02N0501 +arc: A3 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C7 V02N0001 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R78C59:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V01N0101 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 V02S0301 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C1 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 V02S0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R78C60:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 H06E0103 +arc: W1_H02W0701 N3_V06S0203 + +.tile R78C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0201 N3_V06S0103 + +.tile R78C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 N3_V06S0103 +arc: B0 V02N0101 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 H02E0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 W3_H06E0003 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 Q7 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0601 +arc: C4 Q4 +arc: C5 W1_H02E0401 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C65:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 W1_H02E0301 +arc: A2 V02N0701 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C66:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02N0501 +arc: A1 H02W0501 +arc: A2 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 V02S0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 V02N0401 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C67:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02S0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 E1_H02W0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C68:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B5 V02S0701 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C69:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02S0601 +arc: A0 H00R0000 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R78C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: V00T0100 H02W0101 +arc: B0 V02S0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 W1_H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 V06S0103 + +.tile R78C72:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: B0 E1_H02W0101 +arc: B2 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H02E0001 +arc: M2 H02W0601 +arc: M3 W1_H02E0201 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: S3_V06S0003 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000011001110 +word: SLICEA.K1.INIT 0000000011111010 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICEB.K1.INIT 0000000011111010 +word: SLICEC.K0.INIT 0000110000001110 +word: SLICEC.K1.INIT 0000110000001110 +word: SLICED.K0.INIT 0000110000001110 +word: SLICED.K1.INIT 0000111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R78C73:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 F2 +arc: V01S0100 Q1 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEA.K1.INIT 1110111100100000 +word: SLICEB.K1.INIT 1100000011001100 +word: SLICEB.K0.INIT 0010000010101010 +word: SLICEC.K1.INIT 0000101000001111 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R78C74:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000010101110 +word: SLICEA.K1.INIT 0000000011111010 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICEB.K1.INIT 0000000011111010 +word: SLICEC.K0.INIT 0000101000001110 +word: SLICEC.K1.INIT 0000000011110100 +word: SLICED.K0.INIT 0000101000001110 +word: SLICED.K1.INIT 0000000011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R78C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: A4 V00B0000 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K1.INIT 0000000011001111 +word: SLICEA.K1.INIT 0000000011001111 +word: SLICED.K0.INIT 0101010100000101 +word: SLICED.K1.INIT 0000111100000101 +word: SLICEC.K0.INIT 0000000010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R78C76:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: A0 H00L0100 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: A0 W1_H02E0701 +arc: A2 E1_H02W0701 +arc: B0 V02S0301 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R78C78:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: V01S0000 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R78C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0301 +arc: B7 V02S0701 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R78C80:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 N1_V01S0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S3_V06S0203 F7 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R78C81:PLC2 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02N0701 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: B2 H00R0100 +arc: B4 H00R0000 +arc: B6 V02N0701 +arc: C2 V02N0401 +arc: C4 V01N0101 +arc: C6 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D6 S1_V02N0601 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R78C82:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S1_V02N0701 + +.tile R78C83:PLC2 +arc: W1_H02W0501 V02N0501 + +.tile R78C84:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R78C85:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C87:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R78C88:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R78C90:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C91:PLC2 +arc: N1_V02N0001 S3_V06N0003 + +.tile R78C93:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C94:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C96:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C99:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R79C35:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R79C36:PLC2 +arc: E1_H02E0701 S1_V02N0701 + +.tile R79C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0501 +arc: A0 W1_H02E0701 +arc: A2 V01N0101 +arc: B1 V01N0001 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: W1_H02W0401 V01N0001 +arc: A0 V01N0101 +arc: A2 H02W0501 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR0 E1_H02W0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C40:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: C0 S1_V02N0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 0000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R79C41:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A1 H00L0000 +arc: A5 V02N0301 +arc: B1 V02N0101 +arc: B5 V02N0701 +arc: C1 N1_V02S0601 +arc: C5 S1_V02N0201 +arc: D1 H02W0201 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: S3_V06S0003 F0 +arc: V00B0100 F5 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1111111000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C42:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 E1_H02W0001 +arc: A0 S1_V02N0501 +arc: C0 H02E0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110101010 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R79C43:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: C0 H00L0000 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R79C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: A0 N1_V02S0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 0000100011001100 +word: SLICED.K0.INIT 0000101100001111 +word: SLICEB.K0.INIT 0100111100000000 +word: SLICEC.K1.INIT 1111000010100000 +word: SLICED.K1.INIT 1010001000100010 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEA.K1.INIT 0000011100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C45:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A2 V02N0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: B6 F1 +arc: B7 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0401 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEC.K0.INIT 0000110000000000 +word: SLICED.K1.INIT 1100110011001000 +word: SLICED.K0.INIT 0000010100000001 +word: SLICEC.K1.INIT 0000011100000101 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1100110001000000 +word: SLICEB.K1.INIT 1100110011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R79C46:PLC2 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 H01E0001 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEA.K1.INIT 1010101011001010 +word: SLICEB.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C47:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111110001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C48:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: A3 H01E0001 +arc: D3 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: H01W0100 F3 +word: SLICEB.K1.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R79C49:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 H01E0101 +arc: A4 F7 +arc: A6 V00T0100 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C6 F4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: LSR0 H02W0501 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0501 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000000110011 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100100011000000 +word: SLICEA.K1.INIT 1111000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C50:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1111101101000000 +word: SLICED.K1.INIT 0101010111111100 +word: SLICEB.K0.INIT 1100110011110101 +word: SLICEB.K1.INIT 1100101011000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +word: SLICED.K0.INIT 0010000000111111 +word: SLICEA.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C51:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0501 +arc: C1 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 W1_H02E0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F6 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111110100001101 +word: SLICEC.K1.INIT 1111100000001000 +word: SLICED.K0.INIT 0000000000100000 +word: SLICED.K1.INIT 0000000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 F5 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: M5 H02E0001 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 0101111101011100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100010100000000 +word: SLICEB.K1.INIT 0001110100111111 +word: SLICED.K0.INIT 1110111001001110 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 0101111101011100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R79C53:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A1 N1_V02S0501 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B2 H02W0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: N3_V06N0103 F2 +arc: V01S0100 F3 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001101110111011 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICEC.K1.INIT 0000000001010001 +word: SLICED.K0.INIT 0000101100110011 +word: SLICED.K1.INIT 0001110111011101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C54:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 Q5 +arc: V00B0000 F4 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 1110111000000000 +word: SLICEB.K0.INIT 1010101011001111 +word: SLICEB.K1.INIT 1010101011000000 +word: SLICEA.K0.INIT 0000111011111110 +word: SLICEC.K0.INIT 1010110010101111 +word: SLICEC.K1.INIT 1010110010100000 +word: SLICED.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0000000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02N0701 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A6 H02E0501 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D6 H02W0201 +arc: E1_H01E0001 Q4 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 Q6 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0011010111110101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R79C56:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 V06S0003 +arc: A0 F5 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 N1_V01S0100 +arc: A6 F7 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 H02E0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F7 +arc: LSR0 V00B0100 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F6 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000000000110001 +word: SLICED.K0.INIT 0000100000111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R79C57:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A2 H01E0001 +arc: A5 E1_H01W0000 +arc: B2 H02W0301 +arc: C2 V02N0401 +arc: C5 H02W0601 +arc: D2 S1_V02N0201 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000100000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R79C58:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H01E0001 +arc: A1 F5 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0100000001011111 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C59:PLC2 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B6 H02E0301 +arc: C0 F6 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000100000111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C60:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0701 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C61:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 H02W0201 +arc: A0 E1_H01E0001 +arc: B2 V01N0001 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V02S0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1100111100000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C62:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N1_V02S0001 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 V02N0601 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1010110010101100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C63:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: B3 S1_V02N0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C64:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: A4 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 W1_H02E0301 +arc: B3 H00L0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C65:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: A0 W1_H02E0701 +arc: A3 V00B0000 +arc: A7 H00L0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: B0 H02E0301 +arc: B2 V02S0101 +arc: B6 V00T0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06S0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: A4 N1_V02S0101 +arc: A7 V02S0101 +arc: B2 V02N0101 +arc: B4 V00B0100 +arc: B7 H02W0101 +arc: C2 H02E0401 +arc: C4 E1_H02W0401 +arc: C7 H02E0601 +arc: D2 V02N0201 +arc: D4 S1_V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R79C68:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02N0701 +arc: A4 V02S0101 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B5 H00R0000 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C70:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: V00B0000 H02E0401 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C71:PLC2 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 V02S0601 +arc: S3_V06S0003 H06W0003 +arc: V00T0000 N1_V02S0601 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C72:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0103 N1_V01S0100 +arc: F0 F0_SLICE +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R79C73:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 H02W0701 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C74:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A6 H00R0000 +arc: B1 H01W0100 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0101000001010101 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0101000001010101 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0011000000110011 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 0000101000000000 +word: SLICED.K1.INIT 0000110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C75:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W1_H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: A5 V02N0101 +arc: B1 Q1 +arc: B5 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V01S0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R79C76:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0601 W3_H06E0303 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C77:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 H06E0003 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H01E0001 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 F3 +arc: B2 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F7 +arc: V01S0000 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEB.K1.INIT 0101000000000000 +word: SLICEB.K0.INIT 0010100000111100 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C78:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 V02S0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02N0701 +arc: A3 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: B1 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: M0 V00T0100 +arc: M2 E1_H02W0601 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 1100110000110011 +word: SLICED.K0.INIT 1010101000000010 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0701 +arc: F2 F2_SLICE +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C80:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C4 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 W1_H02E0401 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R79C82:PLC2 +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0501 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A1 V01N0101 +arc: B1 S1_V02N0101 +arc: B7 H02E0101 +arc: C1 V02N0401 +arc: C7 V01N0101 +arc: D1 S1_V02N0001 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 0000001100000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C83:PLC2 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: B2 H00R0000 +arc: C2 W1_H02E0401 +arc: D2 V02N0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C101:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R7C104:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R7C107:PLC2 +arc: S3_V06S0303 W3_H06E0303 + +.tile R7C11:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R7C17:PLC2 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: S3_V06S0303 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R7C23:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R7C29:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R7C35:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C39:PLC2 +arc: E1_H02E0201 E1_H01W0000 + +.tile R7C40:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: V00B0100 V02S0101 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 Q7 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B4 V01S0000 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000100010111000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A2 H02W0501 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 Q7 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C42:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: C0 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C43:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 H02E0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V01N0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 Q7 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C45:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0100 E1_H02W0701 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 H02E0301 +arc: B6 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C5 V00B0100 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C46:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02W0701 +arc: A2 V02S0501 +arc: A4 V00T0000 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C47:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q1 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C48:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 E1_H01W0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C49:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0100 +arc: A2 H02E0501 +arc: A3 V02S0501 +arc: A6 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B4 V00B0100 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C4:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R7C50:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 H00L0000 +arc: B6 V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C51:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: B0 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: C0 H00R0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C52:PLC2 +arc: H00L0000 S1_V02N0001 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H00L0000 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000001000100 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C53:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 + +.tile R7C59:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R7C5:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R7C62:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R7C65:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R7C68:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R7C71:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C77:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C83:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C89:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R7C95:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R80C102:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C105:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R80C108:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C111:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R80C114:PLC2 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C17:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R80C33:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R80C37:PLC2 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R80C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02N0401 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: V00T0100 V02N0701 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0101 F4 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C39:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V01N0101 +arc: A5 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +arc: V00B0000 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C40:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A3 V01N0101 +arc: A4 H02W0701 +arc: A6 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C4 H02E0601 +arc: C6 E1_H02W0401 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 F3 +arc: V01S0000 F0 +arc: V01S0100 F1 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEA.K0.INIT 1011001100000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000011100000 +word: SLICEB.K1.INIT 0000000001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R80C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A4 H02E0501 +arc: B4 V02N0701 +arc: C0 H02W0601 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0001000000000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111111111010 +word: SLICEA.K1.INIT 1111111101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R80C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B2 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 F6 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F5 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 1000110000001100 +word: SLICEA.K0.INIT 1111000011111100 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R80C43:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: A1 W1_H02E0701 +arc: A5 V02N0301 +arc: B3 V02N0301 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110000001100 +word: SLICEC.K1.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R80C44:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: A0 V02N0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEB.K1.INIT 0000101100001111 +word: SLICEB.K0.INIT 0111001100000000 +word: SLICEC.K0.INIT 0001000100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C45:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 F5 +arc: A5 N1_V02S0301 +arc: B1 V00T0000 +arc: C1 H02E0401 +arc: C5 N1_V02S0001 +arc: D1 V01S0100 +arc: D5 H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F1 +word: SLICEC.K1.INIT 1010000010101010 +word: SLICEA.K1.INIT 1111000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C46:PLC2 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: A0 V02N0501 +arc: B0 H02E0301 +arc: C0 H02W0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 F2 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEB.K0.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R80C47:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06S0303 +arc: A0 N1_V02S0701 +arc: B0 H02W0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 N3_V06S0303 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 F5 +arc: B0 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0203 Q4 +arc: V00B0100 F7 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010000010101111 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1100100011000000 +word: SLICEB.K1.INIT 1111111100001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C49:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0301 +arc: B2 V02N0101 +arc: B3 F1 +arc: B4 H02E0301 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 N1_V02S0401 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 1010000010101111 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100100010001000 +word: SLICEC.K1.INIT 1010101000001111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1110000011000000 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C50:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 E1_H02W0101 +arc: C1 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 Q7 +arc: S3_V06S0203 Q7 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q7 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111010101110 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 0001000111010101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C51:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B4 N1_V02S0701 +arc: B5 H01E0101 +arc: B6 V00T0000 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0010011110101111 +word: SLICEC.K0.INIT 0010011110101111 +word: SLICED.K0.INIT 0001101110111011 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R80C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 0100110001111111 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100010100000000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICED.K1.INIT 1111001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R80C53:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02E0701 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B5 S1_V02N0501 +arc: B6 F1 +arc: B7 W1_H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011001111111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R80C54:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 0111011101110100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R80C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B3 E1_H01W0100 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 F2 +arc: N1_V02N0601 F4 +arc: S3_V06S0103 F1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000100001000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R80C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0010101001111111 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 0101111101011100 +word: SLICEA.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 N3_V06S0303 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F6 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001000110110011 +word: SLICEB.K0.INIT 1111101100001011 +word: SLICEB.K1.INIT 1111100000001000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010000000101 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 H02E0501 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F4 +arc: S3_V06S0303 Q5 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0000 Q5 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0011010111110101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 0101111101011100 +word: SLICEB.K0.INIT 1010101011110011 +word: SLICEB.K1.INIT 1010101011000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010000000101 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C59:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00T0000 V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 S1_V02N0701 +arc: A6 W1_H02E0501 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B3 H02E0101 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C6 V02N0001 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 W1_H02E0201 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V02N0201 F0 +arc: N3_V06N0003 F3 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1111110000000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000010000000000 +word: SLICEA.K1.INIT 0000010000000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C60:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 + +.tile R80C61:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0203 E1_H01W0000 +arc: A0 H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0101 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R80C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A3 E1_H02W0501 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D3 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R80C63:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: B1 S1_V02N0301 +arc: B3 F1 +arc: B5 F3 +arc: B6 H02W0301 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C64:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0601 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C65:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 N1_V02S0701 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 N1_V02S0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 F6 +arc: C2 H02E0401 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F7 +arc: S1_V02S0601 F4 +arc: V00B0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R80C66:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 W1_H02E0501 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C67:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 N1_V02S0001 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 N1_V01S0100 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 V01N0001 +arc: B4 V02N0501 +arc: C0 V02S0601 +arc: C3 S1_V02N0601 +arc: C4 H02W0601 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F4 +arc: W1_H02W0101 F3 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R80C69:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 H01E0001 + +.tile R80C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0601 H06W0303 + +.tile R80C71:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: C7 H02E0601 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R80C72:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: B5 H02E0301 +arc: C5 W1_H02E0401 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111111100110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R80C73:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 V02N0301 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C74:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H00L0000 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: B1 E1_H02W0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F4 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C75:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0201 E1_H02W0701 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEA.K1.INIT 1010101011100010 +word: SLICEB.K0.INIT 1011101010001010 +word: SLICEB.K1.INIT 1010101011100010 +word: SLICEC.K0.INIT 1100101011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R80C76:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 N1_V01S0100 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: B0 E1_H02W0301 +arc: B2 N1_V02S0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 H02W0301 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: B0 V02S0101 +arc: B1 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C78:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0301 V06N0003 +arc: A0 H02E0701 +arc: A6 H00R0000 +arc: B1 V00B0000 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D6 H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: LSR1 E1_H02W0501 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 Q6 +arc: V01S0100 Q6 +word: SLICED.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R80C79:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B7 W1_H02E0101 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C80:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06N0303 +arc: A0 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 N1_V02S0301 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: V01S0000 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C81:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1100001101000001 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R80C82:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V01N0101 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D5 H02E0201 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R80C83:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06E0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02N0001 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C84:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C87:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R80C90:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C96:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C99:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R81C100:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C101:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C103:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C104:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R81C106:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C107:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R81C110:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R81C2:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R81C35:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 + +.tile R81C36:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: A4 H02W0701 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B5 H00R0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C37:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C38:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q6 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C39:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 E1_H02W0601 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C40:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: A2 H00L0100 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K0.INIT 1111000000001100 +word: SLICEA.K1.INIT 0000111111000000 +word: SLICEB.K0.INIT 0100111110000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C41:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 H01E0001 +arc: A5 V00T0000 +arc: A7 H00R0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000011100001111 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1110110011111100 +word: SLICEA.K1.INIT 1111101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C42:PLC2 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 V02N0401 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111111110100000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000011110000 +word: SLICEB.K0.INIT 0000000100000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R81C43:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C44:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: B0 H02E0301 +arc: C0 S1_V02N0401 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: N3_V06N0003 F0 +arc: S1_V02S0001 F0 +word: SLICEA.K0.INIT 1100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R81C45:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 + +.tile R81C46:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S3_V06S0303 N3_V06S0203 + +.tile R81C47:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V02S0001 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S3_V06S0103 Q2 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111001011010000 +word: SLICEA.K1.INIT 1111001011010000 +word: SLICEB.K0.INIT 1111001011010000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011001111 +word: SLICEC.K1.INIT 1010101011000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C48:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D3 S1_V02N0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011001111111010 +word: SLICEA.K1.INIT 0000001110110011 +word: SLICED.K0.INIT 1111101000111010 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R81C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0101111101011100 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000111011111110 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C50:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1110111101000101 +word: SLICEC.K1.INIT 1110101001000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 H01E0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A1 V02S0501 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H02E0101 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEC.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 1110111001001110 +word: SLICED.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C5 V00T0100 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q5 +arc: S1_V02S0701 Q5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C53:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H01E0001 +arc: A5 N1_V01N0101 +arc: A6 N1_V01S0100 +arc: A7 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: M4 V00T0000 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0303 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: B0 H01W0100 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 F3 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 F7 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1000000010001100 +word: SLICED.K0.INIT 0011010100111111 +word: SLICED.K1.INIT 1010111111001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C56:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 E1_H02W0701 +arc: A4 F7 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F2 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0101001111110011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 0011001011111110 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000010111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C57:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: A1 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1010111110100011 +word: SLICEC.K1.INIT 1010110010100000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A1 H00L0100 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101011110011 +word: SLICEC.K1.INIT 1010101011000000 +word: SLICED.K1.INIT 0000110101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C59:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: A4 E1_H01W0000 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B5 S1_V02N0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: S3_V06S0203 F4 +arc: V00B0100 F5 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000111111101110 +word: SLICED.K0.INIT 1110111101000101 +word: SLICED.K1.INIT 1110101001000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C60:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V02S0301 +arc: B0 H02E0301 +arc: B4 W1_H02E0101 +arc: C0 F4 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +word: SLICEC.K0.INIT 0000101100110011 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 H02E0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C62:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 H02W0501 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 N1_V02S0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R81C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 N1_V02S0701 +arc: A1 H02W0501 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B2 V02N0101 +arc: B5 N1_V02S0501 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEB.K1.INIT 0000000010100000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C64:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 0101000000000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICEA.K1.INIT 1111111111101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C65:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A4 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F7 +arc: W1_H02W0201 F2 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111011111010 +word: SLICEA.K1.INIT 1111111111111000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000001011000011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R81C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 E1_H01W0000 +arc: A7 S1_V02N0101 +arc: B0 H02W0301 +arc: B1 V02S0301 +arc: B2 E1_H02W0301 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: V00T0100 F1 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 H00L0100 +arc: A4 S1_V02N0101 +arc: A6 V00T0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0601 +arc: C1 F4 +arc: C2 V02S0401 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEA.K1.INIT 1111111011111010 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C68:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICEB.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C69:PLC2 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 + +.tile R81C70:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: S1_V02S0701 E3_H06W0203 + +.tile R81C71:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 H00R0100 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1010000010001000 +word: SLICEA.K1.INIT 1010000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C72:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02W0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: A7 E1_H01W0000 +arc: B5 H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 1100001111110000 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 1100001110100101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C73:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A3 E1_H01E0001 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C7 V02S0201 +arc: D1 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0011001100110011 +word: SLICEB.K1.INIT 1100100100111001 +word: SLICEA.K0.INIT 0011001100110011 +word: SLICEA.K1.INIT 1100110000111100 +word: SLICED.K1.INIT 1100000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 H02W0001 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010101011001010 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101000101010000 +word: SLICEC.K1.INIT 0101000101010000 +word: SLICED.K0.INIT 0101000101010101 +word: SLICED.K1.INIT 0101000101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C75:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: A3 V02N0501 +arc: A5 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011000000110011 +word: SLICEB.K1.INIT 0001000000110011 +word: SLICEC.K0.INIT 0011001100000011 +word: SLICEC.K1.INIT 0001001100000011 +word: SLICED.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R81C76:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 S1_V02N0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 H01E0001 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEA.K1.INIT 0001000100110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R81C77:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 F7 +arc: A1 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 0000100000000100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0100010101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R81C78:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 W1_H02E0501 +arc: A6 N1_V02S0301 +arc: B3 V02S0101 +arc: B5 W1_H02E0301 +arc: B7 H02W0301 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0701 F7 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C79:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C80:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 H01E0101 +arc: A4 H02E0501 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 Q7 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0401 Q4 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICEC.K0.INIT 0101101001011010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C81:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B3 H02E0101 +arc: B5 H01E0101 +arc: E1_H01E0001 F7 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C82:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A2 V00B0000 +arc: A3 N1_V02S0501 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B4 H02E0101 +arc: B7 H02E0301 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C83:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: V00B0100 H02E0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 H01W0000 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: V00B0000 Q4 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C86:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R81C89:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C91:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C92:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R81C94:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C95:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C98:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R83C100:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C101:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C102:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C103:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 + +.tile R83C104:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C105:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R83C106:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C107:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R83C108:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C109:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 + +.tile R83C110:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R83C111:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 + +.tile R83C112:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C114:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C115:PLC2 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R83C117:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C118:PLC2 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C14:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R83C15:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R83C20:PLC2 +arc: N3_V06N0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R83C21:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R83C26:PLC2 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R83C32:PLC2 +arc: C5 V02N0001 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1111000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R83C33:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: W1_H02W0201 V06S0103 + +.tile R83C34:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: A0 H00L0000 +arc: B0 E1_H02W0101 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0111010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0401 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B5 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 H00R0000 +arc: D5 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C36:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C37:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 H01E0101 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C38:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B6 V02N0701 +arc: B7 H02W0301 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0701 Q7 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: V01S0000 F2 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R83C39:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F4 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C3:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R83C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0701 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H01E0001 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0001001100110011 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111011001100 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C41:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q6 +arc: V00B0100 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C42:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V06S0303 +arc: A0 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A7 H00R0000 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000100 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICEC.K1.INIT 0010001100110011 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R83C43:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 V02N0301 +arc: A1 S1_V02N0501 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B5 H00R0000 +arc: C0 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0203 F4 +arc: V00T0000 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000010 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R83C44:PLC2 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 W1_H02E0701 +arc: A3 N1_V02S0501 +arc: B3 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 W1_H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F6 +arc: V01S0000 F6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R83C45:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 W1_H02E0201 + +.tile R83C46:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C6 V00T0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0101111101001110 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R83C47:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 F0 +arc: D3 V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: M0 H01E0001 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEA.K1.INIT 0000000001000101 +word: SLICEB.K0.INIT 0000001110110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C48:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 W1_H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02N0301 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1101010110000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000000010001100 +word: SLICED.K1.INIT 0001001111011111 +word: SLICEB.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 0000010000000101 +word: SLICEC.K0.INIT 0000010111010101 +word: SLICED.K0.INIT 0011001111111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C49:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A6 H02W0701 +arc: A7 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C2 V02S0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M5 H02W0001 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0501 Q7 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q7 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000100000111111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K0.INIT 0000001110110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C50:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A7 V02N0101 +arc: B1 W1_H02E0101 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0303 F6 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C51:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010001100000000 +word: SLICEB.K0.INIT 0101010111111100 +word: SLICED.K0.INIT 0010101001111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C52:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 E1_H01W0100 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0100 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 0101111101011100 +word: SLICED.K1.INIT 0101001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R83C53:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 N1_V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0501 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010011110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C54:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 V02S0701 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000000000100011 +word: SLICEC.K1.INIT 0000010110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A4 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 Q5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q6 +arc: V01S0100 Q4 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 0101010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 W1_H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C57:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0601 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: V01S0000 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0101001111110011 +word: SLICEB.K0.INIT 1111101101010001 +word: SLICEB.K1.INIT 1110101001000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: A1 H02E0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 E1_H01W0000 +arc: A5 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 V02S0701 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0101111100110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 0011111100111010 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 F5 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: V01S0100 F5 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000000000001011 +word: SLICEB.K1.INIT 0000110101010101 +word: SLICEC.K0.INIT 0010000000111111 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C60:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06S0303 +arc: A1 H00R0000 +arc: A3 W1_H02E0501 +arc: A6 S1_V02N0301 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 H01E0101 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +arc: W1_H02W0401 F4 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000101100110011 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0011000101010101 +word: SLICEC.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R83C61:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 + +.tile R83C62:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0401 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 F4 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000010001000 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICED.K1.INIT 0000110000000000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C63:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 F1 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 1111111011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: A0 V02S0501 +arc: A1 E1_H02W0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H01E0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V01S0100 F4 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111101100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R83C65:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B5 H02W0301 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C6 H02W0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 F2 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111111111101010 +word: SLICEC.K1.INIT 1000100001000100 +word: SLICEB.K0.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C66:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: A0 H02W0501 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 Q4 +arc: C5 V00T0100 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110101011000000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110101011000000 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 Q5 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101000011011100 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICEB.K0.INIT 1111100010001000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110110010100000 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1110110010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C68:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A4 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B4 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C69:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: C0 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000110010101110 +word: SLICEB.K0.INIT 1100111000001010 +word: SLICEB.K1.INIT 0011101100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C70:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M1 H00R0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F1 +arc: V01S0000 Q7 +arc: V01S0100 F1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0101000001010000 +word: SLICEA.K0.INIT 0000110001011100 +word: SLICEC.K0.INIT 1010000011101100 +word: SLICEC.K1.INIT 0101110100001100 +word: SLICED.K0.INIT 0101000011011100 +word: SLICED.K1.INIT 1010000011101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C71:PLC2 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02E0701 +arc: A3 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B3 V02N0301 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 V02S0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 1100110000111100 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 1001101010010101 +word: SLICEA.K0.INIT 1111110001011100 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111111000110010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C72:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 H00L0000 +arc: B0 H02W0301 +arc: B2 H02W0301 +arc: B4 H02W0301 +arc: B6 H02W0301 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 E1_H02W0201 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0010110100111100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0110010101010101 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K0.INIT 0110011001010110 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0110011001010110 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R83C73:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: LSR0 V00T0100 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: S3_V06S0303 F5 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000110011011100 +word: SLICEA.K1.INIT 1111010010110000 +word: SLICEB.K0.INIT 1101110010001100 +word: SLICEB.K1.INIT 1000110011011100 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1010111110101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R83C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: B0 H02E0301 +arc: B2 H02E0301 +arc: B4 V02N0501 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 0101101000011110 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0101100101010101 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K0.INIT 0010001111011100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0011000111001110 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R83C75:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 H01E0001 +arc: A6 H02W0501 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D6 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 F4 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F1 +arc: V01S0000 F3 +arc: V01S0100 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICED.K0.INIT 0111000000000000 +word: SLICEB.K1.INIT 0101010110101010 +word: SLICEA.K1.INIT 1111000011111111 +word: SLICEC.K1.INIT 1100000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R83C76:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C0 W1_H02E0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V00T0100 F1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R83C77:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0301 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 F2 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEA.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1100110001011100 +word: SLICEC.K1.INIT 1100110010101100 +word: SLICED.K0.INIT 1100110010101100 +word: SLICED.K1.INIT 1100110001011100 +word: SLICEB.K0.INIT 0000101000001111 +word: SLICEB.K1.INIT 0000001000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C78:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 H00L0100 +arc: A4 H02W0501 +arc: A6 H02E0501 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B4 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 H00R0100 +arc: C2 H00R0100 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D4 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: N1_V01N0001 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C79:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B1 N1_V02S0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 F0 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 0000100100000000 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C80:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: A2 F7 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: S3_V06S0103 F2 +arc: V01S0000 F3 +arc: W1_H02W0301 F1 +arc: W3_H06W0103 F1 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000000001010000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R83C81:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: B0 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C82:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: A4 V02S0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B5 N1_V02S0501 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C83:PLC2 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 N1_V02S0701 +arc: A4 W1_H02E0501 +arc: B4 H00L0000 +arc: C4 W1_H02E0601 +arc: D4 N1_V02S0401 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: N3_V06N0203 F4 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000001001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R83C84:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile R83C85:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R83C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C87:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R83C88:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C89:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C90:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C91:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R83C92:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R83C93:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R83C94:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 + +.tile R83C95:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C96:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C97:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C98:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C99:PLC2 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 + +.tile R84C100:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C103:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R84C105:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C106:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R84C108:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R84C109:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C111:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R84C112:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R84C115:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C32:PLC2 +arc: N1_V02N0001 S1_V02N0501 + +.tile R84C33:PLC2 +arc: E1_H02E0001 E3_H06W0003 + +.tile R84C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 + +.tile R84C35:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00T0000 V02N0601 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: A4 H02W0701 +arc: B3 H02E0101 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R84C36:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 V01N0101 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A6 H02E0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 V00T0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R84C37:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: A0 H00R0000 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 V02S0101 +arc: B1 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C4 H02E0401 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q6 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100000010101010 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R84C38:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A4 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1010000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C39:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N1_V01S0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V00B0000 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0001 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0100000000000000 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEC.K1.INIT 1000000011110000 +word: SLICEB.K1.INIT 1000000011001100 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C40:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100000011110000 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICEC.K0.INIT 0100110000001000 +word: SLICED.K1.INIT 1100010010000000 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R84C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0101010011111100 +word: SLICED.K0.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0010100000000000 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C42:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V06N0003 +arc: A2 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C43:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0010100000000000 +word: SLICED.K0.INIT 0010000010000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R84C44:PLC2 +arc: E1_H02E0601 H01E0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C45:PLC2 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 H01E0001 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V00T0100 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000100000100 +word: SLICEC.K0.INIT 0010100000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R84C46:PLC2 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 + +.tile R84C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K0.INIT 0101111101011100 +word: SLICEA.K0.INIT 1010101011001111 +word: SLICEA.K1.INIT 1010101011000000 +word: SLICEB.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 0000010000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 F7 +arc: A1 F7 +arc: A3 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B3 S1_V02N0301 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 V02S0001 +arc: D5 H02W0201 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 0011001011111110 +word: SLICEB.K1.INIT 0101010111111100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R84C49:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q2 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0601 F4 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011011101 +word: SLICED.K1.INIT 1111000010001000 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C50:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 H01E0101 +arc: A2 E1_H02W0501 +arc: A5 V02S0101 +arc: A7 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H02W0301 +arc: B3 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 1111000000110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R84C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 0100011111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C52:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000010101100 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0001101110111011 +word: SLICED.K0.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C53:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 0000000011011000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 0101010111111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C54:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0501 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 N1_V02S0301 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0501 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011111101010101 +word: SLICED.K0.INIT 0101111100110011 +word: SLICEC.K0.INIT 1100101011001111 +word: SLICEC.K1.INIT 1100101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R84C55:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A1 F7 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K1.INIT 1111000010100000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 0111011101110100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R84C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A6 F7 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B3 H00L0000 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C3 E1_H01W0000 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0101010111111100 +word: SLICED.K1.INIT 0101111100110011 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C57:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 F7 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 F4 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +arc: W1_H02W0301 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 0001101110111011 +word: SLICEC.K1.INIT 0010101001111111 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0101010111111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R84C58:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C3 V02S0401 +arc: C5 H01E0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H01W0100 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110011 +word: SLICED.K1.INIT 1010101011000000 +word: SLICEA.K1.INIT 0010101001111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R84C59:PLC2 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 H02E0601 +arc: M3 W1_H02E0201 +arc: M4 V00T0100 +arc: M6 N1_V01N0101 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000001000000011 +word: SLICEC.K0.INIT 1100110010101111 +word: SLICEC.K1.INIT 1111100000001000 +word: SLICEA.K1.INIT 0101111101011100 +word: SLICED.K0.INIT 1100110010101111 +word: SLICED.K1.INIT 1111000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R84C60:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F7 +arc: A1 F7 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C7 W1_H02E0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V02N0201 F2 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICEA.K1.INIT 0000001000000011 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000001000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C61:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E1_H02W0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 + +.tile R84C62:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: A0 H00L0100 +arc: A3 V01N0101 +arc: A4 V00B0000 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B6 V02N0501 +arc: C0 F4 +arc: C1 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 1111111011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C63:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 V06S0203 +arc: A0 F5 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 F3 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C64:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEB.K1.INIT 0000000011000000 +word: SLICEA.K1.INIT 1111111011111100 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C65:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0501 +arc: A1 F5 +arc: A2 F7 +arc: A4 H02E0701 +arc: A5 E1_H02W0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000011111111 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C66:PLC2 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 V06S0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B6 F3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: V00T0000 Q0 +arc: V01S0100 F1 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011000000 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R84C67:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C0 V02S0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000010100000 +word: SLICEC.K0.INIT 0000101011001110 +word: SLICEC.K1.INIT 1100111000001010 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C68:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H02W0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: H01W0100 F0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F6 +arc: V00B0000 Q6 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011101000110000 +word: SLICEA.K1.INIT 0011000010111010 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1010101001010101 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1010111011101010 +word: SLICEC.K1.INIT 1110101010101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C69:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 F0 +arc: D6 F0 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1111111110010000 +word: SLICEC.K1.INIT 1111111101100000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 1111111101100000 +word: SLICED.K1.INIT 1111111110010000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1100111011101100 +word: SLICEB.K1.INIT 1110110011001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 H02E0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02S0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 0010111011100010 +word: SLICEC.K1.INIT 1011100001110100 +word: SLICED.K0.INIT 1011100001110100 +word: SLICED.K1.INIT 0111010010111000 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEB.K0.INIT 0000110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R84C71:PLC2 +arc: H00R0000 V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A4 V02N0301 +arc: B3 H01W0100 +arc: B4 F3 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: LSR1 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0601 F4 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1010010110010101 +word: SLICEB.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R84C72:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H01E0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V01N0101 +arc: A4 E1_H02W0501 +arc: A5 V02N0101 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B5 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1110000000011111 +word: SLICEB.K0.INIT 1010101011000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R84C73:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H01W0100 +arc: B6 V02N0701 +arc: C0 V02S0401 +arc: D0 V02S0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R84C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 V06S0303 + +.tile R84C75:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 F1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02S0601 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: V01S0000 F1 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K1.INIT 1010010110100101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1001100111110000 +word: SLICEC.K1.INIT 0110011011110000 +word: SLICED.K0.INIT 0110011011110000 +word: SLICED.K1.INIT 1001100111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 V01N0001 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 H01E0001 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 Q5 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H01W0000 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0501 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 F0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0100111011100100 +word: SLICEA.K1.INIT 1110010001001110 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0010111011100010 +word: SLICED.K0.INIT 1100101000111010 +word: SLICED.K1.INIT 0011101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 V02N0101 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEB.K0.INIT 0101110010101100 +word: SLICEB.K1.INIT 1010110001011100 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICEA.K0.INIT 0110111101100000 +word: SLICEA.K1.INIT 1010110001011100 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R84C78:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 F5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 F0 +arc: V01S0000 Q3 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 0101101011001100 +word: SLICEC.K1.INIT 1010010111001100 +word: SLICED.K0.INIT 1010110001011100 +word: SLICED.K1.INIT 0101101011001100 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R84C79:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR1 H02E0501 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q7 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1110010001001110 +word: SLICEB.K1.INIT 0100111011100100 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICED.K0.INIT 0110111101100000 +word: SLICED.K1.INIT 1100101000111010 +word: SLICEA.K0.INIT 1001111110010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C80:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A6 F5 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0001 F0 +arc: N1_V02N0701 F5 +arc: N3_V06N0303 F6 +arc: V01S0100 F7 +arc: W1_H02W0201 F0 +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R84C81:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 + +.tile R84C82:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C84:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C85:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R84C87:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R84C88:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C90:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R84C91:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R84C93:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R84C94:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C96:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R84C99:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R85C34:PLC2 +arc: E1_H02E0201 V02S0201 + +.tile R85C35:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 V02S0001 +arc: N1_V02N0501 E1_H01W0100 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1100000010101010 +word: SLICEC.K1.INIT 1100000010101010 +word: SLICED.K0.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C36:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 V02S0301 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 0011000011001100 +word: SLICEB.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C37:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C38:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: A1 H02W0501 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C39:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 H00R0000 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R85C40:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 F5 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 V02S0701 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEB.K0.INIT 0001001001001000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010100110011010 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0110100110010110 +word: SLICEB.K1.INIT 1100110000110011 +word: SLICEB.K0.INIT 1100100111000110 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1111000010010110 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0301 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001010100101010 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +word: SLICEA.K1.INIT 0101000011001100 +word: SLICEB.K0.INIT 0111001101000000 +word: SLICEB.K1.INIT 0011111100101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C43:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 H01E0101 +arc: A2 F5 +arc: A3 V02N0701 +arc: A5 H02W0701 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F7 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0010000010000000 +word: SLICEC.K1.INIT 0000000010010110 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000110010101100 +word: SLICED.K0.INIT 1110101100010100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V01N0101 +arc: A0 V02S0701 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: C0 N1_V02S0401 +arc: C1 V02S0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR1 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111011100000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000101011001010 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C45:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H02E0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A2 H01E0001 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B3 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: N1_V01N0001 F7 +arc: V01S0000 F5 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1111101011001000 +word: SLICEB.K0.INIT 0000000001010101 +word: SLICEB.K1.INIT 0011111100101010 +word: SLICED.K0.INIT 0111011101110000 +word: SLICEA.K1.INIT 0011001011111010 +word: SLICEC.K0.INIT 0101111101001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0101111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C46:PLC2 +arc: W1_H02W0401 H01E0001 + +.tile R85C47:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06W0203 + +.tile R85C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 + +.tile R85C49:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: A0 N1_V02S0701 +arc: A4 N1_V02S0101 +arc: A5 V02S0101 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C50:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B6 E1_H02W0301 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00T0000 F0 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 0101010111111100 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R85C51:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C3 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001110111011101 +word: SLICEC.K1.INIT 0001110111011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C52:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H02W0101 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C53:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 W1_H02E0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 N1_V02S0301 +arc: B4 V02N0701 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 N1_V02S0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V01S0000 F3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1011100000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 0001110111011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C54:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 N1_V02S0501 +arc: A5 V00B0000 +arc: A6 V02N0301 +arc: A7 F5 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 N1_V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C55:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 V01N0001 +arc: A1 N1_V02S0701 +arc: A3 V00B0000 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 0010101001111111 +word: SLICEB.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R85C56:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02S0601 +arc: D5 N1_V02S0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000010111000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: A1 H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B4 H01E0101 +arc: B5 F1 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0203 F7 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000011011000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 0001110111011101 +word: SLICEC.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C58:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: B0 H02E0301 +arc: B1 W1_H02E0101 +arc: B3 V02S0301 +arc: B5 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 Q1 +arc: V00T0000 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R85C59:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0701 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 Q6 +arc: V00T0100 F1 +arc: V01S0100 F6 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICED.K0.INIT 0011001111111010 +word: SLICEA.K1.INIT 0000111011111110 +word: SLICEB.K0.INIT 1111000010111011 +word: SLICEB.K1.INIT 1110101001000000 +word: SLICED.K1.INIT 0000111011111110 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C60:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B6 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C6 E1_H02W0401 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0001 F0 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0100 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEA.K0.INIT 1110111101000101 +word: SLICEA.K1.INIT 1110101001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C61:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0401 H01E0001 +arc: A3 V00B0000 +arc: B2 H01W0100 +arc: B3 N1_V02S0101 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R85C62:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00L0100 V02N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 V01N0101 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H02E0601 +arc: C3 E1_H01W0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000010100000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H01E0001 +arc: A1 F7 +arc: A2 V02N0701 +arc: A4 F7 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: C0 F6 +arc: C1 F4 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101010101010101 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C64:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: A0 F7 +arc: A1 E1_H02W0501 +arc: A2 F7 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0701 +arc: B0 N1_V02S0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B5 S1_V02N0501 +arc: B6 F1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0301 F1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0011001111111111 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R85C65:PLC2 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q5 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 1111100010001000 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1110101011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C66:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0601 E3_H06W0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0701 + +.tile R85C67:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F7 +arc: V00T0000 Q2 +arc: V01S0000 F1 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q4 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111100010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C68:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: V01S0000 F6 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1110110011001110 +word: SLICEA.K1.INIT 1100111011101100 +word: SLICEB.K0.INIT 1111111100101000 +word: SLICEB.K1.INIT 1111111110000010 +word: SLICEC.K0.INIT 1111010011111000 +word: SLICEC.K1.INIT 1111100011110100 +word: SLICED.K0.INIT 0011101100001010 +word: SLICED.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C69:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 F0 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 F0 +arc: V01S0000 F2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1011100001110100 +word: SLICEB.K1.INIT 0111010010111000 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111101101001000 +word: SLICEA.K0.INIT 1100110000110011 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1010000011101100 +word: SLICED.K1.INIT 0000101011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C70:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1011011110000100 +word: SLICEB.K1.INIT 0101101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICEA.K1.INIT 0111010010111000 +word: SLICED.K0.INIT 1100111011101100 +word: SLICED.K1.INIT 1110110011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1001111110010000 +word: SLICEB.K0.INIT 1001100111110000 +word: SLICEB.K1.INIT 0011110010101010 +word: SLICED.K1.INIT 0011001111001100 +word: SLICEA.K1.INIT 0000101000001010 +word: SLICEC.K0.INIT 1111001011111000 +word: SLICEC.K1.INIT 1111100011110010 +word: SLICED.K0.INIT 1100110011000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R85C72:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0001111011100001 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1110000100011110 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEA.K1.INIT 0101100101011010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110011 +word: SLICEA.K0.INIT 1010101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C73:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F1 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 F1 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F1 +word: SLICEC.K1.INIT 0011001111001100 +word: SLICEB.K0.INIT 1110101000010101 +word: SLICEB.K1.INIT 0001010111101010 +word: SLICEA.K0.INIT 0001010111101010 +word: SLICEA.K1.INIT 1110101000010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: B0 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H02W0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 W1_H02E0501 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1001100110010110 +word: SLICEC.K0.INIT 0011110001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R85C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A6 F7 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0601 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: LSR1 V00T0000 +arc: M2 W1_H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F6 +arc: S3_V06S0203 F7 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 0101101000011110 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEC.K1.INIT 0011110000111100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0111110100101000 +word: SLICEB.K1.INIT 1101011110000010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0101 F1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 0001010111101010 +word: SLICEA.K1.INIT 1110101000010101 +word: SLICEB.K0.INIT 1110101000010101 +word: SLICEB.K1.INIT 0001010111101010 +word: SLICEC.K0.INIT 0111101101001000 +word: SLICEC.K1.INIT 1011011110000100 +word: SLICED.K0.INIT 1100001110101010 +word: SLICED.K1.INIT 0011110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 0011101011001010 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 0101110010101100 +word: SLICED.K1.INIT 1110010001001110 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEA.K1.INIT 1100101000111010 +word: SLICEB.K0.INIT 0110111101100000 +word: SLICEB.K1.INIT 0110111101100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C78:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: A0 H02W0701 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 Q1 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 0111110100101000 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0111001011011000 +word: SLICEC.K0.INIT 1110010001001110 +word: SLICEC.K1.INIT 0100111011100100 +word: SLICED.K0.INIT 0111101101001000 +word: SLICED.K1.INIT 1011011110000100 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C79:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0501 Q5 +arc: V01S0000 F0 +arc: V01S0100 F4 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEA.K1.INIT 0011101011001010 +word: SLICEB.K0.INIT 0111101101001000 +word: SLICEB.K1.INIT 1011011110000100 +word: SLICEC.K0.INIT 1011100001110100 +word: SLICEC.K1.INIT 0111010010111000 +word: SLICED.K0.INIT 0101110010101100 +word: SLICED.K1.INIT 1010110001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C80:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 S1_V02N0301 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F1 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 F7 +arc: V00B0000 Q6 +arc: V01S0100 F7 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000000001111 +word: SLICED.K1.INIT 0000111111110000 +word: SLICEA.K0.INIT 0111001011011000 +word: SLICEA.K1.INIT 1101100001110010 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0010111011100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C81:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 + +.tile R85C82:PLC2 +arc: W1_H02W0401 S1_V02N0401 + +.tile R85C83:PLC2 +arc: W3_H06W0003 N3_V06S0003 + +.tile R86C17:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R86C23:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R86C29:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R86C32:PLC2 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0501 H06W0303 + +.tile R86C35:PLC2 +arc: N1_V02N0501 H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R86C37:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 + +.tile R86C38:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02E0701 + +.tile R86C39:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 + +.tile R86C40:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: B0 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 V01N0001 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C3 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 H02W0401 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEB.K0.INIT 1100110000110011 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEA.K0.INIT 0110100101101001 +word: SLICEB.K1.INIT 1001011001101001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R86C41:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V01N0101 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A3 F5 +arc: A4 F5 +arc: A5 Q5 +arc: A6 V02S0101 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 0100000100010100 +word: SLICED.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C42:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A3 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A5 Q5 +arc: A6 W1_H02E0501 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: S1_V02S0001 Q2 +arc: V00B0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0011111100101010 +word: SLICEB.K0.INIT 0011111100101010 +word: SLICEB.K1.INIT 0011111100101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0011001011111010 +word: SLICED.K0.INIT 0100010011100100 +word: SLICED.K1.INIT 0011001011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C43:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A4 H02E0501 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F5 +arc: S1_V02S0301 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICED.K0.INIT 0110100110010110 +word: SLICED.K1.INIT 1001011001101001 +word: SLICEA.K1.INIT 0000101011001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICEB.K1.INIT 0000000011111100 +word: SLICEC.K0.INIT 0111001001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C44:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0501 W3_H06E0303 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B6 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEC.K0.INIT 0000010101010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010010101011010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000000010011001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C45:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 N3_V06S0303 + +.tile R86C46:PLC2 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 + +.tile R86C47:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 + +.tile R86C48:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W3_H06E0003 + +.tile R86C49:PLC2 +arc: N1_V02N0001 E1_H02W0001 + +.tile R86C50:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0601 H02W0601 + +.tile R86C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0303 Q6 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V01S0000 Q6 +word: SLICED.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C52:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V01S0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: A6 F7 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C53:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06S0003 +arc: A5 V02S0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B5 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0011001100100011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C54:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0701 V06S0203 +arc: A1 W1_H02E0701 +arc: A2 V00T0000 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C55:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: A4 V00T0000 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V02N0101 +arc: A3 H02W0501 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1000010010100101 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C57:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0100 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C58:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 V02N0601 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A4 F7 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 0011111101010101 +word: SLICEB.K0.INIT 1010001011110011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R86C59:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C60:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N3_V06S0303 + +.tile R86C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V06S0203 + +.tile R86C62:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: A0 F5 +arc: A2 F5 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C63:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V02S0501 +arc: A4 V02N0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B4 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 H00L0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R86C64:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A6 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 F4 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0011001111111111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000111111111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000111100001111 +word: SLICEB.K0.INIT 1000111100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C65:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 E1_H01W0000 + +.tile R86C66:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0701 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100111011101100 +word: SLICEB.K1.INIT 1110110011001110 +word: SLICEC.K1.INIT 1000001000101000 +word: SLICEA.K0.INIT 1010111110101010 +word: SLICEA.K1.INIT 0101000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C67:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0501 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: V01S0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1010111011101010 +word: SLICEB.K1.INIT 1110101010101110 +word: SLICEC.K0.INIT 1110101110101010 +word: SLICEC.K1.INIT 1101111011001100 +word: SLICEA.K0.INIT 0100111101000100 +word: SLICEA.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 1100111011101100 +word: SLICED.K1.INIT 1110110011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F6 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 0010111011100010 +word: SLICEA.K1.INIT 1110001000101110 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 0000110010101110 +word: SLICEC.K0.INIT 1110110011011100 +word: SLICEC.K1.INIT 1101110011101100 +word: SLICED.K0.INIT 1111111110010000 +word: SLICED.K1.INIT 1111111101100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C69:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 N1_V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0100 F5 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0111110100101000 +word: SLICEC.K1.INIT 1101011110000010 +word: SLICED.K0.INIT 1101011110000010 +word: SLICED.K1.INIT 0111110100101000 +word: SLICEB.K0.INIT 0010111011100010 +word: SLICEB.K1.INIT 1110001000101110 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0100111011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C70:PLC2 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1011100001110100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0111110100101000 +word: SLICEC.K1.INIT 1101011110000010 +word: SLICED.K0.INIT 1101011110000010 +word: SLICED.K1.INIT 0111110100101000 +word: SLICEB.K0.INIT 0101101010100101 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R86C71:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A4 V02S0301 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B4 V02S0701 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100101000111010 +word: SLICEA.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 0001111011100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R86C72:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 V01N0101 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: C0 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100110000000101 +word: SLICEB.K1.INIT 1111000001010101 +word: SLICEA.K0.INIT 1100111100000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C73:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 E1_H02W0301 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 V06S0203 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 0011110000110011 +word: SLICEA.K1.INIT 1010010111110000 +word: SLICEB.K0.INIT 1010010111110000 +word: SLICEB.K1.INIT 0101101000001111 +word: SLICEC.K0.INIT 0011000111001110 +word: SLICEC.K1.INIT 1100111000110001 +word: SLICED.K0.INIT 1100110000111001 +word: SLICED.K1.INIT 0011000111001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C75:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 E1_H02W0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: LSR0 E1_H02W0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0110011001101001 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEB.K0.INIT 1101011110000010 +word: SLICEB.K1.INIT 0111110100101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0301 V02N0301 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 W1_H02E0001 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 W1_H02E0001 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C77:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V01N0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: A2 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 N1_V02S0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0110111101100000 +word: SLICEB.K1.INIT 0011110011000011 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0101110010101100 +word: SLICED.K0.INIT 1001111110010000 +word: SLICED.K1.INIT 0110111101100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0111101101001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 W1_H02E0401 +arc: M5 H00R0100 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 0100111011100100 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 1110010001001110 +word: SLICED.K1.INIT 0100111011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C79:PLC2 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H00R0100 F5 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR1 H02E0501 +arc: M0 W1_H02E0601 +arc: M1 H02E0001 +arc: M2 W1_H02E0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1110010001001110 +word: SLICEA.K1.INIT 0111001011011000 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICED.K0.INIT 0011101011001010 +word: SLICED.K1.INIT 1100101000111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C80:PLC2 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0701 W1_H02E0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0301 +arc: B2 H00R0100 +arc: B3 Q3 +arc: C0 V02S0601 +arc: C2 V02S0601 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1101011110000010 +word: SLICEB.K1.INIT 0100111011100100 +word: SLICEA.K0.INIT 0111110100101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C81:PLC2 +arc: W1_H02W0301 V06S0003 + +.tile R87C11:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R87C17:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R87C23:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R87C29:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R87C2:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R87C35:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R87C37:PLC2 +arc: N1_V02N0501 E1_H02W0501 + +.tile R87C38:PLC2 +arc: E1_H02E0701 V06S0203 + +.tile R87C39:PLC2 +arc: N1_V02N0701 H02E0701 +arc: W1_H02W0501 N3_V06S0303 + +.tile R87C40:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 E1_H02W0601 +arc: A0 H00L0000 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C41:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICED.K1.INIT 0110100110010110 +word: SLICEC.K1.INIT 0110100110010110 +word: SLICEC.K0.INIT 0110011010011001 +word: SLICED.K0.INIT 0110011010011001 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1101110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R87C42:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H00R0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 W1_H02E0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q3 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110000000011 +word: SLICEC.K1.INIT 0000100100000110 +word: SLICED.K0.INIT 1001011010010110 +word: SLICEA.K1.INIT 0110100110010110 +word: SLICED.K1.INIT 0101101010100101 +word: SLICEC.K0.INIT 1001011001101001 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C43:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F5 +arc: A1 H00R0000 +arc: A3 H02W0501 +arc: A7 W1_H02E0701 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B7 H01E0101 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H02W0601 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 Q0 +arc: V01S0000 F7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0011001111001100 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000101000000101 +word: SLICED.K1.INIT 1001000010010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R87C44:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A5 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B7 V02S0701 +arc: C0 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0701 F5 +arc: W1_H02W0501 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0011001111001100 +word: SLICEC.K1.INIT 0101010110101010 +word: SLICEA.K1.INIT 1001100101100110 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000100100000110 +word: SLICEB.K0.INIT 0110011010011001 +word: SLICEA.K0.INIT 0000100100000110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R87C45:PLC2 +arc: N1_V02N0201 W1_H02E0201 + +.tile R87C46:PLC2 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 + +.tile R87C47:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R87C48:PLC2 +arc: A0 V02N0701 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 V02N0401 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A5 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D5 V02N0401 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0110011011000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 0000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R87C50:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: A0 H00L0000 +arc: A4 E1_H01W0000 +arc: A6 H02E0701 +arc: B0 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V02N0701 +arc: C0 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: D0 H02W0201 +arc: D4 W1_H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R87C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: V00T0000 H02W0201 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R87C52:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: A3 N1_V02S0501 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: B6 V00T0000 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R87C53:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R87C54:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: A4 V00B0000 +arc: A5 N1_V02S0301 +arc: B0 N1_V02S0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R87C55:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: F0 F0_SLICE +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R87C56:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: W1_H02W0001 N1_V02S0001 + +.tile R87C57:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 + +.tile R87C58:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0601 N3_V06S0303 + +.tile R87C59:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 + +.tile R87C5:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R87C61:PLC2 +arc: E1_H02E0001 E3_H06W0003 + +.tile R87C62:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 + +.tile R87C63:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 + +.tile R87C64:PLC2 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 + +.tile R87C65:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0301 +arc: C0 S1_V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0100 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R87C66:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 F2 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N3_V06N0203 Q4 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111111100101000 +word: SLICEA.K1.INIT 1111111110000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C67:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010111011101010 +word: SLICEA.K1.INIT 1110101010101110 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111100111110000 +word: SLICEB.K1.INIT 1111011011110000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111111100101000 +word: SLICEC.K1.INIT 1111111110000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C68:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 W1_H02E0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1110001000101110 +word: SLICEA.K1.INIT 0010111011100010 +word: SLICEB.K0.INIT 0010111011100010 +word: SLICEB.K1.INIT 1110001000101110 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111101101001000 +word: SLICED.K0.INIT 1110001000101110 +word: SLICED.K1.INIT 0010111011100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C69:PLC2 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C1 H00R0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEB.K0.INIT 1110001000101110 +word: SLICEB.K1.INIT 0010111011100010 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111110100101000 +word: SLICED.K0.INIT 1100001110101010 +word: SLICED.K1.INIT 0011101011001010 +word: SLICEA.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R87C70:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1110101010101110 +word: SLICEC.K1.INIT 1010111011101010 +word: SLICED.K0.INIT 1011111010101010 +word: SLICED.K1.INIT 1110101110101010 +word: SLICEA.K0.INIT 0011000011111111 +word: SLICEA.K1.INIT 1100110000110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R87C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C3 H00L0100 +arc: C5 V01N0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C72:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H01E0001 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F5 +arc: LSR0 V00T0100 +arc: M4 H02E0401 +arc: M5 H02E0001 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V01S0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010010111110000 +word: SLICEC.K1.INIT 0101101000001111 +word: SLICED.K0.INIT 1001100111001001 +word: SLICED.K1.INIT 0011001111000110 +word: SLICEA.K0.INIT 1111010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C73:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A5 V02S0101 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: D0 V02S0201 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: N3_V06N0003 F3 +word: SLICEA.K0.INIT 1011010001001011 +word: SLICEA.K1.INIT 1001011011000011 +word: SLICEB.K0.INIT 0110100100111100 +word: SLICEB.K1.INIT 0110100100111100 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 1001101001100101 +word: SLICED.K0.INIT 0011110011000011 +word: SLICED.K1.INIT 0110010110011010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R87C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 + +.tile R87C75:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1001100101101001 +word: SLICEA.K1.INIT 1001100101101001 +word: SLICEB.K0.INIT 0110011010010110 +word: SLICEB.K1.INIT 0110011010010110 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 1001011010011001 +word: SLICED.K0.INIT 0101101010100101 +word: SLICED.K1.INIT 0101100110100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R87C76:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 E1_H02W0601 +arc: M1 H02W0001 +arc: M2 E1_H02W0601 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1010101010100101 +word: SLICEA.K0.INIT 1010111101010000 +word: SLICEA.K1.INIT 0101000010101111 +word: SLICEB.K0.INIT 1011101001000101 +word: SLICEB.K1.INIT 0100010110111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R87C77:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 V01N0101 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICED.K1.INIT 0000111111110000 +word: SLICED.K0.INIT 0001111011100001 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEC.K0.INIT 0010111011100010 +word: SLICEC.K1.INIT 1110001000101110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H00L0100 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 0011110011000011 +word: SLICEA.K0.INIT 0011110010101010 +word: SLICEA.K1.INIT 1101100001110010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C79:PLC2 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: A0 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 F1 +arc: V01S0100 F5 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 0111110100101000 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 0100111011100100 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 1110010001001110 +word: SLICED.K1.INIT 0100111011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C80:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 + +.tile R87C81:PLC2 +arc: W1_H02W0001 S1_V02N0001 + +.tile R87C82:PLC2 +arc: N1_V02N0401 W3_H06E0203 + +.tile R88C41:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: V00T0100 N1_V02S0501 +arc: A0 V02S0501 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C42:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0001 +arc: A0 E1_H02W0501 +arc: A1 H02W0501 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R88C43:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A5 V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K1.INIT 1100101010101010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111011111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C44:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111101101000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEB.K0.INIT 0111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R88C45:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H01E0001 +arc: A1 F7 +arc: A6 E1_H01W0000 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: S1_V02S0701 F5 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 1100000011000000 +word: SLICED.K0.INIT 0000000001110101 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000110011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R88C46:PLC2 +arc: H00R0000 V02N0401 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V02N0101 +arc: B3 H00R0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D5 V02N0401 +arc: D7 V02N0601 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 F5 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1011101100000010 +word: SLICEB.K1.INIT 0011000000010001 +word: SLICEB.K0.INIT 1111000011110101 +word: SLICEC.K1.INIT 0011001100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R88C47:PLC2 +arc: W1_H02W0201 V02N0201 + +.tile R88C48:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: A0 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011001101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C49:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: A2 H01E0001 +arc: A3 V00B0000 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R88C50:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A3 V02S0701 +arc: A5 V02N0101 +arc: A7 E1_H01W0000 +arc: B2 V02S0101 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R88C51:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00R0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B1 V00B0000 +arc: B4 F1 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: V00B0000 Q4 +arc: V01S0000 Q5 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110110010100000 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R88C52:PLC2 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 + +.tile R88C53:PLC2 +arc: N1_V02N0401 N1_V01S0000 + +.tile R88C58:PLC2 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 + +.tile R88C63:PLC2 +arc: E1_H02E0501 V02S0501 + +.tile R88C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00L0000 H02W0201 +arc: H00L0100 V02S0301 +arc: N1_V02N0301 H02W0301 +arc: A0 H00L0100 +arc: B0 V01N0001 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0101110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C65:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C3 E1_H01W0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0000000000110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0100010011110000 +word: SLICEA.K1.INIT 0000001111000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: V00T0000 H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: A1 H01E0001 +arc: B1 E1_H01W0100 +arc: C0 F6 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D6 V02S0601 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R88C67:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0111001001010000 +word: SLICEA.K1.INIT 0101110100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C68:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02S0401 +arc: A0 H02E0701 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0100111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C69:PLC2 +arc: N1_V02N0101 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: A0 F7 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 V02N0301 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: V01S0000 F7 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 0011110011000011 +word: SLICED.K1.INIT 1001011001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C70:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02S0501 +arc: B0 V02N0301 +arc: B3 V02N0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 V00B0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C71:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A0 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B3 H00R0100 +arc: B5 H02E0301 +arc: C0 V02N0401 +arc: C3 H02W0401 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q3 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: B1 W1_H02E0301 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V02S0001 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: M0 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C73:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 H00L0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H02W0001 +arc: M6 H02W0401 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0011100111000110 +word: SLICEB.K0.INIT 0011011011001001 +word: SLICEB.K1.INIT 0011011011001001 +word: SLICEC.K0.INIT 0101101010100101 +word: SLICEC.K1.INIT 0110011010010110 +word: SLICED.K0.INIT 0101101001011010 +word: SLICED.K1.INIT 0101101001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C74:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 + +.tile R88C75:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 W3_H06E0003 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 E1_H02W0401 +arc: M5 H02E0001 +arc: M6 E1_H02W0401 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 0110011010010110 +word: SLICEA.K1.INIT 0110011010010110 +word: SLICEB.K0.INIT 0110011001101001 +word: SLICEB.K1.INIT 0110011001101001 +word: SLICEC.K0.INIT 0110100101101001 +word: SLICEC.K1.INIT 0110100101100110 +word: SLICED.K0.INIT 0011110000111100 +word: SLICED.K1.INIT 0110011001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C76:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00R0000 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1010101001011010 +word: SLICEA.K1.INIT 0101010110100101 +word: SLICEB.K0.INIT 0101010110100101 +word: SLICEB.K1.INIT 1010101001011010 +word: SLICEC.K0.INIT 1001100111001001 +word: SLICEC.K1.INIT 0110011000110110 +word: SLICED.K0.INIT 0110011000110110 +word: SLICED.K1.INIT 1001100111001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C77:PLC2 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 W1_H02E0401 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0110100101100110 +word: SLICEB.K0.INIT 1001011010011001 +word: SLICEB.K1.INIT 1001011010011001 +word: SLICEC.K0.INIT 0011110011000011 +word: SLICEC.K1.INIT 0110100101100110 +word: SLICED.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1001011010011001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C78:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0601 S1_V02N0601 + +.tile R88C79:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 + +.tile R88C80:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R88C81:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R89C12:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C15:PLC2 +arc: N3_V06N0203 H06W0203 + +.tile R89C18:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R89C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C21:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R89C24:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R89C25:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R89C30:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R89C31:PLC2 +arc: E1_H02E0001 W3_H06E0003 + +.tile R89C33:PLC2 +arc: V00T0000 W1_H02E0001 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0203 Q4 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C36:PLC2 +arc: N3_V06N0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C39:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R89C3:PLC2 +arc: N3_V06N0303 H06W0303 + +.tile R89C40:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 + +.tile R89C41:PLC2 +arc: V00B0100 W1_H02E0701 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C42:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile R89C43:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B6 V02N0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 V02N0001 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: W1_H02W0001 Q2 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1111110001001100 +word: SLICEA.K1.INIT 1111101000101010 +word: SLICEB.K0.INIT 1011111110100000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 0011000000000000 +word: SLICEB.K1.INIT 1111010011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C44:PLC2 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 H02W0701 +arc: A3 H00L0100 +arc: A7 H02W0501 +arc: B0 V02S0301 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: C0 V02S0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0110000010100000 +word: SLICEA.K0.INIT 0101110110000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEC.K1.INIT 0000110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R89C45:PLC2 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0701 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: N1_V01N0101 F6 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C46:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: D2 V02N0201 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R89C47:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: W1_H02W0101 W3_H06E0103 + +.tile R89C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C49:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00R0100 V02S0501 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C50:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C51:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0103 H06W0103 + +.tile R89C52:PLC2 +arc: W1_H02W0401 W3_H06E0203 + +.tile R89C54:PLC2 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C57:PLC2 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 H06W0103 + +.tile R89C60:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C64:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 E1_H02W0201 +arc: V00T0000 E1_H02W0201 +arc: B0 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C65:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0301 V01N0101 +arc: A0 H00R0000 +arc: A2 V02S0701 +arc: A3 H02W0701 +arc: A6 N1_V01S0100 +arc: B1 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C66:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 W1_H02E0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C4 Q4 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 H02E0501 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V00B0100 Q7 +arc: V01S0000 Q6 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +word: SLICED.K0.INIT 0100010011110000 +word: SLICED.K1.INIT 0101000011001100 +word: SLICEC.K1.INIT 0000101011001100 +word: SLICEC.K0.INIT 0011000010101010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R89C67:PLC2 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: B0 H02W0301 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K1.INIT 0011101100001000 +word: SLICEB.K0.INIT 0101110100001000 +word: SLICEA.K0.INIT 0000111110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C68:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 F7 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A5 N1_V01N0101 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B5 H00L0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M3 H00R0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F6 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEA.K0.INIT 0110110000001100 +word: SLICEA.K1.INIT 0000110000111100 +word: SLICEB.K0.INIT 0110110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000000001101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C69:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 + +.tile R89C6:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R89C70:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 + +.tile R89C71:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0110100101100110 +word: SLICEB.K0.INIT 1001011010011001 +word: SLICEB.K1.INIT 1001011010011001 +word: SLICEC.K0.INIT 0101101010100101 +word: SLICEC.K1.INIT 0110100101011010 +word: SLICED.K0.INIT 1010010101011010 +word: SLICED.K1.INIT 1001011010100101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R89C72:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1010111101010000 +word: SLICEA.K1.INIT 0101000010101111 +word: SLICEB.K0.INIT 0101000010101111 +word: SLICEB.K1.INIT 1010111101010000 +word: SLICEC.K0.INIT 1001110010011001 +word: SLICEC.K1.INIT 0110001101100110 +word: SLICED.K0.INIT 0110001101100110 +word: SLICED.K1.INIT 1001110010011001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R89C73:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 + +.tile R89C74:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E3_H06W0103 +arc: W1_H02W0401 N3_V06S0203 + +.tile R89C75:PLC2 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0103 N3_V06S0103 + +.tile R89C76:PLC2 +arc: N1_V02N0401 W1_H02E0401 + +.tile R89C77:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 + +.tile R89C78:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R89C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C80:PLC2 +arc: W3_H06W0103 N3_V06S0103 + +.tile R89C81:PLC2 +arc: N1_V02N0001 W3_H06E0003 + +.tile R89C84:PLC2 +arc: N3_V06N0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C90:PLC2 +arc: F7 F7_SLICE +arc: N3_V06N0203 F7 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C15:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R8C18:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R8C21:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R8C27:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R8C33:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 + +.tile R8C39:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R8C40:PLC2 +arc: H00L0000 V02S0201 +arc: H00R0000 N1_V02S0601 +arc: A0 S1_V02N0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B4 V02N0701 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 E1_H02W0601 +arc: M1 H02E0001 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C41:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 H00R0100 +arc: C1 F4 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C42:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 V02S0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A6 H02E0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0101 +arc: B6 V02S0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1000110111011000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C43:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02S0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: S3_V06S0103 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00R0100 V02S0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: B0 V02S0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C45:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C46:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: V00B0000 S1_V02N0201 +arc: A0 H00L0000 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C0 V02S0401 +arc: C2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1000101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: N1_V02N0201 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 H02E0701 +arc: A2 V01N0101 +arc: B0 H02E0101 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C49:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 V02S0701 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 H02E0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C50:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: A0 W1_H02E0701 +arc: A2 V02S0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B4 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H01E0001 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1000110111011000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C51:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 E1_H02W0701 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: B0 V01N0001 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C52:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A6 V02N0301 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q5 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C53:PLC2 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 V02S0701 +arc: A0 H02E0501 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H01W0000 Q6 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0601 Q6 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C57:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R8C63:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R8C66:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R8C7:PLC2 +arc: E1_H02E0201 S1_V02N0201 + +.tile R8C8:PLC2 +arc: V00T0000 H02E0201 +arc: CLK0 G_HPBX0000 +arc: D3 H02E0201 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 Q6 +arc: F3 F3_SLICE +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R8C9:PLC2 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q7 +arc: E3_H06E0203 Q4 +arc: H00R0000 Q6 +arc: LSR0 H02E0301 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C43:PLC2 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 + +.tile R90C44:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: A0 H02W0701 +arc: B0 N1_V02S0301 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0101010110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C45:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: B0 E1_H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0111001001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C46:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: V00T0000 W1_H02E0201 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R90C47:PLC2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R90C50:PLC2 +arc: N1_V02N0701 N1_V01S0100 + +.tile R90C64:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B7 H02W0101 +arc: C7 N1_V02S0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 0000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R90C65:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 N1_V02S0501 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +word: SLICEA.K0.INIT 0011101011000000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 0111010000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C66:PLC2 +arc: H00R0000 V02S0601 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A1 H00L0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 0010001011100010 +word: SLICEA.K1.INIT 0011000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C67:PLC2 +arc: W1_H02W0101 N1_V01S0100 + +.tile R90C68:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile R90C70:PLC2 +arc: N1_V02N0301 N3_V06S0003 + +.tile R90C71:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 + +.tile R90C72:PLC2 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 + +.tile R90C78:PLC2 +arc: N1_V02N0601 W3_H06E0303 + +.tile R91C71:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R91C75:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R9C39:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: V00B0000 V02N0001 +arc: A0 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R9C40:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V02S0501 +arc: A4 V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00B0100 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101000111000000 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100010111001010 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C42:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C43:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A4 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B2 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H01E0101 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010101000111100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C44:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 H02E0301 +arc: B6 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C45:PLC2 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C46:PLC2 +arc: E1_H02E0101 V06N0103 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: B0 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: E1_H02E0601 Q6 +arc: F0 F5A_SLICE +arc: LSR0 V00B0100 +arc: M0 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F0 +arc: S1_V02S0401 Q6 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C47:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0701 +arc: A2 V02S0701 +arc: A4 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F6 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C49:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A4 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1111000000100010 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C50:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 E1_H01E0001 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B6 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0501 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0501 +arc: A2 E1_H02W0501 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V02N0301 Q1 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C52:PLC2 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: A4 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 N1_V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C53:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 + +.tile TAP_R11C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R11C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R12C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R12C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R13C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R13C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R14C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R14C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R16C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R16C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R16C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R17C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R17C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R17C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R17C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R18C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R19C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R23C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R24C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R25C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R27C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + 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G_VPTX0000 + +.tile TAP_R29C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R30C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R31C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R32C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R33C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R35C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R36C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + 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TAP_R39C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R3C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R3C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R40C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R41C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + 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G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R43C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R43C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R44C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R44C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R45C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R45C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R47C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R48C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R49C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R49C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R4C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R4C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R50C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R50C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R51C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R52C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R5C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R5C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R60C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R67C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R68C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R69C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R6C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R6C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R71C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R71C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R71C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R73C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R73C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R74C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R74C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R75C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R77C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R77C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R77C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R78C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R78C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R79C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R79C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R79C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R7C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R7C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R80C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R80C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R80C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R84C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R84C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R84C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R89C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R89C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R89C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R8C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R8C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R8C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R90C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R9C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R9C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile_group MIB_R58C73:MIB_DSP4 MIB_R58C73:MIB2_DSP4 MIB_R58C74:MIB_DSP5 MIB_R58C74:MIB2_DSP5 MIB_R58C75:MIB_DSP6 MIB_R58C75:MIB2_DSP6 MIB_R58C76:MIB_DSP7 MIB_R58C76:MIB2_DSP7 MIB_R58C77:MIB_DSP8 MIB_R58C77:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R4C0:PLL0_UL MIB_R5C0:PLL1_UL +word: CLKI_DIV 0000100 +word: CLKFB_DIV 0000001 +word: CLKOP_DIV 0111011 +word: CLKOP_CPHASE 0011110 +word: CLKOP_FPHASE 000 +word: CLKOS_DIV 0000111 +word: CLKOS_CPHASE 0000000 +word: CLKOS_FPHASE 000 +word: CLKOS2_DIV 0000111 +word: CLKOS2_CPHASE 0000000 +word: CLKOS2_FPHASE 000 +word: CLKOS3_DIV 0000111 +word: CLKOS3_CPHASE 0000000 +word: CLKOS3_FPHASE 000 +word: PLL_LOCK_MODE 000 +word: KVCO 000 +word: LPF_CAPACITOR 00 +word: LPF_RESISTOR 0001000 +word: ICP_CURRENT 01100 +word: FREQ_LOCK_ACCURACY 00 +word: MFG_GMC_GAIN 000 +word: MFG_GMC_TEST 1110 +word: MFG1_TEST 000 +word: MFG2_TEST 000 +word: MFG_FORCE_VFILTER 0 +word: MFG_ICP_TEST 0 +word: MFG_EN_UP 0 +word: MFG_FLOAT_ICP 0 +word: MFG_GMC_PRESET 0 +word: MFG_LF_PRESET 0 +word: MFG_GMC_RESET 0 +word: MFG_LF_RESET 0 +word: MFG_LF_RESGRND 0 +word: MFG_GMCREF_SEL 10 +word: MFG_ENABLE_FILTEROPAMP 1 +enum: MODE EHXPLLL +enum: CLKOP_ENABLE ENABLED +enum: CLKOS_ENABLE ENABLED +enum: CLKOS2_ENABLE ENABLED +enum: CLKOS3_ENABLE ENABLED +enum: FEEDBK_PATH INT_OP +enum: CLKOP_TRIM_POL RISING +enum: CLKOP_TRIM_DELAY 0 +enum: CLKOS_TRIM_POL RISING +enum: CLKOS_TRIM_DELAY 0 +enum: OUTDIVIDER_MUXA DIVA +enum: OUTDIVIDER_MUXB DIVB +enum: OUTDIVIDER_MUXC DIVC +enum: OUTDIVIDER_MUXD DIVD +enum: STDBY_ENABLE DISABLED +enum: REFIN_RESET DISABLED +enum: SYNC_ENABLE DISABLED +enum: INT_LOCK_STICKY ENABLED +enum: DPHASE_SOURCE DISABLED +enum: PLLRST_ENA DISABLED +enum: INTFB_WAKE DISABLED + diff --git a/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.svf b/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.svf new file mode 100644 index 00000000..9c34af1a --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-1/ulx3s_lsc1_packet.svf @@ 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@@ -0,0 +1,32855 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command ` +read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v; +read_verilog -sv ulx3s_packet_top.sv ulx3s_core_pll.sv uart_bridge.sv uart_rx.sv uart_tx.sv ../../asic_core/rtl/lean_silicon_lsc1.sv ../../asic_core/rtl/lean_silicon_lsc1_mincore.sv ../../asic_core/rtl/lsc1_packet_frontend.sv ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_blake3_lifecycle.sv ../../asic_core/rtl/lsc1_response_payload_mux.sv ../../asic_core/rtl/lsc1_blake3_alias_check.sv ../../asic_core/rtl/lsc1_request_validator.sv ../../asic_core/rtl/lsc1_cell_alias_check.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv; +hierarchy -check -top ulx3s_packet_top; +proc; check; +synth_ecp5 -abc9 -nodffe -top ulx3s_packet_top; +write_json ulx3s_packet_top.json +' -- + +1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\DP16KD'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCUA'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: ulx3s_packet_top.sv +Parsing SystemVerilog input from `ulx3s_packet_top.sv' to AST representation. +Generating RTLIL representation for module `\ulx3s_packet_top'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: ulx3s_core_pll.sv +Parsing SystemVerilog input from `ulx3s_core_pll.sv' to AST representation. +Generating RTLIL representation for module `\ulx3s_core_pll'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: uart_bridge.sv +Parsing SystemVerilog input from `uart_bridge.sv' to AST representation. +Generating RTLIL representation for module `\uart_bridge'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: uart_rx.sv +Parsing SystemVerilog input from `uart_rx.sv' to AST representation. +Generating RTLIL representation for module `\uart_rx'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: uart_tx.sv +Parsing SystemVerilog input from `uart_tx.sv' to AST representation. +Generating RTLIL representation for module `\uart_tx'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: ../../asic_core/rtl/lean_silicon_lsc1.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lean_silicon_lsc1.sv' to AST representation. +Generating RTLIL representation for module `\lean_silicon_lsc1'. +Successfully finished Verilog frontend. + +9. Executing Verilog-2005 frontend: ../../asic_core/rtl/lean_silicon_lsc1_mincore.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lean_silicon_lsc1_mincore.sv' to AST representation. +Generating RTLIL representation for module `\lean_silicon_lsc1_mincore'. +Successfully finished Verilog frontend. + +10. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Warning: Replacing memory \staged_out_value with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:839 +Warning: Replacing memory \staged_out_present with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:838 +Warning: Replacing memory \staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:814, ../../asic_core/rtl/lsc1_packet_frontend.sv:556 +Warning: Replacing memory \scalar_staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:505 +Successfully finished Verilog frontend. + +11. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +12. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +13. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +14. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +15. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_blake3_lifecycle.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_blake3_lifecycle.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_blake3_lifecycle'. +Successfully finished Verilog frontend. + +16. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_response_payload_mux.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_response_payload_mux.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_response_payload_mux'. +Successfully finished Verilog frontend. + +17. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_blake3_alias_check.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_blake3_alias_check.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_blake3_alias_check'. +Successfully finished Verilog frontend. + +18. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_request_validator.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_request_validator.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_request_validator'. +Successfully finished Verilog frontend. + +19. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_cell_alias_check.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_cell_alias_check.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_cell_alias_check'. +Successfully finished Verilog frontend. + +20. Executing Verilog-2005 frontend: ../../asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `../../asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +21. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +22. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +23. Executing HIERARCHY pass (managing design hierarchy). + +23.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1_mincore +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \uart_tx +Used module: \uart_rx +Used module: \ulx3s_core_pll +Parameter \PACKET_MODE = 1'1 +Parameter \CLK_HZ = 10000000 + +23.2. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_bridge'. +Parameter \PACKET_MODE = 1'1 +Parameter \CLK_HZ = 10000000 +Generating RTLIL representation for module `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +23.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +23.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +23.5. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +23.6. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: \uart_tx +Used module: \uart_rx +Used module: \ulx3s_core_pll +Reprocessing module lsc1_packet_frontend because instantiated module lsc1_response_payload_mux has become available. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Warning: Replacing memory \staged_out_value with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:839 +Warning: Replacing memory \staged_out_present with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:838 +Warning: Replacing memory \staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:814, ../../asic_core/rtl/lsc1_packet_frontend.sv:556 +Warning: Replacing memory \scalar_staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:505 +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 + +23.7. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 + +23.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx'. + +23.9. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll + +23.10. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll +Removing unused module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx'. +Removing unused module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx'. +Removing unused module `\gf2n_mul_bitstream'. +Removing unused module `\lean_silicon_lsc1_mincore'. +Removing unused module `\uart_tx'. +Removing unused module `\uart_rx'. +Removing unused module `\uart_bridge'. +Removed 7 unused modules. + +24. Executing PROC pass (convert processes to netlists). + +24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. +Cleaned up 11 empty switches. + +24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 12 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866 in module leanvm_b_stream_alu. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575 in module lsc1_request_validator. +Marked 1 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547 in module lsc1_request_validator. +Removed 5 dead cases from process $proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155 in module lsc1_response_payload_mux. +Marked 36 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155 in module lsc1_response_payload_mux. +Marked 2 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143 in module lsc1_blake3_lifecycle. +Marked 5 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008 in module lsc1_stream_adapter. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721 in module lsc1_packet_tx. +Marked 10 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525 in module lsc1_packet_rx. +Marked 5 switch rules as full_case in process $proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 4 switch rules as full_case in process $proc$uart_tx.sv:22$4375 in module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Marked 112 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203 in module lsc1_packet_frontend. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:149$2991 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:131$2983 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:113$2981 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:96$2975 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:28$2969 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 8 switch rules as full_case in process $proc$uart_rx.sv:33$4386 in module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114 in module DPR16X4C. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56 in module TRELLIS_DPR16X4. +Removed a total of 5 dead cases. + +24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 16 redundant assignments. +Promoted 374 assignments to connections. + +24.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. + Set init value: \por_shift = 8'00000000 +Found init rule in `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. + Set init value: \heartbeat = 24'000000000000000000000000 +Found init rule in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. + Set init value: \Q = 1'0 + +24.5. Executing PROC_ARST pass (detect async resets in processes). + +24.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +24.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + 1/5: $0\scratch_byte[7:0] [7:1] + 2/5: $0\scratch_byte[7:0] [0] + 3/5: $0\byte_index[3:0] + 4/5: $0\state[3:0] + 5/5: $0\fault[0:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. + 1/13: $2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875 + 2/13: $2\rx_ready[0:0] + 3/13: $2\tx_data[7:0] + 4/13: $2\tx_valid[0:0] + 5/13: $1\rx_ready[0:0] + 6/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.index[3:0]$2870 + 7/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2869 + 8/13: $1\mul_result_shift[0:0] + 9/13: $1\mul_bit_value[0:0] + 10/13: $1\mul_bit_valid[0:0] + 11/13: $1\mul_a_valid[0:0] + 12/13: $1\tx_valid[0:0] + 13/13: $1\tx_data[7:0] +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. + 1/37: $7\fault_detail[7:0] + 2/37: $7\fault_txn[31:0] + 3/37: $7\fault_status[7:0] + 4/37: $7\reject[0:0] + 5/37: $7\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2586 + 6/37: $6\fault_detail[7:0] + 7/37: $6\fault_txn[31:0] + 8/37: $6\fault_status[7:0] + 9/37: $6\reject[0:0] + 10/37: $6\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2585 + 11/37: $5\fault_detail[7:0] + 12/37: $5\fault_txn[31:0] + 13/37: $5\fault_status[7:0] + 14/37: $5\reject[0:0] + 15/37: $5\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2584 + 16/37: $4\fault_detail[7:0] + 17/37: $4\fault_txn[31:0] + 18/37: $4\fault_status[7:0] + 19/37: $4\reject[0:0] + 20/37: $4\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2583 + 21/37: $3\fault_detail[7:0] + 22/37: $3\fault_txn[31:0] + 23/37: $3\fault_status[7:0] + 24/37: $3\reject[0:0] + 25/37: $3\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2582 + 26/37: $2\fault_detail[7:0] + 27/37: $2\fault_txn[31:0] + 28/37: $2\fault_status[7:0] + 29/37: $2\reject[0:0] + 30/37: $2\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn[31:0]$2580 + 31/37: $2\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2581 + 32/37: $1\fault_detail[7:0] + 33/37: $1\fault_txn[31:0] + 34/37: $1\fault_status[7:0] + 35/37: $1\reject[0:0] + 36/37: $1\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2579 + 37/37: $1\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn[31:0]$2578 +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. + 1/1: $1\expected_length[15:0] +Creating decoders for process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +Creating decoders for process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +Creating decoders for process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. + 1/127: $31\payload_data[7:0] + 2/127: $30\payload_data[7:0] + 3/127: $29\payload_data[7:0] + 4/127: $28\payload_data[7:0] + 5/127: $27\payload_data[7:0] + 6/127: $26\payload_data[7:0] + 7/127: $25\payload_data[7:0] + 8/127: $24\payload_data[7:0] + 9/127: $23\payload_data[7:0] + 10/127: $22\payload_data[7:0] + 11/127: $21\payload_data[7:0] + 12/127: $20\payload_data[7:0] + 13/127: $19\payload_data[7:0] + 14/127: $18\payload_data[7:0] + 15/127: $17\payload_data[7:0] + 16/127: $10$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2323 + 17/127: $16\payload_data[7:0] + 18/127: $9$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2318 + 19/127: $9$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2317 + 20/127: $15\ext_word[31:0] + 21/127: $15\payload_data[7:0] + 22/127: $8$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2313 + 23/127: $8$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2312 + 24/127: $14\ext_word[31:0] + 25/127: $9$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2302 + 26/127: $9$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2296 + 27/127: $14\payload_data[7:0] + 28/127: $8$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2293 + 29/127: $8$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2292 + 30/127: $8$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2295 + 31/127: $8$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2294 + 32/127: $7$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2284 + 33/127: $7$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2283 + 34/127: $7$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2282 + 35/127: $7$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2281 + 36/127: $13\payload_data[7:0] + 37/127: $13\ext_word[31:0] + 38/127: $7$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2286 + 39/127: $7$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2285 + 40/127: $12\payload_data[7:0] + 41/127: $6$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2277 + 42/127: $6$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2276 + 43/127: $6$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2275 + 44/127: $6$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2274 + 45/127: $6$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2273 + 46/127: $6$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2272 + 47/127: $12\ext_word[31:0] + 48/127: $11\payload_data[7:0] + 49/127: $5$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2266 + 50/127: $5$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2265 + 51/127: $5$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2264 + 52/127: $5$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2263 + 53/127: $5$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2262 + 54/127: $5$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2261 + 55/127: $11\ext_word[31:0] + 56/127: $10\payload_data[7:0] + 57/127: $4$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2255 + 58/127: $4$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2254 + 59/127: $4$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2253 + 60/127: $4$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2252 + 61/127: $4$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2251 + 62/127: $4$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2250 + 63/127: $10\ext_word[31:0] + 64/127: $9\payload_data[7:0] + 65/127: $3$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2245 + 66/127: $3$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2244 + 67/127: $3$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2243 + 68/127: $3$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2242 + 69/127: $3$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2241 + 70/127: $3$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2240 + 71/127: $9\ext_word[31:0] + 72/127: $2$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2238 + 73/127: $2$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2237 + 74/127: $2$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2236 + 75/127: $2$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2235 + 76/127: $2$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2234 + 77/127: $2$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2233 + 78/127: $8\ext_word[31:0] + 79/127: $8\payload_data[7:0] + 80/127: $8$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2222 + 81/127: $7\payload_data[7:0] + 82/127: $7$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2219 + 83/127: $7$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2218 + 84/127: $7\ext_word[31:0] + 85/127: $7$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2211 + 86/127: $6\payload_data[7:0] + 87/127: $6$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2206 + 88/127: $6$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2205 + 89/127: $6\ext_word[31:0] + 90/127: $6$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2208 + 91/127: $6$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2207 + 92/127: $5\payload_data[7:0] + 93/127: $5$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2203 + 94/127: $5$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2202 + 95/127: $5$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2201 + 96/127: $5$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2200 + 97/127: $5\ext_word[31:0] + 98/127: $4\payload_data[7:0] + 99/127: $4$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2198 + 100/127: $4$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2197 + 101/127: $4$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2196 + 102/127: $4$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2195 + 103/127: $4\ext_word[31:0] + 104/127: $3\payload_data[7:0] + 105/127: $3$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2189 + 106/127: $3$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2188 + 107/127: $3$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2187 + 108/127: $3$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2186 + 109/127: $3\ext_word[31:0] + 110/127: $2\payload_data[7:0] + 111/127: $2$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2181 + 112/127: $2$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2180 + 113/127: $2$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2179 + 114/127: $2$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2178 + 115/127: $2\ext_word[31:0] + 116/127: $1$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2170 + 117/127: $1$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2169 + 118/127: $1$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2168 + 119/127: $1$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2167 + 120/127: $1\ext_word[31:0] + 121/127: $1\payload_data[7:0] + 122/127: $1$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2176 + 123/127: $1$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2175 + 124/127: $1$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2174 + 125/127: $1$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2173 + 126/127: $1$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2172 + 127/127: $1$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2171 +Creating decoders for process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + 1/10: $0\done_pulse[0:0] + 2/10: $0\service_seq[31:0] + 3/10: $0\staged_service_id[31:0] + 4/10: $0\service_pending[0:0] + 5/10: $0\retire_seq[31:0] + 6/10: $0\staged_result_crc[31:0] + 7/10: $0\staged_next_fp[31:0] + 8/10: $0\staged_next_pc[31:0] + 9/10: $0\staged_txn_id[31:0] + 10/10: $0\result_pending[0:0] +Creating decoders for process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + 1/19: $3\next_accumulator[127:0] + 2/19: $3\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2129 + 3/19: $3\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2130 + 4/19: $2\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2127 + 5/19: $2\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2126 + 6/19: $2\next_accumulator[127:0] + 7/19: $0\multiply_start[0:0] + 8/19: $0\done_pulse[0:0] + 9/19: $1\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2123 + 10/19: $1\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2122 + 11/19: $1\next_accumulator[127:0] + 12/19: $0\accumulator[127:0] + 13/19: $0\saved_index[15:0] + 14/19: $0\bit_index[4:0] + 15/19: $0\result[127:0] + 16/19: $0\operand_b[127:0] + 17/19: $0\operand_a[127:0] + 18/19: $0\fault[0:0] + 19/19: $0\busy[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + 1/38: $6$lookahead\result$2032[127:0]$2100 + 2/38: $4$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2098 + 3/38: $4$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2097 + 4/38: $4$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2099 + 5/38: $5$lookahead\result$2032[127:0]$2074 + 6/38: $4$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2072 + 7/38: $4$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2071 + 8/38: $4$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2073 + 9/38: $4$lookahead\result$2032[127:0]$2065 + 10/38: $3$lookahead\result$2032[127:0]$2064 + 11/38: $3$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2063 + 12/38: $3$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2062 + 13/38: $3$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2061 + 14/38: $3$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2060 + 15/38: $3$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2059 + 16/38: $3$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2058 + 17/38: $2$lookahead\result$2032[127:0]$2055 + 18/38: $2$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2054 + 19/38: $2$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2053 + 20/38: $2$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2052 + 21/38: $2$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2051 + 22/38: $2$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2050 + 23/38: $2$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2049 + 24/38: $0\done_pulse[0:0] + 25/38: $1$lookahead\result$2032[127:0]$2048 + 26/38: $1$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2047 + 27/38: $1$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2046 + 28/38: $1$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2045 + 29/38: $1$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2044 + 30/38: $1$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2043 + 31/38: $1$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2042 + 32/38: $0\result_index[4:0] + 33/38: $0\saved_b[127:0] + 34/38: $0\saved_a[127:0] + 35/38: $0\saved_operation[7:0] + 36/38: $0\state[2:0] + 37/38: $0\payload_index[5:0] + 38/38: $0\fault[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. + 1/9: $6\core_rx_data[7:0] + 2/9: $5\core_rx_data[7:0] + 3/9: $4\core_rx_data[7:0] + 4/9: $3\core_rx_data[7:0] + 5/9: $3\core_rx_valid[0:0] + 6/9: $2\core_rx_data[7:0] + 7/9: $2\core_rx_valid[0:0] + 8/9: $1\core_rx_data[7:0] + 9/9: $1\core_rx_valid[0:0] +Creating decoders for process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + 1/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1918 + 2/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1921 + 3/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1922 + 4/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1920 + 5/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1919 + 6/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1913 + 7/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1916 + 8/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1917 + 9/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1915 + 10/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1914 + 11/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1873 + 12/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1876 + 13/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1877 + 14/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1875 + 15/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1874 + 16/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1838 + 17/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1837 + 18/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1836 + 19/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1835 + 20/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1834 + 21/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1833 + 22/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1832 + 23/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1831 + 24/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1830 + 25/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1829 + 26/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1828 + 27/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1827 + 28/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1826 + 29/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1825 + 30/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1824 + 31/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1819 + 32/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1822 + 33/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1823 + 34/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1821 + 35/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1820 + 36/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1816 + 37/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1815 + 38/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1814 + 39/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1813 + 40/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1812 + 41/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1811 + 42/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1810 + 43/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1809 + 44/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1808 + 45/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1807 + 46/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1806 + 47/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1805 + 48/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1804 + 49/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1803 + 50/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1802 + 51/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1801 + 52/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1800 + 53/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1799 + 54/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1798 + 55/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1797 + 56/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1795 + 57/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1794 + 58/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1793 + 59/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1792 + 60/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1791 + 61/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1790 + 62/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1789 + 63/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1788 + 64/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1787 + 65/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1786 + 66/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1785 + 67/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1784 + 68/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1783 + 69/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1782 + 70/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1781 + 71/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1780 + 72/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1779 + 73/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1778 + 74/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1777 + 75/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1776 + 76/104: $0\done_pulse[0:0] + 77/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1773 + 78/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1772 + 79/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1771 + 80/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1770 + 81/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1769 + 82/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1768 + 83/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1767 + 84/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1766 + 85/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1765 + 86/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1764 + 87/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1763 + 88/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1762 + 89/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1761 + 90/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1760 + 91/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1759 + 92/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1758 + 93/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1757 + 94/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1756 + 95/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1755 + 96/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1754 + 97/104: $0\payload_crc_work[31:0] + 98/104: $0\envelope_crc_work[31:0] + 99/104: $0\saved_crc[31:0] + 100/104: $0\saved_status[7:0] + 101/104: $0\saved_length[15:0] + 102/104: $0\active[0:0] + 103/104: $0\index[15:0] + 104/104: $0\payload_crc[31:0] +Creating decoders for process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. + 1/7: $7\tx_data[7:0] + 2/7: $6\tx_data[7:0] + 3/7: $5\tx_data[7:0] + 4/7: $4\tx_data[7:0] + 5/7: $3\tx_data[7:0] + 6/7: $2\tx_data[7:0] + 7/7: $1\tx_data[7:0] +Creating decoders for process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + 1/264: $0\received_crc[31:0] [31:24] + 2/264: $0\received_crc[31:0] [23:16] + 3/264: $0\received_crc[31:0] [15:8] + 4/264: $0\received_crc[31:0] [7:0] + 5/264: $0\frame_payload_prefix[1519:0] [1511:1504] + 6/264: $0\frame_payload_prefix[1519:0] [1503:1496] + 7/264: $0\frame_payload_prefix[1519:0] [1495:1488] + 8/264: $0\frame_payload_prefix[1519:0] [1487:1480] + 9/264: $0\frame_payload_prefix[1519:0] [1479:1472] + 10/264: $0\frame_payload_prefix[1519:0] [1471:1464] + 11/264: $0\frame_payload_prefix[1519:0] [1463:1456] + 12/264: $0\frame_payload_prefix[1519:0] [1455:1448] + 13/264: $0\frame_payload_prefix[1519:0] [1447:1440] + 14/264: $0\frame_payload_prefix[1519:0] [1439:1432] + 15/264: $0\frame_payload_prefix[1519:0] [1431:1424] + 16/264: $0\frame_payload_prefix[1519:0] [1423:1416] + 17/264: $0\frame_payload_prefix[1519:0] [1415:1408] + 18/264: $0\frame_payload_prefix[1519:0] [1407:1400] + 19/264: $0\frame_payload_prefix[1519:0] [1399:1392] + 20/264: $0\frame_payload_prefix[1519:0] [1391:1384] + 21/264: $0\frame_payload_prefix[1519:0] [1383:1376] + 22/264: $0\frame_payload_prefix[1519:0] [1375:1368] + 23/264: $0\frame_payload_prefix[1519:0] [1367:1360] + 24/264: $0\frame_payload_prefix[1519:0] [1359:1352] + 25/264: $0\frame_payload_prefix[1519:0] [1351:1344] + 26/264: $0\frame_payload_prefix[1519:0] [1343:1336] + 27/264: $0\frame_payload_prefix[1519:0] [1335:1328] + 28/264: $0\frame_payload_prefix[1519:0] [1327:1320] + 29/264: $0\frame_payload_prefix[1519:0] [1319:1312] + 30/264: $0\frame_payload_prefix[1519:0] [1311:1304] + 31/264: $0\frame_payload_prefix[1519:0] [1303:1296] + 32/264: $0\frame_payload_prefix[1519:0] [1295:1288] + 33/264: $0\frame_payload_prefix[1519:0] [1287:1280] + 34/264: $0\frame_payload_prefix[1519:0] [1279:1272] + 35/264: $0\frame_payload_prefix[1519:0] [1271:1264] + 36/264: $0\frame_payload_prefix[1519:0] [1263:1256] + 37/264: $0\frame_payload_prefix[1519:0] [1255:1248] + 38/264: $0\frame_payload_prefix[1519:0] [1247:1240] + 39/264: $0\frame_payload_prefix[1519:0] [1239:1232] + 40/264: $0\frame_payload_prefix[1519:0] [1231:1224] + 41/264: $0\frame_payload_prefix[1519:0] [1223:1216] + 42/264: $0\frame_payload_prefix[1519:0] [1215:1208] + 43/264: $0\frame_payload_prefix[1519:0] [1207:1200] + 44/264: $0\frame_payload_prefix[1519:0] [1199:1192] + 45/264: $0\frame_payload_prefix[1519:0] [1191:1184] + 46/264: $0\frame_payload_prefix[1519:0] [1183:1176] + 47/264: $0\frame_payload_prefix[1519:0] [1175:1168] + 48/264: $0\frame_payload_prefix[1519:0] [1167:1160] + 49/264: $0\frame_payload_prefix[1519:0] [1159:1152] + 50/264: $0\frame_payload_prefix[1519:0] [1151:1144] + 51/264: $0\frame_payload_prefix[1519:0] [1143:1136] + 52/264: $0\frame_payload_prefix[1519:0] [1135:1128] + 53/264: $0\frame_payload_prefix[1519:0] [1127:1120] + 54/264: $0\frame_payload_prefix[1519:0] [1119:1112] + 55/264: $0\frame_payload_prefix[1519:0] [1111:1104] + 56/264: $0\frame_payload_prefix[1519:0] [1103:1096] + 57/264: $0\frame_payload_prefix[1519:0] [1095:1088] + 58/264: $0\frame_payload_prefix[1519:0] [1087:1080] + 59/264: $0\frame_payload_prefix[1519:0] [1079:1072] + 60/264: $0\frame_payload_prefix[1519:0] [1071:1064] + 61/264: $0\frame_payload_prefix[1519:0] [1063:1056] + 62/264: $0\frame_payload_prefix[1519:0] [1055:1048] + 63/264: $0\frame_payload_prefix[1519:0] [1047:1040] + 64/264: $0\frame_payload_prefix[1519:0] [1039:1032] + 65/264: $0\frame_payload_prefix[1519:0] [1031:1024] + 66/264: $0\frame_payload_prefix[1519:0] [1023:1016] + 67/264: $0\frame_payload_prefix[1519:0] [1015:1008] + 68/264: $0\frame_payload_prefix[1519:0] [1007:1000] + 69/264: $0\frame_payload_prefix[1519:0] [999:992] + 70/264: $0\frame_payload_prefix[1519:0] [991:984] + 71/264: $0\frame_payload_prefix[1519:0] [983:976] + 72/264: $0\frame_payload_prefix[1519:0] [975:968] + 73/264: $0\frame_payload_prefix[1519:0] [967:960] + 74/264: $0\frame_payload_prefix[1519:0] [959:952] + 75/264: $0\frame_payload_prefix[1519:0] [951:944] + 76/264: $0\frame_payload_prefix[1519:0] [943:936] + 77/264: $0\frame_payload_prefix[1519:0] [935:928] + 78/264: $0\frame_payload_prefix[1519:0] [927:920] + 79/264: $0\frame_payload_prefix[1519:0] [919:912] + 80/264: $0\frame_payload_prefix[1519:0] [911:904] + 81/264: $0\frame_payload_prefix[1519:0] [903:896] + 82/264: $0\frame_payload_prefix[1519:0] [895:888] + 83/264: $0\frame_payload_prefix[1519:0] [887:880] + 84/264: $0\frame_payload_prefix[1519:0] [879:872] + 85/264: $0\frame_payload_prefix[1519:0] [871:864] + 86/264: $0\frame_payload_prefix[1519:0] [863:856] + 87/264: $0\frame_payload_prefix[1519:0] [855:848] + 88/264: $0\frame_payload_prefix[1519:0] [847:840] + 89/264: $0\frame_payload_prefix[1519:0] [839:832] + 90/264: $0\frame_payload_prefix[1519:0] [831:824] + 91/264: $0\frame_payload_prefix[1519:0] [823:816] + 92/264: $0\frame_payload_prefix[1519:0] [815:808] + 93/264: $0\frame_payload_prefix[1519:0] [807:800] + 94/264: $0\frame_payload_prefix[1519:0] [799:792] + 95/264: $0\frame_payload_prefix[1519:0] [791:784] + 96/264: $0\frame_payload_prefix[1519:0] [783:776] + 97/264: $0\frame_payload_prefix[1519:0] [775:768] + 98/264: $0\frame_payload_prefix[1519:0] [767:760] + 99/264: $0\frame_payload_prefix[1519:0] [759:752] + 100/264: $0\frame_payload_prefix[1519:0] [751:744] + 101/264: $0\frame_payload_prefix[1519:0] [743:736] + 102/264: $0\frame_payload_prefix[1519:0] [735:728] + 103/264: $0\frame_payload_prefix[1519:0] [727:720] + 104/264: $0\frame_payload_prefix[1519:0] [719:712] + 105/264: $0\frame_payload_prefix[1519:0] [711:704] + 106/264: $0\frame_payload_prefix[1519:0] [703:696] + 107/264: $0\frame_payload_prefix[1519:0] [695:688] + 108/264: $0\frame_payload_prefix[1519:0] [687:680] + 109/264: $0\frame_payload_prefix[1519:0] [679:672] + 110/264: $0\frame_payload_prefix[1519:0] [671:664] + 111/264: $0\frame_payload_prefix[1519:0] [663:656] + 112/264: $0\frame_payload_prefix[1519:0] [655:648] + 113/264: $0\frame_payload_prefix[1519:0] [647:640] + 114/264: $0\frame_payload_prefix[1519:0] [639:632] + 115/264: $0\frame_payload_prefix[1519:0] [631:624] + 116/264: $0\frame_payload_prefix[1519:0] [623:616] + 117/264: $0\frame_payload_prefix[1519:0] [615:608] + 118/264: $0\frame_payload_prefix[1519:0] [607:600] + 119/264: $0\frame_payload_prefix[1519:0] [599:592] + 120/264: $0\frame_payload_prefix[1519:0] [591:584] + 121/264: $0\frame_payload_prefix[1519:0] [583:576] + 122/264: $0\frame_payload_prefix[1519:0] [575:568] + 123/264: $0\frame_payload_prefix[1519:0] [567:560] + 124/264: $0\frame_payload_prefix[1519:0] [559:552] + 125/264: $0\frame_payload_prefix[1519:0] [551:544] + 126/264: $0\frame_payload_prefix[1519:0] [543:536] + 127/264: $0\frame_payload_prefix[1519:0] [535:528] + 128/264: $0\frame_payload_prefix[1519:0] [527:520] + 129/264: $0\frame_payload_prefix[1519:0] [519:512] + 130/264: $0\frame_payload_prefix[1519:0] [511:504] + 131/264: $0\frame_payload_prefix[1519:0] [503:496] + 132/264: $0\frame_payload_prefix[1519:0] [495:488] + 133/264: $0\frame_payload_prefix[1519:0] [487:480] + 134/264: $0\frame_payload_prefix[1519:0] [479:472] + 135/264: $0\frame_payload_prefix[1519:0] [471:464] + 136/264: $0\frame_payload_prefix[1519:0] [463:456] + 137/264: $0\frame_payload_prefix[1519:0] [455:448] + 138/264: $0\frame_payload_prefix[1519:0] [447:440] + 139/264: $0\frame_payload_prefix[1519:0] [439:432] + 140/264: $0\frame_payload_prefix[1519:0] [431:424] + 141/264: $0\frame_payload_prefix[1519:0] [423:416] + 142/264: $0\frame_payload_prefix[1519:0] [415:408] + 143/264: $0\frame_payload_prefix[1519:0] [407:400] + 144/264: $0\frame_payload_prefix[1519:0] [399:392] + 145/264: $0\frame_payload_prefix[1519:0] [391:384] + 146/264: $0\frame_payload_prefix[1519:0] [383:376] + 147/264: $0\frame_payload_prefix[1519:0] [375:368] + 148/264: $0\frame_payload_prefix[1519:0] [367:360] + 149/264: $0\frame_payload_prefix[1519:0] [359:352] + 150/264: $0\frame_payload_prefix[1519:0] [351:344] + 151/264: $0\frame_payload_prefix[1519:0] [343:336] + 152/264: $0\frame_payload_prefix[1519:0] [335:328] + 153/264: $0\frame_payload_prefix[1519:0] [327:320] + 154/264: $0\frame_payload_prefix[1519:0] [319:312] + 155/264: $0\frame_payload_prefix[1519:0] [311:304] + 156/264: $0\frame_payload_prefix[1519:0] [303:296] + 157/264: $0\frame_payload_prefix[1519:0] [295:288] + 158/264: $0\frame_payload_prefix[1519:0] [287:280] + 159/264: $0\frame_payload_prefix[1519:0] [279:272] + 160/264: $0\frame_payload_prefix[1519:0] [271:264] + 161/264: $0\frame_payload_prefix[1519:0] [263:256] + 162/264: $0\frame_payload_prefix[1519:0] [255:248] + 163/264: $0\frame_payload_prefix[1519:0] [247:240] + 164/264: $0\frame_payload_prefix[1519:0] [239:232] + 165/264: $0\frame_payload_prefix[1519:0] [231:224] + 166/264: $0\frame_payload_prefix[1519:0] [223:216] + 167/264: $0\frame_payload_prefix[1519:0] [215:208] + 168/264: $0\frame_payload_prefix[1519:0] [207:200] + 169/264: $0\frame_payload_prefix[1519:0] [199:192] + 170/264: $0\frame_payload_prefix[1519:0] [191:184] + 171/264: $0\frame_payload_prefix[1519:0] [183:176] + 172/264: $0\frame_payload_prefix[1519:0] [175:168] + 173/264: $0\frame_payload_prefix[1519:0] [167:160] + 174/264: $0\frame_payload_prefix[1519:0] [159:152] + 175/264: $0\frame_payload_prefix[1519:0] [151:144] + 176/264: $0\frame_payload_prefix[1519:0] [143:136] + 177/264: $0\frame_payload_prefix[1519:0] [135:128] + 178/264: $0\frame_payload_prefix[1519:0] [127:120] + 179/264: $0\frame_payload_prefix[1519:0] [119:112] + 180/264: $0\frame_payload_prefix[1519:0] [111:104] + 181/264: $0\frame_payload_prefix[1519:0] [103:96] + 182/264: $0\frame_payload_prefix[1519:0] [95:88] + 183/264: $0\frame_payload_prefix[1519:0] [87:80] + 184/264: $0\frame_payload_prefix[1519:0] [79:72] + 185/264: $0\frame_payload_prefix[1519:0] [71:64] + 186/264: $0\frame_payload_prefix[1519:0] [63:56] + 187/264: $0\frame_payload_prefix[1519:0] [55:48] + 188/264: $0\frame_payload_prefix[1519:0] [47:40] + 189/264: $0\frame_payload_prefix[1519:0] [39:32] + 190/264: $0\frame_payload_prefix[1519:0] [31:24] + 191/264: $0\frame_payload_prefix[1519:0] [23:16] + 192/264: $0\frame_payload_prefix[1519:0] [15:8] + 193/264: $0\frame_payload_prefix[1519:0] [7:0] + 194/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1665 + 195/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1666 + 196/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1664 + 197/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1663 + 198/264: $4\payload_byte[31:0] + 199/264: $0\declared_length[15:0] [15:8] + 200/264: $0\declared_length[15:0] [7:0] + 201/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1589 + 202/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1588 + 203/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1587 + 204/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1575 + 205/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1574 + 206/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1573 + 207/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1572 + 208/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1585 + 209/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1584 + 210/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1583 + 211/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1582 + 212/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1581 + 213/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1580 + 214/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1579 + 215/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1578 + 216/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1577 + 217/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1576 + 218/264: $3\payload_byte[31:0] + 219/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1571 + 220/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1570 + 221/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1569 + 222/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1568 + 223/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1567 + 224/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1566 + 225/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1565 + 226/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1564 + 227/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1563 + 228/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1562 + 229/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1561 + 230/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1560 + 231/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1559 + 232/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1558 + 233/264: $2\payload_byte[31:0] + 234/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1555 + 235/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1554 + 236/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1553 + 237/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1552 + 238/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1551 + 239/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1550 + 240/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1549 + 241/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1548 + 242/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1547 + 243/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1546 + 244/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1545 + 245/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1544 + 246/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1543 + 247/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1542 + 248/264: $1\payload_byte[31:0] + 249/264: $0\payload_write_enable[189:0] + 250/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1662 + 251/264: $0\frame_payload_prefix[1519:0] [1519:1512] + 252/264: $0\crc[31:0] + 253/264: $0\flags[7:0] + 254/264: $0\opcode[7:0] + 255/264: $0\version[7:0] + 256/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1590 + 257/264: $0\body_index[15:0] + 258/264: $0\header_index[2:0] + 259/264: $0\state[2:0] + 260/264: $0\fault_valid[0:0] + 261/264: $0\fault_status[7:0] + 262/264: $0\frame_length[15:0] + 263/264: $0\frame_opcode[7:0] + 264/264: $0\frame_valid[0:0] +Creating decoders for process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + 1/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3093 + 2/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3095 + 3/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3094 + 4/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3091 + 5/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3090 + 6/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3089 + 7/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3084 [127:120] + 8/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3084 [119:0] + 9/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3081 + 10/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3083 + 11/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3082 + 12/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3087 + 13/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3086 + 14/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3085 + 15/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3080 + 16/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3079 + 17/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3078 + 18/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3077 + 19/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3076 + 20/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3075 + 21/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3074 + 22/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3073 + 23/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3072 + 24/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3071 + 25/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3070 + 26/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3069 + 27/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3068 + 28/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3067 + 29/30: $0\a_shift[127:0] + 30/30: $0\accumulator[127:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + 1/5: $0\shift[8:0] + 2/5: $0\bit_cnt[3:0] + 3/5: $0\div_cnt[15:0] + 4/5: $0\tx_serial[0:0] + 5/5: $0\tx_ready[0:0] +Creating decoders for process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + 1/2051: $56\result_length[31:0] + 2/2051: $55\result_length[31:0] + 3/2051: $54\result_length[31:0] + 4/2051: $53\result_length[31:0] + 5/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4362 + 6/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4361 + 7/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4360 + 8/2051: $21\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4363 + 9/2051: $52\result_length[31:0] + 10/2051: $20\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4358 + 11/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4357 + 12/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4356 + 13/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4355 + 14/2051: $51\result_length[31:0] + 15/2051: $41\decision_deferred[0:0] + 16/2051: $40\decision_deferred[0:0] + 17/2051: $39\decision_deferred[0:0] + 18/2051: $51\decision_fault[7:0] + 19/2051: $51\decision_ok[0:0] + 20/2051: $38\decision_deferred[0:0] + 21/2051: $50\decision_fault[7:0] + 22/2051: $50\decision_ok[0:0] + 23/2051: $37\decision_deferred[0:0] + 24/2051: $36\decision_deferred[0:0] + 25/2051: $49\decision_ok[0:0] + 26/2051: $49\decision_fault[7:0] + 27/2051: $35\decision_deferred[0:0] + 28/2051: $48\decision_ok[0:0] + 29/2051: $48\decision_fault[7:0] + 30/2051: $47\decision_fault[7:0] + 31/2051: $47\decision_ok[0:0] + 32/2051: $46\decision_fault[7:0] + 33/2051: $46\decision_ok[0:0] + 34/2051: $28\addr_c[31:0] + 35/2051: $28\addr_b[31:0] + 36/2051: $31\addr_a[31:0] + 37/2051: $34\decision_deferred[0:0] + 38/2051: $45\decision_ok[0:0] + 39/2051: $45\decision_fault[7:0] + 40/2051: $26\solved_b[127:0] + 41/2051: $26\solved_a[127:0] + 42/2051: $27\addr_c[31:0] + 43/2051: $27\addr_b[31:0] + 44/2051: $30\addr_a[31:0] + 45/2051: $24\inv_value[127:0] + 46/2051: $24\inv_present[7:0] + 47/2051: $24\val_c[127:0] + 48/2051: $24\pres_c[7:0] + 49/2051: $24\val_b[127:0] + 50/2051: $24\pres_b[7:0] + 51/2051: $24\val_a[127:0] + 52/2051: $24\pres_a[7:0] + 53/2051: $24\off_c[31:0] + 54/2051: $24\off_b[31:0] + 55/2051: $24\off_a[31:0] + 56/2051: $29\decision_detail[7:0] + 57/2051: $44\decision_fault[7:0] + 58/2051: $44\decision_ok[0:0] + 59/2051: $28\decision_detail[7:0] + 60/2051: $43\decision_fault[7:0] + 61/2051: $43\decision_ok[0:0] + 62/2051: $42\decision_fault[7:0] + 63/2051: $42\decision_ok[0:0] + 64/2051: $33\decision_deferred[0:0] + 65/2051: $41\decision_fault[7:0] + 66/2051: $41\decision_ok[0:0] + 67/2051: $32\decision_deferred[0:0] + 68/2051: $31\decision_deferred[0:0] + 69/2051: $40\decision_ok[0:0] + 70/2051: $40\decision_fault[7:0] + 71/2051: $27\decision_detail[7:0] + 72/2051: $26\decision_detail[7:0] + 73/2051: $39\decision_fault[7:0] + 74/2051: $39\decision_ok[0:0] + 75/2051: $30\decision_deferred[0:0] + 76/2051: $38\decision_fault[7:0] + 77/2051: $38\decision_ok[0:0] + 78/2051: $29\decision_deferred[0:0] + 79/2051: $25\decision_detail[7:0] + 80/2051: $37\decision_fault[7:0] + 81/2051: $37\decision_ok[0:0] + 82/2051: $28\decision_deferred[0:0] + 83/2051: $24\decision_detail[7:0] + 84/2051: $26\addr_c[31:0] + 85/2051: $26\addr_b[31:0] + 86/2051: $29\addr_a[31:0] + 87/2051: $27\decision_deferred[0:0] + 88/2051: $36\decision_ok[0:0] + 89/2051: $23\decision_detail[7:0] + 90/2051: $36\decision_fault[7:0] + 91/2051: $25\addr_c[31:0] + 92/2051: $25\addr_b[31:0] + 93/2051: $28\addr_a[31:0] + 94/2051: $23\inv_value[127:0] + 95/2051: $23\inv_present[7:0] + 96/2051: $23\proposed_fp[31:0] + 97/2051: $23\proposed_pc[31:0] + 98/2051: $23\val_c[127:0] + 99/2051: $23\val_b[127:0] + 100/2051: $23\val_a[127:0] + 101/2051: $23\off_c[31:0] + 102/2051: $23\off_b[31:0] + 103/2051: $23\off_a[31:0] + 104/2051: $25\solved_b[127:0] + 105/2051: $25\solved_a[127:0] + 106/2051: $23\pres_c[7:0] + 107/2051: $23\pres_b[7:0] + 108/2051: $23\pres_a[7:0] + 109/2051: $35\decision_fault[7:0] + 110/2051: $35\decision_ok[0:0] + 111/2051: $26\decision_deferred[0:0] + 112/2051: $34\decision_fault[7:0] + 113/2051: $34\decision_ok[0:0] + 114/2051: $25\decision_deferred[0:0] + 115/2051: $24\addr_c[31:0] + 116/2051: $24\addr_b[31:0] + 117/2051: $27\addr_a[31:0] + 118/2051: $33\decision_fault[7:0] + 119/2051: $33\decision_ok[0:0] + 120/2051: $24\decision_deferred[0:0] + 121/2051: $23\addr_c[31:0] + 122/2051: $23\addr_b[31:0] + 123/2051: $26\addr_a[31:0] + 124/2051: $23\decision_deferred[0:0] + 125/2051: $32\decision_ok[0:0] + 126/2051: $32\decision_fault[7:0] + 127/2051: $22\addr_c[31:0] + 128/2051: $22\addr_b[31:0] + 129/2051: $25\addr_a[31:0] + 130/2051: $22\val_c[127:0] + 131/2051: $22\pres_c[7:0] + 132/2051: $22\val_b[127:0] + 133/2051: $22\pres_b[7:0] + 134/2051: $22\base_index[31:0] + 135/2051: $22\val_a[127:0] + 136/2051: $22\off_c[31:0] + 137/2051: $22\off_b[31:0] + 138/2051: $22\off_a[31:0] + 139/2051: $22\decision_detail[7:0] + 140/2051: $24\solved_b[127:0] + 141/2051: $24\solved_a[127:0] + 142/2051: $22\inv_value[127:0] + 143/2051: $22\inv_present[7:0] + 144/2051: $22\pres_a[7:0] + 145/2051: $22\proposed_fp[31:0] + 146/2051: $22\proposed_pc[31:0] + 147/2051: $36\n_writes[31:0] + 148/2051: $36\write_value[127:0] + 149/2051: $36\write_address[31:0] + 150/2051: $24\addr_a[31:0] + 151/2051: $31\decision_fault[7:0] + 152/2051: $31\decision_ok[0:0] + 153/2051: $35\write_address[31:0] + 154/2051: $23\addr_a[31:0] + 155/2051: $35\n_writes[31:0] + 156/2051: $35\write_value[127:0] + 157/2051: $30\decision_fault[7:0] + 158/2051: $30\decision_ok[0:0] + 159/2051: $34\write_address[31:0] + 160/2051: $22\addr_a[31:0] + 161/2051: $34\n_writes[31:0] + 162/2051: $34\write_value[127:0] + 163/2051: $21\addr_c[31:0] + 164/2051: $21\addr_b[31:0] + 165/2051: $21\addr_a[31:0] + 166/2051: $29\decision_ok[0:0] + 167/2051: $29\decision_fault[7:0] + 168/2051: $33\write_address[31:0] + 169/2051: $33\n_writes[31:0] + 170/2051: $33\write_value[127:0] + 171/2051: $21\val_a[127:0] + 172/2051: $21\pres_a[7:0] + 173/2051: $21\result_value[127:0] + 174/2051: $21\off_a[31:0] + 175/2051: $22\decision_deferred[0:0] + 176/2051: $21\decision_detail[7:0] + 177/2051: $23\solved_b[127:0] + 178/2051: $23\solved_a[127:0] + 179/2051: $21\inv_value[127:0] + 180/2051: $21\val_c[127:0] + 181/2051: $21\val_b[127:0] + 182/2051: $21\inv_present[7:0] + 183/2051: $21\pres_c[7:0] + 184/2051: $21\pres_b[7:0] + 185/2051: $21\proposed_fp[31:0] + 186/2051: $21\proposed_pc[31:0] + 187/2051: $21\base_index[31:0] + 188/2051: $21\off_c[31:0] + 189/2051: $21\off_b[31:0] + 190/2051: $21\decision_deferred[0:0] + 191/2051: $28\decision_fault[7:0] + 192/2051: $28\decision_ok[0:0] + 193/2051: $27\decision_fault[7:0] + 194/2051: $27\decision_ok[0:0] + 195/2051: $26\decision_fault[7:0] + 196/2051: $26\decision_ok[0:0] + 197/2051: $25\decision_fault[7:0] + 198/2051: $25\decision_ok[0:0] + 199/2051: $24\decision_fault[7:0] + 200/2051: $24\decision_ok[0:0] + 201/2051: $20\decision_deferred[0:0] + 202/2051: $23\decision_ok[0:0] + 203/2051: $23\decision_fault[7:0] + 204/2051: $20\staged_access[6][31:0] + 205/2051: $20\staged_access[4][31:0] + 206/2051: $20\staged_access[3][31:0] + 207/2051: $20\staged_access[2][31:0] + 208/2051: $20\staged_access[1][31:0] + 209/2051: $20\staged_access[0][31:0] + 210/2051: $20\decision_detail[7:0] + 211/2051: $32\write_address[31:0] + 212/2051: $22\solved_b[127:0] + 213/2051: $22\solved_a[127:0] + 214/2051: $20\result_value[127:0] + 215/2051: $20\inv_value[127:0] + 216/2051: $20\val_c[127:0] + 217/2051: $20\val_b[127:0] + 218/2051: $20\val_a[127:0] + 219/2051: $20\inv_present[7:0] + 220/2051: $20\pres_c[7:0] + 221/2051: $20\pres_b[7:0] + 222/2051: $20\pres_a[7:0] + 223/2051: $20\proposed_fp[31:0] + 224/2051: $20\proposed_pc[31:0] + 225/2051: $20\base_index[31:0] + 226/2051: $20\addr_c[31:0] + 227/2051: $20\addr_b[31:0] + 228/2051: $20\addr_a[31:0] + 229/2051: $20\off_c[31:0] + 230/2051: $20\off_b[31:0] + 231/2051: $20\off_a[31:0] + 232/2051: $32\n_writes[31:0] + 233/2051: $32\write_value[127:0] + 234/2051: $22\decision_fault[7:0] + 235/2051: $22\decision_ok[0:0] + 236/2051: $21\decision_fault[7:0] + 237/2051: $21\decision_ok[0:0] + 238/2051: $20\decision_fault[7:0] + 239/2051: $20\decision_ok[0:0] + 240/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4210 + 241/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4209 + 242/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4208 + 243/2051: $19\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4214 + 244/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4213 + 245/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4212 + 246/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4211 + 247/2051: $19\staged_access[6][31:0] + 248/2051: $19\staged_access[4][31:0] + 249/2051: $19\staged_access[3][31:0] + 250/2051: $19\staged_access[2][31:0] + 251/2051: $19\staged_access[1][31:0] + 252/2051: $19\staged_access[0][31:0] + 253/2051: $19\decision_deferred[0:0] + 254/2051: $19\decision_ok[0:0] + 255/2051: $19\decision_detail[7:0] + 256/2051: $19\decision_fault[7:0] + 257/2051: $31\write_address[31:0] + 258/2051: $21\solved_b[127:0] + 259/2051: $21\solved_a[127:0] + 260/2051: $19\result_value[127:0] + 261/2051: $19\inv_value[127:0] + 262/2051: $19\val_c[127:0] + 263/2051: $19\val_b[127:0] + 264/2051: $19\val_a[127:0] + 265/2051: $19\inv_present[7:0] + 266/2051: $19\pres_c[7:0] + 267/2051: $19\pres_b[7:0] + 268/2051: $19\pres_a[7:0] + 269/2051: $19\profile[7:0] + 270/2051: $26\deferred_local[31:0] + 271/2051: $26\deferred_target[31:0] + 272/2051: $21\next_fp_value[31:0] + 273/2051: $21\next_pc_value[31:0] + 274/2051: $19\proposed_fp[31:0] + 275/2051: $19\proposed_pc[31:0] + 276/2051: $19\base_index[31:0] + 277/2051: $19\addr_c[31:0] + 278/2051: $19\addr_b[31:0] + 279/2051: $19\addr_a[31:0] + 280/2051: $19\off_c[31:0] + 281/2051: $19\off_b[31:0] + 282/2051: $19\off_a[31:0] + 283/2051: $19\fp[31:0] + 284/2051: $19\pc[31:0] + 285/2051: $19\txn_id[31:0] + 286/2051: $50\result_length[31:0] + 287/2051: $26\n_deferred[31:0] + 288/2051: $31\n_writes[31:0] + 289/2051: $31\write_value[127:0] + 290/2051: $25\staged_write_count[1:0] + 291/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4203 + 292/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4202 + 293/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4201 + 294/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4200 + 295/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4199 + 296/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4198 + 297/2051: $24\staged_write_count[1:0] + 298/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4193 + 299/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4192 + 300/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4191 + 301/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4190 + 302/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4189 + 303/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4188 + 304/2051: $23\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4173 + 305/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4186 + 306/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4185 + 307/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4184 + 308/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4183 + 309/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4182 + 310/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4181 + 311/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4180 + 312/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4179 + 313/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4178 + 314/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4177 + 315/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4176 + 316/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4175 + 317/2051: $23\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4174 + 318/2051: $23\staged_write_count[1:0] + 319/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4145 + 320/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4144 + 321/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4159 + 322/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4158 + 323/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4157 + 324/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4156 + 325/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4155 + 326/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4154 + 327/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4153 + 328/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4152 + 329/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4151 + 330/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4150 + 331/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4149 + 332/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4148 + 333/2051: $22\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4147 + 334/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4146 + 335/2051: $22\staged_write_count[1:0] + 336/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4122 + 337/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4138 + 338/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4137 + 339/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4136 + 340/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4135 + 341/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4134 + 342/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4133 + 343/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4132 + 344/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4131 + 345/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4130 + 346/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4129 + 347/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4128 + 348/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4127 + 349/2051: $21\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4126 + 350/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4125 + 351/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4124 + 352/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4123 + 353/2051: $21\staged_write_count[1:0] + 354/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4120 + 355/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4119 + 356/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4118 + 357/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4117 + 358/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4116 + 359/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4115 + 360/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4114 + 361/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4113 + 362/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4112 + 363/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4111 + 364/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4110 + 365/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4109 + 366/2051: $20\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4108 + 367/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4107 + 368/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4106 + 369/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4105 + 370/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4104 + 371/2051: $20\staged_write_count[1:0] + 372/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4085 + 373/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4102 + 374/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4101 + 375/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4100 + 376/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4099 + 377/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4098 + 378/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4097 + 379/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4096 + 380/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4095 + 381/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4094 + 382/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4093 + 383/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4092 + 384/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4091 + 385/2051: $19\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4090 + 386/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4089 + 387/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4088 + 388/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4087 + 389/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4086 + 390/2051: $19\staged_write_count[1:0] + 391/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4083 + 392/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4082 + 393/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4081 + 394/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4080 + 395/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4079 + 396/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4078 + 397/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4077 + 398/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4076 + 399/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4075 + 400/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4074 + 401/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4073 + 402/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4072 + 403/2051: $18\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4064 + 404/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4063 + 405/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4062 + 406/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4061 + 407/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4060 + 408/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4059 + 409/2051: $18\staged_write_count[1:0] + 410/2051: $18\txn_id[31:0] + 411/2051: $18\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4071 + 412/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4070 + 413/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4069 + 414/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4068 + 415/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4067 + 416/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4066 + 417/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4065 + 418/2051: $18\staged_access[6][31:0] + 419/2051: $18\staged_access[4][31:0] + 420/2051: $18\staged_access[3][31:0] + 421/2051: $18\staged_access[2][31:0] + 422/2051: $18\staged_access[1][31:0] + 423/2051: $18\staged_access[0][31:0] + 424/2051: $18\decision_deferred[0:0] + 425/2051: $18\decision_ok[0:0] + 426/2051: $18\decision_detail[7:0] + 427/2051: $18\decision_fault[7:0] + 428/2051: $30\write_address[31:0] + 429/2051: $20\solved_b[127:0] + 430/2051: $20\solved_a[127:0] + 431/2051: $18\result_value[127:0] + 432/2051: $18\inv_value[127:0] + 433/2051: $18\val_c[127:0] + 434/2051: $18\val_b[127:0] + 435/2051: $18\val_a[127:0] + 436/2051: $18\inv_present[7:0] + 437/2051: $18\pres_c[7:0] + 438/2051: $18\pres_b[7:0] + 439/2051: $18\pres_a[7:0] + 440/2051: $18\profile[7:0] + 441/2051: $25\deferred_local[31:0] + 442/2051: $25\deferred_target[31:0] + 443/2051: $20\next_fp_value[31:0] + 444/2051: $20\next_pc_value[31:0] + 445/2051: $18\proposed_fp[31:0] + 446/2051: $18\proposed_pc[31:0] + 447/2051: $18\base_index[31:0] + 448/2051: $18\addr_c[31:0] + 449/2051: $18\addr_b[31:0] + 450/2051: $18\addr_a[31:0] + 451/2051: $18\off_c[31:0] + 452/2051: $18\off_b[31:0] + 453/2051: $18\off_a[31:0] + 454/2051: $18\fp[31:0] + 455/2051: $18\pc[31:0] + 456/2051: $49\result_length[31:0] + 457/2051: $25\n_deferred[31:0] + 458/2051: $30\n_writes[31:0] + 459/2051: $30\write_value[127:0] + 460/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4054 + 461/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4053 + 462/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4047 + 463/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4049 + 464/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4048 + 465/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4044 + 466/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4043 + 467/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4038 + 468/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4037 + 469/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4041 + 470/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4040 + 471/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4039 + 472/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$4031 + 473/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4036 + 474/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4035 + 475/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4034 + 476/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4033 + 477/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4032 + 478/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4004 + 479/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4003 + 480/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4002 + 481/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4001 + 482/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4000 + 483/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3999 + 484/2051: $17\txn_id[31:0] + 485/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4029 + 486/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4028 + 487/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4027 + 488/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4026 + 489/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4025 + 490/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4024 + 491/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4023 + 492/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4022 + 493/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4021 + 494/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4020 + 495/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4019 + 496/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4018 + 497/2051: $17\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4017 + 498/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4016 + 499/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4015 + 500/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4014 + 501/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4013 + 502/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4012 + 503/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4011 + 504/2051: $17\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4010 + 505/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4009 + 506/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4008 + 507/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4007 + 508/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4006 + 509/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4005 + 510/2051: $17\staged_access[6][31:0] + 511/2051: $17\staged_access[4][31:0] + 512/2051: $17\staged_access[3][31:0] + 513/2051: $17\staged_access[2][31:0] + 514/2051: $17\staged_access[1][31:0] + 515/2051: $17\staged_access[0][31:0] + 516/2051: $17\decision_deferred[0:0] + 517/2051: $17\decision_ok[0:0] + 518/2051: $17\decision_detail[7:0] + 519/2051: $17\decision_fault[7:0] + 520/2051: $29\write_address[31:0] + 521/2051: $19\solved_b[127:0] + 522/2051: $19\solved_a[127:0] + 523/2051: $17\result_value[127:0] + 524/2051: $17\inv_value[127:0] + 525/2051: $17\val_c[127:0] + 526/2051: $17\val_b[127:0] + 527/2051: $17\val_a[127:0] + 528/2051: $17\inv_present[7:0] + 529/2051: $17\pres_c[7:0] + 530/2051: $17\pres_b[7:0] + 531/2051: $17\pres_a[7:0] + 532/2051: $17\profile[7:0] + 533/2051: $24\deferred_local[31:0] + 534/2051: $24\deferred_target[31:0] + 535/2051: $19\next_fp_value[31:0] + 536/2051: $19\next_pc_value[31:0] + 537/2051: $17\proposed_fp[31:0] + 538/2051: $17\proposed_pc[31:0] + 539/2051: $17\base_index[31:0] + 540/2051: $17\addr_c[31:0] + 541/2051: $17\addr_b[31:0] + 542/2051: $17\addr_a[31:0] + 543/2051: $17\off_c[31:0] + 544/2051: $17\off_b[31:0] + 545/2051: $17\off_a[31:0] + 546/2051: $17\fp[31:0] + 547/2051: $17\pc[31:0] + 548/2051: $48\result_length[31:0] + 549/2051: $24\n_deferred[31:0] + 550/2051: $29\n_writes[31:0] + 551/2051: $17\staged_write_count[1:0] + 552/2051: $29\write_value[127:0] + 553/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3988 + 554/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3987 + 555/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3986 + 556/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3985 + 557/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3984 + 558/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3983 + 559/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3982 + 560/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3981 + 561/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3980 + 562/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3979 + 563/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3978 + 564/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3977 + 565/2051: $16\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3976 + 566/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3975 + 567/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3974 + 568/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3973 + 569/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3972 + 570/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3971 + 571/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3970 + 572/2051: $16\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3969 + 573/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3968 + 574/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3967 + 575/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3966 + 576/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3965 + 577/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3964 + 578/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3963 + 579/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3962 + 580/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3961 + 581/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3960 + 582/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3959 + 583/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3958 + 584/2051: $16\staged_access[6][31:0] + 585/2051: $16\staged_access[4][31:0] + 586/2051: $16\staged_access[3][31:0] + 587/2051: $16\staged_access[2][31:0] + 588/2051: $16\staged_access[1][31:0] + 589/2051: $16\staged_access[0][31:0] + 590/2051: $16\decision_deferred[0:0] + 591/2051: $16\decision_ok[0:0] + 592/2051: $16\decision_detail[7:0] + 593/2051: $16\decision_fault[7:0] + 594/2051: $28\write_address[31:0] + 595/2051: $18\solved_b[127:0] + 596/2051: $18\solved_a[127:0] + 597/2051: $16\result_value[127:0] + 598/2051: $16\inv_value[127:0] + 599/2051: $16\val_c[127:0] + 600/2051: $16\val_b[127:0] + 601/2051: $16\val_a[127:0] + 602/2051: $16\inv_present[7:0] + 603/2051: $16\pres_c[7:0] + 604/2051: $16\pres_b[7:0] + 605/2051: $16\pres_a[7:0] + 606/2051: $16\profile[7:0] + 607/2051: $23\deferred_local[31:0] + 608/2051: $23\deferred_target[31:0] + 609/2051: $18\next_fp_value[31:0] + 610/2051: $18\next_pc_value[31:0] + 611/2051: $16\proposed_fp[31:0] + 612/2051: $16\proposed_pc[31:0] + 613/2051: $16\base_index[31:0] + 614/2051: $16\addr_c[31:0] + 615/2051: $16\addr_b[31:0] + 616/2051: $16\addr_a[31:0] + 617/2051: $16\off_c[31:0] + 618/2051: $16\off_b[31:0] + 619/2051: $16\off_a[31:0] + 620/2051: $16\fp[31:0] + 621/2051: $16\pc[31:0] + 622/2051: $16\txn_id[31:0] + 623/2051: $47\result_length[31:0] + 624/2051: $23\n_deferred[31:0] + 625/2051: $28\n_writes[31:0] + 626/2051: $16\staged_write_count[1:0] + 627/2051: $28\write_value[127:0] + 628/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3952 + 629/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3951 + 630/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3950 + 631/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3949 + 632/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3948 + 633/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3947 + 634/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3946 + 635/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3945 + 636/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3944 + 637/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3943 + 638/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3942 + 639/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3941 + 640/2051: $15\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3940 + 641/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3939 + 642/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3938 + 643/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3937 + 644/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3936 + 645/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3935 + 646/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3934 + 647/2051: $15\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3933 + 648/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3932 + 649/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3931 + 650/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3930 + 651/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3929 + 652/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3928 + 653/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3927 + 654/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3926 + 655/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3925 + 656/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3924 + 657/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3923 + 658/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3922 + 659/2051: $15\staged_access[6][31:0] + 660/2051: $15\staged_access[4][31:0] + 661/2051: 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691/2051: $15\addr_a[31:0] + 692/2051: $15\off_c[31:0] + 693/2051: $15\off_b[31:0] + 694/2051: $15\off_a[31:0] + 695/2051: $15\fp[31:0] + 696/2051: $15\pc[31:0] + 697/2051: $15\txn_id[31:0] + 698/2051: $46\result_length[31:0] + 699/2051: $22\n_deferred[31:0] + 700/2051: $27\n_writes[31:0] + 701/2051: $15\staged_write_count[1:0] + 702/2051: $27\write_value[127:0] + 703/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3887 + 704/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3886 + 705/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3918 + 706/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3917 + 707/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3916 + 708/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3915 + 709/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3914 + 710/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3913 + 711/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3912 + 712/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3911 + 713/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3910 + 714/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3909 + 715/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3908 + 716/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3907 + 717/2051: $14\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3906 + 718/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3905 + 719/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3904 + 720/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3903 + 721/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3902 + 722/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3901 + 723/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3900 + 724/2051: $14\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3899 + 725/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3898 + 726/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3897 + 727/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3896 + 728/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3895 + 729/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3894 + 730/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3893 + 731/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3892 + 732/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3891 + 733/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3890 + 734/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3889 + 735/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3888 + 736/2051: $14\staged_access[6][31:0] + 737/2051: $14\staged_access[4][31:0] + 738/2051: $14\staged_access[3][31:0] + 739/2051: $14\staged_access[2][31:0] + 740/2051: $14\staged_access[1][31:0] + 741/2051: $14\staged_access[0][31:0] + 742/2051: $14\decision_deferred[0:0] + 743/2051: $14\decision_ok[0:0] + 744/2051: $14\decision_detail[7:0] + 745/2051: $14\decision_fault[7:0] + 746/2051: $26\write_address[31:0] + 747/2051: $16\solved_b[127:0] + 748/2051: $16\solved_a[127:0] + 749/2051: $14\result_value[127:0] + 750/2051: $14\inv_value[127:0] + 751/2051: $14\val_c[127:0] + 752/2051: $14\val_b[127:0] + 753/2051: $14\val_a[127:0] + 754/2051: $14\inv_present[7:0] + 755/2051: $14\pres_c[7:0] + 756/2051: $14\pres_b[7:0] + 757/2051: $14\pres_a[7:0] + 758/2051: $14\profile[7:0] + 759/2051: $21\deferred_local[31:0] + 760/2051: $21\deferred_target[31:0] + 761/2051: $16\next_fp_value[31:0] + 762/2051: $16\next_pc_value[31:0] + 763/2051: $14\proposed_fp[31:0] + 764/2051: $14\proposed_pc[31:0] + 765/2051: $14\base_index[31:0] + 766/2051: $14\addr_c[31:0] + 767/2051: $14\addr_b[31:0] + 768/2051: $14\addr_a[31:0] + 769/2051: $14\off_c[31:0] + 770/2051: $14\off_b[31:0] + 771/2051: $14\off_a[31:0] + 772/2051: $14\fp[31:0] + 773/2051: $14\pc[31:0] + 774/2051: $14\txn_id[31:0] + 775/2051: $45\result_length[31:0] + 776/2051: $21\n_deferred[31:0] + 777/2051: $26\n_writes[31:0] + 778/2051: $14\staged_write_count[1:0] + 779/2051: $26\write_value[127:0] + 780/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3885 + 781/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3884 + 782/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3883 + 783/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3882 + 784/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3881 + 785/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3880 + 786/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3879 + 787/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3878 + 788/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3877 + 789/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3876 + 790/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3875 + 791/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3874 + 792/2051: $13\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3873 + 793/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3872 + 794/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3871 + 795/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3870 + 796/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3869 + 797/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3868 + 798/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3867 + 799/2051: $13\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3866 + 800/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3865 + 801/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3864 + 802/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3863 + 803/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3862 + 804/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3861 + 805/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3860 + 806/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3859 + 807/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3858 + 808/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3857 + 809/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3856 + 810/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3855 + 811/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3854 + 812/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3853 + 813/2051: $13\staged_access[6][31:0] + 814/2051: $13\staged_access[4][31:0] + 815/2051: $13\staged_access[3][31:0] + 816/2051: $13\staged_access[2][31:0] + 817/2051: $13\staged_access[1][31:0] + 818/2051: $13\staged_access[0][31:0] + 819/2051: $13\decision_deferred[0:0] + 820/2051: $13\decision_ok[0:0] + 821/2051: $13\decision_detail[7:0] + 822/2051: $13\decision_fault[7:0] + 823/2051: $25\write_address[31:0] + 824/2051: $15\solved_b[127:0] + 825/2051: $15\solved_a[127:0] + 826/2051: $13\result_value[127:0] + 827/2051: $13\inv_value[127:0] + 828/2051: $13\val_c[127:0] + 829/2051: $13\val_b[127:0] + 830/2051: $13\val_a[127:0] + 831/2051: $13\inv_present[7:0] + 832/2051: $13\pres_c[7:0] + 833/2051: $13\pres_b[7:0] + 834/2051: $13\pres_a[7:0] + 835/2051: $13\profile[7:0] + 836/2051: $20\deferred_local[31:0] + 837/2051: $20\deferred_target[31:0] + 838/2051: $15\next_fp_value[31:0] + 839/2051: $15\next_pc_value[31:0] + 840/2051: $13\proposed_fp[31:0] + 841/2051: $13\proposed_pc[31:0] + 842/2051: $13\base_index[31:0] + 843/2051: $13\addr_c[31:0] + 844/2051: $13\addr_b[31:0] + 845/2051: $13\addr_a[31:0] + 846/2051: $13\off_c[31:0] + 847/2051: $13\off_b[31:0] + 848/2051: $13\off_a[31:0] + 849/2051: $13\fp[31:0] + 850/2051: $13\pc[31:0] + 851/2051: $13\txn_id[31:0] + 852/2051: $44\result_length[31:0] + 853/2051: $20\n_deferred[31:0] + 854/2051: $25\n_writes[31:0] + 855/2051: $13\staged_write_count[1:0] + 856/2051: $25\write_value[127:0] + 857/2051: $43\result_length[31:0] + 858/2051: $42\result_length[31:0] + 859/2051: $41\result_length[31:0] + 860/2051: $40\result_length[31:0] + 861/2051: $24\n_writes[31:0] + 862/2051: $24\write_value[127:0] + 863/2051: $24\write_address[31:0] + 864/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3847 + 865/2051: $23\write_address[31:0] + 866/2051: $39\result_length[31:0] + 867/2051: $23\n_writes[31:0] + 868/2051: $23\write_value[127:0] + 869/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3842 + 870/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3844 + 871/2051: $13\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3843 + 872/2051: $22\write_address[31:0] + 873/2051: $38\result_length[31:0] + 874/2051: $22\n_writes[31:0] + 875/2051: $22\write_value[127:0] + 876/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3808 + 877/2051: $12\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3807 + 878/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3806 + 879/2051: $21\write_address[31:0] + 880/2051: $37\result_length[31:0] + 881/2051: $21\n_writes[31:0] + 882/2051: $21\write_value[127:0] + 883/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3841 + 884/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3840 + 885/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3839 + 886/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3838 + 887/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3837 + 888/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3836 + 889/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3835 + 890/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3834 + 891/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3833 + 892/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3832 + 893/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3831 + 894/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3830 + 895/2051: $12\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3829 + 896/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3828 + 897/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3827 + 898/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3826 + 899/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3825 + 900/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3824 + 901/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3823 + 902/2051: $12\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3822 + 903/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3821 + 904/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3820 + 905/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3819 + 906/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3818 + 907/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3817 + 908/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3816 + 909/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3815 + 910/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3814 + 911/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3813 + 912/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3812 + 913/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3811 + 914/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3810 + 915/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3809 + 916/2051: $12\staged_access[6][31:0] + 917/2051: $12\staged_access[4][31:0] + 918/2051: $12\staged_access[3][31:0] + 919/2051: $12\staged_access[2][31:0] + 920/2051: $12\staged_access[1][31:0] + 921/2051: $12\staged_access[0][31:0] + 922/2051: $12\decision_deferred[0:0] + 923/2051: $12\decision_ok[0:0] + 924/2051: $12\decision_detail[7:0] + 925/2051: $12\decision_fault[7:0] + 926/2051: $14\solved_b[127:0] + 927/2051: $14\solved_a[127:0] + 928/2051: $12\result_value[127:0] + 929/2051: $12\inv_value[127:0] + 930/2051: $12\val_c[127:0] + 931/2051: $12\val_b[127:0] + 932/2051: $12\val_a[127:0] + 933/2051: $12\inv_present[7:0] + 934/2051: $12\pres_c[7:0] + 935/2051: $12\pres_b[7:0] + 936/2051: $12\pres_a[7:0] + 937/2051: $12\profile[7:0] + 938/2051: $19\deferred_local[31:0] + 939/2051: $19\deferred_target[31:0] + 940/2051: $14\next_fp_value[31:0] + 941/2051: $14\next_pc_value[31:0] + 942/2051: $12\proposed_fp[31:0] + 943/2051: $12\proposed_pc[31:0] + 944/2051: $12\base_index[31:0] + 945/2051: $12\addr_c[31:0] + 946/2051: $12\addr_b[31:0] + 947/2051: $12\addr_a[31:0] + 948/2051: $12\off_c[31:0] + 949/2051: $12\off_b[31:0] + 950/2051: $12\off_a[31:0] + 951/2051: $12\fp[31:0] + 952/2051: $12\pc[31:0] + 953/2051: $12\txn_id[31:0] + 954/2051: $19\n_deferred[31:0] + 955/2051: $12\staged_write_count[1:0] + 956/2051: $13\solved_a[127:0] + 957/2051: $13\solved_b[127:0] + 958/2051: $20\n_writes[31:0] + 959/2051: $20\write_value[127:0] + 960/2051: $20\write_address[31:0] + 961/2051: $12\solved_b[127:0] + 962/2051: $12\solved_a[127:0] + 963/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3798 + 964/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3797 + 965/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3796 + 966/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3795 + 967/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3794 + 968/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3793 + 969/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3792 + 970/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3791 + 971/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3790 + 972/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3789 + 973/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3788 + 974/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3787 + 975/2051: $11\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3786 + 976/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3785 + 977/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3784 + 978/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3783 + 979/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3782 + 980/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3781 + 981/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3780 + 982/2051: $11\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3779 + 983/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3778 + 984/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3777 + 985/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3776 + 986/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3775 + 987/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3774 + 988/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3773 + 989/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3772 + 990/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3771 + 991/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3770 + 992/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3769 + 993/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3768 + 994/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3767 + 995/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3766 + 996/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3765 + 997/2051: $11\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3764 + 998/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3763 + 999/2051: $11\staged_access[6][31:0] + 1000/2051: $11\staged_access[4][31:0] + 1001/2051: $11\staged_access[3][31:0] + 1002/2051: $11\staged_access[2][31:0] + 1003/2051: $11\staged_access[1][31:0] + 1004/2051: $11\staged_access[0][31:0] + 1005/2051: $11\decision_deferred[0:0] + 1006/2051: $11\decision_ok[0:0] + 1007/2051: $11\decision_detail[7:0] + 1008/2051: $11\decision_fault[7:0] + 1009/2051: $11\result_value[127:0] + 1010/2051: $11\inv_value[127:0] + 1011/2051: $11\val_c[127:0] + 1012/2051: $11\val_b[127:0] + 1013/2051: $11\val_a[127:0] + 1014/2051: $11\inv_present[7:0] + 1015/2051: $11\pres_c[7:0] + 1016/2051: $11\pres_b[7:0] + 1017/2051: $11\pres_a[7:0] + 1018/2051: $11\profile[7:0] + 1019/2051: $18\deferred_local[31:0] + 1020/2051: $18\deferred_target[31:0] + 1021/2051: $13\next_fp_value[31:0] + 1022/2051: $13\next_pc_value[31:0] + 1023/2051: $11\proposed_fp[31:0] + 1024/2051: $11\proposed_pc[31:0] + 1025/2051: $11\base_index[31:0] + 1026/2051: $11\addr_c[31:0] + 1027/2051: $11\addr_b[31:0] + 1028/2051: $11\addr_a[31:0] + 1029/2051: $11\off_c[31:0] + 1030/2051: $11\off_b[31:0] + 1031/2051: $11\off_a[31:0] + 1032/2051: $11\fp[31:0] + 1033/2051: $11\pc[31:0] + 1034/2051: $11\txn_id[31:0] + 1035/2051: $36\result_length[31:0] + 1036/2051: $18\n_deferred[31:0] + 1037/2051: $11\staged_write_count[1:0] + 1038/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3760 + 1039/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3721 + 1040/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3757 + 1041/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3756 + 1042/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3755 + 1043/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3754 + 1044/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3753 + 1045/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3752 + 1046/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3751 + 1047/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3750 + 1048/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3749 + 1049/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3748 + 1050/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3747 + 1051/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3746 + 1052/2051: $10\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3745 + 1053/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3744 + 1054/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3743 + 1055/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3742 + 1056/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3741 + 1057/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3740 + 1058/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3739 + 1059/2051: $10\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3738 + 1060/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3737 + 1061/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3736 + 1062/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3735 + 1063/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3734 + 1064/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3733 + 1065/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3732 + 1066/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3731 + 1067/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3730 + 1068/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3729 + 1069/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3728 + 1070/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3727 + 1071/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3726 + 1072/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3725 + 1073/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3724 + 1074/2051: $10\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3723 + 1075/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3722 + 1076/2051: $10\staged_access[6][31:0] + 1077/2051: $10\staged_access[4][31:0] + 1078/2051: $10\staged_access[3][31:0] + 1079/2051: $10\staged_access[2][31:0] + 1080/2051: $10\staged_access[1][31:0] + 1081/2051: $10\staged_access[0][31:0] + 1082/2051: $10\decision_deferred[0:0] + 1083/2051: $10\decision_ok[0:0] + 1084/2051: $10\decision_detail[7:0] + 1085/2051: $10\decision_fault[7:0] + 1086/2051: $19\write_address[31:0] + 1087/2051: $11\solved_b[127:0] + 1088/2051: $11\solved_a[127:0] + 1089/2051: $10\result_value[127:0] + 1090/2051: $10\inv_value[127:0] + 1091/2051: $10\val_c[127:0] + 1092/2051: $10\val_b[127:0] + 1093/2051: $10\val_a[127:0] + 1094/2051: $10\inv_present[7:0] + 1095/2051: $10\pres_c[7:0] + 1096/2051: $10\pres_b[7:0] + 1097/2051: $10\pres_a[7:0] + 1098/2051: $10\profile[7:0] + 1099/2051: $17\deferred_local[31:0] + 1100/2051: $17\deferred_target[31:0] + 1101/2051: $12\next_fp_value[31:0] + 1102/2051: $12\next_pc_value[31:0] + 1103/2051: $10\proposed_fp[31:0] + 1104/2051: $10\proposed_pc[31:0] + 1105/2051: $10\base_index[31:0] + 1106/2051: $10\addr_c[31:0] + 1107/2051: $10\addr_b[31:0] + 1108/2051: $10\addr_a[31:0] + 1109/2051: $10\off_c[31:0] + 1110/2051: $10\off_b[31:0] + 1111/2051: $10\off_a[31:0] + 1112/2051: $10\fp[31:0] + 1113/2051: $10\pc[31:0] + 1114/2051: $10\txn_id[31:0] + 1115/2051: $35\result_length[31:0] + 1116/2051: $17\n_deferred[31:0] + 1117/2051: $19\n_writes[31:0] + 1118/2051: $10\staged_write_count[1:0] + 1119/2051: $19\write_value[127:0] + 1120/2051: $10\solved_a[127:0] + 1121/2051: $10\solved_b[127:0] + 1122/2051: $18\n_writes[31:0] + 1123/2051: $18\write_value[127:0] + 1124/2051: $18\write_address[31:0] + 1125/2051: $9\solved_b[127:0] + 1126/2051: $9\solved_a[127:0] + 1127/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3715 + 1128/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3714 + 1129/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3713 + 1130/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3712 + 1131/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3711 + 1132/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3710 + 1133/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3709 + 1134/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3708 + 1135/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3707 + 1136/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3706 + 1137/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3705 + 1138/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3704 + 1139/2051: $9\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3703 + 1140/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3702 + 1141/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3701 + 1142/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3700 + 1143/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3699 + 1144/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3698 + 1145/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3697 + 1146/2051: $9\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3696 + 1147/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3695 + 1148/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3694 + 1149/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3693 + 1150/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3692 + 1151/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3691 + 1152/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3690 + 1153/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3689 + 1154/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3688 + 1155/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3687 + 1156/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3686 + 1157/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3685 + 1158/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3684 + 1159/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3683 + 1160/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3682 + 1161/2051: $9\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3681 + 1162/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3680 + 1163/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3679 + 1164/2051: $9\staged_access[6][31:0] + 1165/2051: $9\staged_access[4][31:0] + 1166/2051: $9\staged_access[3][31:0] + 1167/2051: $9\staged_access[2][31:0] + 1168/2051: $9\staged_access[1][31:0] + 1169/2051: $9\staged_access[0][31:0] + 1170/2051: $9\decision_deferred[0:0] + 1171/2051: $9\decision_ok[0:0] + 1172/2051: $9\decision_detail[7:0] + 1173/2051: $9\decision_fault[7:0] + 1174/2051: $9\result_value[127:0] + 1175/2051: $9\inv_value[127:0] + 1176/2051: $9\val_c[127:0] + 1177/2051: $9\val_b[127:0] + 1178/2051: $9\val_a[127:0] + 1179/2051: $9\inv_present[7:0] + 1180/2051: $9\pres_c[7:0] + 1181/2051: $9\pres_b[7:0] + 1182/2051: $9\pres_a[7:0] + 1183/2051: $9\profile[7:0] + 1184/2051: $16\deferred_local[31:0] + 1185/2051: $16\deferred_target[31:0] + 1186/2051: $11\next_fp_value[31:0] + 1187/2051: $11\next_pc_value[31:0] + 1188/2051: $9\proposed_fp[31:0] + 1189/2051: $9\proposed_pc[31:0] + 1190/2051: $9\base_index[31:0] + 1191/2051: $9\addr_c[31:0] + 1192/2051: $9\addr_b[31:0] + 1193/2051: $9\addr_a[31:0] + 1194/2051: $9\off_c[31:0] + 1195/2051: $9\off_b[31:0] + 1196/2051: $9\off_a[31:0] + 1197/2051: $9\fp[31:0] + 1198/2051: $9\pc[31:0] + 1199/2051: $9\txn_id[31:0] + 1200/2051: $34\result_length[31:0] + 1201/2051: $16\n_deferred[31:0] + 1202/2051: $9\staged_write_count[1:0] + 1203/2051: $33\result_length[31:0] + 1204/2051: $32\result_length[31:0] + 1205/2051: $31\result_length[31:0] + 1206/2051: $30\result_length[31:0] + 1207/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3673 + 1208/2051: $29\result_length[31:0] + 1209/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3633 + 1210/2051: $28\result_length[31:0] + 1211/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3670 + 1212/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3669 + 1213/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3668 + 1214/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3667 + 1215/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3666 + 1216/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3665 + 1217/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3664 + 1218/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3663 + 1219/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3662 + 1220/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3661 + 1221/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3660 + 1222/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3659 + 1223/2051: $8\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3658 + 1224/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3657 + 1225/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3656 + 1226/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3655 + 1227/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3654 + 1228/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3653 + 1229/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3652 + 1230/2051: $8\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3651 + 1231/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3650 + 1232/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3649 + 1233/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3648 + 1234/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3647 + 1235/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3646 + 1236/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3645 + 1237/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3644 + 1238/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3643 + 1239/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3642 + 1240/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3641 + 1241/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3640 + 1242/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3639 + 1243/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3638 + 1244/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3637 + 1245/2051: $8\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3636 + 1246/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3635 + 1247/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3634 + 1248/2051: $8\staged_access[6][31:0] + 1249/2051: $8\staged_access[4][31:0] + 1250/2051: $8\staged_access[3][31:0] + 1251/2051: $8\staged_access[2][31:0] + 1252/2051: $8\staged_access[1][31:0] + 1253/2051: $8\staged_access[0][31:0] + 1254/2051: $8\decision_deferred[0:0] + 1255/2051: $8\decision_ok[0:0] + 1256/2051: $8\decision_detail[7:0] + 1257/2051: $8\decision_fault[7:0] + 1258/2051: $17\write_address[31:0] + 1259/2051: $8\solved_b[127:0] + 1260/2051: $8\solved_a[127:0] + 1261/2051: $8\result_value[127:0] + 1262/2051: $8\inv_value[127:0] + 1263/2051: $8\val_c[127:0] + 1264/2051: $8\val_b[127:0] + 1265/2051: $8\val_a[127:0] + 1266/2051: $8\inv_present[7:0] + 1267/2051: $8\pres_c[7:0] + 1268/2051: $8\pres_b[7:0] + 1269/2051: $8\pres_a[7:0] + 1270/2051: $8\profile[7:0] + 1271/2051: $15\deferred_local[31:0] + 1272/2051: $15\deferred_target[31:0] + 1273/2051: $10\next_fp_value[31:0] + 1274/2051: $10\next_pc_value[31:0] + 1275/2051: $8\proposed_fp[31:0] + 1276/2051: $8\proposed_pc[31:0] + 1277/2051: $8\base_index[31:0] + 1278/2051: $8\addr_c[31:0] + 1279/2051: $8\addr_b[31:0] + 1280/2051: $8\addr_a[31:0] + 1281/2051: $8\off_c[31:0] + 1282/2051: $8\off_b[31:0] + 1283/2051: $8\off_a[31:0] + 1284/2051: $8\fp[31:0] + 1285/2051: $8\pc[31:0] + 1286/2051: $8\txn_id[31:0] + 1287/2051: $15\n_deferred[31:0] + 1288/2051: $17\n_writes[31:0] + 1289/2051: $8\staged_write_count[1:0] + 1290/2051: $17\write_value[127:0] + 1291/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3630 + 1292/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3589 + 1293/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3627 + 1294/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3626 + 1295/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3625 + 1296/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3624 + 1297/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3623 + 1298/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3622 + 1299/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3621 + 1300/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3620 + 1301/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3619 + 1302/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3618 + 1303/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3617 + 1304/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3616 + 1305/2051: $7\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3615 + 1306/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3614 + 1307/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3613 + 1308/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3612 + 1309/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3611 + 1310/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3610 + 1311/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3609 + 1312/2051: $7\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3608 + 1313/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3607 + 1314/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3606 + 1315/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3605 + 1316/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3604 + 1317/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3603 + 1318/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3602 + 1319/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3601 + 1320/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3600 + 1321/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3599 + 1322/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3598 + 1323/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3597 + 1324/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3596 + 1325/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3595 + 1326/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3594 + 1327/2051: $7\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3593 + 1328/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3592 + 1329/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3591 + 1330/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3590 + 1331/2051: $7\staged_access[6][31:0] + 1332/2051: $7\staged_access[4][31:0] + 1333/2051: $7\staged_access[3][31:0] + 1334/2051: $7\staged_access[2][31:0] + 1335/2051: $7\staged_access[1][31:0] + 1336/2051: $7\staged_access[0][31:0] + 1337/2051: $7\decision_deferred[0:0] + 1338/2051: $7\decision_ok[0:0] + 1339/2051: $7\decision_detail[7:0] + 1340/2051: $7\decision_fault[7:0] + 1341/2051: $16\write_address[31:0] + 1342/2051: $7\solved_b[127:0] + 1343/2051: $7\solved_a[127:0] + 1344/2051: $7\result_value[127:0] + 1345/2051: $7\inv_value[127:0] + 1346/2051: $7\val_c[127:0] + 1347/2051: $7\val_b[127:0] + 1348/2051: $7\val_a[127:0] + 1349/2051: $7\inv_present[7:0] + 1350/2051: $7\pres_c[7:0] + 1351/2051: $7\pres_b[7:0] + 1352/2051: $7\pres_a[7:0] + 1353/2051: $7\profile[7:0] + 1354/2051: $14\deferred_local[31:0] + 1355/2051: $14\deferred_target[31:0] + 1356/2051: $9\next_fp_value[31:0] + 1357/2051: $9\next_pc_value[31:0] + 1358/2051: $7\proposed_fp[31:0] + 1359/2051: $7\proposed_pc[31:0] + 1360/2051: $7\base_index[31:0] + 1361/2051: $7\addr_c[31:0] + 1362/2051: $7\addr_b[31:0] + 1363/2051: $7\addr_a[31:0] + 1364/2051: $7\off_c[31:0] + 1365/2051: $7\off_b[31:0] + 1366/2051: $7\off_a[31:0] + 1367/2051: $7\fp[31:0] + 1368/2051: $7\pc[31:0] + 1369/2051: $7\txn_id[31:0] + 1370/2051: $27\result_length[31:0] + 1371/2051: $14\n_deferred[31:0] + 1372/2051: $16\n_writes[31:0] + 1373/2051: $7\staged_write_count[1:0] + 1374/2051: $16\write_value[127:0] + 1375/2051: $26\result_length[31:0] + 1376/2051: $25\result_length[31:0] + 1377/2051: $24\result_length[31:0] + 1378/2051: $23\result_length[31:0] + 1379/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3583 + 1380/2051: $8\next_fp_value[31:0] + 1381/2051: $8\next_pc_value[31:0] + 1382/2051: $22\result_length[31:0] + 1383/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3580 + 1384/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3581 + 1385/2051: $7\next_fp_value[31:0] + 1386/2051: $7\next_pc_value[31:0] + 1387/2051: $21\result_length[31:0] + 1388/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3540 + 1389/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3539 + 1390/2051: $6\next_fp_value[31:0] + 1391/2051: $6\next_pc_value[31:0] + 1392/2051: $20\result_length[31:0] + 1393/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3579 + 1394/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3578 + 1395/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3577 + 1396/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3576 + 1397/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3575 + 1398/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3574 + 1399/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3573 + 1400/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3572 + 1401/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3571 + 1402/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3570 + 1403/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3569 + 1404/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3568 + 1405/2051: $6\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3567 + 1406/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3566 + 1407/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3565 + 1408/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3564 + 1409/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3563 + 1410/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3562 + 1411/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3561 + 1412/2051: $6\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3560 + 1413/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3559 + 1414/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3558 + 1415/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3557 + 1416/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3556 + 1417/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3555 + 1418/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3554 + 1419/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3553 + 1420/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3552 + 1421/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3551 + 1422/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3550 + 1423/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3549 + 1424/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3548 + 1425/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3547 + 1426/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3546 + 1427/2051: $6\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3545 + 1428/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3544 + 1429/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3543 + 1430/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3542 + 1431/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3541 + 1432/2051: $6\staged_access[6][31:0] + 1433/2051: $6\staged_access[4][31:0] + 1434/2051: $6\staged_access[3][31:0] + 1435/2051: $6\staged_access[2][31:0] + 1436/2051: $6\staged_access[1][31:0] + 1437/2051: $6\staged_access[0][31:0] + 1438/2051: $6\decision_deferred[0:0] + 1439/2051: $6\decision_ok[0:0] + 1440/2051: $6\decision_detail[7:0] + 1441/2051: $6\decision_fault[7:0] + 1442/2051: $15\write_address[31:0] + 1443/2051: $6\solved_b[127:0] + 1444/2051: $6\solved_a[127:0] + 1445/2051: $6\result_value[127:0] + 1446/2051: $6\inv_value[127:0] + 1447/2051: $6\val_c[127:0] + 1448/2051: $6\val_b[127:0] + 1449/2051: $6\val_a[127:0] + 1450/2051: $6\inv_present[7:0] + 1451/2051: $6\pres_c[7:0] + 1452/2051: $6\pres_b[7:0] + 1453/2051: $6\pres_a[7:0] + 1454/2051: $6\profile[7:0] + 1455/2051: $13\deferred_local[31:0] + 1456/2051: $13\deferred_target[31:0] + 1457/2051: $6\proposed_fp[31:0] + 1458/2051: $6\proposed_pc[31:0] + 1459/2051: $6\base_index[31:0] + 1460/2051: $6\addr_c[31:0] + 1461/2051: $6\addr_b[31:0] + 1462/2051: $6\addr_a[31:0] + 1463/2051: $6\off_c[31:0] + 1464/2051: $6\off_b[31:0] + 1465/2051: $6\off_a[31:0] + 1466/2051: $6\fp[31:0] + 1467/2051: $6\pc[31:0] + 1468/2051: $6\txn_id[31:0] + 1469/2051: $13\n_deferred[31:0] + 1470/2051: $15\n_writes[31:0] + 1471/2051: $6\staged_write_count[1:0] + 1472/2051: $15\write_value[127:0] + 1473/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3536 + 1474/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3533 + 1475/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3534 + 1476/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3491 + 1477/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3490 + 1478/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3532 + 1479/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3531 + 1480/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3530 + 1481/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3529 + 1482/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3528 + 1483/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3527 + 1484/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3526 + 1485/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3525 + 1486/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3524 + 1487/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3523 + 1488/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3522 + 1489/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3521 + 1490/2051: $5\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3520 + 1491/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3519 + 1492/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3518 + 1493/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3517 + 1494/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3516 + 1495/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3515 + 1496/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3514 + 1497/2051: $5\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3513 + 1498/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3512 + 1499/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3511 + 1500/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3510 + 1501/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3509 + 1502/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3508 + 1503/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3507 + 1504/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3506 + 1505/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3505 + 1506/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3504 + 1507/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3503 + 1508/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3502 + 1509/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3501 + 1510/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3500 + 1511/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3499 + 1512/2051: $5\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3498 + 1513/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3497 + 1514/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3496 + 1515/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3495 + 1516/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3494 + 1517/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3493 + 1518/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3492 + 1519/2051: $5\staged_access[6][31:0] + 1520/2051: $5\staged_access[4][31:0] + 1521/2051: $5\staged_access[3][31:0] + 1522/2051: $5\staged_access[2][31:0] + 1523/2051: $5\staged_access[1][31:0] + 1524/2051: $5\staged_access[0][31:0] + 1525/2051: $5\decision_deferred[0:0] + 1526/2051: $5\decision_ok[0:0] + 1527/2051: $5\decision_detail[7:0] + 1528/2051: $5\decision_fault[7:0] + 1529/2051: $14\write_address[31:0] + 1530/2051: $5\solved_b[127:0] + 1531/2051: $5\solved_a[127:0] + 1532/2051: $5\result_value[127:0] + 1533/2051: $5\inv_value[127:0] + 1534/2051: $5\val_c[127:0] + 1535/2051: $5\val_b[127:0] + 1536/2051: $5\val_a[127:0] + 1537/2051: $5\inv_present[7:0] + 1538/2051: $5\pres_c[7:0] + 1539/2051: $5\pres_b[7:0] + 1540/2051: $5\pres_a[7:0] + 1541/2051: $5\profile[7:0] + 1542/2051: $12\deferred_local[31:0] + 1543/2051: $12\deferred_target[31:0] + 1544/2051: $5\next_fp_value[31:0] + 1545/2051: $5\next_pc_value[31:0] + 1546/2051: $5\proposed_fp[31:0] + 1547/2051: $5\proposed_pc[31:0] + 1548/2051: $5\base_index[31:0] + 1549/2051: $5\addr_c[31:0] + 1550/2051: $5\addr_b[31:0] + 1551/2051: $5\addr_a[31:0] + 1552/2051: $5\off_c[31:0] + 1553/2051: $5\off_b[31:0] + 1554/2051: $5\off_a[31:0] + 1555/2051: $5\fp[31:0] + 1556/2051: $5\pc[31:0] + 1557/2051: $5\txn_id[31:0] + 1558/2051: $19\result_length[31:0] + 1559/2051: $12\n_deferred[31:0] + 1560/2051: $14\n_writes[31:0] + 1561/2051: $5\staged_write_count[1:0] + 1562/2051: $14\write_value[127:0] + 1563/2051: $18\result_length[31:0] + 1564/2051: $17\result_length[31:0] + 1565/2051: $16\result_length[31:0] + 1566/2051: $15\result_length[31:0] + 1567/2051: $13\write_value[127:0] + 1568/2051: $13\write_address[31:0] + 1569/2051: $13\n_writes[31:0] + 1570/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3483 + 1571/2051: $12\write_address[31:0] + 1572/2051: $14\result_length[31:0] + 1573/2051: $12\n_writes[31:0] + 1574/2051: $12\write_value[127:0] + 1575/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3479 + 1576/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3480 + 1577/2051: $11\write_address[31:0] + 1578/2051: $13\result_length[31:0] + 1579/2051: $11\n_writes[31:0] + 1580/2051: $11\write_value[127:0] + 1581/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3435 + 1582/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3434 + 1583/2051: $10\write_address[31:0] + 1584/2051: $12\result_length[31:0] + 1585/2051: $10\n_writes[31:0] + 1586/2051: $10\write_value[127:0] + 1587/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3478 + 1588/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3477 + 1589/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3476 + 1590/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3475 + 1591/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3474 + 1592/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3473 + 1593/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3472 + 1594/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3471 + 1595/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3470 + 1596/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3469 + 1597/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3468 + 1598/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3467 + 1599/2051: $4\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3466 + 1600/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3465 + 1601/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3464 + 1602/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3463 + 1603/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3462 + 1604/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3461 + 1605/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3460 + 1606/2051: $4\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3459 + 1607/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3458 + 1608/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3457 + 1609/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3456 + 1610/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3455 + 1611/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3454 + 1612/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3453 + 1613/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3452 + 1614/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3451 + 1615/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3450 + 1616/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3449 + 1617/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3448 + 1618/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3447 + 1619/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3446 + 1620/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3445 + 1621/2051: $4\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3444 + 1622/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3443 + 1623/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3442 + 1624/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3441 + 1625/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3440 + 1626/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3439 + 1627/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3438 + 1628/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3437 + 1629/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3436 + 1630/2051: $4\staged_access[6][31:0] + 1631/2051: $4\staged_access[4][31:0] + 1632/2051: $4\staged_access[3][31:0] + 1633/2051: $4\staged_access[2][31:0] + 1634/2051: $4\staged_access[1][31:0] + 1635/2051: $4\staged_access[0][31:0] + 1636/2051: $4\decision_deferred[0:0] + 1637/2051: $4\decision_ok[0:0] + 1638/2051: $4\decision_detail[7:0] + 1639/2051: $4\decision_fault[7:0] + 1640/2051: $4\solved_b[127:0] + 1641/2051: $4\solved_a[127:0] + 1642/2051: $4\result_value[127:0] + 1643/2051: $4\inv_value[127:0] + 1644/2051: $4\val_c[127:0] + 1645/2051: $4\val_b[127:0] + 1646/2051: $4\val_a[127:0] + 1647/2051: $4\inv_present[7:0] + 1648/2051: $4\pres_c[7:0] + 1649/2051: $4\pres_b[7:0] + 1650/2051: $4\pres_a[7:0] + 1651/2051: $4\profile[7:0] + 1652/2051: $11\deferred_local[31:0] + 1653/2051: $11\deferred_target[31:0] + 1654/2051: $4\next_fp_value[31:0] + 1655/2051: $4\next_pc_value[31:0] + 1656/2051: $4\proposed_fp[31:0] + 1657/2051: $4\proposed_pc[31:0] + 1658/2051: $4\base_index[31:0] + 1659/2051: $4\addr_c[31:0] + 1660/2051: $4\addr_b[31:0] + 1661/2051: $4\addr_a[31:0] + 1662/2051: $4\off_c[31:0] + 1663/2051: $4\off_b[31:0] + 1664/2051: $4\off_a[31:0] + 1665/2051: $4\fp[31:0] + 1666/2051: $4\pc[31:0] + 1667/2051: $4\txn_id[31:0] + 1668/2051: $11\n_deferred[31:0] + 1669/2051: $4\staged_write_count[1:0] + 1670/2051: $11\result_length[31:0] + 1671/2051: $10\result_length[31:0] + 1672/2051: $9\result_length[31:0] + 1673/2051: $8\result_length[31:0] + 1674/2051: $10\deferred_local[31:0] + 1675/2051: $10\deferred_target[31:0] + 1676/2051: $10\n_deferred[31:0] + 1677/2051: $9\write_value[127:0] + 1678/2051: $9\write_address[31:0] + 1679/2051: $9\n_writes[31:0] + 1680/2051: $9\deferred_local[31:0] + 1681/2051: $9\deferred_target[31:0] + 1682/2051: $9\n_deferred[31:0] + 1683/2051: $8\write_value[127:0] + 1684/2051: $8\write_address[31:0] + 1685/2051: $8\n_writes[31:0] + 1686/2051: $8\deferred_local[31:0] + 1687/2051: $8\deferred_target[31:0] + 1688/2051: $8\n_deferred[31:0] + 1689/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3418 + 1690/2051: $7\write_address[31:0] + 1691/2051: $7\deferred_local[31:0] + 1692/2051: $7\deferred_target[31:0] + 1693/2051: $7\result_length[31:0] + 1694/2051: $7\n_deferred[31:0] + 1695/2051: $7\n_writes[31:0] + 1696/2051: $7\write_value[127:0] + 1697/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3413 + 1698/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3414 + 1699/2051: $6\write_address[31:0] + 1700/2051: $6\deferred_local[31:0] + 1701/2051: $6\deferred_target[31:0] + 1702/2051: $6\result_length[31:0] + 1703/2051: $6\n_deferred[31:0] + 1704/2051: $6\n_writes[31:0] + 1705/2051: $6\write_value[127:0] + 1706/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3409 + 1707/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3408 + 1708/2051: $5\write_address[31:0] + 1709/2051: $5\deferred_local[31:0] + 1710/2051: $5\deferred_target[31:0] + 1711/2051: $5\result_length[31:0] + 1712/2051: $5\n_deferred[31:0] + 1713/2051: $5\n_writes[31:0] + 1714/2051: $5\write_value[127:0] + 1715/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3404 + 1716/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3406 + 1717/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3405 + 1718/2051: $4\write_address[31:0] + 1719/2051: $4\deferred_local[31:0] + 1720/2051: $4\deferred_target[31:0] + 1721/2051: $4\result_length[31:0] + 1722/2051: $4\n_deferred[31:0] + 1723/2051: $4\n_writes[31:0] + 1724/2051: $4\write_value[127:0] + 1725/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3356 + 1726/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3355 + 1727/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3354 + 1728/2051: $3\write_address[31:0] + 1729/2051: $3\deferred_local[31:0] + 1730/2051: $3\deferred_target[31:0] + 1731/2051: $3\result_length[31:0] + 1732/2051: $3\n_deferred[31:0] + 1733/2051: $3\n_writes[31:0] + 1734/2051: $3\write_value[127:0] + 1735/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3401 + 1736/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3400 + 1737/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3399 + 1738/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3398 + 1739/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3397 + 1740/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3396 + 1741/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3395 + 1742/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3394 + 1743/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3393 + 1744/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3392 + 1745/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3391 + 1746/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3390 + 1747/2051: $3\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3389 + 1748/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3388 + 1749/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3387 + 1750/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3386 + 1751/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3385 + 1752/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3384 + 1753/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3383 + 1754/2051: $3\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3382 + 1755/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3381 + 1756/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3380 + 1757/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3379 + 1758/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3378 + 1759/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3377 + 1760/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3376 + 1761/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3375 + 1762/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3374 + 1763/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3373 + 1764/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3372 + 1765/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3371 + 1766/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3370 + 1767/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3369 + 1768/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3368 + 1769/2051: $3\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3367 + 1770/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3366 + 1771/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3365 + 1772/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3364 + 1773/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3363 + 1774/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3362 + 1775/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3361 + 1776/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3360 + 1777/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3359 + 1778/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3358 + 1779/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3357 + 1780/2051: $3\staged_access[6][31:0] + 1781/2051: $3\staged_access[4][31:0] + 1782/2051: $3\staged_access[3][31:0] + 1783/2051: $3\staged_access[2][31:0] + 1784/2051: $3\staged_access[1][31:0] + 1785/2051: $3\staged_access[0][31:0] + 1786/2051: $3\decision_deferred[0:0] + 1787/2051: $3\decision_ok[0:0] + 1788/2051: $3\decision_detail[7:0] + 1789/2051: $3\decision_fault[7:0] + 1790/2051: $3\solved_b[127:0] + 1791/2051: $3\solved_a[127:0] + 1792/2051: $3\result_value[127:0] + 1793/2051: $3\inv_value[127:0] + 1794/2051: $3\val_c[127:0] + 1795/2051: $3\val_b[127:0] + 1796/2051: $3\val_a[127:0] + 1797/2051: $3\inv_present[7:0] + 1798/2051: $3\pres_c[7:0] + 1799/2051: $3\pres_b[7:0] + 1800/2051: $3\pres_a[7:0] + 1801/2051: $3\profile[7:0] + 1802/2051: $3\next_fp_value[31:0] + 1803/2051: $3\next_pc_value[31:0] + 1804/2051: $3\proposed_fp[31:0] + 1805/2051: $3\proposed_pc[31:0] + 1806/2051: $3\base_index[31:0] + 1807/2051: $3\addr_c[31:0] + 1808/2051: $3\addr_b[31:0] + 1809/2051: $3\addr_a[31:0] + 1810/2051: $3\off_c[31:0] + 1811/2051: $3\off_b[31:0] + 1812/2051: $3\off_a[31:0] + 1813/2051: $3\fp[31:0] + 1814/2051: $3\pc[31:0] + 1815/2051: $3\txn_id[31:0] + 1816/2051: $3\staged_write_count[1:0] + 1817/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3348 + 1818/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3347 + 1819/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3346 + 1820/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3345 + 1821/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3344 + 1822/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3343 + 1823/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3342 + 1824/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3341 + 1825/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3340 + 1826/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3339 + 1827/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3338 + 1828/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3337 + 1829/2051: $2\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3336 + 1830/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3335 + 1831/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3334 + 1832/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3333 + 1833/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3332 + 1834/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3331 + 1835/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3330 + 1836/2051: $2\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3329 + 1837/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3328 + 1838/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3327 + 1839/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3326 + 1840/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3325 + 1841/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3324 + 1842/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3323 + 1843/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3322 + 1844/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3321 + 1845/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3320 + 1846/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3319 + 1847/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3318 + 1848/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3317 + 1849/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3316 + 1850/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3315 + 1851/2051: $2\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3314 + 1852/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3313 + 1853/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3312 + 1854/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3311 + 1855/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3310 + 1856/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3309 + 1857/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3308 + 1858/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3307 + 1859/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3306 + 1860/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3305 + 1861/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3304 + 1862/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3303 + 1863/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3302 + 1864/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3301 + 1865/2051: $2\staged_access[6][31:0] + 1866/2051: $2\staged_access[4][31:0] + 1867/2051: $2\staged_access[3][31:0] + 1868/2051: $2\staged_access[2][31:0] + 1869/2051: $2\staged_access[1][31:0] + 1870/2051: $2\staged_access[0][31:0] + 1871/2051: $2\decision_deferred[0:0] + 1872/2051: $2\decision_ok[0:0] + 1873/2051: $2\decision_detail[7:0] + 1874/2051: $2\decision_fault[7:0] + 1875/2051: $2\write_address[31:0] + 1876/2051: $2\solved_b[127:0] + 1877/2051: $2\solved_a[127:0] + 1878/2051: $2\result_value[127:0] + 1879/2051: $2\inv_value[127:0] + 1880/2051: $2\val_c[127:0] + 1881/2051: $2\val_b[127:0] + 1882/2051: $2\val_a[127:0] + 1883/2051: $2\inv_present[7:0] + 1884/2051: $2\pres_c[7:0] + 1885/2051: $2\pres_b[7:0] + 1886/2051: $2\pres_a[7:0] + 1887/2051: $2\profile[7:0] + 1888/2051: $2\deferred_local[31:0] + 1889/2051: $2\deferred_target[31:0] + 1890/2051: $2\next_fp_value[31:0] + 1891/2051: $2\next_pc_value[31:0] + 1892/2051: $2\proposed_fp[31:0] + 1893/2051: $2\proposed_pc[31:0] + 1894/2051: $2\base_index[31:0] + 1895/2051: $2\addr_c[31:0] + 1896/2051: $2\addr_b[31:0] + 1897/2051: $2\addr_a[31:0] + 1898/2051: $2\off_c[31:0] + 1899/2051: $2\off_b[31:0] + 1900/2051: $2\off_a[31:0] + 1901/2051: $2\fp[31:0] + 1902/2051: $2\pc[31:0] + 1903/2051: $2\txn_id[31:0] + 1904/2051: $2\result_length[31:0] + 1905/2051: $2\n_deferred[31:0] + 1906/2051: $2\n_writes[31:0] + 1907/2051: $2\staged_write_count[1:0] + 1908/2051: $2\write_value[127:0] + 1909/2051: $0\core_done_pulse[0:0] + 1910/2051: $0\blake_service_discard[0:0] + 1911/2051: $0\blake_service_accept[0:0] + 1912/2051: $0\blake_service_start[0:0] + 1913/2051: $1\staged_write_count[1:0] + 1914/2051: $0\encoder_start[0:0] + 1915/2051: $0\alu_start[0:0] + 1916/2051: $0\tx_start[0:0] + 1917/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3300 + 1918/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3299 + 1919/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3298 + 1920/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3297 + 1921/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3296 + 1922/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3295 + 1923/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3294 + 1924/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3293 + 1925/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3292 + 1926/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3291 + 1927/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3290 + 1928/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3289 + 1929/2051: $1\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3288 + 1930/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3287 + 1931/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3286 + 1932/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3285 + 1933/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3284 + 1934/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3283 + 1935/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3282 + 1936/2051: $1\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3281 + 1937/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3280 + 1938/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3279 + 1939/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3278 + 1940/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3277 + 1941/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3276 + 1942/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3275 + 1943/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3274 + 1944/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3273 + 1945/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3272 + 1946/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3271 + 1947/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3270 + 1948/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3269 + 1949/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3268 + 1950/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3267 + 1951/2051: $1\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3266 + 1952/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3265 + 1953/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3264 + 1954/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3263 + 1955/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3262 + 1956/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3261 + 1957/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3260 + 1958/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3259 + 1959/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3258 + 1960/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3257 + 1961/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3256 + 1962/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3255 + 1963/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3254 + 1964/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3253 + 1965/2051: $1\staged_access[6][31:0] + 1966/2051: $1\staged_access[4][31:0] + 1967/2051: $1\staged_access[3][31:0] + 1968/2051: $1\staged_access[2][31:0] + 1969/2051: $1\staged_access[1][31:0] + 1970/2051: $1\staged_access[0][31:0] + 1971/2051: $1\decision_deferred[0:0] + 1972/2051: $1\decision_ok[0:0] + 1973/2051: $1\decision_detail[7:0] + 1974/2051: $1\decision_fault[7:0] + 1975/2051: $1\write_address[31:0] + 1976/2051: $1\solved_b[127:0] + 1977/2051: $1\solved_a[127:0] + 1978/2051: $1\result_value[127:0] + 1979/2051: $1\inv_value[127:0] + 1980/2051: $1\val_c[127:0] + 1981/2051: $1\val_b[127:0] + 1982/2051: $1\val_a[127:0] + 1983/2051: $1\inv_present[7:0] + 1984/2051: $1\pres_c[7:0] + 1985/2051: $1\pres_b[7:0] + 1986/2051: $1\pres_a[7:0] + 1987/2051: $1\profile[7:0] + 1988/2051: $1\deferred_local[31:0] + 1989/2051: $1\deferred_target[31:0] + 1990/2051: $1\next_fp_value[31:0] + 1991/2051: $1\next_pc_value[31:0] + 1992/2051: $1\proposed_fp[31:0] + 1993/2051: $1\proposed_pc[31:0] + 1994/2051: $1\base_index[31:0] + 1995/2051: $1\addr_c[31:0] + 1996/2051: $1\addr_b[31:0] + 1997/2051: $1\addr_a[31:0] + 1998/2051: $1\off_c[31:0] + 1999/2051: $1\off_b[31:0] + 2000/2051: $1\off_a[31:0] + 2001/2051: $1\fp[31:0] + 2002/2051: $1\pc[31:0] + 2003/2051: $1\txn_id[31:0] + 2004/2051: $1\result_length[31:0] + 2005/2051: $1\n_deferred[31:0] + 2006/2051: $1\n_writes[31:0] + 2007/2051: $1\write_value[127:0] + 2008/2051: $0\staged_out_value[1][127:0] + 2009/2051: $0\staged_out_value[0][127:0] + 2010/2051: $0\staged_out_present[1][7:0] + 2011/2051: $0\staged_out_present[0][7:0] + 2012/2051: $0\staged_access[7][31:0] + 2013/2051: $0\staged_access[5][31:0] + 2014/2051: $0\scalar_staged_access[2][31:0] + 2015/2051: $0\scalar_staged_access[1][31:0] + 2016/2051: $0\scalar_staged_access[0][31:0] + 2017/2051: $0\last_fault[7:0] + 2018/2051: $0\last_status[7:0] + 2019/2051: $0\active_profile[7:0] + 2020/2051: $0\retire_seq[31:0] + 2021/2051: $0\committed_fp[31:0] + 2022/2051: $0\committed_pc[31:0] + 2023/2051: $0\state_valid[0:0] + 2024/2051: $0\scalar_staged_deferred_local[31:0] + 2025/2051: $0\scalar_staged_deferred_target[31:0] + 2026/2051: $0\scalar_staged_write_value[127:0] + 2027/2051: $0\scalar_staged_write_address[31:0] + 2028/2051: $0\scalar_staged_access_count[7:0] + 2029/2051: $0\scalar_staged_deferred[0:0] + 2030/2051: $0\scalar_staged_write_count[1:0] + 2031/2051: $0\staged_result_crc[31:0] + 2032/2051: $0\staged_next_fp[31:0] + 2033/2051: $0\staged_next_pc[31:0] + 2034/2051: $0\staged_txn_id[31:0] + 2035/2051: $0\staged_operation[7:0] + 2036/2051: $0\blake_start_next_fp[31:0] + 2037/2051: $0\blake_start_next_pc[31:0] + 2038/2051: $0\blake_start_txn_id[31:0] + 2039/2051: $0\result_pending[0:0] + 2040/2051: $0\encoder_index[15:0] + 2041/2051: $0\alu_operand_b[127:0] + 2042/2051: $0\alu_operand_a[127:0] + 2043/2051: $0\alu_operation[7:0] + 2044/2051: $0\compute_state[3:0] + 2045/2051: $0\capture_result_crc[0:0] + 2046/2051: $0\short_detail[7:0] + 2047/2051: $0\short_txn_id[31:0] + 2048/2051: $0\tx_external_kind[2:0] + 2049/2051: $0\tx_length[15:0] + 2050/2051: $0\tx_status[7:0] + 2051/2051: $0\fault[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + 1/2: $0\tx_data_q[7:0] + 2/2: $0\tx_full[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. + 1/1: $0\rx_overrun[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + 1/2: $0\rx_data_q[7:0] + 2/2: $0\rx_full[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. + 1/1: $0\abort_q[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. + 1/1: $0\por_shift[7:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + 1/27: $5$lookahead\shift$4385[7:0]$4419 + 2/27: $5$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4417 + 3/27: $5$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4416 + 4/27: $5$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4418 + 5/27: $4$lookahead\shift$4385[7:0]$4412 + 6/27: $4$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4411 + 7/27: $4$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4410 + 8/27: $4$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4409 + 9/27: $3$lookahead\shift$4385[7:0]$4407 + 10/27: $3$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4406 + 11/27: $3$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4405 + 12/27: $3$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4404 + 13/27: $2$lookahead\shift$4385[7:0]$4400 + 14/27: $2$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4399 + 15/27: $2$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4398 + 16/27: $2$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4397 + 17/27: $0\framing_err[0:0] + 18/27: $0\rx_valid[0:0] + 19/27: $1$lookahead\shift$4385[7:0]$4395 + 20/27: $1$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4394 + 21/27: $1$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4393 + 22/27: $1$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4392 + 23/27: $0\wait_idle[0:0] + 24/27: $0\receiving[0:0] + 25/27: $0\bit_cnt[3:0] + 26/27: $0\div_cnt[15:0] + 27/27: $0\rx_data[7:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. +Creating decoders for process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. +Creating decoders for process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + 1/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_EN[3:0]$120 + 2/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_DATA[3:0]$119 + 3/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_ADDR[3:0]$118 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + 1/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_EN[3:0]$62 + 2/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_DATA[3:0]$61 + 3/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_ADDR[3:0]$60 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. + +24.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\leanvm_b_stream_alu.\tx_data' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\rx_ready' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_a_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_value' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_result_shift' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.index' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2789.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2788.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2787.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2504.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2503.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2502.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2501.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2500.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2499.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2498.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2497.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2496.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2495.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2494.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2493.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2492.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2491.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2490.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2489.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2488.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2487.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2486.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2485.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\reject' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_status' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_detail' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\expected_length' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[2]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[3]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[4]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[5]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[6]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[7]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[2]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[3]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_cv[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_cv[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_address[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_address[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_value[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_value[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\payload_data' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Latch inferred for signal `\lsc1_response_payload_mux.\ext_word' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155': $auto$proc_dlatch.cc:427:proc_dlatch$88733 +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_data' from process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_valid' from process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +No latch inferred for signal `\lsc1_packet_tx.\tx_data' from process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. + +24.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\leanvm_b_stream_alu.\fault' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88734' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\state' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88735' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\byte_index' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88736' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\scratch_byte' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88737' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\done_pulse' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88738' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\result_pending' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88739' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_txn_id' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88740' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_next_pc' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88741' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_next_fp' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88742' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_result_crc' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88743' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\retire_seq' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88744' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\service_pending' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88745' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_service_id' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88746' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\service_seq' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88747' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\busy' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88748' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\fault' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88749' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\done_pulse' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88750' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_a' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88751' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_b' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88752' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\result' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88753' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\multiply_start' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88754' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\bit_index' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88755' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\saved_index' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88756' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\accumulator' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88757' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\next_accumulator' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88758' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88759' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88760' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\fault' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88761' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\done_pulse' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88762' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\payload_index' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88763' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88764' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\state' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88765' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_operation' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88766' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_a' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88767' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_b' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88768' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result_index' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88769' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88770' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88771' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88772' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88773' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88774' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88775' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$lookahead\result$2032' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88776' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\done_pulse' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88777' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88778' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88779' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\active' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88780' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_length' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88781' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_status' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88782' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_crc' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88783' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\envelope_crc_work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88784' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc_work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88785' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88786' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88787' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88788' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88789' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88790' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88791' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88792' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88793' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88794' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88795' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88796' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88797' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88798' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88799' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88800' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88801' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88802' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88803' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88804' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88805' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88806' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88807' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88808' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88809' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88810' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88811' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88812' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88813' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88814' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88815' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88816' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88817' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88818' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88819' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload_prefix' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88820' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\payload_write_enable' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88821' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\payload_byte' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88822' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88823' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88824' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88825' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88826' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88827' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88828' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88829' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88830' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88831' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88832' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88833' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88834' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88835' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88836' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\accumulator' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88837' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\a_shift' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88838' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88839' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88840' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88841' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88842' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88843' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88844' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88845' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\tx_ready' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88846' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\tx_serial' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88847' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\div_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88848' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\bit_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88849' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\shift' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88850' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88851' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88852' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88853' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88854' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_external_kind' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88855' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\short_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88856' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\short_detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88857' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\capture_result_crc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88858' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\compute_state' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88859' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88860' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operation' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88861' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88862' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88863' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88864' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_index' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88865' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_pending' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88866' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88867' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_accept' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88868' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_discard' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88869' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88870' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_next_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88871' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_next_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88872' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\core_done_pulse' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88873' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_operation' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88874' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88875' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88876' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88877' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_result_crc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88878' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88879' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88880' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88881' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_address' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88882' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88883' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88884' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred_target' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88885' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred_local' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88886' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\state_valid' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88887' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88888' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88889' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\retire_seq' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88890' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\active_profile' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88891' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88892' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88893' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_write_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88894' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_writes' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88895' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88896' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88897' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88898' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88899' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88900' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88901' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88902' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88903' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88904' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88905' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88906' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\base_index' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88907' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88908' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88909' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_pc_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88910' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_fp_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88911' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_target' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88912' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_local' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88913' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\profile' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88914' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88915' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88916' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88917' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_present' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88918' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88919' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88920' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88921' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88922' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88923' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88924' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88925' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_address' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88926' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88927' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88928' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_ok' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88929' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88930' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88931' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88932' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[2]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88933' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88934' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88935' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[2]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88936' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[3]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88937' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[4]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88938' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[5]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88939' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[6]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88940' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[7]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88941' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_present[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88942' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_present[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88943' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_value[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88944' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_value[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88945' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88946' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88947' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88948' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88949' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88950' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88951' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88952' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88953' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88954' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88955' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88956' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88957' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88958' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88959' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88960' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88961' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88962' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88963' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88964' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88965' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88966' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88967' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88968' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88969' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88970' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88971' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88972' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88973' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88974' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88975' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88976' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88977' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88978' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88979' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88980' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88981' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88982' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88983' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88984' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88985' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88986' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88987' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88988' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88989' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88990' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88991' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88992' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88993' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\tx_full' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + created $dff cell `$procdff$88994' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\tx_data_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + created $dff cell `$procdff$88995' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_overrun' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. + created $dff cell `$procdff$88996' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_full' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + created $dff cell `$procdff$88997' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_data_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + created $dff cell `$procdff$88998' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\abort_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. + created $dff cell `$procdff$88999' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\por_shift' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. + created $dff cell `$procdff$89000' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_data' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89001' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_valid' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89002' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\framing_err' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89003' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\div_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89004' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\bit_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89005' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\shift' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89006' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\receiving' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89007' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\wait_idle' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89008' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$mask$uart_rx.sv:72$4381' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89009' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$data$uart_rx.sv:72$4382' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89010' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$sel$uart_rx.sv:72$4383' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89011' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$lookahead\shift$4385' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89012' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_m' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. + created $dff cell `$procdff$89013' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_s' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. + created $dff cell `$procdff$89014' with positive edge clock. +Creating register for signal `\ulx3s_packet_top.\heartbeat' using process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. + created $dff cell `$procdff$89015' with positive edge clock. +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. + created $dff cell `$procdff$89016' with positive edge clock. +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$98_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$99_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$100_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$101_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$102_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$103_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$104_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$105_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$106_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$107_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$108_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$109_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$110_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$111_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$112_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_ADDR' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89017' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_DATA' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89018' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89019' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$38_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$39_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$40_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$41_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$42_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$43_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$44_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$45_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$46_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$47_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$48_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$49_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$50_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$51_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$52_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$53_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89020' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89021' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89022' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. + created direct connection (no actual register cell created). + +24.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 23 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. +Found and cleaned up 3 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +Found and cleaned up 7 empty switches in `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +Found and cleaned up 1 empty switch in `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +Removing empty process `lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +Removing empty process `lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +Found and cleaned up 36 empty switches in `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Removing empty process `lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Found and cleaned up 8 empty switches in `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. +Removing empty process `lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. +Found and cleaned up 5 empty switches in `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. +Removing empty process `lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. +Found and cleaned up 14 empty switches in `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. +Removing empty process `lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. +Found and cleaned up 6 empty switches in `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +Removing empty process `lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. +Removing empty process `lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. +Removing empty process `lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. +Found and cleaned up 203 empty switches in `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. +Removing empty process `lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. +Found and cleaned up 7 empty switches in `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. +Removing empty process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. +Found and cleaned up 5 empty switches in `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. +Found and cleaned up 114 empty switches in `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Removing empty process `lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. +Found and cleaned up 4 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. +Found and cleaned up 2 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. +Found and cleaned up 4 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. +Found and cleaned up 1 empty switch in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. +Found and cleaned up 1 empty switch in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. +Found and cleaned up 10 empty switches in `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. +Removing empty process `ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. +Removing empty process `ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. +Removing empty process `DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. +Cleaned up 472 empty switches. + +24.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module gf128_mul_bitstream. +Optimizing module leanvm_b_stream_alu. + +Optimizing module lsc1_cell_alias_check. +Optimizing module lsc1_request_validator. + +Optimizing module lsc1_blake3_alias_check. +Optimizing module lsc1_response_payload_mux. + +Optimizing module lsc1_blake3_lifecycle. + +Optimizing module lsc1_field_encoder. + +Optimizing module lsc1_stream_adapter. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_packet_rx. + +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. + +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. + +Optimizing module lean_silicon_lsc1. + +Optimizing module lsc1_packet_frontend. + +Optimizing module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. + +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. + +Optimizing module ulx3s_core_pll. +Optimizing module ulx3s_packet_top. + +25. Executing CHECK pass (checking for obvious problems). +Checking module gf128_mul_bitstream... +Checking module leanvm_b_stream_alu... +Checking module lsc1_cell_alias_check... +Checking module lsc1_request_validator... +Checking module lsc1_blake3_alias_check... +Checking module lsc1_response_payload_mux... +Checking module lsc1_blake3_lifecycle... +Checking module lsc1_field_encoder... +Checking module lsc1_stream_adapter... +Checking module lsc1_packet_tx... +Checking module lsc1_packet_rx... +Checking module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream... +Checking module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx... +Checking module lean_silicon_lsc1... +Checking module lsc1_packet_frontend... +Checking module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000... +Checking module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx... +Checking module ulx3s_core_pll... +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +26. Executing SYNTH_ECP5 pass. + +26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Replacing existing module `\LUT4' at /usr/bin/../share/yosys/ecp5/cells_sim.v:4.1-16.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\$__ABC9_LUT5' at /usr/bin/../share/yosys/ecp5/cells_sim.v:22.1-30.10. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Replacing existing blackbox module `\$__ABC9_LUT6' at /usr/bin/../share/yosys/ecp5/cells_sim.v:36.1-45.10. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Replacing existing blackbox module `\$__ABC9_LUT7' at /usr/bin/../share/yosys/ecp5/cells_sim.v:51.1-61.10. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Replacing existing module `\L6MUX21' at /usr/bin/../share/yosys/ecp5/cells_sim.v:65.1-72.10. +Generating RTLIL representation for module `\L6MUX21'. +Replacing existing module `\CCU2C' at /usr/bin/../share/yosys/ecp5/cells_sim.v:76.1-134.10. +Generating RTLIL representation for module `\CCU2C'. +Replacing existing blackbox module `\TRELLIS_RAM16X2' at /usr/bin/../share/yosys/ecp5/cells_sim.v:138.1-175.10. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Replacing existing module `\PFUMX' at /usr/bin/../share/yosys/ecp5/cells_sim.v:179.1-186.10. +Generating RTLIL representation for module `\PFUMX'. +Replacing existing module `\TRELLIS_DPR16X4' at /usr/bin/../share/yosys/ecp5/cells_sim.v:190.1-231.10. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Replacing existing module `\DPR16X4C' at /usr/bin/../share/yosys/ecp5/cells_sim.v:236.1-295.10. +Generating RTLIL representation for module `\DPR16X4C'. +Replacing existing module `\LUT2' at /usr/bin/../share/yosys/ecp5/cells_sim.v:300.1-304.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing module `\TRELLIS_FF' at /usr/bin/../share/yosys/ecp5/cells_sim.v:311.1-376.10. +Generating RTLIL representation for module `\TRELLIS_FF'. +Replacing existing blackbox module `\TRELLIS_IO' at /usr/bin/../share/yosys/ecp5/cells_sim.v:380.1-406.10. +Generating RTLIL representation for module `\TRELLIS_IO'. +Replacing existing blackbox module `\INV' at /usr/bin/../share/yosys/ecp5/cells_sim.v:410.1-412.10. +Generating RTLIL representation for module `\INV'. +Replacing existing blackbox module `\TRELLIS_COMB' at /usr/bin/../share/yosys/ecp5/cells_sim.v:416.1-457.10. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Replacing existing blackbox module `\DP16KD' at /usr/bin/../share/yosys/ecp5/cells_sim.v:460.1-674.10. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /usr/bin/../share/yosys/ecp5/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /usr/bin/../share/yosys/ecp5/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /usr/bin/../share/yosys/ecp5/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /usr/bin/../share/yosys/ecp5/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Replacing existing blackbox module `\MULT18X18D' at /usr/bin/../share/yosys/ecp5/cells_bb.v:5.1-48.10. +Generating RTLIL representation for module `\MULT18X18D'. +Replacing existing blackbox module `\ALU54B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:51.1-117.10. +Generating RTLIL representation for module `\ALU54B'. +Replacing existing blackbox module `\EHXPLLL' at /usr/bin/../share/yosys/ecp5/cells_bb.v:120.1-165.10. +Generating RTLIL representation for module `\EHXPLLL'. +Replacing existing blackbox module `\DTR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:168.1-172.10. +Generating RTLIL representation for module `\DTR'. +Replacing existing blackbox module `\OSCG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:175.1-179.10. +Generating RTLIL representation for module `\OSCG'. +Replacing existing blackbox module `\USRMCLK' at /usr/bin/../share/yosys/ecp5/cells_bb.v:182.1-186.10. +Generating RTLIL representation for module `\USRMCLK'. +Replacing existing blackbox module `\JTAGG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:189.1-204.10. +Generating RTLIL representation for module `\JTAGG'. +Replacing existing blackbox module `\DELAYF' at /usr/bin/../share/yosys/ecp5/cells_bb.v:207.1-213.10. +Generating RTLIL representation for module `\DELAYF'. +Replacing existing blackbox module `\DELAYG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:216.1-222.10. +Generating RTLIL representation for module `\DELAYG'. +Replacing existing blackbox module `\IDDRX1F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:225.1-230.10. +Generating RTLIL representation for module `\IDDRX1F'. +Replacing existing blackbox module `\IDDRX2F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:233.1-238.10. +Generating RTLIL representation for module `\IDDRX2F'. +Replacing existing blackbox module `\IDDR71B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:241.1-246.10. +Generating RTLIL representation for module `\IDDR71B'. +Replacing existing blackbox module `\IDDRX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:249.1-255.10. +Generating RTLIL representation for module `\IDDRX2DQA'. +Replacing existing blackbox module `\ODDRX1F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:258.1-263.10. +Generating RTLIL representation for module `\ODDRX1F'. +Replacing existing blackbox module `\ODDRX2F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:266.1-271.10. +Generating RTLIL representation for module `\ODDRX2F'. +Replacing existing blackbox module `\ODDR71B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:274.1-279.10. +Generating RTLIL representation for module `\ODDR71B'. +Replacing existing blackbox module `\OSHX2A' at /usr/bin/../share/yosys/ecp5/cells_bb.v:282.1-287.10. +Generating RTLIL representation for module `\OSHX2A'. +Replacing existing blackbox module `\ODDRX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:290.1-295.10. +Generating RTLIL representation for module `\ODDRX2DQA'. +Replacing existing blackbox module `\ODDRX2DQSB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:298.1-303.10. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Replacing existing blackbox module `\TSHX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:306.1-312.10. +Generating RTLIL representation for module `\TSHX2DQA'. +Replacing existing blackbox module `\TSHX2DQSA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:315.1-321.10. +Generating RTLIL representation for module `\TSHX2DQSA'. +Replacing existing blackbox module `\DQSBUFM' at /usr/bin/../share/yosys/ecp5/cells_bb.v:324.1-339.10. +Generating RTLIL representation for module `\DQSBUFM'. +Replacing existing blackbox module `\DDRDLLA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:342.1-348.10. +Generating RTLIL representation for module `\DDRDLLA'. +Replacing existing blackbox module `\DLLDELD' at /usr/bin/../share/yosys/ecp5/cells_bb.v:351.1-357.10. +Generating RTLIL representation for module `\DLLDELD'. +Replacing existing blackbox module `\CLKDIVF' at /usr/bin/../share/yosys/ecp5/cells_bb.v:360.1-366.10. +Generating RTLIL representation for module `\CLKDIVF'. +Replacing existing blackbox module `\ECLKSYNCB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:369.1-373.10. +Generating RTLIL representation for module `\ECLKSYNCB'. +Replacing existing blackbox module `\ECLKBRIDGECS' at /usr/bin/../share/yosys/ecp5/cells_bb.v:376.1-380.10. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Replacing existing blackbox module `\DCCA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:383.1-387.10. +Generating RTLIL representation for module `\DCCA'. +Replacing existing blackbox module `\DCSC' at /usr/bin/../share/yosys/ecp5/cells_bb.v:390.1-397.10. +Generating RTLIL representation for module `\DCSC'. +Replacing existing blackbox module `\DCUA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:400.1-715.10. +Generating RTLIL representation for module `\DCUA'. +Replacing existing blackbox module `\EXTREFB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:718.1-728.10. +Generating RTLIL representation for module `\EXTREFB'. +Replacing existing blackbox module `\PCSCLKDIV' at /usr/bin/../share/yosys/ecp5/cells_bb.v:731.1-736.10. +Generating RTLIL representation for module `\PCSCLKDIV'. +Replacing existing blackbox module `\PUR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:740.1-744.10. +Generating RTLIL representation for module `\PUR'. +Replacing existing blackbox module `\GSR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:747.1-750.10. +Generating RTLIL representation for module `\GSR'. +Replacing existing blackbox module `\SGSR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:753.1-756.10. +Generating RTLIL representation for module `\SGSR'. +Replacing existing blackbox module `\PDPW16KD' at /usr/bin/../share/yosys/ecp5/cells_bb.v:760.1-850.10. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +26.3. Executing HIERARCHY pass (managing design hierarchy). + +26.3.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll + +26.3.2. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll +Removed 0 unused modules. + +26.4. Executing PROC pass (convert processes to netlists). + +26.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. +Cleaned up 1 empty switch. + +26.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316 in module DPR16X4C. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258 in module TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +26.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 42 assignments to connections. + +26.4.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. + Set init value: \Q = 1'0 + +26.4.5. Executing PROC_ARST pass (detect async resets in processes). + +26.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +26.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + 1/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_EN[3:0]$89320 + 2/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_DATA[3:0]$89321 + 3/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_ADDR[3:0]$89322 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + 1/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_EN[3:0]$89262 + 2/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_DATA[3:0]$89263 + 3/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_ADDR[3:0]$89264 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. + +26.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +26.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. + created $dff cell `$procdff$89389' with positive edge clock. +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89314_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89313_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89312_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89311_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89310_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89309_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89308_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89307_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89306_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89305_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89304_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89303_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89302_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89301_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89300_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89390' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_DATA' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89391' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_ADDR' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89392' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89255_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89254_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89253_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89252_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89251_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89250_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89249_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89248_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89247_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89246_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89245_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89244_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89243_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89242_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89241_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89240_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89393' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89394' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89395' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. + created direct connection (no actual register cell created). + +26.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +26.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. +Removing empty process `DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. +Cleaned up 4 empty switches. + +26.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_cell_alias_check. +Optimizing module lsc1_request_validator. +Optimizing module lsc1_blake3_alias_check. +Optimizing module lsc1_response_payload_mux. +Optimizing module lsc1_blake3_lifecycle. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_stream_adapter. +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_rx. +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Optimizing module lean_silicon_lsc1. +Optimizing module lsc1_packet_frontend. +Optimizing module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Optimizing module ulx3s_core_pll. +Optimizing module ulx3s_packet_top. +Optimizing module gf128_mul_bitstream. + +26.5. Executing FLATTEN pass (flatten design). +Deleting now unused module leanvm_b_stream_alu. +Deleting now unused module lsc1_cell_alias_check. +Deleting now unused module lsc1_request_validator. +Deleting now unused module lsc1_blake3_alias_check. +Deleting now unused module lsc1_response_payload_mux. +Deleting now unused module lsc1_blake3_lifecycle. +Deleting now unused module lsc1_field_encoder. +Deleting now unused module lsc1_stream_adapter. +Deleting now unused module lsc1_packet_tx. +Deleting now unused module lsc1_packet_rx. +Deleting now unused module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Deleting now unused module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Deleting now unused module lean_silicon_lsc1. +Deleting now unused module lsc1_packet_frontend. +Deleting now unused module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Deleting now unused module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Deleting now unused module ulx3s_core_pll. +Deleting now unused module gf128_mul_bitstream. + + +26.6. Executing TRIBUF pass. + +26.7. Executing DEMINOUT pass (demote inout ports to input or output). + +26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 9329 unused cells and 40894 unused wires. + + +26.10. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +26.11. Executing OPT pass (performing simple optimizations). + +26.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1008 cells. + +26.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15648: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86029: \bridge.g_packet.asic.packet_core.result_pending -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15124: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88031: \bridge.urx.wait_idle -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88029: \bridge.urx.wait_idle -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88048: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88044: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88040: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88054: \bridge.urx.receiving -> 1'0 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88051: \bridge.urx.receiving -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12978: \bridge.utx.tx_ready -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12975: \bridge.utx.tx_ready -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12973: \bridge.utx.tx_ready -> 1'0 + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15464. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15467. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15470. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15473. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15476. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15479. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15482. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15485. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15488. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15491. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15494. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15497. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15504. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15507. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15510. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15513. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15516. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15519. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15522. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15525. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15528. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15531. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15534. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15536. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15539. 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$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6936. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6938. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7020. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7023. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7025. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7092. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7094. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7145. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15438. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15441. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15444. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8953. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8956. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8959. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8962. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8965. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8968. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8974. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8977. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8980. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8983. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8986. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8992. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8995. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8998. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9001. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9007. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9010. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9013. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9019. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9022. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9028. + dead port 1/2 on $mux $flatten\bridge.\urx.$procmux$87804. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87806. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87809. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87812. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87863. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87866. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87869. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87911. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87914. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87947. +Removed 14532 multiplexer ports. + + +26.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New input vector for $reduce_or cell $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$reduce_or$../../asic_core/rtl/lsc1_blake3_alias_check.sv:63$2341: { \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [55] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [47:46] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [39:37] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [31:28] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [23:19] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [15:10] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [7:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=128'11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4609: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $auto$opt_reduce.cc:134:opt_pmux$89397 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4621: { $auto$opt_reduce.cc:134:opt_pmux$89399 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640: { $auto$opt_reduce.cc:134:opt_pmux$89401 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4642_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4688: { $auto$opt_reduce.cc:134:opt_pmux$89405 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89403 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4732: { $auto$opt_reduce.cc:134:opt_pmux$89409 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89407 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7733: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4609: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $auto$opt_reduce.cc:134:opt_pmux$89411 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4621: { $auto$opt_reduce.cc:134:opt_pmux$89413 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640: { $auto$opt_reduce.cc:134:opt_pmux$89415 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4642_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4688: { $auto$opt_reduce.cc:134:opt_pmux$89419 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89417 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4732: { $auto$opt_reduce.cc:134:opt_pmux$89423 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89421 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12522: { $auto$opt_reduce.cc:134:opt_pmux$89425 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=128'11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5245: { $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5200_CMP $auto$opt_reduce.cc:134:opt_pmux$89427 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5195_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5191_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5190_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5188_CMP } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4193, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4190, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4203, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4200, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4186, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4183, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4180, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4177, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4159, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4156, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4153, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4150, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4135, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4132, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4129, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4138, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4120, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4117, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4114, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4111, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4102, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4099, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4096, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4093, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4083, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4080, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4077, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4074, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4029, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4026, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4023, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4020, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3982, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3979, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3988, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3985, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3952, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3949, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3946, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3943, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3918, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3915, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3912, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3909, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3885, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3882, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3879, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3876, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3841, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3838, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3835, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3832, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3798, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3795, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3792, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3789, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3757, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3754, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3751, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3748, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3715, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3712, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3709, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3706, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3661, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3670, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3667, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3664, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3627, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3624, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3621, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3618, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3579, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3576, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3573, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3570, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3532, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3529, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3526, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3523, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3478, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3475, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3472, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3469, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3401, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3398, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3395, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3392, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83235: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3348, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83244: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3345, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83253: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3342, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83262: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3339, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 111 changes. + +26.11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 226 cells. + +26.11.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 15739 unused wires. + + +26.11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7617: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7609_CMP $auto$opt_reduce.cc:134:opt_pmux$89429 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89431 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4540: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89433 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7617: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP $auto$opt_reduce.cc:134:opt_pmux$89435 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89437 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4540: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89439 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 6 changes. + +26.11.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.11.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.11.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.11.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.11.20. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.11.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.23. Finished OPT passes. (There is nothing left to do.) + +26.12. Executing FSM pass (extract and optimize FSM). + +26.12.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.adapter.datapath.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.adapter.state as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.alu_operation as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.compute_state. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.n_deferred as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.n_writes as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.receiver.fault_status as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.receiver.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.scalar_staged_access_count as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.tx_external_kind. + +26.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\bridge.g_packet.asic.packet_core.adapter.datapath.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88735 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89433 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + found state code: 4'1010 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last + found state code: 4'0110 + found state code: 4'1000 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.core_rx_fire + found state code: 4'0111 + found state code: 4'0001 + found state code: 4'0010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP + found state code: 4'1001 + found state code: 4'0100 + found state code: 4'0011 + found state code: 4'0101 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last \bridge.g_packet.asic.packet_core.adapter.core_tx_fire \bridge.g_packet.asic.packet_core.adapter.core_rx_fire $auto$opt_reduce.cc:134:opt_pmux$89433 } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP } + transition: 4'0000 14'0------------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10----------0- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10--000000--1- -> 4'1010 15'010100010000000 + transition: 4'0000 14'10-------1--1- -> 4'0001 15'000010010000000 + transition: 4'0000 14'10------1---1- -> 4'0101 15'001010010000000 + transition: 4'0000 14'10-----1----1- -> 4'0011 15'000110010000000 + transition: 4'0000 14'10----1-----1- -> 4'0100 15'001000010000000 + transition: 4'0000 14'10---1------1- -> 4'1001 15'010010010000000 + transition: 4'0000 14'10--1-------1- -> 4'0000 15'000000010000000 + transition: 4'0000 14'11------------ -> 4'0000 15'000000010000000 + transition: 4'1000 14'0------------- -> 4'0000 15'000000000010000 + transition: 4'1000 14'10---------0-- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--------01-- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--------11-- -> 4'0000 15'000000000010000 + transition: 4'1000 14'11------------ -> 4'0000 15'000000000010000 + transition: 4'0100 14'0------------- -> 4'0000 15'000000001000000 + transition: 4'0100 14'10--------0--- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--------10-- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--------11-- -> 4'0000 15'000000001000000 + transition: 4'0100 14'11------------ -> 4'0000 15'000000001000000 + transition: 4'0010 14'0------------- -> 4'0000 15'000000000000010 + transition: 4'0010 14'10---------0-- -> 4'0010 15'000100000000010 + transition: 4'0010 14'10--------01-- -> 4'0001 15'000010000000010 + transition: 4'0010 14'10--------11-- -> 4'0000 15'000000000000010 + transition: 4'0010 14'11------------ -> 4'0000 15'000000000000010 + transition: 4'1010 14'0------------- -> 4'0000 15'000000000000001 + transition: 4'1010 14'10---------0-- -> 4'1010 15'010100000000001 + transition: 4'1010 14'10---------1-- -> 4'0000 15'000000000000001 + transition: 4'1010 14'11------------ -> 4'0000 15'000000000000001 + transition: 4'0110 14'0------------- -> 4'0000 15'000001000000000 + transition: 4'0110 14'10----------0- -> 4'0110 15'001101000000000 + transition: 4'0110 14'10----------1- -> 4'0111 15'001111000000000 + transition: 4'0110 14'11------------ -> 4'0000 15'000001000000000 + transition: 4'0001 14'0------------- -> 4'0000 15'000000100000000 + transition: 4'0001 14'10----------0- -> 4'0001 15'000010100000000 + transition: 4'0001 14'10----------1- -> 4'0010 15'000100100000000 + transition: 4'0001 14'11------------ -> 4'0000 15'000000100000000 + transition: 4'1001 14'0------------- -> 4'0000 15'000000000100000 + transition: 4'1001 14'10---------0-- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10-0-------1-- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10-1-------1-- -> 4'0000 15'000000000100000 + transition: 4'1001 14'11------------ -> 4'0000 15'000000000100000 + transition: 4'0101 14'0------------- -> 4'0000 15'000000000001000 + transition: 4'0101 14'10----------0- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10--------0-1- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10--------1-1- -> 4'0110 15'001100000001000 + transition: 4'0101 14'11------------ -> 4'0000 15'000000000001000 + transition: 4'0011 14'0------------- -> 4'0000 15'000000000000100 + transition: 4'0011 14'10---------0-- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--------01-- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--------11-- -> 4'0000 15'000000000000100 + transition: 4'0011 14'11------------ -> 4'0000 15'000000000000100 + transition: 4'0111 14'0------------- -> 4'0000 15'100000000000000 + transition: 4'0111 14'100----------- -> 4'0111 15'101110000000000 + transition: 4'0111 14'101-------0--- -> 4'0110 15'101100000000000 + transition: 4'0111 14'101-------1--- -> 4'1000 15'110000000000000 + transition: 4'0111 14'11------------ -> 4'0000 15'100000000000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.compute_state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88859 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.fault_valid + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_reject + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_validator.is_xor + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y + found state code: 4'0001 + found state code: 4'0101 + found state code: 4'0011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y + found ctrl input: \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y + found state code: 4'1000 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y + found state code: 4'0110 + found state code: 4'0100 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + found state code: 4'0010 + found state code: 4'1001 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + found state code: 4'1010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + found state code: 4'0111 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.request_reject $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP \bridge.g_packet.asic.packet_core.request_validator.is_xor \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.field_encoder.fault } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y } + transition: 4'0000 44'0------------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-000000------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'100010000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'101010000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'110000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--101------01-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'101100000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-011----------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-1------------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-1--------------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'101000000000000 + transition: 4'0000 44'10100--00-00-000001000--------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10-00--00-00-000001001--------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10-10--00-00-00000100---------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-00000101---------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-0000011----------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-000001-----------------------1- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-00001-------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-0001--------------------------- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10--0--00-000001---------------------------- -> 4'0010 15'100100000000000 + transition: 4'0000 44'10--0--00-001001---------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-01----------------------------- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10--0--00-00-1------------------------------ -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-010------------------------------- -> 4'1001 15'110010000000000 + transition: 4'0000 44'10--0--00-011------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-1--------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--010---------------------------------0 -> 4'1010 15'110100000000000 + transition: 4'0000 44'10--0--011---------------------------------0 -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--01----------------------------------1 -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--1------------------------------------ -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--100------------------------------------- -> 4'0111 15'101110000000000 + transition: 4'0000 44'10--101------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--11-------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'11------------------------------------------ -> 4'0000 15'100000000000000 + transition: 4'1000 44'0------------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-000000------------------------- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--101------01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-011----------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-1------------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-1--------------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000100000 + transition: 4'1000 44'10100--00-00-000001000--------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10-00--00-00-000001001--------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10-10--00-00-00000100---------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-00000101---------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-0000011----------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-000001-----------------------1- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000100000 + transition: 4'1000 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-010------------------------------- -> 4'1001 15'010010000100000 + transition: 4'1000 44'10--0--00-011------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--010---------------------------------0 -> 4'1010 15'010100000100000 + transition: 4'1000 44'10--0--011---------------------------------0 -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--01----------------------------------1 -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--1------------------------------------ -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--100------------------------------------- -> 4'0111 15'001110000100000 + transition: 4'1000 44'10--101------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--11-------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'11------------------------------------------ -> 4'0000 15'000000000100000 + transition: 4'0100 44'0------------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-000000------------------------- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--101------01-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-011----------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-1------------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-1--------------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10100--00-00-000001000--------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10-00--00-00-000001001--------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10-10--00-00-00000100---------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-00000101---------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-0000011----------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-000001-----------------------1- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000010000 + transition: 4'0100 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-010------------------------------- -> 4'1001 15'010010000010000 + transition: 4'0100 44'10--0--00-011------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--010---------------------------------0 -> 4'1010 15'010100000010000 + transition: 4'0100 44'10--0--011---------------------------------0 -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--01----------------------------------1 -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--1------------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--100------------------------------------- -> 4'0111 15'001110000010000 + transition: 4'0100 44'10--101------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--11-------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'11------------------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0010 44'0------------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-000000------------------------- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--101------01-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-011----------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-1------------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-1--------------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000010 + transition: 4'0010 44'10100--00-00-000001000--------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10-00--00-00-000001001--------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10-10--00-00-00000100---------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-00000101---------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-0000011----------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-000001-----------------------1- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000010 + transition: 4'0010 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000010 + transition: 4'0010 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--1------------------------------------ -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--100------------------------------------- -> 4'0111 15'001110000000010 + transition: 4'0010 44'10--101------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--11-------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'11------------------------------------------ -> 4'0000 15'000000000000010 + transition: 4'1010 44'0------------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-000000------------------------- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--101------01-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-011----------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-1------------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-1--------------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000001000000 + transition: 4'1010 44'10100--00-00-000001000--------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10-00--00-00-000001001--------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10-10--00-00-00000100---------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-00000101---------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-0000011----------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-000001-----------------------1- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10--0--00-000001---------------------------- -> 4'0010 15'000100001000000 + transition: 4'1010 44'10--0--00-001001---------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-010------------------------------- -> 4'1001 15'010010001000000 + transition: 4'1010 44'10--0--00-011------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-1--------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--010---------------------------------0 -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--011---------------------------------0 -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--01----------------------------------1 -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--1------------------------------------ -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--100------------------------------------- -> 4'0111 15'001110001000000 + transition: 4'1010 44'10--101------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--11-------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'11------------------------------------------ -> 4'0000 15'000000001000000 + transition: 4'0110 44'0------------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-000000------------------------- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000011000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001011000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010001000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--101------01-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-011----------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-1------------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-1--------------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001001000000000 + transition: 4'0110 44'10100--00-00-000001000--------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10-00--00-00-000001001--------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10-10--00-00-00000100---------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-00000101---------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-0000011----------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-000001-----------------------1- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10--0--00-000001---------------------------- -> 4'0010 15'000101000000000 + transition: 4'0110 44'10--0--00-001001---------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-01----------------------------- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10--0--00-00-1------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-010------------------------------- -> 4'1001 15'010011000000000 + transition: 4'0110 44'10--0--00-011------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-1--------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--010---------------------------------0 -> 4'1010 15'010101000000000 + transition: 4'0110 44'10--0--011---------------------------------0 -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--01----------------------------------1 -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--1------------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--100------------------------------------- -> 4'0111 15'001111000000000 + transition: 4'0110 44'10--101------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--11-------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'11------------------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0001 44'0------------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-000000------------------------- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--101------01-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-011----------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-1------------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-1--------------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000100 + transition: 4'0001 44'10100--00-00-000001000--------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10-00--00-00-000001001--------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10-10--00-00-00000100---------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-00000101---------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-0000011----------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-000001-----------------------1- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000100 + transition: 4'0001 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000100 + transition: 4'0001 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000100 + transition: 4'0001 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--1------------------------------------ -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--100------------------------------------- -> 4'0111 15'001110000000100 + transition: 4'0001 44'10--101------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--11-------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'11------------------------------------------ -> 4'0000 15'000000000000100 + transition: 4'1001 44'0------------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-000000------------------------- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--101------01-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-011----------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-1------------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-1--------------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000010000000 + transition: 4'1001 44'10100--00-00-000001000--------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10-00--00-00-000001001--------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10-10--00-00-00000100---------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-00000101---------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-0000011----------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-000001-----------------------1- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10--0--00-000001---------------------------- -> 4'0010 15'000100010000000 + transition: 4'1001 44'10--0--00-001001---------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-010------------------------------- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-011------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-1--------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--010---------------------------------0 -> 4'1010 15'010100010000000 + transition: 4'1001 44'10--0--011---------------------------------0 -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--01----------------------------------1 -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--1------------------------------------ -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--100------------------------------------- -> 4'0111 15'001110010000000 + transition: 4'1001 44'10--101------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--11-------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'11------------------------------------------ -> 4'0000 15'000000010000000 + transition: 4'0101 44'0------------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-000000------------------------- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--101------01-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-011----------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-1------------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-1--------------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000001000 + transition: 4'0101 44'10100--00-00-000001000--------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10-00--00-00-000001001--------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10-10--00-00-00000100---------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-00000101---------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-0000011----------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-000001-----------------------1- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000001000 + transition: 4'0101 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-010------------------------------- -> 4'1001 15'010010000001000 + transition: 4'0101 44'10--0--00-011------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--010---------------------------------0 -> 4'1010 15'010100000001000 + transition: 4'0101 44'10--0--011---------------------------------0 -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--01----------------------------------1 -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--1------------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--100------------------------------------- -> 4'0111 15'001110000001000 + transition: 4'0101 44'10--101------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--11-------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'11------------------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0011 44'0------------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-000000------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--101------01-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-011----------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-1------------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-1--------------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000001 + transition: 4'0011 44'10100--00-00-000001000--------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10-00--00-00-000001001--------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10-10--00-00-00000100---------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-00000101---------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-0000011----------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-000001-----------------------1- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000001 + transition: 4'0011 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000001 + transition: 4'0011 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000001 + transition: 4'0011 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--1------------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--100------------------------------------- -> 4'0111 15'001110000000001 + transition: 4'0011 44'10--101------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--11-------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'11------------------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0111 44'0------------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-000000------------------------- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--101------01-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-011----------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-1------------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-1--------------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000100000000 + transition: 4'0111 44'10100--00-00-000001000--------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10-00--00-00-000001001--------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10-10--00-00-00000100---------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-00000101---------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-0000011----------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-000001-----------------------1- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10--0--00-000001---------------------------- -> 4'0010 15'000100100000000 + transition: 4'0111 44'10--0--00-001001---------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-010------------------------------- -> 4'1001 15'010010100000000 + transition: 4'0111 44'10--0--00-011------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-1--------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--010---------------------------------0 -> 4'1010 15'010100100000000 + transition: 4'0111 44'10--0--011---------------------------------0 -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--01----------------------------------1 -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--1------------------------------------ -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--100------------------------------------- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--101------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--11-------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'11------------------------------------------ -> 4'0000 15'000000100000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88735 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89439 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + found state code: 4'1010 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last + found state code: 4'0110 + found state code: 4'1000 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + found state code: 4'0111 + found state code: 4'0001 + found state code: 4'0010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP + found state code: 4'1001 + found state code: 4'0100 + found state code: 4'0011 + found state code: 4'0101 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q $auto$opt_reduce.cc:134:opt_pmux$89439 \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y } + transition: 4'0000 14'0------------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-0---------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-1--000000-- -> 4'1010 15'000000010010100 + transition: 4'0000 14'10-1--1------- -> 4'0001 15'000000010000010 + transition: 4'0000 14'10-1---1------ -> 4'0101 15'000000010001010 + transition: 4'0000 14'10-1----1----- -> 4'0011 15'000000010000110 + transition: 4'0000 14'10-1-----1---- -> 4'0100 15'000000010001000 + transition: 4'0000 14'10-1------1--- -> 4'1001 15'000000010010010 + transition: 4'0000 14'10-1-------1-- -> 4'0000 15'000000010000000 + transition: 4'0000 14'11------------ -> 4'0000 15'000000010000000 + transition: 4'1000 14'0------------- -> 4'0000 15'000010000000000 + transition: 4'1000 14'10--0--------- -> 4'1000 15'000010000010000 + transition: 4'1000 14'10--10-------- -> 4'1000 15'000010000010000 + transition: 4'1000 14'10--11-------- -> 4'0000 15'000010000000000 + transition: 4'1000 14'11------------ -> 4'0000 15'000010000000000 + transition: 4'0100 14'0------------- -> 4'0000 15'000000100000000 + transition: 4'0100 14'10---0-------- -> 4'0100 15'000000100001000 + transition: 4'0100 14'10--01-------- -> 4'0100 15'000000100001000 + transition: 4'0100 14'10--11-------- -> 4'0000 15'000000100000000 + transition: 4'0100 14'11------------ -> 4'0000 15'000000100000000 + transition: 4'0010 14'0------------- -> 4'0000 15'010000000000000 + transition: 4'0010 14'10--0--------- -> 4'0010 15'010000000000100 + transition: 4'0010 14'10--10-------- -> 4'0001 15'010000000000010 + transition: 4'0010 14'10--11-------- -> 4'0000 15'010000000000000 + transition: 4'0010 14'11------------ -> 4'0000 15'010000000000000 + transition: 4'1010 14'0------------- -> 4'0000 15'100000000000000 + transition: 4'1010 14'10--0--------- -> 4'1010 15'100000000010100 + transition: 4'1010 14'10--1--------- -> 4'0000 15'100000000000000 + transition: 4'1010 14'11------------ -> 4'0000 15'100000000000000 + transition: 4'0110 14'0------------- -> 4'0000 15'000000000100000 + transition: 4'0110 14'10-0---------- -> 4'0110 15'000000000101100 + transition: 4'0110 14'10-1---------- -> 4'0111 15'000000000101110 + transition: 4'0110 14'11------------ -> 4'0000 15'000000000100000 + transition: 4'0001 14'0------------- -> 4'0000 15'000000001000000 + transition: 4'0001 14'10-0---------- -> 4'0001 15'000000001000010 + transition: 4'0001 14'10-1---------- -> 4'0010 15'000000001000100 + transition: 4'0001 14'11------------ -> 4'0000 15'000000001000000 + transition: 4'1001 14'0------------- -> 4'0000 15'000001000000000 + transition: 4'1001 14'10--0--------- -> 4'1001 15'000001000010010 + transition: 4'1001 14'10--1-------0- -> 4'1001 15'000001000010010 + transition: 4'1001 14'10--1-------1- -> 4'0000 15'000001000000000 + transition: 4'1001 14'11------------ -> 4'0000 15'000001000000000 + transition: 4'0101 14'0------------- -> 4'0000 15'000100000000000 + transition: 4'0101 14'10-0---------- -> 4'0101 15'000100000001010 + transition: 4'0101 14'10-1-0-------- -> 4'0101 15'000100000001010 + transition: 4'0101 14'10-1-1-------- -> 4'0110 15'000100000001100 + transition: 4'0101 14'11------------ -> 4'0000 15'000100000000000 + transition: 4'0011 14'0------------- -> 4'0000 15'001000000000000 + transition: 4'0011 14'10--0--------- -> 4'0011 15'001000000000110 + transition: 4'0011 14'10--10-------- -> 4'0011 15'001000000000110 + transition: 4'0011 14'10--11-------- -> 4'0000 15'001000000000000 + transition: 4'0011 14'11------------ -> 4'0000 15'001000000000000 + transition: 4'0111 14'0------------- -> 4'0000 15'000000000000001 + transition: 4'0111 14'10-----------0 -> 4'0111 15'000000000001111 + transition: 4'0111 14'10---0-------1 -> 4'0110 15'000000000001101 + transition: 4'0111 14'10---1-------1 -> 4'1000 15'000000000010001 + transition: 4'0111 14'11------------ -> 4'0000 15'000000000000001 +Extracting FSM `\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88765 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 3'000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y + found state code: 3'100 + found state code: 3'011 + found state code: 3'010 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiply_start + found state code: 3'001 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y \bridge.g_packet.asic.packet_core.field_encoder.multiply_start } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP } + transition: 3'000 8'0------- -> 3'000 8'00000001 + transition: 3'000 8'10-----0 -> 3'000 8'00000001 + transition: 3'000 8'10-----1 -> 3'001 8'00000101 + transition: 3'000 8'11------ -> 3'000 8'00000001 + transition: 3'100 8'0------- -> 3'000 8'00000010 + transition: 3'100 8'10-0---- -> 3'100 8'00010010 + transition: 3'100 8'10-1--0- -> 3'100 8'00010010 + transition: 3'100 8'10-1--1- -> 3'000 8'00000010 + transition: 3'100 8'11------ -> 3'000 8'00000010 + transition: 3'010 8'0------- -> 3'000 8'00100000 + transition: 3'010 8'100----- -> 3'010 8'00101000 + transition: 3'010 8'101----- -> 3'011 8'00101100 + transition: 3'010 8'11------ -> 3'000 8'00100000 + transition: 3'001 8'0------- -> 3'000 8'01000000 + transition: 3'001 8'100----- -> 3'001 8'01000100 + transition: 3'001 8'101----- -> 3'010 8'01001000 + transition: 3'001 8'11------ -> 3'000 8'01000000 + transition: 3'011 8'0------- -> 3'000 8'10000000 + transition: 3'011 8'100----- -> 3'011 8'10001100 + transition: 3'011 8'101-0--- -> 3'011 8'10001100 + transition: 3'011 8'101-10-- -> 3'000 8'10000000 + transition: 3'011 8'101-11-- -> 3'100 8'10010000 + transition: 3'011 8'11------ -> 3'000 8'10000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.receiver.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88811 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.rx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y + found state code: 3'000 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP + found state code: 3'011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89425 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y + found state code: 3'010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y + found state code: 3'001 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$89425 $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y \bridge.g_packet.asic.packet_core.receiver.rx_fire $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y } + transition: 3'000 10'-0-----000 -> 3'000 7'0100001 + transition: 3'000 10'-1-----000 -> 3'000 7'0100001 + transition: 3'000 10'-------100 -> 3'000 7'0100001 + transition: 3'000 10'------0-10 -> 3'001 7'0100011 + transition: 3'000 10'------1-10 -> 3'011 7'0100111 + transition: 3'000 10'---------1 -> 3'000 7'0100001 + transition: 3'010 10'-0-----000 -> 3'010 7'0010101 + transition: 3'010 10'-1-----000 -> 3'000 7'0010001 + transition: 3'010 10'-------100 -> 3'000 7'0010001 + transition: 3'010 10'-00-0--010 -> 3'010 7'0010101 + transition: 3'010 10'-10-0--010 -> 3'000 7'0010001 + transition: 3'010 10'--0-0--110 -> 3'000 7'0010001 + transition: 3'010 10'--1-0---10 -> 3'011 7'0010111 + transition: 3'010 10'-0--1--010 -> 3'010 7'0010101 + transition: 3'010 10'-1--1--010 -> 3'000 7'0010001 + transition: 3'010 10'----1--110 -> 3'000 7'0010001 + transition: 3'010 10'---------1 -> 3'000 7'0010001 + transition: 3'001 10'-0-----000 -> 3'001 7'1000011 + transition: 3'001 10'-1-----000 -> 3'000 7'1000001 + transition: 3'001 10'-------100 -> 3'000 7'1000001 + transition: 3'001 10'0--0----10 -> 3'000 7'1000001 + transition: 3'001 10'10-----010 -> 3'001 7'1000011 + transition: 3'001 10'11-----010 -> 3'000 7'1000001 + transition: 3'001 10'1------110 -> 3'000 7'1000001 + transition: 3'001 10'---1-0--10 -> 3'010 7'1000101 + transition: 3'001 10'---1-1--10 -> 3'011 7'1000111 + transition: 3'001 10'---------1 -> 3'000 7'1000001 + transition: 3'011 10'-0-----000 -> 3'011 7'0000110 + transition: 3'011 10'-1-----000 -> 3'000 7'0000000 + transition: 3'011 10'-------100 -> 3'000 7'0000000 + transition: 3'011 10'--------10 -> 3'000 7'0000000 + transition: 3'011 10'---------1 -> 3'000 7'0000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.tx_external_kind' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88855 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 3'000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.fault_valid + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_reject + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] + found state code: 3'100 + found state code: 3'011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] + found state code: 3'001 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y + found ctrl input: \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y + found state code: 3'010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y + found ctrl input: \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending + found ctrl input: \bridge.g_packet.asic.packet_core.result_pending + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y + found state code: 3'111 + found ctrl input: \bridge.g_packet.asic.packet_core.blake_retire_match + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_validator.bad_state + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y + found state code: 3'110 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y + found state code: 3'101 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.result_pending \bridge.g_packet.asic.packet_core.blake_retire_match \bridge.g_packet.asic.packet_core.request_reject $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] \bridge.g_packet.asic.packet_core.request_validator.bad_state \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.adapter.fault \bridge.g_packet.asic.packet_core.field_encoder.fault \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y } + transition: 3'000 51'0-------------------------------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000000 + transition: 3'000 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000000 + transition: 3'000 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000000 + transition: 3'000 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000000 + transition: 3'000 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000000 + transition: 3'000 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000000 + transition: 3'000 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000000 + transition: 3'000 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-001--------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-000-01---------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-1----------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-10-------------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-10---------------------------------0-- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----1------------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----100------------------------------------------ -> 3'000 10'0000000000 + transition: 3'000 51'10----10100---------------------------------------- -> 3'011 10'0011000000 + transition: 3'000 51'10----10101---------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----1011----------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----11------------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'11------------------------------------------------- -> 3'000 10'0000000000 + transition: 3'100 51'0-------------------------------------------------- -> 3'000 10'0000000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000100 + transition: 3'100 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000100 + transition: 3'100 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000100 + transition: 3'100 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000100 + transition: 3'100 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000100 + transition: 3'100 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000100 + transition: 3'100 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000100 + transition: 3'100 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-001--------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-000-01---------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-1----------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-10-------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-10---------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----1------------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----100------------------------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10----10100---------------------------------------- -> 3'011 10'0011000100 + transition: 3'100 51'10----10101---------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----1011----------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----11------------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'11------------------------------------------------- -> 3'000 10'0000000100 + transition: 3'010 51'0-------------------------------------------------- -> 3'000 10'1000000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'1100000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'1011000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'1001000000 + transition: 3'010 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'1010000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'1100000000 + transition: 3'010 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'1100000000 + transition: 3'010 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'1111000000 + transition: 3'010 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'1100000000 + transition: 3'010 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'1100000000 + transition: 3'010 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'1111000000 + transition: 3'010 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'1110000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'1101000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-001--------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-000-01---------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-1----------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-10-------------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-10---------------------------------0-- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-11---------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-1----------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----10-----------------------------------0-- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----11-----------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----1------------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----100------------------------------------------ -> 3'010 10'1010000000 + transition: 3'010 51'10----10100---------------------------------------- -> 3'011 10'1011000000 + transition: 3'010 51'10----10101---------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----1011----------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----11------------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'11------------------------------------------------- -> 3'000 10'1000000000 + transition: 3'110 51'0-------------------------------------------------- -> 3'000 10'0000010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001010000 + transition: 3'110 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100010000 + transition: 3'110 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100010000 + transition: 3'110 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111010000 + transition: 3'110 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100010000 + transition: 3'110 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100010000 + transition: 3'110 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111010000 + transition: 3'110 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-001--------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-000-01---------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-1----------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-10-------------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-10---------------------------------0-- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----10-----------------------------------0-- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----11-----------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----1------------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----100------------------------------------------ -> 3'110 10'0110010000 + transition: 3'110 51'10----10100---------------------------------------- -> 3'011 10'0011010000 + transition: 3'110 51'10----10101---------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----1011----------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----11------------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'11------------------------------------------------- -> 3'000 10'0000010000 + transition: 3'001 51'0-------------------------------------------------- -> 3'000 10'0000000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000001 + transition: 3'001 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000001 + transition: 3'001 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000001 + transition: 3'001 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000001 + transition: 3'001 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000001 + transition: 3'001 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000001 + transition: 3'001 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-001--------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-000-01---------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-1----------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-10-------------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-10---------------------------------0-- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----1------------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----100------------------------------------------ -> 3'001 10'0001000001 + transition: 3'001 51'10----10100---------------------------------------- -> 3'011 10'0011000001 + transition: 3'001 51'10----10101---------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----1011----------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----11------------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'11------------------------------------------------- -> 3'000 10'0000000001 + transition: 3'101 51'0-------------------------------------------------- -> 3'000 10'0000001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001001000 + transition: 3'101 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100001000 + transition: 3'101 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100001000 + transition: 3'101 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111001000 + transition: 3'101 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100001000 + transition: 3'101 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100001000 + transition: 3'101 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111001000 + transition: 3'101 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-001--------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-000-01---------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-1----------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-10-------------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-10---------------------------------0-- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----10-----------------------------------0-- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----11-----------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----1------------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----100------------------------------------------ -> 3'101 10'0101001000 + transition: 3'101 51'10----10100---------------------------------------- -> 3'011 10'0011001000 + transition: 3'101 51'10----10101---------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----1011----------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----11------------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'11------------------------------------------------- -> 3'000 10'0000001000 + transition: 3'011 51'0-------------------------------------------------- -> 3'000 10'0000000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000010 + transition: 3'011 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000010 + transition: 3'011 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000010 + transition: 3'011 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000010 + transition: 3'011 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000010 + transition: 3'011 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000010 + transition: 3'011 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000010 + transition: 3'011 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-001--------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-000-01---------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-1----------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-10-------------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-10---------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----1------------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----100------------------------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10----10100---------------------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----10101---------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----1011----------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----11------------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'11------------------------------------------------- -> 3'000 10'0000000010 + transition: 3'111 51'0-------------------------------------------------- -> 3'000 10'0000100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001100000 + transition: 3'111 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100100000 + transition: 3'111 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100100000 + transition: 3'111 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111100000 + transition: 3'111 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100100000 + transition: 3'111 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100100000 + transition: 3'111 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111100000 + transition: 3'111 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-001--------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-000-01---------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-1----------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-10-------------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-10---------------------------------0-- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----10-----------------------------------0-- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----11-----------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----1------------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----100------------------------------------------ -> 3'111 10'0111100000 + transition: 3'111 51'10----10100---------------------------------------- -> 3'011 10'0011100000 + transition: 3'111 51'10----10101---------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----1011----------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----11------------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'11------------------------------------------------- -> 3'000 10'0000100000 + +26.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + Merging pattern 51'10----0----0-0-0-000-01---------------------------- and 51'10----0----0-0-0-010-01---------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-010-01---------------------------- and 51'10----0----0-0-0-000-01---------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-10-------------------------------- and 51'10----0----0-0-0-11-------------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-11-------------------------------- and 51'10----0----0-0-0-10-------------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-10---------------------------------0-- and 51'10----0----0-11---------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-11---------------------------------0-- and 51'10----0----0-10---------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-1----------------------------------0-- and 51'10----0----0-1----------------------------------1-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-1----------------------------------1-- and 51'10----0----0-1----------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1--1-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1--1-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- from group (4 4 10'0001000001). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. + Merging pattern 10'-0-----000 and 10'-1-----000 from group (0 0 7'0100001). + Merging pattern 10'-1-----000 and 10'-0-----000 from group (0 0 7'0100001). + Merging pattern 10'-------000 and 10'-------100 from group (0 0 7'0100001). + Merging pattern 10'-------100 and 10'-------000 from group (0 0 7'0100001). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. + Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$89439. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. + Merging pattern 44'10000--00-00-000001000-0000--1000-----01-00- and 44'10000--00-00-000001000-0000--1001-----01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1001-----01-00- and 44'10000--00-00-000001000-0000--1000-----01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--100------01-00- and 44'10000--00-00-000001000-0000--101------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--101------01-00- and 44'10000--00-00-000001000-0000--100------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------00-00- and 44'10000--00-00-000001000-0000--10-------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------01-00- and 44'10000--00-00-000001000-0000--10-------00-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------0--00- and 44'10000--00-00-000001000-0000--11-------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--11-------0--00- and 44'10000--00-00-000001000-0000--10-------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0--00- and 44'10000--00-00-000001000-0000--1--------0--10- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0--10- and 44'10000--00-00-000001000-0000--1--------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0---0- and 44'10000--00-00-000001000-0100--1--------0---0- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0100--1--------0---0- and 44'10000--00-00-000001000-0000--1--------0---0- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0--00- and 44'10000--00-00-000001000-0-0100---------0--10- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0--10- and 44'10000--00-00-000001000-0-0100---------0--00- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0---0- and 44'10000--00-00-000001000-0-0101---------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0101---------0---0- and 44'10000--00-00-000001000-0-0100---------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-010----------0---0- and 44'10000--00-00-000001000-0-011----------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-011----------0---0- and 44'10000--00-00-000001000-0-010----------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-00000100010-00--0---100000-0-0- and 44'10000--00-00-00000100010-00--0---101000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---101000-0-0- and 44'10000--00-00-00000100010-00--0---100000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---10-000-0-0- and 44'10000--00-00-00000100010-00--0---11-000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---11-000-0-0- and 44'10000--00-00-00000100010-00--0---10-000-0-0- from group (6 6 15'000010000000100). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. + Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$89433. + +26.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 215 unused cells and 216 unused wires. + + +26.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [2]. + +26.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ---1 + 010 -> --1- + 001 -> -1-- + 011 -> 1--- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> -------1 + 100 -> ------1- + 010 -> -----1-- + 110 -> ----1--- + 001 -> ---1---- + 101 -> --1----- + 011 -> -1------ + 111 -> 1------- + +26.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440 (\bridge.g_packet.asic.packet_core.adapter.datapath.state): + + Number of input signals: 13 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.adapter.core_rx_fire + 1: \bridge.g_packet.asic.packet_core.adapter.core_tx_fire + 2: \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last + 3: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + 10: \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last + 11: \bridge.abort_q + 12: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + 1: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + 10: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 13'10----------0 -> 0 11'00010000000 + 1: 0 13'10--1-------1 -> 0 11'00010000000 + 2: 0 13'11----------- -> 0 11'00010000000 + 3: 0 13'0------------ -> 0 11'00010000000 + 4: 0 13'10----1-----1 -> 2 11'00010000000 + 5: 0 13'10--000000--1 -> 4 11'00010000000 + 6: 0 13'10-------1--1 -> 6 11'00010000000 + 7: 0 13'10---1------1 -> 7 11'00010000000 + 8: 0 13'10------1---1 -> 8 11'00010000000 + 9: 0 13'10-----1----1 -> 9 11'00010000000 + 10: 1 13'10--------11- -> 0 11'00000010000 + 11: 1 13'11----------- -> 0 11'00000010000 + 12: 1 13'0------------ -> 0 11'00000010000 + 13: 1 13'10---------0- -> 1 11'00000010000 + 14: 1 13'10--------01- -> 1 11'00000010000 + 15: 2 13'10--------11- -> 0 11'00001000000 + 16: 2 13'11----------- -> 0 11'00001000000 + 17: 2 13'0------------ -> 0 11'00001000000 + 18: 2 13'10--------10- -> 2 11'00001000000 + 19: 2 13'10--------0-- -> 2 11'00001000000 + 20: 3 13'10--------11- -> 0 11'00000000010 + 21: 3 13'11----------- -> 0 11'00000000010 + 22: 3 13'0------------ -> 0 11'00000000010 + 23: 3 13'10---------0- -> 3 11'00000000010 + 24: 3 13'10--------01- -> 6 11'00000000010 + 25: 4 13'10---------1- -> 0 11'00000000001 + 26: 4 13'11----------- -> 0 11'00000000001 + 27: 4 13'0------------ -> 0 11'00000000001 + 28: 4 13'10---------0- -> 4 11'00000000001 + 29: 5 13'11----------- -> 0 11'01000000000 + 30: 5 13'0------------ -> 0 11'01000000000 + 31: 5 13'10----------0 -> 5 11'01000000000 + 32: 5 13'10----------1 -> 10 11'01000000000 + 33: 6 13'11----------- -> 0 11'00100000000 + 34: 6 13'0------------ -> 0 11'00100000000 + 35: 6 13'10----------1 -> 3 11'00100000000 + 36: 6 13'10----------0 -> 6 11'00100000000 + 37: 7 13'10-1-------1- -> 0 11'00000100000 + 38: 7 13'11----------- -> 0 11'00000100000 + 39: 7 13'0------------ -> 0 11'00000100000 + 40: 7 13'10---------0- -> 7 11'00000100000 + 41: 7 13'10-0-------1- -> 7 11'00000100000 + 42: 8 13'11----------- -> 0 11'00000001000 + 43: 8 13'0------------ -> 0 11'00000001000 + 44: 8 13'10--------1-1 -> 5 11'00000001000 + 45: 8 13'10----------0 -> 8 11'00000001000 + 46: 8 13'10--------0-1 -> 8 11'00000001000 + 47: 9 13'10--------11- -> 0 11'00000000100 + 48: 9 13'11----------- -> 0 11'00000000100 + 49: 9 13'0------------ -> 0 11'00000000100 + 50: 9 13'10---------0- -> 9 11'00000000100 + 51: 9 13'10--------01- -> 9 11'00000000100 + 52: 10 13'11----------- -> 0 11'10000000000 + 53: 10 13'0------------ -> 0 11'10000000000 + 54: 10 13'101-------1-- -> 1 11'10000000000 + 55: 10 13'101-------0-- -> 5 11'10000000000 + 56: 10 13'100---------- -> 10 11'10000000000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.compute_state$89453 (\bridge.g_packet.asic.packet_core.compute_state): + + Number of input signals: 44 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.fault + 1: \bridge.g_packet.asic.packet_core.receiver.fault_valid + 2: \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent + 3: \bridge.g_packet.asic.packet_core.request_validator.is_xor + 4: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y + 7: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y + 8: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y + 9: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y + 11: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y + 12: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y + 13: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y + 14: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y + 15: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y + 16: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y + 17: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y + 18: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y + 19: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y + 20: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + 21: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] + 22: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + 23: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + 24: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + 25: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + 26: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + 27: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + 28: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + 29: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + 30: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + 31: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + 32: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + 33: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + 34: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + 35: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + 36: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + 37: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + 38: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + 39: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + 40: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + 41: \bridge.g_packet.asic.packet_core.request_reject + 42: \bridge.abort_q + 43: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y + 7: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y + 8: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y + 9: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 44'10--0--011---------------------------------0 -> 0 11'10000000000 + 1: 0 44'10--0--01----------------------------------1 -> 0 11'10000000000 + 2: 0 44'10000--00-00-000001000-0000--10-------00-00- -> 0 11'10000000000 + 3: 0 44'10000--00-00-000001000-0000--1001-----01-00- -> 0 11'10000000000 + 4: 0 44'10000--00-00-000001000-0000--101------01-00- -> 0 11'10000000000 + 5: 0 44'10000--00-00-000001000-0000--11-------0--00- -> 0 11'10000000000 + 6: 0 44'10000--00-00-000001000-0000--1--------0--10- -> 0 11'10000000000 + 7: 0 44'10000--00-00-000001000-0-0100---------0--10- -> 0 11'10000000000 + 8: 0 44'10000--00-00-00000100010-00--0---101000-0-0- -> 0 11'10000000000 + 9: 0 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 0 11'10000000000 + 10: 0 44'10000--00-00-00000100010-00--0---0--000---0- -> 0 11'10000000000 + 11: 0 44'10000--00-00-00000100000-00--0--------0---0- -> 0 11'10000000000 + 12: 0 44'10000--00-00-000001000-0100--1--------0---0- -> 0 11'10000000000 + 13: 0 44'10000--00-00-000001000-0-0101---------0---0- -> 0 11'10000000000 + 14: 0 44'10000--00-00-000001000-0-011----------0---0- -> 0 11'10000000000 + 15: 0 44'10000--00-00-000001000-0-1------------0---0- -> 0 11'10000000000 + 16: 0 44'10000--00-00-000001000-1--------------0---0- -> 0 11'10000000000 + 17: 0 44'10100--00-00-000001000--------------------0- -> 0 11'10000000000 + 18: 0 44'10-00--00-00-000001001--------------------0- -> 0 11'10000000000 + 19: 0 44'10-10--00-00-00000100---------------------0- -> 0 11'10000000000 + 20: 0 44'10--0--00-00-00000101---------------------0- -> 0 11'10000000000 + 21: 0 44'10--0--00-00-0000011----------------------0- -> 0 11'10000000000 + 22: 0 44'10--0--00-00-000001-----------------------1- -> 0 11'10000000000 + 23: 0 44'10--0--00-00-000000------------------------- -> 0 11'10000000000 + 24: 0 44'10--0--00-00-00001-------------------------- -> 0 11'10000000000 + 25: 0 44'10--0--00-001001---------------------------- -> 0 11'10000000000 + 26: 0 44'10--0--00-00-1------------------------------ -> 0 11'10000000000 + 27: 0 44'10--0--00-011------------------------------- -> 0 11'10000000000 + 28: 0 44'10--0--00-1--------------------------------- -> 0 11'10000000000 + 29: 0 44'10--0--1------------------------------------ -> 0 11'10000000000 + 30: 0 44'10--101------------------------------------- -> 0 11'10000000000 + 31: 0 44'10--11-------------------------------------- -> 0 11'10000000000 + 32: 0 44'11------------------------------------------ -> 0 11'10000000000 + 33: 0 44'0------------------------------------------- -> 0 11'10000000000 + 34: 0 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'10000000000 + 35: 0 44'10000--00-00-000001000----------------1---0- -> 2 11'10000000000 + 36: 0 44'10--0--00-000001---------------------------- -> 3 11'10000000000 + 37: 0 44'10--0--010---------------------------------0 -> 4 11'10000000000 + 38: 0 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'10000000000 + 39: 0 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'10000000000 + 40: 0 44'10--0--00-010------------------------------- -> 7 11'10000000000 + 41: 0 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'10000000000 + 42: 0 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'10000000000 + 43: 0 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'10000000000 + 44: 0 44'10--0--00-00-0001--------------------------- -> 9 11'10000000000 + 45: 0 44'10--0--00-00-01----------------------------- -> 9 11'10000000000 + 46: 0 44'10--100------------------------------------- -> 10 11'10000000000 + 47: 1 44'10--0--011---------------------------------0 -> 0 11'00000100000 + 48: 1 44'10--0--01----------------------------------1 -> 0 11'00000100000 + 49: 1 44'10--0--00-00-00001-------------------------- -> 0 11'00000100000 + 50: 1 44'10--0--00-001001---------------------------- -> 0 11'00000100000 + 51: 1 44'10--0--00-00-1------------------------------ -> 0 11'00000100000 + 52: 1 44'10--0--00-011------------------------------- -> 0 11'00000100000 + 53: 1 44'10--0--00-1--------------------------------- -> 0 11'00000100000 + 54: 1 44'10--0--1------------------------------------ -> 0 11'00000100000 + 55: 1 44'10--101------------------------------------- -> 0 11'00000100000 + 56: 1 44'10--11-------------------------------------- -> 0 11'00000100000 + 57: 1 44'11------------------------------------------ -> 0 11'00000100000 + 58: 1 44'0------------------------------------------- -> 0 11'00000100000 + 59: 1 44'10000--00-00-000001000-0-0100---------0--10- -> 1 11'00000100000 + 60: 1 44'10000--00-00-00000100010-00--0---101000-0-0- -> 1 11'00000100000 + 61: 1 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 1 11'00000100000 + 62: 1 44'10000--00-00-00000100010-00--0---0--000---0- -> 1 11'00000100000 + 63: 1 44'10000--00-00-00000100000-00--0--------0---0- -> 1 11'00000100000 + 64: 1 44'10000--00-00-000001000-0-00--1--------0---0- -> 1 11'00000100000 + 65: 1 44'10000--00-00-000001000-0-0101---------0---0- -> 1 11'00000100000 + 66: 1 44'10000--00-00-000001000-0-011----------0---0- -> 1 11'00000100000 + 67: 1 44'10000--00-00-000001000-0-1------------0---0- -> 1 11'00000100000 + 68: 1 44'10000--00-00-000001000-1--------------0---0- -> 1 11'00000100000 + 69: 1 44'10100--00-00-000001000--------------------0- -> 1 11'00000100000 + 70: 1 44'10-00--00-00-000001001--------------------0- -> 1 11'00000100000 + 71: 1 44'10-10--00-00-00000100---------------------0- -> 1 11'00000100000 + 72: 1 44'10--0--00-00-00000101---------------------0- -> 1 11'00000100000 + 73: 1 44'10--0--00-00-0000011----------------------0- -> 1 11'00000100000 + 74: 1 44'10--0--00-00-000001-----------------------1- -> 1 11'00000100000 + 75: 1 44'10--0--00-00-000000------------------------- -> 1 11'00000100000 + 76: 1 44'10000--00-00-000001000----------------1---0- -> 2 11'00000100000 + 77: 1 44'10--0--00-000001---------------------------- -> 3 11'00000100000 + 78: 1 44'10--0--010---------------------------------0 -> 4 11'00000100000 + 79: 1 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000100000 + 80: 1 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000100000 + 81: 1 44'10--0--00-010------------------------------- -> 7 11'00000100000 + 82: 1 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000100000 + 83: 1 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000100000 + 84: 1 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000100000 + 85: 1 44'10--0--00-00-0001--------------------------- -> 9 11'00000100000 + 86: 1 44'10--0--00-00-01----------------------------- -> 9 11'00000100000 + 87: 1 44'10--100------------------------------------- -> 10 11'00000100000 + 88: 2 44'10--0--011---------------------------------0 -> 0 11'00000010000 + 89: 2 44'10--0--01----------------------------------1 -> 0 11'00000010000 + 90: 2 44'10--0--00-00-00001-------------------------- -> 0 11'00000010000 + 91: 2 44'10--0--00-001001---------------------------- -> 0 11'00000010000 + 92: 2 44'10--0--00-00-1------------------------------ -> 0 11'00000010000 + 93: 2 44'10--0--00-011------------------------------- -> 0 11'00000010000 + 94: 2 44'10--0--00-1--------------------------------- -> 0 11'00000010000 + 95: 2 44'10--0--1------------------------------------ -> 0 11'00000010000 + 96: 2 44'10--101------------------------------------- -> 0 11'00000010000 + 97: 2 44'10--11-------------------------------------- -> 0 11'00000010000 + 98: 2 44'11------------------------------------------ -> 0 11'00000010000 + 99: 2 44'0------------------------------------------- -> 0 11'00000010000 + 100: 2 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000010000 + 101: 2 44'10000--00-00-000001000-0000--10-------00-00- -> 2 11'00000010000 + 102: 2 44'10000--00-00-000001000-0000--1001-----01-00- -> 2 11'00000010000 + 103: 2 44'10000--00-00-000001000-0000--101------01-00- -> 2 11'00000010000 + 104: 2 44'10000--00-00-000001000-0000--11-------0--00- -> 2 11'00000010000 + 105: 2 44'10000--00-00-000001000-0000--1--------0--10- -> 2 11'00000010000 + 106: 2 44'10000--00-00-000001000-0-0100---------0--10- -> 2 11'00000010000 + 107: 2 44'10000--00-00-00000100010-00--0---101000-0-0- -> 2 11'00000010000 + 108: 2 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 2 11'00000010000 + 109: 2 44'10000--00-00-00000100010-00--0---0--000---0- -> 2 11'00000010000 + 110: 2 44'10000--00-00-00000100000-00--0--------0---0- -> 2 11'00000010000 + 111: 2 44'10000--00-00-000001000-0100--1--------0---0- -> 2 11'00000010000 + 112: 2 44'10000--00-00-000001000-0-0101---------0---0- -> 2 11'00000010000 + 113: 2 44'10000--00-00-000001000-0-011----------0---0- -> 2 11'00000010000 + 114: 2 44'10000--00-00-000001000-0-1------------0---0- -> 2 11'00000010000 + 115: 2 44'10000--00-00-000001000-1--------------0---0- -> 2 11'00000010000 + 116: 2 44'10000--00-00-000001000----------------1---0- -> 2 11'00000010000 + 117: 2 44'10100--00-00-000001000--------------------0- -> 2 11'00000010000 + 118: 2 44'10-00--00-00-000001001--------------------0- -> 2 11'00000010000 + 119: 2 44'10-10--00-00-00000100---------------------0- -> 2 11'00000010000 + 120: 2 44'10--0--00-00-00000101---------------------0- -> 2 11'00000010000 + 121: 2 44'10--0--00-00-0000011----------------------0- -> 2 11'00000010000 + 122: 2 44'10--0--00-00-000001-----------------------1- -> 2 11'00000010000 + 123: 2 44'10--0--00-00-000000------------------------- -> 2 11'00000010000 + 124: 2 44'10--0--00-000001---------------------------- -> 3 11'00000010000 + 125: 2 44'10--0--010---------------------------------0 -> 4 11'00000010000 + 126: 2 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000010000 + 127: 2 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000010000 + 128: 2 44'10--0--00-010------------------------------- -> 7 11'00000010000 + 129: 2 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000010000 + 130: 2 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000010000 + 131: 2 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000010000 + 132: 2 44'10--0--00-00-0001--------------------------- -> 9 11'00000010000 + 133: 2 44'10--0--00-00-01----------------------------- -> 9 11'00000010000 + 134: 2 44'10--100------------------------------------- -> 10 11'00000010000 + 135: 3 44'10--0--011---------------------------------0 -> 0 11'00000000010 + 136: 3 44'10--0--01----------------------------------1 -> 0 11'00000000010 + 137: 3 44'10--0--00-00-00001-------------------------- -> 0 11'00000000010 + 138: 3 44'10--0--00-001001---------------------------- -> 0 11'00000000010 + 139: 3 44'10--0--00-00-1------------------------------ -> 0 11'00000000010 + 140: 3 44'10--0--00-011------------------------------- -> 0 11'00000000010 + 141: 3 44'10--0--00-1--------------------------------- -> 0 11'00000000010 + 142: 3 44'10--0--1------------------------------------ -> 0 11'00000000010 + 143: 3 44'10--101------------------------------------- -> 0 11'00000000010 + 144: 3 44'10--11-------------------------------------- -> 0 11'00000000010 + 145: 3 44'11------------------------------------------ -> 0 11'00000000010 + 146: 3 44'0------------------------------------------- -> 0 11'00000000010 + 147: 3 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000000010 + 148: 3 44'10000--00-00-000001000----------------1---0- -> 2 11'00000000010 + 149: 3 44'10000--00-00-000001000-0000--10-------00-00- -> 3 11'00000000010 + 150: 3 44'10000--00-00-000001000-0000--1001-----01-00- -> 3 11'00000000010 + 151: 3 44'10000--00-00-000001000-0000--101------01-00- -> 3 11'00000000010 + 152: 3 44'10000--00-00-000001000-0000--11-------0--00- -> 3 11'00000000010 + 153: 3 44'10000--00-00-000001000-0000--1--------0--10- -> 3 11'00000000010 + 154: 3 44'10000--00-00-000001000-0-0100---------0--10- -> 3 11'00000000010 + 155: 3 44'10000--00-00-00000100010-00--0---101000-0-0- -> 3 11'00000000010 + 156: 3 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 3 11'00000000010 + 157: 3 44'10000--00-00-00000100010-00--0---0--000---0- -> 3 11'00000000010 + 158: 3 44'10000--00-00-00000100000-00--0--------0---0- -> 3 11'00000000010 + 159: 3 44'10000--00-00-000001000-0100--1--------0---0- -> 3 11'00000000010 + 160: 3 44'10000--00-00-000001000-0-0101---------0---0- -> 3 11'00000000010 + 161: 3 44'10000--00-00-000001000-0-011----------0---0- -> 3 11'00000000010 + 162: 3 44'10000--00-00-000001000-0-1------------0---0- -> 3 11'00000000010 + 163: 3 44'10000--00-00-000001000-1--------------0---0- -> 3 11'00000000010 + 164: 3 44'10100--00-00-000001000--------------------0- -> 3 11'00000000010 + 165: 3 44'10-00--00-00-000001001--------------------0- -> 3 11'00000000010 + 166: 3 44'10-10--00-00-00000100---------------------0- -> 3 11'00000000010 + 167: 3 44'10--0--00-00-00000101---------------------0- -> 3 11'00000000010 + 168: 3 44'10--0--00-00-0000011----------------------0- -> 3 11'00000000010 + 169: 3 44'10--0--00-00-000001-----------------------1- -> 3 11'00000000010 + 170: 3 44'10--0--00-00-000000------------------------- -> 3 11'00000000010 + 171: 3 44'10--0--00-000001---------------------------- -> 3 11'00000000010 + 172: 3 44'10--0--010---------------------------------0 -> 4 11'00000000010 + 173: 3 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000000010 + 174: 3 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000000010 + 175: 3 44'10--0--00-010------------------------------- -> 7 11'00000000010 + 176: 3 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000010 + 177: 3 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000010 + 178: 3 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000010 + 179: 3 44'10--0--00-00-0001--------------------------- -> 9 11'00000000010 + 180: 3 44'10--0--00-00-01----------------------------- -> 9 11'00000000010 + 181: 3 44'10--100------------------------------------- -> 10 11'00000000010 + 182: 4 44'10--0--011---------------------------------0 -> 0 11'00001000000 + 183: 4 44'10--0--01----------------------------------1 -> 0 11'00001000000 + 184: 4 44'10--0--00-00-00001-------------------------- -> 0 11'00001000000 + 185: 4 44'10--0--00-001001---------------------------- -> 0 11'00001000000 + 186: 4 44'10--0--00-00-1------------------------------ -> 0 11'00001000000 + 187: 4 44'10--0--00-011------------------------------- -> 0 11'00001000000 + 188: 4 44'10--0--00-1--------------------------------- -> 0 11'00001000000 + 189: 4 44'10--0--1------------------------------------ -> 0 11'00001000000 + 190: 4 44'10--101------------------------------------- -> 0 11'00001000000 + 191: 4 44'10--11-------------------------------------- -> 0 11'00001000000 + 192: 4 44'11------------------------------------------ -> 0 11'00001000000 + 193: 4 44'0------------------------------------------- -> 0 11'00001000000 + 194: 4 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00001000000 + 195: 4 44'10000--00-00-000001000----------------1---0- -> 2 11'00001000000 + 196: 4 44'10--0--00-000001---------------------------- -> 3 11'00001000000 + 197: 4 44'10--0--010---------------------------------0 -> 4 11'00001000000 + 198: 4 44'10000--00-00-000001000-0000--10-------00-00- -> 4 11'00001000000 + 199: 4 44'10000--00-00-000001000-0000--1001-----01-00- -> 4 11'00001000000 + 200: 4 44'10000--00-00-000001000-0000--101------01-00- -> 4 11'00001000000 + 201: 4 44'10000--00-00-000001000-0000--11-------0--00- -> 4 11'00001000000 + 202: 4 44'10000--00-00-000001000-0000--1--------0--10- -> 4 11'00001000000 + 203: 4 44'10000--00-00-000001000-0-0100---------0--10- -> 4 11'00001000000 + 204: 4 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4 11'00001000000 + 205: 4 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4 11'00001000000 + 206: 4 44'10000--00-00-00000100010-00--0---0--000---0- -> 4 11'00001000000 + 207: 4 44'10000--00-00-00000100000-00--0--------0---0- -> 4 11'00001000000 + 208: 4 44'10000--00-00-000001000-0100--1--------0---0- -> 4 11'00001000000 + 209: 4 44'10000--00-00-000001000-0-0101---------0---0- -> 4 11'00001000000 + 210: 4 44'10000--00-00-000001000-0-011----------0---0- -> 4 11'00001000000 + 211: 4 44'10000--00-00-000001000-0-1------------0---0- -> 4 11'00001000000 + 212: 4 44'10000--00-00-000001000-1--------------0---0- -> 4 11'00001000000 + 213: 4 44'10100--00-00-000001000--------------------0- -> 4 11'00001000000 + 214: 4 44'10-00--00-00-000001001--------------------0- -> 4 11'00001000000 + 215: 4 44'10-10--00-00-00000100---------------------0- -> 4 11'00001000000 + 216: 4 44'10--0--00-00-00000101---------------------0- -> 4 11'00001000000 + 217: 4 44'10--0--00-00-0000011----------------------0- -> 4 11'00001000000 + 218: 4 44'10--0--00-00-000001-----------------------1- -> 4 11'00001000000 + 219: 4 44'10--0--00-00-000000------------------------- -> 4 11'00001000000 + 220: 4 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00001000000 + 221: 4 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00001000000 + 222: 4 44'10--0--00-010------------------------------- -> 7 11'00001000000 + 223: 4 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00001000000 + 224: 4 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00001000000 + 225: 4 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00001000000 + 226: 4 44'10--0--00-00-0001--------------------------- -> 9 11'00001000000 + 227: 4 44'10--0--00-00-01----------------------------- -> 9 11'00001000000 + 228: 4 44'10--100------------------------------------- -> 10 11'00001000000 + 229: 5 44'10--0--011---------------------------------0 -> 0 11'01000000000 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11'00000000100 + 295: 6 44'10000--00-00-000001000-0-0100---------0--10- -> 6 11'00000000100 + 296: 6 44'10000--00-00-00000100010-00--0---1--000-0-0- -> 6 11'00000000100 + 297: 6 44'10000--00-00-00000100010-00--0---0--000---0- -> 6 11'00000000100 + 298: 6 44'10000--00-00-00000100000-00--0--------0---0- -> 6 11'00000000100 + 299: 6 44'10000--00-00-000001000-0100--1--------0---0- -> 6 11'00000000100 + 300: 6 44'10000--00-00-000001000-0-0101---------0---0- -> 6 11'00000000100 + 301: 6 44'10000--00-00-000001000-0-011----------0---0- -> 6 11'00000000100 + 302: 6 44'10000--00-00-000001000-0-1------------0---0- -> 6 11'00000000100 + 303: 6 44'10000--00-00-000001000-1--------------0---0- -> 6 11'00000000100 + 304: 6 44'10100--00-00-000001000--------------------0- -> 6 11'00000000100 + 305: 6 44'10-00--00-00-000001001--------------------0- -> 6 11'00000000100 + 306: 6 44'10-10--00-00-00000100---------------------0- -> 6 11'00000000100 + 307: 6 44'10--0--00-00-00000101---------------------0- -> 6 11'00000000100 + 308: 6 44'10--0--00-00-0000011----------------------0- -> 6 11'00000000100 + 309: 6 44'10--0--00-00-000001-----------------------1- -> 6 11'00000000100 + 310: 6 44'10--0--00-00-000000------------------------- -> 6 11'00000000100 + 311: 6 44'10--0--00-010------------------------------- -> 7 11'00000000100 + 312: 6 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000100 + 313: 6 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000100 + 314: 6 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000100 + 315: 6 44'10--0--00-00-0001--------------------------- -> 9 11'00000000100 + 316: 6 44'10--0--00-00-01----------------------------- -> 9 11'00000000100 + 317: 6 44'10--100------------------------------------- -> 10 11'00000000100 + 318: 7 44'10--0--011---------------------------------0 -> 0 11'00010000000 + 319: 7 44'10--0--01----------------------------------1 -> 0 11'00010000000 + 320: 7 44'10--0--00-00-00001-------------------------- -> 0 11'00010000000 + 321: 7 44'10--0--00-001001---------------------------- -> 0 11'00010000000 + 322: 7 44'10--0--00-00-1------------------------------ -> 0 11'00010000000 + 323: 7 44'10--0--00-011------------------------------- -> 0 11'00010000000 + 324: 7 44'10--0--00-1--------------------------------- -> 0 11'00010000000 + 325: 7 44'10--0--1------------------------------------ -> 0 11'00010000000 + 326: 7 44'10--101------------------------------------- -> 0 11'00010000000 + 327: 7 44'10--11-------------------------------------- -> 0 11'00010000000 + 328: 7 44'11------------------------------------------ -> 0 11'00010000000 + 329: 7 44'0------------------------------------------- -> 0 11'00010000000 + 330: 7 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00010000000 + 331: 7 44'10000--00-00-000001000----------------1---0- -> 2 11'00010000000 + 332: 7 44'10--0--00-000001---------------------------- -> 3 11'00010000000 + 333: 7 44'10--0--010---------------------------------0 -> 4 11'00010000000 + 334: 7 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00010000000 + 335: 7 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00010000000 + 336: 7 44'10000--00-00-000001000-0000--10-------00-00- -> 7 11'00010000000 + 337: 7 44'10000--00-00-000001000-0000--1001-----01-00- -> 7 11'00010000000 + 338: 7 44'10000--00-00-000001000-0000--101------01-00- -> 7 11'00010000000 + 339: 7 44'10000--00-00-000001000-0000--11-------0--00- -> 7 11'00010000000 + 340: 7 44'10000--00-00-000001000-0000--1--------0--10- -> 7 11'00010000000 + 341: 7 44'10000--00-00-000001000-0-0100---------0--10- -> 7 11'00010000000 + 342: 7 44'10000--00-00-00000100010-00--0---101000-0-0- -> 7 11'00010000000 + 343: 7 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 7 11'00010000000 + 344: 7 44'10000--00-00-00000100010-00--0---0--000---0- -> 7 11'00010000000 + 345: 7 44'10000--00-00-00000100000-00--0--------0---0- -> 7 11'00010000000 + 346: 7 44'10000--00-00-000001000-0100--1--------0---0- -> 7 11'00010000000 + 347: 7 44'10000--00-00-000001000-0-0101---------0---0- -> 7 11'00010000000 + 348: 7 44'10000--00-00-000001000-0-011----------0---0- -> 7 11'00010000000 + 349: 7 44'10000--00-00-000001000-0-1------------0---0- -> 7 11'00010000000 + 350: 7 44'10000--00-00-000001000-1--------------0---0- -> 7 11'00010000000 + 351: 7 44'10100--00-00-000001000--------------------0- -> 7 11'00010000000 + 352: 7 44'10-00--00-00-000001001--------------------0- -> 7 11'00010000000 + 353: 7 44'10-10--00-00-00000100---------------------0- -> 7 11'00010000000 + 354: 7 44'10--0--00-00-00000101---------------------0- -> 7 11'00010000000 + 355: 7 44'10--0--00-00-0000011----------------------0- -> 7 11'00010000000 + 356: 7 44'10--0--00-00-000001-----------------------1- -> 7 11'00010000000 + 357: 7 44'10--0--00-00-000000------------------------- -> 7 11'00010000000 + 358: 7 44'10--0--00-010------------------------------- -> 7 11'00010000000 + 359: 7 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00010000000 + 360: 7 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00010000000 + 361: 7 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00010000000 + 362: 7 44'10--0--00-00-0001--------------------------- -> 9 11'00010000000 + 363: 7 44'10--0--00-00-01----------------------------- -> 9 11'00010000000 + 364: 7 44'10--100------------------------------------- -> 10 11'00010000000 + 365: 8 44'10--0--011---------------------------------0 -> 0 11'00000001000 + 366: 8 44'10--0--01----------------------------------1 -> 0 11'00000001000 + 367: 8 44'10--0--00-00-00001-------------------------- -> 0 11'00000001000 + 368: 8 44'10--0--00-001001---------------------------- -> 0 11'00000001000 + 369: 8 44'10--0--00-00-1------------------------------ -> 0 11'00000001000 + 370: 8 44'10--0--00-011------------------------------- -> 0 11'00000001000 + 371: 8 44'10--0--00-1--------------------------------- -> 0 11'00000001000 + 372: 8 44'10--0--1------------------------------------ -> 0 11'00000001000 + 373: 8 44'10--101------------------------------------- -> 0 11'00000001000 + 374: 8 44'10--11-------------------------------------- -> 0 11'00000001000 + 375: 8 44'11------------------------------------------ -> 0 11'00000001000 + 376: 8 44'0------------------------------------------- -> 0 11'00000001000 + 377: 8 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000001000 + 378: 8 44'10000--00-00-000001000----------------1---0- -> 2 11'00000001000 + 379: 8 44'10--0--00-000001---------------------------- -> 3 11'00000001000 + 380: 8 44'10--0--010---------------------------------0 -> 4 11'00000001000 + 381: 8 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000001000 + 382: 8 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000001000 + 383: 8 44'10--0--00-010------------------------------- -> 7 11'00000001000 + 384: 8 44'10000--00-00-000001000-0000--10-------00-00- -> 8 11'00000001000 + 385: 8 44'10000--00-00-000001000-0000--1001-----01-00- -> 8 11'00000001000 + 386: 8 44'10000--00-00-000001000-0000--101------01-00- -> 8 11'00000001000 + 387: 8 44'10000--00-00-000001000-0000--11-------0--00- -> 8 11'00000001000 + 388: 8 44'10000--00-00-000001000-0000--1--------0--10- -> 8 11'00000001000 + 389: 8 44'10000--00-00-000001000-0-0100---------0--10- -> 8 11'00000001000 + 390: 8 44'10000--00-00-00000100010-00--0---101000-0-0- -> 8 11'00000001000 + 391: 8 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 8 11'00000001000 + 392: 8 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000001000 + 393: 8 44'10000--00-00-00000100010-00--0---0--000---0- -> 8 11'00000001000 + 394: 8 44'10000--00-00-00000100000-00--0--------0---0- -> 8 11'00000001000 + 395: 8 44'10000--00-00-000001000-0100--1--------0---0- -> 8 11'00000001000 + 396: 8 44'10000--00-00-000001000-0-0101---------0---0- -> 8 11'00000001000 + 397: 8 44'10000--00-00-000001000-0-011----------0---0- -> 8 11'00000001000 + 398: 8 44'10000--00-00-000001000-0-1------------0---0- -> 8 11'00000001000 + 399: 8 44'10000--00-00-000001000-1--------------0---0- -> 8 11'00000001000 + 400: 8 44'10100--00-00-000001000--------------------0- -> 8 11'00000001000 + 401: 8 44'10-00--00-00-000001001--------------------0- -> 8 11'00000001000 + 402: 8 44'10-10--00-00-00000100---------------------0- -> 8 11'00000001000 + 403: 8 44'10--0--00-00-00000101---------------------0- -> 8 11'00000001000 + 404: 8 44'10--0--00-00-0000011----------------------0- -> 8 11'00000001000 + 405: 8 44'10--0--00-00-000001-----------------------1- -> 8 11'00000001000 + 406: 8 44'10--0--00-00-000000------------------------- -> 8 11'00000001000 + 407: 8 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000001000 + 408: 8 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000001000 + 409: 8 44'10--0--00-00-0001--------------------------- -> 9 11'00000001000 + 410: 8 44'10--0--00-00-01----------------------------- -> 9 11'00000001000 + 411: 8 44'10--100------------------------------------- -> 10 11'00000001000 + 412: 9 44'10--0--011---------------------------------0 -> 0 11'00000000001 + 413: 9 44'10--0--01----------------------------------1 -> 0 11'00000000001 + 414: 9 44'10--0--00-00-00001-------------------------- -> 0 11'00000000001 + 415: 9 44'10--0--00-001001---------------------------- -> 0 11'00000000001 + 416: 9 44'10--0--00-00-1------------------------------ -> 0 11'00000000001 + 417: 9 44'10--0--00-011------------------------------- -> 0 11'00000000001 + 418: 9 44'10--0--00-1--------------------------------- -> 0 11'00000000001 + 419: 9 44'10--0--1------------------------------------ -> 0 11'00000000001 + 420: 9 44'10--101------------------------------------- -> 0 11'00000000001 + 421: 9 44'10--11-------------------------------------- -> 0 11'00000000001 + 422: 9 44'11------------------------------------------ -> 0 11'00000000001 + 423: 9 44'0------------------------------------------- -> 0 11'00000000001 + 424: 9 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000000001 + 425: 9 44'10000--00-00-000001000----------------1---0- -> 2 11'00000000001 + 426: 9 44'10--0--00-000001---------------------------- -> 3 11'00000000001 + 427: 9 44'10--0--010---------------------------------0 -> 4 11'00000000001 + 428: 9 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000000001 + 429: 9 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000000001 + 430: 9 44'10--0--00-010------------------------------- -> 7 11'00000000001 + 431: 9 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000001 + 432: 9 44'10000--00-00-000001000-0000--10-------00-00- -> 9 11'00000000001 + 433: 9 44'10000--00-00-000001000-0000--1001-----01-00- -> 9 11'00000000001 + 434: 9 44'10000--00-00-000001000-0000--101------01-00- -> 9 11'00000000001 + 435: 9 44'10000--00-00-000001000-0000--11-------0--00- -> 9 11'00000000001 + 436: 9 44'10000--00-00-000001000-0000--1--------0--10- -> 9 11'00000000001 + 437: 9 44'10000--00-00-000001000-0-0100---------0--10- -> 9 11'00000000001 + 438: 9 44'10000--00-00-00000100010-00--0---101000-0-0- -> 9 11'00000000001 + 439: 9 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 9 11'00000000001 + 440: 9 44'10000--00-00-00000100010-00--0---0--000---0- -> 9 11'00000000001 + 441: 9 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000001 + 442: 9 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000001 + 443: 9 44'10000--00-00-00000100000-00--0--------0---0- -> 9 11'00000000001 + 444: 9 44'10000--00-00-000001000-0100--1--------0---0- -> 9 11'00000000001 + 445: 9 44'10000--00-00-000001000-0-0101---------0---0- -> 9 11'00000000001 + 446: 9 44'10000--00-00-000001000-0-011----------0---0- -> 9 11'00000000001 + 447: 9 44'10000--00-00-000001000-0-1------------0---0- -> 9 11'00000000001 + 448: 9 44'10000--00-00-000001000-1--------------0---0- -> 9 11'00000000001 + 449: 9 44'10100--00-00-000001000--------------------0- -> 9 11'00000000001 + 450: 9 44'10-00--00-00-000001001--------------------0- -> 9 11'00000000001 + 451: 9 44'10-10--00-00-00000100---------------------0- -> 9 11'00000000001 + 452: 9 44'10--0--00-00-00000101---------------------0- -> 9 11'00000000001 + 453: 9 44'10--0--00-00-0000011----------------------0- -> 9 11'00000000001 + 454: 9 44'10--0--00-00-000001-----------------------1- -> 9 11'00000000001 + 455: 9 44'10--0--00-00-000000------------------------- -> 9 11'00000000001 + 456: 9 44'10--0--00-00-0001--------------------------- -> 9 11'00000000001 + 457: 9 44'10--0--00-00-01----------------------------- -> 9 11'00000000001 + 458: 9 44'10--100------------------------------------- -> 10 11'00000000001 + 459: 10 44'10--0--011---------------------------------0 -> 0 11'00100000000 + 460: 10 44'10--0--01----------------------------------1 -> 0 11'00100000000 + 461: 10 44'10--0--00-00-00001-------------------------- -> 0 11'00100000000 + 462: 10 44'10--0--00-001001---------------------------- -> 0 11'00100000000 + 463: 10 44'10--0--00-00-1------------------------------ -> 0 11'00100000000 + 464: 10 44'10--0--00-011------------------------------- -> 0 11'00100000000 + 465: 10 44'10--0--00-1--------------------------------- -> 0 11'00100000000 + 466: 10 44'10--0--1------------------------------------ -> 0 11'00100000000 + 467: 10 44'10--101------------------------------------- -> 0 11'00100000000 + 468: 10 44'10--11-------------------------------------- -> 0 11'00100000000 + 469: 10 44'11------------------------------------------ -> 0 11'00100000000 + 470: 10 44'0------------------------------------------- -> 0 11'00100000000 + 471: 10 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00100000000 + 472: 10 44'10000--00-00-000001000----------------1---0- -> 2 11'00100000000 + 473: 10 44'10--0--00-000001---------------------------- -> 3 11'00100000000 + 474: 10 44'10--0--010---------------------------------0 -> 4 11'00100000000 + 475: 10 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00100000000 + 476: 10 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00100000000 + 477: 10 44'10--0--00-010------------------------------- -> 7 11'00100000000 + 478: 10 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00100000000 + 479: 10 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00100000000 + 480: 10 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00100000000 + 481: 10 44'10--0--00-00-0001--------------------------- -> 9 11'00100000000 + 482: 10 44'10--0--00-00-01----------------------------- -> 9 11'00100000000 + 483: 10 44'10000--00-00-000001000-0000--10-------00-00- -> 10 11'00100000000 + 484: 10 44'10000--00-00-000001000-0000--1001-----01-00- -> 10 11'00100000000 + 485: 10 44'10000--00-00-000001000-0000--101------01-00- -> 10 11'00100000000 + 486: 10 44'10000--00-00-000001000-0000--11-------0--00- -> 10 11'00100000000 + 487: 10 44'10000--00-00-000001000-0000--1--------0--10- -> 10 11'00100000000 + 488: 10 44'10000--00-00-000001000-0-0100---------0--10- -> 10 11'00100000000 + 489: 10 44'10000--00-00-00000100010-00--0---101000-0-0- -> 10 11'00100000000 + 490: 10 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 10 11'00100000000 + 491: 10 44'10000--00-00-00000100010-00--0---0--000---0- -> 10 11'00100000000 + 492: 10 44'10000--00-00-00000100000-00--0--------0---0- -> 10 11'00100000000 + 493: 10 44'10000--00-00-000001000-0100--1--------0---0- -> 10 11'00100000000 + 494: 10 44'10000--00-00-000001000-0-0101---------0---0- -> 10 11'00100000000 + 495: 10 44'10000--00-00-000001000-0-011----------0---0- -> 10 11'00100000000 + 496: 10 44'10000--00-00-000001000-0-1------------0---0- -> 10 11'00100000000 + 497: 10 44'10000--00-00-000001000-1--------------0---0- -> 10 11'00100000000 + 498: 10 44'10100--00-00-000001000--------------------0- -> 10 11'00100000000 + 499: 10 44'10-00--00-00-000001001--------------------0- -> 10 11'00100000000 + 500: 10 44'10-10--00-00-00000100---------------------0- -> 10 11'00100000000 + 501: 10 44'10--0--00-00-00000101---------------------0- -> 10 11'00100000000 + 502: 10 44'10--0--00-00-0000011----------------------0- -> 10 11'00100000000 + 503: 10 44'10--0--00-00-000001-----------------------1- -> 10 11'00100000000 + 504: 10 44'10--0--00-00-000000------------------------- -> 10 11'00100000000 + 505: 10 44'10--100------------------------------------- -> 10 11'00100000000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466 (\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state): + + Number of input signals: 13 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP + 8: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last + 9: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + 10: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + 11: \bridge.abort_q + 12: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + 10: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 13'101-------1-- -> 0 11'00000001000 + 1: 0 13'100---------- -> 0 11'00000001000 + 2: 0 13'11----------- -> 0 11'00000001000 + 3: 0 13'0------------ -> 0 11'00000001000 + 4: 0 13'101-----1---- -> 2 11'00000001000 + 5: 0 13'101--000000-- -> 4 11'00000001000 + 6: 0 13'101--1------- -> 6 11'00000001000 + 7: 0 13'101------1--- -> 7 11'00000001000 + 8: 0 13'101---1------ -> 8 11'00000001000 + 9: 0 13'101----1----- -> 9 11'00000001000 + 10: 1 13'10-11-------- -> 0 11'00001000000 + 11: 1 13'11----------- -> 0 11'00001000000 + 12: 1 13'0------------ -> 0 11'00001000000 + 13: 1 13'10-10-------- -> 1 11'00001000000 + 14: 1 13'10-0--------- -> 1 11'00001000000 + 15: 2 13'10-11-------- -> 0 11'00000010000 + 16: 2 13'11----------- -> 0 11'00000010000 + 17: 2 13'0------------ -> 0 11'00000010000 + 18: 2 13'10--0-------- -> 2 11'00000010000 + 19: 2 13'10-01-------- -> 2 11'00000010000 + 20: 3 13'10-11-------- -> 0 11'01000000000 + 21: 3 13'11----------- -> 0 11'01000000000 + 22: 3 13'0------------ -> 0 11'01000000000 + 23: 3 13'10-0--------- -> 3 11'01000000000 + 24: 3 13'10-10-------- -> 6 11'01000000000 + 25: 4 13'10-1--------- -> 0 11'10000000000 + 26: 4 13'11----------- -> 0 11'10000000000 + 27: 4 13'0------------ -> 0 11'10000000000 + 28: 4 13'10-0--------- -> 4 11'10000000000 + 29: 5 13'11----------- -> 0 11'00000000010 + 30: 5 13'0------------ -> 0 11'00000000010 + 31: 5 13'100---------- -> 5 11'00000000010 + 32: 5 13'101---------- -> 10 11'00000000010 + 33: 6 13'11----------- -> 0 11'00000000100 + 34: 6 13'0------------ -> 0 11'00000000100 + 35: 6 13'101---------- -> 3 11'00000000100 + 36: 6 13'100---------- -> 6 11'00000000100 + 37: 7 13'10-1-------1- -> 0 11'00000100000 + 38: 7 13'11----------- -> 0 11'00000100000 + 39: 7 13'0------------ -> 0 11'00000100000 + 40: 7 13'10-1-------0- -> 7 11'00000100000 + 41: 7 13'10-0--------- -> 7 11'00000100000 + 42: 8 13'11----------- -> 0 11'00010000000 + 43: 8 13'0------------ -> 0 11'00010000000 + 44: 8 13'101-1-------- -> 5 11'00010000000 + 45: 8 13'101-0-------- -> 8 11'00010000000 + 46: 8 13'100---------- -> 8 11'00010000000 + 47: 9 13'10-11-------- -> 0 11'00100000000 + 48: 9 13'11----------- -> 0 11'00100000000 + 49: 9 13'0------------ -> 0 11'00100000000 + 50: 9 13'10-10-------- -> 9 11'00100000000 + 51: 9 13'10-0--------- -> 9 11'00100000000 + 52: 10 13'11----------- -> 0 11'00000000001 + 53: 10 13'0------------ -> 0 11'00000000001 + 54: 10 13'10--1-------1 -> 1 11'00000000001 + 55: 10 13'10--0-------1 -> 5 11'00000000001 + 56: 10 13'10----------0 -> 10 11'00000000001 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479 (\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state): + + Number of input signals: 8 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.multiply_start + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y + 4: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + 5: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + 6: \bridge.abort_q + 7: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 8'10-----0 -> 0 5'00001 + 1: 0 8'11------ -> 0 5'00001 + 2: 0 8'0------- -> 0 5'00001 + 3: 0 8'10-----1 -> 3 5'00001 + 4: 1 8'10-1--1- -> 0 5'00010 + 5: 1 8'11------ -> 0 5'00010 + 6: 1 8'0------- -> 0 5'00010 + 7: 1 8'10-1--0- -> 1 5'00010 + 8: 1 8'10-0---- -> 1 5'00010 + 9: 2 8'11------ -> 0 5'00100 + 10: 2 8'0------- -> 0 5'00100 + 11: 2 8'100----- -> 2 5'00100 + 12: 2 8'101----- -> 4 5'00100 + 13: 3 8'11------ -> 0 5'01000 + 14: 3 8'0------- -> 0 5'01000 + 15: 3 8'101----- -> 2 5'01000 + 16: 3 8'100----- -> 3 5'01000 + 17: 4 8'101-10-- -> 0 5'10000 + 18: 4 8'11------ -> 0 5'10000 + 19: 4 8'0------- -> 0 5'10000 + 20: 4 8'101-11-- -> 1 5'10000 + 21: 4 8'101-0--- -> 4 5'10000 + 22: 4 8'100----- -> 4 5'10000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486 (\bridge.g_packet.asic.packet_core.receiver.state): + + Number of input signals: 10 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y + 1: \bridge.g_packet.asic.packet_core.receiver.rx_fire + 2: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y + 9: $auto$opt_reduce.cc:134:opt_pmux$89425 + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 10'--------00 -> 0 4'0101 + 1: 0 10'---------1 -> 0 4'0101 + 2: 0 10'------0-10 -> 2 4'0101 + 3: 0 10'------1-10 -> 3 4'0101 + 4: 1 10'-1-----000 -> 0 4'0011 + 5: 1 10'-------100 -> 0 4'0011 + 6: 1 10'-10-0--010 -> 0 4'0011 + 7: 1 10'-1--1--010 -> 0 4'0011 + 8: 1 10'--0-0--110 -> 0 4'0011 + 9: 1 10'----1--110 -> 0 4'0011 + 10: 1 10'---------1 -> 0 4'0011 + 11: 1 10'-0-----000 -> 1 4'0011 + 12: 1 10'-00-0--010 -> 1 4'0011 + 13: 1 10'-0--1--010 -> 1 4'0011 + 14: 1 10'--1-0---10 -> 3 4'0011 + 15: 2 10'-1-----000 -> 0 4'1001 + 16: 2 10'-------100 -> 0 4'1001 + 17: 2 10'11-----010 -> 0 4'1001 + 18: 2 10'1------110 -> 0 4'1001 + 19: 2 10'0--0----10 -> 0 4'1001 + 20: 2 10'---------1 -> 0 4'1001 + 21: 2 10'---1-0--10 -> 1 4'1001 + 22: 2 10'-0-----000 -> 2 4'1001 + 23: 2 10'10-----010 -> 2 4'1001 + 24: 2 10'---1-1--10 -> 3 4'1001 + 25: 3 10'-1-----000 -> 0 4'0000 + 26: 3 10'-------100 -> 0 4'0000 + 27: 3 10'--------10 -> 0 4'0000 + 28: 3 10'---------1 -> 0 4'0000 + 29: 3 10'-0-----000 -> 3 4'0000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492 (\bridge.g_packet.asic.packet_core.tx_external_kind): + + Number of input signals: 51 + Number of output signals: 7 + Number of state bits: 8 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending + 1: \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending + 2: \bridge.g_packet.asic.packet_core.field_encoder.fault + 3: \bridge.g_packet.asic.packet_core.adapter.fault + 4: \bridge.g_packet.asic.packet_core.receiver.fault_valid + 5: \bridge.g_packet.asic.packet_core.request_validator.bad_state + 6: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] + 7: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] + 8: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] + 9: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y + 11: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y + 12: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y + 13: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y + 14: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + 15: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y + 16: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y + 17: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y + 18: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y + 19: $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y + 20: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y + 21: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + 22: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y + 23: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + 24: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + 25: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y + 26: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + 27: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + 28: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + 29: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + 30: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y + 31: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + 32: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + 33: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + 34: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y + 35: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + 36: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + 37: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + 38: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y + 39: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + 40: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y + 41: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y + 42: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + 43: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + 44: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + 45: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + 46: \bridge.g_packet.asic.packet_core.request_reject + 47: \bridge.g_packet.asic.packet_core.blake_retire_match + 48: \bridge.g_packet.asic.packet_core.result_pending + 49: \bridge.abort_q + 50: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y + + State encoding: + 0: 8'-------1 + 1: 8'------1- + 2: 8'-----1-- + 3: 8'----1--- + 4: 8'---1---- + 5: 8'--1----- + 6: 8'-1------ + 7: 8'1------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 51'10----0----0-10---------------------------------0-- -> 0 7'0000000 + 1: 0 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 0 7'0000000 + 2: 0 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 0 7'0000000 + 3: 0 51'10----0----0-0-0-0-0-0000-0------------------------ -> 0 7'0000000 + 4: 0 51'10----0----0-0-0-0-0-001--------------------------- -> 0 7'0000000 + 5: 0 51'10----0----0-0-0-000-01---------------------------- -> 0 7'0000000 + 6: 0 51'10----0----0-0-0-0-0-1----------------------------- -> 0 7'0000000 + 7: 0 51'10----0----0-0-0-10-------------------------------- -> 0 7'0000000 + 8: 0 51'10----100------------------------------------------ -> 0 7'0000000 + 9: 0 51'11------------------------------------------------- -> 0 7'0000000 + 10: 0 51'0-------------------------------------------------- -> 0 7'0000000 + 11: 0 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000000 + 12: 0 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000000 + 13: 0 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000000 + 14: 0 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000000 + 15: 0 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000000 + 16: 0 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000000 + 17: 0 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000000 + 18: 0 51'10----0----0-11---------------------------------0-- -> 1 7'0000000 + 19: 0 51'10----0----11-----------------------------------0-- -> 1 7'0000000 + 20: 0 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000000 + 21: 0 51'10----0----0-1----------------------------------1-- -> 1 7'0000000 + 22: 0 51'10----0----1------------------------------------1-- -> 1 7'0000000 + 23: 0 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000000 + 24: 0 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000000 + 25: 0 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000000 + 26: 0 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000000 + 27: 0 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000000 + 28: 0 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000000 + 29: 0 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000000 + 30: 0 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000000 + 31: 0 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000000 + 32: 0 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000000 + 33: 0 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000000 + 34: 0 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000000 + 35: 0 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000000 + 36: 0 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000000 + 37: 0 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000000 + 38: 0 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000000 + 39: 0 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000000 + 40: 0 51'10----10101---------------------------------------- -> 1 7'0000000 + 41: 0 51'10----1011----------------------------------------- -> 1 7'0000000 + 42: 0 51'10----11------------------------------------------- -> 1 7'0000000 + 43: 0 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000000 + 44: 0 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000000 + 45: 0 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000000 + 46: 0 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000000 + 47: 0 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000000 + 48: 0 51'10----0----10-----------------------------------0-- -> 6 7'0000000 + 49: 0 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000000 + 50: 0 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000000 + 51: 0 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000000 + 52: 0 51'10----10100---------------------------------------- -> 6 7'0000000 + 53: 0 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000000 + 54: 0 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000000 + 55: 1 51'11------------------------------------------------- -> 0 7'0000100 + 56: 1 51'0-------------------------------------------------- -> 0 7'0000100 + 57: 1 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000100 + 58: 1 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000100 + 59: 1 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000100 + 60: 1 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000100 + 61: 1 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000100 + 62: 1 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000100 + 63: 1 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000100 + 64: 1 51'10----0----11-----------------------------------0-- -> 1 7'0000100 + 65: 1 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000100 + 66: 1 51'10----0----1------------------------------------1-- -> 1 7'0000100 + 67: 1 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000100 + 68: 1 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000100 + 69: 1 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000100 + 70: 1 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000100 + 71: 1 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000100 + 72: 1 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000100 + 73: 1 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 1 7'0000100 + 74: 1 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 1 7'0000100 + 75: 1 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000100 + 76: 1 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000100 + 77: 1 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000100 + 78: 1 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000100 + 79: 1 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000100 + 80: 1 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000100 + 81: 1 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000100 + 82: 1 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000100 + 83: 1 51'10----0----0-0-0-0-0-0000-0------------------------ -> 1 7'0000100 + 84: 1 51'10----0----0-0-0-0-0-001--------------------------- -> 1 7'0000100 + 85: 1 51'10----0----0-0-0-0-0-01---------------------------- -> 1 7'0000100 + 86: 1 51'10----0----0-0-0-0-0-1----------------------------- -> 1 7'0000100 + 87: 1 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000100 + 88: 1 51'10----0----0-0-0-1--------------------------------- -> 1 7'0000100 + 89: 1 51'10----0----0-1------------------------------------- -> 1 7'0000100 + 90: 1 51'10----10101---------------------------------------- -> 1 7'0000100 + 91: 1 51'10----1011----------------------------------------- -> 1 7'0000100 + 92: 1 51'10----100------------------------------------------ -> 1 7'0000100 + 93: 1 51'10----11------------------------------------------- -> 1 7'0000100 + 94: 1 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000100 + 95: 1 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000100 + 96: 1 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000100 + 97: 1 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000100 + 98: 1 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000100 + 99: 1 51'10----0----10-----------------------------------0-- -> 6 7'0000100 + 100: 1 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000100 + 101: 1 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000100 + 102: 1 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000100 + 103: 1 51'10----10100---------------------------------------- -> 6 7'0000100 + 104: 1 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000100 + 105: 1 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000100 + 106: 2 51'11------------------------------------------------- -> 0 7'1000000 + 107: 2 51'0-------------------------------------------------- -> 0 7'1000000 + 108: 2 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'1000000 + 109: 2 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'1000000 + 110: 2 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'1000000 + 111: 2 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'1000000 + 112: 2 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'1000000 + 113: 2 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'1000000 + 114: 2 51'10----0----0-0-11-------------------------------0-- -> 1 7'1000000 + 115: 2 51'10----0----0-11---------------------------------0-- -> 1 7'1000000 + 116: 2 51'10----0----11-----------------------------------0-- -> 1 7'1000000 + 117: 2 51'10----0----0-0-1--------------------------------1-- -> 1 7'1000000 + 118: 2 51'10----0----0-1----------------------------------1-- -> 1 7'1000000 + 119: 2 51'10----0----1------------------------------------1-- -> 1 7'1000000 + 120: 2 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'1000000 + 121: 2 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'1000000 + 122: 2 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'1000000 + 123: 2 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'1000000 + 124: 2 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'1000000 + 125: 2 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'1000000 + 126: 2 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'1000000 + 127: 2 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'1000000 + 128: 2 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'1000000 + 129: 2 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'1000000 + 130: 2 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'1000000 + 131: 2 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'1000000 + 132: 2 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'1000000 + 133: 2 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'1000000 + 134: 2 51'10----0----0-0-0-010-01---------------------------- -> 1 7'1000000 + 135: 2 51'10----0----0-0-0-0-11------------------------------ -> 1 7'1000000 + 136: 2 51'10----0----0-0-0-11-------------------------------- -> 1 7'1000000 + 137: 2 51'10----10101---------------------------------------- -> 1 7'1000000 + 138: 2 51'10----1011----------------------------------------- -> 1 7'1000000 + 139: 2 51'10----11------------------------------------------- -> 1 7'1000000 + 140: 2 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'1000000 + 141: 2 51'10----0----0-10---------------------------------0-- -> 2 7'1000000 + 142: 2 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 2 7'1000000 + 143: 2 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 2 7'1000000 + 144: 2 51'10----0----0-0-0-0-0-0000-0------------------------ -> 2 7'1000000 + 145: 2 51'10----0----0-0-0-0-0-001--------------------------- -> 2 7'1000000 + 146: 2 51'10----0----0-0-0-000-01---------------------------- -> 2 7'1000000 + 147: 2 51'10----0----0-0-0-0-0-1----------------------------- -> 2 7'1000000 + 148: 2 51'10----0----0-0-0-10-------------------------------- -> 2 7'1000000 + 149: 2 51'10----100------------------------------------------ -> 2 7'1000000 + 150: 2 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'1000000 + 151: 2 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'1000000 + 152: 2 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'1000000 + 153: 2 51'10----0----0-0-10-------------------------------0-- -> 6 7'1000000 + 154: 2 51'10----0----10-----------------------------------0-- -> 6 7'1000000 + 155: 2 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'1000000 + 156: 2 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'1000000 + 157: 2 51'10----0----0-0-0-0-10------------------------------ -> 6 7'1000000 + 158: 2 51'10----10100---------------------------------------- -> 6 7'1000000 + 159: 2 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'1000000 + 160: 2 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'1000000 + 161: 3 51'11------------------------------------------------- -> 0 7'0010000 + 162: 3 51'0-------------------------------------------------- -> 0 7'0010000 + 163: 3 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0010000 + 164: 3 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0010000 + 165: 3 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0010000 + 166: 3 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0010000 + 167: 3 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0010000 + 168: 3 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0010000 + 169: 3 51'10----0----0-0-11-------------------------------0-- -> 1 7'0010000 + 170: 3 51'10----0----0-11---------------------------------0-- -> 1 7'0010000 + 171: 3 51'10----0----11-----------------------------------0-- -> 1 7'0010000 + 172: 3 51'10----0----0-0-1--------------------------------1-- -> 1 7'0010000 + 173: 3 51'10----0----0-1----------------------------------1-- -> 1 7'0010000 + 174: 3 51'10----0----1------------------------------------1-- -> 1 7'0010000 + 175: 3 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0010000 + 176: 3 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0010000 + 177: 3 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0010000 + 178: 3 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0010000 + 179: 3 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0010000 + 180: 3 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0010000 + 181: 3 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0010000 + 182: 3 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0010000 + 183: 3 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0010000 + 184: 3 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0010000 + 185: 3 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0010000 + 186: 3 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0010000 + 187: 3 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0010000 + 188: 3 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0010000 + 189: 3 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0010000 + 190: 3 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0010000 + 191: 3 51'10----0----0-0-0-11-------------------------------- -> 1 7'0010000 + 192: 3 51'10----10101---------------------------------------- -> 1 7'0010000 + 193: 3 51'10----1011----------------------------------------- -> 1 7'0010000 + 194: 3 51'10----11------------------------------------------- -> 1 7'0010000 + 195: 3 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0010000 + 196: 3 51'10----0----0-10---------------------------------0-- -> 3 7'0010000 + 197: 3 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0010000 + 198: 3 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3 7'0010000 + 199: 3 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3 7'0010000 + 200: 3 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3 7'0010000 + 201: 3 51'10----0----0-0-0-0-0-001--------------------------- -> 3 7'0010000 + 202: 3 51'10----0----0-0-0-000-01---------------------------- -> 3 7'0010000 + 203: 3 51'10----0----0-0-0-0-0-1----------------------------- -> 3 7'0010000 + 204: 3 51'10----0----0-0-0-10-------------------------------- -> 3 7'0010000 + 205: 3 51'10----100------------------------------------------ -> 3 7'0010000 + 206: 3 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0010000 + 207: 3 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0010000 + 208: 3 51'10----0----0-0-10-------------------------------0-- -> 6 7'0010000 + 209: 3 51'10----0----10-----------------------------------0-- -> 6 7'0010000 + 210: 3 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0010000 + 211: 3 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0010000 + 212: 3 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0010000 + 213: 3 51'10----10100---------------------------------------- -> 6 7'0010000 + 214: 3 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0010000 + 215: 3 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0010000 + 216: 4 51'11------------------------------------------------- -> 0 7'0000001 + 217: 4 51'0-------------------------------------------------- -> 0 7'0000001 + 218: 4 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000001 + 219: 4 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000001 + 220: 4 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000001 + 221: 4 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000001 + 222: 4 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000001 + 223: 4 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000001 + 224: 4 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000001 + 225: 4 51'10----0----0-11---------------------------------0-- -> 1 7'0000001 + 226: 4 51'10----0----11-----------------------------------0-- -> 1 7'0000001 + 227: 4 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000001 + 228: 4 51'10----0----0-1----------------------------------1-- -> 1 7'0000001 + 229: 4 51'10----0----1------------------------------------1-- -> 1 7'0000001 + 230: 4 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000001 + 231: 4 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000001 + 232: 4 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000001 + 233: 4 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000001 + 234: 4 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000001 + 235: 4 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000001 + 236: 4 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000001 + 237: 4 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000001 + 238: 4 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000001 + 239: 4 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000001 + 240: 4 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000001 + 241: 4 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000001 + 242: 4 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000001 + 243: 4 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000001 + 244: 4 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000001 + 245: 4 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000001 + 246: 4 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000001 + 247: 4 51'10----10101---------------------------------------- -> 1 7'0000001 + 248: 4 51'10----1011----------------------------------------- -> 1 7'0000001 + 249: 4 51'10----11------------------------------------------- -> 1 7'0000001 + 250: 4 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000001 + 251: 4 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000001 + 252: 4 51'10----0----0-10---------------------------------0-- -> 4 7'0000001 + 253: 4 51'10--000----0-0-0-0-0-0000-10-0------0-------1-0---- -> 4 7'0000001 + 254: 4 51'10----0----0-0-0-0-0-0000-0------------------------ -> 4 7'0000001 + 255: 4 51'10----0----0-0-0-0-0-001--------------------------- -> 4 7'0000001 + 256: 4 51'10----0----0-0-0-000-01---------------------------- -> 4 7'0000001 + 257: 4 51'10----0----0-0-0-0-0-1----------------------------- -> 4 7'0000001 + 258: 4 51'10----0----0-0-0-10-------------------------------- -> 4 7'0000001 + 259: 4 51'10----100------------------------------------------ -> 4 7'0000001 + 260: 4 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000001 + 261: 4 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000001 + 262: 4 51'10----0----10-----------------------------------0-- -> 6 7'0000001 + 263: 4 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000001 + 264: 4 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000001 + 265: 4 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000001 + 266: 4 51'10----10100---------------------------------------- -> 6 7'0000001 + 267: 4 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000001 + 268: 4 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000001 + 269: 5 51'11------------------------------------------------- -> 0 7'0001000 + 270: 5 51'0-------------------------------------------------- -> 0 7'0001000 + 271: 5 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0001000 + 272: 5 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0001000 + 273: 5 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0001000 + 274: 5 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0001000 + 275: 5 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0001000 + 276: 5 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0001000 + 277: 5 51'10----0----0-0-11-------------------------------0-- -> 1 7'0001000 + 278: 5 51'10----0----0-11---------------------------------0-- -> 1 7'0001000 + 279: 5 51'10----0----11-----------------------------------0-- -> 1 7'0001000 + 280: 5 51'10----0----0-0-1--------------------------------1-- -> 1 7'0001000 + 281: 5 51'10----0----0-1----------------------------------1-- -> 1 7'0001000 + 282: 5 51'10----0----1------------------------------------1-- -> 1 7'0001000 + 283: 5 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0001000 + 284: 5 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0001000 + 285: 5 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0001000 + 286: 5 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0001000 + 287: 5 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0001000 + 288: 5 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0001000 + 289: 5 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0001000 + 290: 5 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0001000 + 291: 5 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0001000 + 292: 5 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0001000 + 293: 5 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0001000 + 294: 5 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0001000 + 295: 5 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0001000 + 296: 5 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0001000 + 297: 5 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0001000 + 298: 5 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0001000 + 299: 5 51'10----0----0-0-0-11-------------------------------- -> 1 7'0001000 + 300: 5 51'10----10101---------------------------------------- -> 1 7'0001000 + 301: 5 51'10----1011----------------------------------------- -> 1 7'0001000 + 302: 5 51'10----11------------------------------------------- -> 1 7'0001000 + 303: 5 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0001000 + 304: 5 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0001000 + 305: 5 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0001000 + 306: 5 51'10----0----0-10---------------------------------0-- -> 5 7'0001000 + 307: 5 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 5 7'0001000 + 308: 5 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 5 7'0001000 + 309: 5 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0001000 + 310: 5 51'10----0----0-0-0-0-0-0000-0------------------------ -> 5 7'0001000 + 311: 5 51'10----0----0-0-0-0-0-001--------------------------- -> 5 7'0001000 + 312: 5 51'10----0----0-0-0-000-01---------------------------- -> 5 7'0001000 + 313: 5 51'10----0----0-0-0-0-0-1----------------------------- -> 5 7'0001000 + 314: 5 51'10----0----0-0-0-10-------------------------------- -> 5 7'0001000 + 315: 5 51'10----100------------------------------------------ -> 5 7'0001000 + 316: 5 51'10----0----0-0-10-------------------------------0-- -> 6 7'0001000 + 317: 5 51'10----0----10-----------------------------------0-- -> 6 7'0001000 + 318: 5 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0001000 + 319: 5 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0001000 + 320: 5 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0001000 + 321: 5 51'10----10100---------------------------------------- -> 6 7'0001000 + 322: 5 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0001000 + 323: 5 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0001000 + 324: 6 51'11------------------------------------------------- -> 0 7'0000010 + 325: 6 51'0-------------------------------------------------- -> 0 7'0000010 + 326: 6 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000010 + 327: 6 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000010 + 328: 6 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000010 + 329: 6 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000010 + 330: 6 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000010 + 331: 6 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000010 + 332: 6 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000010 + 333: 6 51'10----0----0-11---------------------------------0-- -> 1 7'0000010 + 334: 6 51'10----0----11-----------------------------------0-- -> 1 7'0000010 + 335: 6 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000010 + 336: 6 51'10----0----0-1----------------------------------1-- -> 1 7'0000010 + 337: 6 51'10----0----1------------------------------------1-- -> 1 7'0000010 + 338: 6 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000010 + 339: 6 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000010 + 340: 6 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000010 + 341: 6 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000010 + 342: 6 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000010 + 343: 6 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000010 + 344: 6 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000010 + 345: 6 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000010 + 346: 6 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000010 + 347: 6 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000010 + 348: 6 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000010 + 349: 6 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000010 + 350: 6 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000010 + 351: 6 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000010 + 352: 6 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000010 + 353: 6 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000010 + 354: 6 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000010 + 355: 6 51'10----10101---------------------------------------- -> 1 7'0000010 + 356: 6 51'10----1011----------------------------------------- -> 1 7'0000010 + 357: 6 51'10----11------------------------------------------- -> 1 7'0000010 + 358: 6 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000010 + 359: 6 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000010 + 360: 6 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000010 + 361: 6 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000010 + 362: 6 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000010 + 363: 6 51'10----0----0-10---------------------------------0-- -> 6 7'0000010 + 364: 6 51'10----0----10-----------------------------------0-- -> 6 7'0000010 + 365: 6 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000010 + 366: 6 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000010 + 367: 6 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 6 7'0000010 + 368: 6 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 6 7'0000010 + 369: 6 51'10----0----0-0-0-0-0-0000-0------------------------ -> 6 7'0000010 + 370: 6 51'10----0----0-0-0-0-0-001--------------------------- -> 6 7'0000010 + 371: 6 51'10----0----0-0-0-000-01---------------------------- -> 6 7'0000010 + 372: 6 51'10----0----0-0-0-0-0-1----------------------------- -> 6 7'0000010 + 373: 6 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000010 + 374: 6 51'10----0----0-0-0-10-------------------------------- -> 6 7'0000010 + 375: 6 51'10----10100---------------------------------------- -> 6 7'0000010 + 376: 6 51'10----100------------------------------------------ -> 6 7'0000010 + 377: 6 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000010 + 378: 6 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000010 + 379: 7 51'11------------------------------------------------- -> 0 7'0100000 + 380: 7 51'0-------------------------------------------------- -> 0 7'0100000 + 381: 7 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0100000 + 382: 7 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0100000 + 383: 7 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0100000 + 384: 7 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0100000 + 385: 7 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0100000 + 386: 7 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0100000 + 387: 7 51'10----0----0-0-11-------------------------------0-- -> 1 7'0100000 + 388: 7 51'10----0----0-11---------------------------------0-- -> 1 7'0100000 + 389: 7 51'10----0----11-----------------------------------0-- -> 1 7'0100000 + 390: 7 51'10----0----0-0-1--------------------------------1-- -> 1 7'0100000 + 391: 7 51'10----0----0-1----------------------------------1-- -> 1 7'0100000 + 392: 7 51'10----0----1------------------------------------1-- -> 1 7'0100000 + 393: 7 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0100000 + 394: 7 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0100000 + 395: 7 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0100000 + 396: 7 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0100000 + 397: 7 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0100000 + 398: 7 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0100000 + 399: 7 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0100000 + 400: 7 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0100000 + 401: 7 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0100000 + 402: 7 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0100000 + 403: 7 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0100000 + 404: 7 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0100000 + 405: 7 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0100000 + 406: 7 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0100000 + 407: 7 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0100000 + 408: 7 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0100000 + 409: 7 51'10----0----0-0-0-11-------------------------------- -> 1 7'0100000 + 410: 7 51'10----10101---------------------------------------- -> 1 7'0100000 + 411: 7 51'10----1011----------------------------------------- -> 1 7'0100000 + 412: 7 51'10----11------------------------------------------- -> 1 7'0100000 + 413: 7 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0100000 + 414: 7 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0100000 + 415: 7 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0100000 + 416: 7 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0100000 + 417: 7 51'10----0----0-0-10-------------------------------0-- -> 6 7'0100000 + 418: 7 51'10----0----10-----------------------------------0-- -> 6 7'0100000 + 419: 7 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0100000 + 420: 7 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0100000 + 421: 7 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0100000 + 422: 7 51'10----10100---------------------------------------- -> 6 7'0100000 + 423: 7 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0100000 + 424: 7 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0100000 + 425: 7 51'10----0----0-10---------------------------------0-- -> 7 7'0100000 + 426: 7 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 7 7'0100000 + 427: 7 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 7 7'0100000 + 428: 7 51'10----0----0-0-0-0-0-0000-0------------------------ -> 7 7'0100000 + 429: 7 51'10----0----0-0-0-0-0-001--------------------------- -> 7 7'0100000 + 430: 7 51'10----0----0-0-0-000-01---------------------------- -> 7 7'0100000 + 431: 7 51'10----0----0-0-0-0-0-1----------------------------- -> 7 7'0100000 + 432: 7 51'10----0----0-0-0-10-------------------------------- -> 7 7'0100000 + 433: 7 51'10----100------------------------------------------ -> 7 7'0100000 + +------------------------------------- + +26.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + +26.13. Executing OPT pass (performing simple optimizations). + +26.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 317 cells. + +26.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88850 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12932_Y, Q = \bridge.utx.shift, rval = 9'111111111). +Adding EN signal on $auto$ff.cc:266:slice$91348 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12932_Y, Q = \bridge.utx.shift). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88849 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12946_Y, Q = \bridge.utx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$91356 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12946_Y, Q = \bridge.utx.bit_cnt). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88848 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12957_Y, Q = \bridge.utx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91364 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12957_Y, Q = \bridge.utx.div_cnt). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88847 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12963_Y, Q = \bridge.utx.tx_serial, rval = 1'1). +Adding EN signal on $auto$ff.cc:266:slice$91368 ($sdff) from module ulx3s_packet_top (D = \bridge.utx.shift [0], Q = \bridge.utx.tx_serial). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88846 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12980_Y, Q = \bridge.utx.tx_ready, rval = 1'1). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89008 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88033_Y, Q = \bridge.urx.wait_idle, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$91375 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88033_Y, Q = \bridge.urx.wait_idle). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89007 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88056_Y, Q = \bridge.urx.receiving, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89006 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$2$lookahead\shift$4385[7:0]$4400, Q = \bridge.urx.shift, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91388 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$or$uart_rx.sv:0$4430_Y, Q = \bridge.urx.shift). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89005 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88079_Y, Q = \bridge.urx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$91394 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88079_Y, Q = \bridge.urx.bit_cnt). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89004 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88093_Y, Q = \bridge.urx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91408 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88093_Y, Q = \bridge.urx.div_cnt). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89003 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$87969_Y, Q = \bridge.urx.framing_err, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89002 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$87987_Y, Q = \bridge.urx.rx_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89001 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88111_Y, Q = \bridge.urx.rx_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91434 ($sdff) from module ulx3s_packet_top (D = \bridge.urx.shift, Q = \bridge.urx.rx_data). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88785 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8861_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$91442 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88784 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8873_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$91448 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88783 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8888_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$91454 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$not$../../asic_core/rtl/lsc1_packet_tx.sv:99$1956_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88782 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8897_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91460 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.tx_status, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88781 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8903_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91462 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.tx_length, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88780 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8915_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$91464 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8915_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.active). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88779 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8924_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91472 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88778 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8942_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$91480 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:100$1992_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88777 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8784_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.done_pulse, rval = 1'0). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88821 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12351_Y, Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88820 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12387_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9109_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9124_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9139_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9154_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9169_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9184_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9199_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9214_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9229_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9244_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9259_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9274_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9289_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9304_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9319_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9334_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9349_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9364_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9379_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9394_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9409_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9424_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9439_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9454_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9469_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9484_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9499_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9514_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9529_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9544_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9559_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9574_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9589_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9604_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9619_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9634_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9649_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9664_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9679_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9694_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9709_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9724_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9739_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9754_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9769_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9784_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9799_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9814_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9829_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9844_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9859_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9874_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9889_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9904_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9919_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9934_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9949_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9964_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9979_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9994_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10009_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10024_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10039_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10054_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10069_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10084_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10099_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10114_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10129_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10144_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10159_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10174_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10189_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10204_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10219_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10234_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10249_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10264_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10279_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10294_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10309_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10324_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10339_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10354_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10369_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10384_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10399_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10414_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10429_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10444_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10459_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10474_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10489_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10504_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10519_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10534_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10549_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10564_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10579_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10594_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10609_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10624_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10639_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10654_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10669_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10684_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10699_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10714_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10729_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10744_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10759_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10774_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10789_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10804_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10819_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10834_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10849_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10864_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10879_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10894_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10909_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10924_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10939_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10954_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10969_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10984_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10999_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11014_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11029_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11044_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11059_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11074_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11089_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11104_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11119_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11134_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11149_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11164_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11179_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11194_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11209_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11224_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11239_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11254_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11269_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11284_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11299_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11314_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11329_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11344_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11359_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11374_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11389_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11404_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11419_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11434_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11449_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11464_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11479_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11494_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11509_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11524_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11539_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11554_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11569_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11584_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11599_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11614_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11629_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11644_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11659_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11674_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11689_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11704_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11719_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11734_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11749_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11764_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11779_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11794_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11809_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11824_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11839_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11854_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11869_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11884_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11899_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11914_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11929_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix, rval = 1520'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11926_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11911_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11896_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [23:16]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11881_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [31:24]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11866_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [39:32]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11851_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [47:40]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11836_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [55:48]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11821_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [63:56]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11806_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [71:64]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11791_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [79:72]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11776_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [87:80]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11761_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:88]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11746_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [103:96]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11731_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [111:104]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11716_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [119:112]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11701_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [127:120]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11686_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [135:128]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11671_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [143:136]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11656_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [151:144]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11641_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [159:152]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11626_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [167:160]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11611_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [175:168]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11596_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [183:176]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11581_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [191:184]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11566_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [199:192]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11551_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [207:200]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11536_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [215:208]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11521_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [223:216]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11506_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [231:224]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11491_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [239:232]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11476_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [247:240]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11461_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [255:248]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11446_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [263:256]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11431_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [271:264]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11416_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [279:272]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11401_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [287:280]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11386_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [295:288]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11371_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [303:296]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11356_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [311:304]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11341_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [319:312]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11326_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [327:320]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11311_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [335:328]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11296_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [343:336]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11281_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [351:344]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11266_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [359:352]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11251_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [367:360]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11236_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [375:368]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11221_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [383:376]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11206_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [391:384]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11191_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [399:392]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11176_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [407:400]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11161_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [415:408]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11146_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [423:416]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11131_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [431:424]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11116_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [439:432]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11101_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [447:440]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11086_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [455:448]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11071_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [463:456]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11056_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [471:464]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11041_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [479:472]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11026_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [487:480]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11011_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [495:488]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10996_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [503:496]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10981_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [511:504]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10966_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [519:512]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10951_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [527:520]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10936_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [535:528]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10921_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [543:536]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10906_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [551:544]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10891_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [559:552]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10876_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [567:560]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10861_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [575:568]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10846_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [583:576]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10831_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [591:584]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10816_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [599:592]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10801_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [607:600]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10786_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [615:608]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10771_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [623:616]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10756_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [631:624]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10741_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [639:632]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10726_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [647:640]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10711_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [655:648]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10696_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [663:656]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10681_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [671:664]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10666_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [679:672]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10651_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [687:680]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10636_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [695:688]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10621_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [703:696]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10606_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [711:704]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10591_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [719:712]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10576_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [727:720]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10561_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [735:728]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10546_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [743:736]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10531_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [751:744]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10516_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [759:752]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10501_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [767:760]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10486_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [775:768]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10471_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [783:776]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10456_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [791:784]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10441_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [799:792]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10426_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [807:800]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10411_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [815:808]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10396_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [823:816]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10381_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [831:824]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10366_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [839:832]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10351_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [847:840]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10336_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [855:848]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10321_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [863:856]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10306_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [871:864]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10291_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [879:872]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10276_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [887:880]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10261_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [895:888]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10246_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [903:896]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10231_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [911:904]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10216_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [919:912]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10201_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [927:920]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10186_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [935:928]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10171_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [943:936]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10156_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [951:944]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10141_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [959:952]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10126_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [967:960]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10111_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [975:968]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10096_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [983:976]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10081_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [991:984]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10066_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [999:992]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10051_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1007:1000]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10036_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1015:1008]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10021_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1023:1016]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10006_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1031:1024]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9991_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1039:1032]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9976_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1047:1040]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9961_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1055:1048]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9946_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1063:1056]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9931_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1071:1064]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9916_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1079:1072]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9901_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1087:1080]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9886_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1095:1088]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9871_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1103:1096]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9856_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1111:1104]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9841_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1119:1112]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9826_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1127:1120]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9811_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1135:1128]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9796_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1143:1136]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9781_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1151:1144]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9766_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1159:1152]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9751_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1167:1160]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9736_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1175:1168]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9721_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1183:1176]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9706_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1191:1184]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9691_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1199:1192]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9676_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1207:1200]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9661_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1215:1208]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9646_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1223:1216]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9631_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1231:1224]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9616_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1239:1232]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9601_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1247:1240]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9586_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1255:1248]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9571_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1263:1256]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9556_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1271:1264]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9541_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1279:1272]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9526_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1287:1280]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9511_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1295:1288]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9496_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1303:1296]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9481_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1311:1304]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9466_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1319:1312]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9451_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1327:1320]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9436_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1335:1328]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9421_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1343:1336]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9406_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1351:1344]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9391_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1359:1352]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9376_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1367:1360]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9361_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1375:1368]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9346_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1383:1376]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9331_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1391:1384]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9316_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1399:1392]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9301_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1407:1400]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9286_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1415:1408]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9271_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1423:1416]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9256_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1431:1424]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9241_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1439:1432]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9226_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1447:1440]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9211_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1455:1448]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9196_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1463:1456]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9181_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1471:1464]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9166_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1479:1472]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9151_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1487:1480]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9136_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1495:1488]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9121_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1503:1496]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9106_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1511:1504]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12384_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1519:1512]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88819 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9043_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9059_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9076_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9094_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9056_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [23:16]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9073_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9091_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9040_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [31:24]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88818 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12404_Y, Q = \bridge.g_packet.asic.packet_core.receiver.crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$93252 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12397_Y, Q = \bridge.g_packet.asic.packet_core.receiver.crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88817 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12419_Y, Q = \bridge.g_packet.asic.packet_core.receiver.flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93262 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.flags). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88816 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12435_Y, Q = \bridge.g_packet.asic.packet_core.receiver.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93266 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.opcode). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88815 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12452_Y, Q = \bridge.g_packet.asic.packet_core.receiver.version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93270 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.version). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88814 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12002_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12016_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93274 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$93274 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length [7:0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88813 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12480_Y, Q = \bridge.g_packet.asic.packet_core.receiver.body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93281 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12473_Y, Q = \bridge.g_packet.asic.packet_core.receiver.body_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88812 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12494_Y, Q = \bridge.g_packet.asic.packet_core.receiver.header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$93289 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12488_Y, Q = \bridge.g_packet.asic.packet_core.receiver.header_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88810 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12569_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88809 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12603_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93298 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88808 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12626_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93316 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.declared_length, Q = \bridge.g_packet.asic.packet_core.receiver.frame_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88807 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12649_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93328 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.opcode, Q = \bridge.g_packet.asic.packet_core.receiver.frame_opcode). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88806 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12674_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$88838 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93341 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$88837 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93353 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88737 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4441_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4463_Y }, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93365 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4463_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$93365 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4441_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte [7:1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88736 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$93396 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.byte_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88734 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93422 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88769 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$93432 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88768 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7820_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93448 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.field_encoder.operand_b, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88767 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7836_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93454 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.field_encoder.operand_a, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88766 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7852_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93460 ($sdff) from module ulx3s_packet_top (D = 8'00000010, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88764 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93466 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88763 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$93480 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.payload_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88762 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7733_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88761 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7932_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.fault, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88756 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7408_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.saved_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93504 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.encoder_index, Q = \bridge.g_packet.asic.packet_core.field_encoder.saved_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88755 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423_Y [3:0], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [3:0], rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88755 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7420_Y [4], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [4], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93507 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136_Y [4], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [4]). +Adding EN signal on $auto$ff.cc:266:slice$93506 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423_Y [3:0], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [3:0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88754 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7364_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiply_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88753 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7438_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93527 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88752 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [0], rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88752 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93536 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$93535 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88751 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7468_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [0], rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88751 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7465_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93556 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$93555 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7468_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88750 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7374_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88749 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7477_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93580 ($sdff) from module ulx3s_packet_top (D = 1'1, Q = \bridge.g_packet.asic.packet_core.field_encoder.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88748 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7495_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93586 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7495_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.busy). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88747 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7226_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93594 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_seq). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88746 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7234_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_service_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93600 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_service_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88745 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7239_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93606 ($sdff) from module ulx3s_packet_top (D = 1'1, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88743 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7265_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93612 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7265_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_result_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88742 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7276_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93620 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_next_fp, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88741 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7284_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93626 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_next_pc, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88740 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7292_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93632 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_txn_id, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88739 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7299_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93638 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7299_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procdff$88838 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93646 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procdff$88837 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93658 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88737 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4441_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4463_Y }, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93670 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4463_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$93670 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4441_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte [7:1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88736 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$93701 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.byte_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88734 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93727 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88769 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.adapter.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$93737 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.adapter.result_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88768 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7820_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93753 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operand_b, Q = \bridge.g_packet.asic.packet_core.adapter.saved_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88767 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7836_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93759 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operand_a, Q = \bridge.g_packet.asic.packet_core.adapter.saved_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88766 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7852_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93765 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operation, Q = \bridge.g_packet.asic.packet_core.adapter.saved_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88765 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864_Y, Q = \bridge.g_packet.asic.packet_core.adapter.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$93771 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864_Y, Q = \bridge.g_packet.asic.packet_core.adapter.state). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88764 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.adapter.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93793 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.adapter.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88763 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.adapter.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$93807 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.adapter.payload_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88762 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7733_Y, Q = \bridge.g_packet.asic.packet_core.adapter.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88761 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7932_Y, Q = \bridge.g_packet.asic.packet_core.adapter.fault, rval = 1'0). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88945 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1519:1392], Q = \bridge.g_packet.asic.packet_core.staged_out_value[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88944 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1383:1256], Q = \bridge.g_packet.asic.packet_core.staged_out_value[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88943 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1391:1384], Q = \bridge.g_packet.asic.packet_core.staged_out_present[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88942 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1255:1248], Q = \bridge.g_packet.asic.packet_core.staged_out_present[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88941 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[7]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88940 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[6]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88939 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[5]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88938 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[4]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88937 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[3]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88936 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.cell_alias_check.address_c, Q = \bridge.g_packet.asic.packet_core.staged_access[2]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88935 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88934 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.cell_alias_check.address_a, Q = \bridge.g_packet.asic.packet_core.staged_access[0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88933 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83866_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[2], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94211 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83863_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[2]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88932 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83962_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[1], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94267 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83959_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88931 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84058_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[0], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94323 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84055_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88926 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\write_address[31:0], Q = \bridge.g_packet.asic.packet_core.write_address). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88925 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$9\solved_b[127:0], Q = \bridge.g_packet.asic.packet_core.solved_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88924 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$9\solved_a[127:0], Q = \bridge.g_packet.asic.packet_core.solved_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88923 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\result_value[127:0], Q = \bridge.g_packet.asic.packet_core.result_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88922 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$23\inv_value[127:0], Q = \bridge.g_packet.asic.packet_core.inv_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88921 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\val_c[127:0], Q = \bridge.g_packet.asic.packet_core.val_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88920 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\val_b[127:0], Q = \bridge.g_packet.asic.packet_core.val_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88919 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$21\val_a[127:0], Q = \bridge.g_packet.asic.packet_core.val_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88917 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\pres_c[7:0], Q = \bridge.g_packet.asic.packet_core.pres_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88916 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\pres_b[7:0], Q = \bridge.g_packet.asic.packet_core.pres_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88915 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$21\pres_a[7:0], Q = \bridge.g_packet.asic.packet_core.pres_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88914 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [103:96], Q = \bridge.g_packet.asic.packet_core.profile). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88913 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\deferred_local[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_local). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88912 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\deferred_target[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_target). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88911 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$6\next_fp_value[31:0], Q = \bridge.g_packet.asic.packet_core.next_fp_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88910 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$6\next_pc_value[31:0], Q = \bridge.g_packet.asic.packet_core.next_pc_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88909 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [687:656], Q = \bridge.g_packet.asic.packet_core.proposed_fp). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88908 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [655:624], Q = \bridge.g_packet.asic.packet_core.proposed_pc). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88906 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_c[31:0], Q = \bridge.g_packet.asic.packet_core.addr_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88905 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_b[31:0], Q = \bridge.g_packet.asic.packet_core.addr_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88904 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_a[31:0], Q = \bridge.g_packet.asic.packet_core.addr_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88900 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:64], Q = \bridge.g_packet.asic.packet_core.fp). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88899 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [63:32], Q = \bridge.g_packet.asic.packet_core.pc). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88898 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$17\txn_id[31:0], Q = \bridge.g_packet.asic.packet_core.txn_id). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88896 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\n_deferred[31:0], Q = \bridge.g_packet.asic.packet_core.n_deferred). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88895 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\n_writes[31:0], Q = \bridge.g_packet.asic.packet_core.n_writes). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88894 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$2\staged_write_count[1:0], Q = \bridge.g_packet.asic.packet_core.staged_write_count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$95461 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$25\staged_write_count[1:0], Q = \bridge.g_packet.asic.packet_core.staged_write_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88893 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [6:5] \bridge.g_packet.asic.packet_core.last_fault [3:2] }, rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88893 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [7] \bridge.g_packet.asic.packet_core.last_fault [4] \bridge.g_packet.asic.packet_core.last_fault [1:0] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$95508 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [7] \bridge.g_packet.asic.packet_core.last_fault [4] \bridge.g_packet.asic.packet_core.last_fault [1:0] }). +Adding EN signal on $auto$ff.cc:266:slice$95503 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [6:5] \bridge.g_packet.asic.packet_core.last_fault [3:2] }). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88892 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_status [6:5] \bridge.g_packet.asic.packet_core.last_status [3:2] }, rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88892 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_status [7] \bridge.g_packet.asic.packet_core.last_status [4] \bridge.g_packet.asic.packet_core.last_status [1:0] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$95588 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_status [7] \bridge.g_packet.asic.packet_core.last_status [4] \bridge.g_packet.asic.packet_core.last_status [1:0] }). +Adding EN signal on $auto$ff.cc:266:slice$95583 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_status [6:5] \bridge.g_packet.asic.packet_core.last_status [3:2] }). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88891 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84439_Y, Q = \bridge.g_packet.asic.packet_core.active_profile, rval = 8'00000001). +Adding EN signal on $auto$ff.cc:266:slice$95623 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [23:16], Q = \bridge.g_packet.asic.packet_core.active_profile). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88890 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84505_Y, Q = \bridge.g_packet.asic.packet_core.retire_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95661 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84456_Y, Q = \bridge.g_packet.asic.packet_core.retire_seq). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88889 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84571_Y, Q = \bridge.g_packet.asic.packet_core.committed_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95701 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84522_Y, Q = \bridge.g_packet.asic.packet_core.committed_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88888 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84637_Y, Q = \bridge.g_packet.asic.packet_core.committed_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95741 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84588_Y, Q = \bridge.g_packet.asic.packet_core.committed_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88887 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84703_Y, Q = \bridge.g_packet.asic.packet_core.state_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$95781 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84654_Y, Q = \bridge.g_packet.asic.packet_core.state_valid). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88886 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84799_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_local, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95821 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84796_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_local). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88885 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84895_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_target, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95877 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84892_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_target). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88884 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\write_value[127:0], Q = \bridge.g_packet.asic.packet_core.write_value). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88883 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84991_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_value, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$95978 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84988_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_value). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88882 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85087_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_address, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96034 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85084_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_address). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88881 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85183_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access_count, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96090 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88880 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85279_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$96146 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85276_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88879 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85375_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$96202 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85372_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88878 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85473_Y, Q = \bridge.g_packet.asic.packet_core.staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96258 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85470_Y, Q = \bridge.g_packet.asic.packet_core.staged_result_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88877 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85569_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96260 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85566_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88876 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85665_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96316 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85662_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88875 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85761_Y, Q = \bridge.g_packet.asic.packet_core.staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96372 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85758_Y, Q = \bridge.g_packet.asic.packet_core.staged_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88872 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85881_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96428 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:64], Q = \bridge.g_packet.asic.packet_core.blake_start_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88871 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85944_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96466 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88870 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86007_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96504 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [31:0], Q = \bridge.g_packet.asic.packet_core.blake_start_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88869 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82693_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_discard, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88868 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82762_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_accept, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88867 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82833_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88866 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86111_Y, Q = \bridge.g_packet.asic.packet_core.result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$96571 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86111_Y, Q = \bridge.g_packet.asic.packet_core.result_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88865 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86204_Y, Q = \bridge.g_packet.asic.packet_core.encoder_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96631 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86201_Y, Q = \bridge.g_packet.asic.packet_core.encoder_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88864 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82976_Y, Q = \bridge.g_packet.asic.packet_core.encoder_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88863 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86318_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96692 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86297_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88862 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86432_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96754 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86411_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88861 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86546_Y, Q = \bridge.g_packet.asic.packet_core.alu_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96816 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y, Q = \bridge.g_packet.asic.packet_core.alu_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88860 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83072_Y, Q = \bridge.g_packet.asic.packet_core.alu_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88858 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86785_Y, Q = \bridge.g_packet.asic.packet_core.capture_result_crc, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88857 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86944_Y, Q = \bridge.g_packet.asic.packet_core.short_detail, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96888 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86941_Y, Q = \bridge.g_packet.asic.packet_core.short_detail). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88856 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87095_Y, Q = \bridge.g_packet.asic.packet_core.short_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96928 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87092_Y, Q = \bridge.g_packet.asic.packet_core.short_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88854 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87419_Y, Q = \bridge.g_packet.asic.packet_core.tx_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96962 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87416_Y, Q = \bridge.g_packet.asic.packet_core.tx_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88853 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87581_Y, Q = \bridge.g_packet.asic.packet_core.tx_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96982 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87578_Y, Q = \bridge.g_packet.asic.packet_core.tx_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88852 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83226_Y, Q = \bridge.g_packet.asic.packet_core.tx_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.$procdff$89000 ($dff) from module ulx3s_packet_top (D = \bridge.por_shift [6:0], Q = \bridge.por_shift [7:1], rval = 7'0000000). +Adding SRST signal on $flatten\bridge.$procdff$88999 ($dff) from module ulx3s_packet_top (D = \bridge.urx.framing_err, Q = \bridge.abort_q, rval = 1'0). +Adding SRST signal on $flatten\bridge.$procdff$88998 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87777_Y, Q = \bridge.rx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$97010 ($sdff) from module ulx3s_packet_top (D = \bridge.urx.rx_data, Q = \bridge.rx_data_q). +Adding SRST signal on $flatten\bridge.$procdff$88997 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87785_Y, Q = \bridge.rx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$97016 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87785_Y, Q = \bridge.rx_full). +Adding SRST signal on $flatten\bridge.$procdff$88995 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87752_Y, Q = \bridge.tx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$97024 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.transmitter.tx_data, Q = \bridge.tx_data_q). +Adding SRST signal on $flatten\bridge.$procdff$88994 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87760_Y, Q = \bridge.tx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$97030 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87760_Y, Q = \bridge.tx_full). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. + +26.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 1539 unused cells and 1727 unused wires. + + +26.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7956. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7956. + dead port 1/3 on $pmux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7970. + dead port 2/3 on $pmux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7970. +Removed 4 multiplexer ports. + + +26.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1946 cells. + +26.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 2 unused cells and 1953 unused wires. + + +26.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.13.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.13.20. Executing OPT_DFF pass (perform DFF optimizations). + +26.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.13.23. Finished OPT passes. (There is nothing left to do.) + +26.14. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89023 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89024 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89025 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89026 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:284$4371 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:284$4372 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:285$4373 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:285$4374 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2288 ($div). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mod$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2290 ($mod). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91378 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91380 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96919 ($ne). +Removed top 8 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96913 ($ne). +Removed top 6 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96719 ($ne). +Removed top 6 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96717 ($ne). +Removed top 6 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96715 ($ne). +Removed top 6 bits (of 17) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96713 ($ne). +Removed top 6 bits (of 17) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96711 ($ne). +Removed top 6 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96709 ($ne). +Removed top 6 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96707 ($ne). +Removed top 6 bits (of 23) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96705 ($ne). +Removed top 6 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96703 ($ne). +Removed top 6 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96701 ($ne). +Removed top 6 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96699 ($ne). +Removed top 6 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96697 ($ne). +Removed top 6 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96695 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96674 ($ne). +Removed top 12 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96648 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96646 ($ne). +Removed top 12 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96644 ($ne). +Removed top 12 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96642 ($ne). +Removed top 12 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96640 ($ne). +Removed top 12 bits (of 23) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96638 ($ne). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96636 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96634 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95668 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95612 ($ne). +Removed top 12 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95610 ($ne). +Removed top 13 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95595 ($ne). +Removed top 13 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95593 ($ne). +Removed top 5 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95576 ($ne). +Removed top 10 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95568 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95564 ($ne). +Removed top 10 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95562 ($ne). +Removed top 9 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95560 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95558 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95556 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95554 ($ne). +Removed top 11 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95548 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95543 ($ne). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95541 ($ne). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95539 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95537 ($ne). +Removed top 9 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95535 ($ne). +Removed top 11 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95531 ($ne). +Removed top 13 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95529 ($ne). +Removed top 13 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95527 ($ne). +Removed top 11 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95525 ($ne). +Removed top 10 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95523 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95521 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95519 ($ne). +Removed top 4 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95517 ($ne). +Removed top 1 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95515 ($ne). +Removed top 1 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95513 ($ne). +Removed top 12 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95511 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95015 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95013 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95011 ($ne). +Removed top 4 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95009 ($ne). +Removed top 5 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95007 ($ne). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95005 ($ne). +Removed top 7 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95001 ($ne). +Removed top 7 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94999 ($ne). +Removed top 7 bits (of 11) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94997 ($ne). +Removed top 8 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94993 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94927 ($ne). +Removed top 9 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94911 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94819 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94817 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94727 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94452 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94450 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94446 ($ne). +Removed top 4 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94444 ($ne). +Removed top 4 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94442 ($ne). +Removed top 5 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94438 ($ne). +Removed top 6 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94434 ($ne). +Removed top 6 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94432 ($ne). +Removed top 6 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94430 ($ne). +Removed top 6 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94428 ($ne). +Removed top 6 bits (of 16) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94426 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94409 ($ne). +Removed top 5 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94405 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94254 ($ne). +Removed top 4 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94252 ($ne). +Removed top 5 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94250 ($ne). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94248 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94246 ($ne). +Removed top 8 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94244 ($ne). +Removed top 10 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94240 ($ne). +Removed top 10 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94238 ($ne). +Removed top 10 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94236 ($ne). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94232 ($ne). +Removed top 12 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94228 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94226 ($ne). +Removed top 9 bits (of 11) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94224 ($ne). +Removed top 9 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94222 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94220 ($ne). +Removed top 3 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94218 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94216 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94214 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93788 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93784 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93750 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93730 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93653 ($ne). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93591 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93521 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93425 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93362 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90938 ($eq). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90921 ($eq). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90917 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90902 ($eq). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90890 ($eq). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91353 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91469 ($ne). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177 ($lt). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2184 ($shiftx). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2193 ($shiftx). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:56$2199 ($eq). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 26 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 10 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2216 ($shiftx). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217 ($lt). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 11 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 3 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2227 ($shiftx). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2231 ($shiftx). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2259 ($shiftx). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2270 ($shiftx). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271 ($eq). +Removed top 27 bits (of 30) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). +Removed top 25 bits (of 30) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 3 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 3 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311 ($eq). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2316 ($eq). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 11 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 26 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2330 ($shiftx). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:200$2336 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:199$2337 ($mux). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5186_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5187_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5188_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5190_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5191_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5194_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5195_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5196_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5198_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5199_CMP0 ($eq). +Removed top 15 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5200_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5293_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5294_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5295_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5296_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5376_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5377_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5378_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5379_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5380_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5381_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5382_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5422_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5423_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5424_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5425_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5426_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5427_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5428_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5429_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5506_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5507_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5508_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5509_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5510_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5511_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5512_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5513_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5514_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5515_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5516_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5517_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5630_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5631_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5632_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6799_CMP0 ($eq). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$ternary$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:37$2142 ($mux). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131 ($mux). +Removed top 120 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$xor$../../asic_core/rtl/lsc1_field_encoder.sv:27$2132 ($xor). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453 ($mux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP0 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP0 ($eq). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP0 ($eq). +Removed top 4 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640 ($pmux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4642_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4643_CMP0 ($eq). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4667 ($mux). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096 ($mux). +Removed top 120 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$xor$../../asic_core/rtl/gf2n_mul_bitstream.sv:65$3097 ($xor). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113 ($eq). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2092 ($eq). +Removed top 24 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Converting cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg) from signed to unsigned. +Removed top 1 bits (of 9) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 25 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2014 ($shiftx). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:83$2859 ($eq). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:83$2859 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010 ($eq). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2014 ($shiftx). +Removed top 23 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2019 ($shiftx). +Removed top 23 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2023 ($shiftx). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 25 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2031 ($shiftx). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:116$2066 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:116$2067 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:117$2069 ($eq). +Removed top 24 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Converting cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg) from signed to unsigned. +Removed top 1 bits (of 9) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2088 ($eq). +Removed top 2 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2089 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$ne$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2091 ($ne). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2092 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095 ($eq). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113 ($eq). +Removed top 2 bits (of 3) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7883 ($mux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7943_CMP0 ($eq). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096 ($mux). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4667 ($mux). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4643_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4642_CMP0 ($eq). +Removed top 4 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640 ($pmux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP0 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922 ($eq). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714 ($ge). +Removed top 29 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:52$1720 ($mux). +Removed top 15 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726 ($eq). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818 ($le). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89027 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89029 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89031 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89033 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89035 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89037 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89039 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89041 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89043 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89045 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89047 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89049 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89051 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89053 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89055 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89057 ($not). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8950_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8949_CMP0 ($eq). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:104$1994 ($eq). +Removed top 24 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89091 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89093 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89095 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89097 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89099 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89101 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89103 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89105 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89107 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89109 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89111 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89113 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89115 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89117 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89119 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89121 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89123 ($not). +Removed top 7 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657 ($gt). +Removed top 189 bits (of 190) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:124$1659 ($mux). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700 ($sub). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:153$1703 ($ne). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9052_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9069_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12013_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12416_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12432_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742 ($gt). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4852 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4942 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5017 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5077 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5122 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5158 ($mux). +Removed top 16 bits (of 32) from FF cell ulx3s_packet_top.$auto$ff.cc:266:slice$95264 ($dffe). +Removed top 16 bits (of 32) from FF cell ulx3s_packet_top.$auto$ff.cc:266:slice$95301 ($dffe). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334 ($mux). +Removed top 12 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316 ($mux). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305 ($mux). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298 ($mux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91405 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91397 ($ne). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$83259 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$83241 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82124 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82088 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81410 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81356 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$80194 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79265 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79193 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77609 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77519 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76106 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75998 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75588 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74003 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73877 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72062 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71918 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71676 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69806 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69644 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67235 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67055 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64820 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64523 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61880 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61664 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$60678 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57845 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57611 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54720 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54468 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51285 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51150 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47709 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47421 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44265 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43959 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39171 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38847 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38170 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37828 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37057 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36877 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36010 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35632 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35179 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34585 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33907 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33493 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32998 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32782 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32710 ($mux). +Removed top 31 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$23518 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$16945 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197 ($mux). +Removed top 28 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$13129 ($mux). +Removed top 28 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$12987 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:372$4367 ($eq). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4353 ($eq). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:969$4332 ($eq). +Removed top 24 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4314 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4312 ($eq). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304 ($ge). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303 ($ge). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301 ($ne). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4287 ($eq). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281 ($gt). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279 ($ge). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:874$4268 ($eq). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:834$4254 ($eq). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233 ($gt). +Removed top 4 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4224 ($eq). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222 ($ge). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221 ($ge). +Removed top 26 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 16 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 16 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 16 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 27 bits (of 30) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). +Removed top 25 bits (of 30) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:755$4163 ($mux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:753$4142 ($ne). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084 ($ne). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058 ($eq). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:727$4056 ($mux). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997 ($ne). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994 ($ge). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993 ($le). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990 ($gt). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989 ($ne). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957 ($eq). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921 ($eq). +Removed top 31 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:659$3920 ($mux). +Removed top 127 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3628 ($ne). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430 ($add). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:468$3429 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3200 ($eq). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\utx.$eq$uart_tx.sv:40$4377 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$eq$uart_rx.sv:62$4403 ($eq). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$le$uart_rx.sv:71$4415 ($le). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). +Converting cell ulx3s_packet_top.$flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg) from signed to unsigned. +Removed top 1 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.$procmux$87797 ($mux). +Removed top 3 bits (of 8) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 2 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7420 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450 ($mux). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7418 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7448 ($mux). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7415 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7445 ($mux). +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.$0\por_shift[7:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3240. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3241. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3246. +Removed top 4 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3244. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3746. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3752. +Removed top 26 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3787. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3788. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3793. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3830. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3836. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3874. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3880. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3907. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3913. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3941. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3947. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3977. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3983. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4018. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4024. +Removed top 28 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4072. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4078. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4091. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4097. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3337. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3338. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3343. +Removed top 10 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3341. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4109. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4115. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4127. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4133. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4148. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4154. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4175. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4181. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4188. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4198. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_detail[7:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3390. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3396. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$30\result_length[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$36\n_writes[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3467. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3473. +Removed top 26 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$40\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3521. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3527. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$53\result_length[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$54\result_length[31:0]. +Removed top 28 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$55\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3568. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3574. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3616. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3622. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3659. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3665. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3704. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3710. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205_Y. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4300_Y. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32782_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305_Y. +Removed top 12 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:659$3920_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:727$4056_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:755$4163_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4314_Y. +Removed top 7 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:957$4317_Y. +Removed top 2 bits (of 3) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7883_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028_Y. +Removed top 4 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$2\tx_data[7:0]. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096_Y. +Removed top 1 bits (of 5) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7415_Y. +Removed top 1 bits (of 5) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7418_Y. +Removed top 127 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450_Y. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028_Y. +Removed top 4 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$2\tx_data[7:0]. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1596_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1600_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1608_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1649_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1595_Y. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_detail[7:0]. +Removed top 29 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$14\ext_word[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$7\ext_word[31:0]. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2215_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2226_Y. +Removed top 27 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2329_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279_Y. +Removed top 27 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2210_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305_Y. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:199$2337_Y. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:200$2336_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1840_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1844_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1864_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$xor$../../asic_core/rtl/lsc1_packet_tx.sv:39$1839_Y. +Removed top 1 bits (of 33) from wire ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:0$4421_Y. + +26.15. Executing PEEPOPT pass (run peephole optimizers). + +26.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 134 unused wires. + + +26.17. Executing SHARE pass (SAT-based resource sharing). +Found 4 cells in module ulx3s_packet_top that may be considered for resource sharing. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul): + Found 3 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88278 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2405:ReduceOr$88222 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + Found 1 candidates: $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 + Analyzing resource sharing with $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul): + Found 1 activation_patterns using ctrl signal { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending }. + Forbidden control signals for this pair of cells: { $auto$wreduce.cc:461:run$97164 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$xor$../../asic_core/rtl/lsc1_packet_tx.sv:39$1878_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88278 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2405:ReduceOr$88222 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5633_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5632_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5631_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5630_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5629_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5628_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5627_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5626_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y } + Activation pattern for cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278: { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 } = 12'010000010000 + Activation pattern for cell $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending } = 21'000000000001001000001 + Size of SAT problem: 0 cells, 3320 variables, 8113 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278: $auto$share.cc:977:make_cell_activation_logic$97166 + New cell: $auto$share.cc:667:make_supercell$97173 ($mul) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$97173 ($mul): + Found 2 activation_patterns using ctrl signal { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 }. + No candidates found. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2288 ($div): + Found 1 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + No candidates found. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mod$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2290 ($mod): + Found 1 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + No candidates found. +Removing 2 cells in module ulx3s_packet_top: + Removing cell $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). + Removing cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). + +26.18. Executing TECHMAP pass (map to technology primitives). + +26.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +26.18.2. Continuing TECHMAP pass. +Using template $paramod$8de9ae31f210b773e84137e37ebdc8a9cec5484d\_90_lut_cmp_ for cells of type $le. +No more expansions possible. + + +26.19. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.20. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 6 unused wires. + + +26.21. Executing TECHMAP pass (map to technology primitives). + +26.21.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/usr/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +26.21.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/dsp_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL18X18'. +Successfully finished Verilog frontend. + +26.21.3. Continuing TECHMAP pass. +Using template $paramod$6b45b5ab16ff1f3173b7cf3a190b9b2e0bbf2838\_80_mul for cells of type $mul. +Using template $paramod$1dafd33bc1a8aa1686876f77247edd05aadd21e4\_80_mul for cells of type $mul. +Using template $paramod$ebf35d89a536bf64810c60aaed904912ddcf22dd\$__MUL18X18 for cells of type $__MUL18X18. +No more expansions possible. + + +26.22. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module ulx3s_packet_top: + creating $macc model for $add$ulx3s_packet_top.sv:21$159 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730 ($sub). + creating $macc model for $flatten\bridge.\urx.$add$uart_rx.sv:69$4414 ($add). + creating $macc model for $flatten\bridge.\urx.$add$uart_rx.sv:86$4433 ($add). + creating $macc model for $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg). + creating $macc model for $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). + creating $macc model for $flatten\bridge.\utx.$add$uart_tx.sv:55$4379 ($add). + creating $macc model for $flatten\bridge.\utx.$add$uart_tx.sv:58$4380 ($add). + merging $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 into $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321. + merging $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 into $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207. + creating $alu model for $macc $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420. + creating $alu model for $macc $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422. + creating $alu model for $macc $flatten\bridge.\urx.$add$uart_rx.sv:86$4433. + creating $alu model for $macc $flatten\bridge.\urx.$add$uart_rx.sv:69$4414. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190. + creating $alu model for $macc $flatten\bridge.\utx.$add$uart_tx.sv:55$4379. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430. + creating $alu model for $macc $flatten\bridge.\utx.$add$uart_tx.sv:58$4380. + creating $alu model for $macc $add$ulx3s_packet_top.sv:21$159. + creating $macc cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321: $auto$alumacc.cc:365:replace_macc$97182 + creating $macc cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207: $auto$alumacc.cc:365:replace_macc$97183 + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:820$4232 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:829$4249 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:830$4252 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4238 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:826$4240 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:827$4243 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:828$4246 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4277 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993 ($le): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818 ($le): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997 ($ne): merged with $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818. + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717: $auto$alumacc.cc:485:replace_alu$97233 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818, $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912: $auto$alumacc.cc:485:replace_alu$97238 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714: $auto$alumacc.cc:485:replace_alu$97247 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291: $auto$alumacc.cc:485:replace_alu$97256 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311: $auto$alumacc.cc:485:replace_alu$97267 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271: $auto$alumacc.cc:485:replace_alu$97278 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217: $auto$alumacc.cc:485:replace_alu$97289 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204: $auto$alumacc.cc:485:replace_alu$97300 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194: $auto$alumacc.cc:485:replace_alu$97311 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0: $auto$alumacc.cc:485:replace_alu$97322 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742: $auto$alumacc.cc:485:replace_alu$97333 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732: $auto$alumacc.cc:485:replace_alu$97338 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722: $auto$alumacc.cc:485:replace_alu$97343 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702: $auto$alumacc.cc:485:replace_alu$97348 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692: $auto$alumacc.cc:485:replace_alu$97353 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682: $auto$alumacc.cc:485:replace_alu$97358 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672: $auto$alumacc.cc:485:replace_alu$97363 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662: $auto$alumacc.cc:485:replace_alu$97368 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652: $auto$alumacc.cc:485:replace_alu$97373 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642: $auto$alumacc.cc:485:replace_alu$97378 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632: $auto$alumacc.cc:485:replace_alu$97383 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622: $auto$alumacc.cc:485:replace_alu$97388 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612: $auto$alumacc.cc:485:replace_alu$97393 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602: $auto$alumacc.cc:485:replace_alu$97398 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592: $auto$alumacc.cc:485:replace_alu$97403 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571: $auto$alumacc.cc:485:replace_alu$97408 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559: $auto$alumacc.cc:485:replace_alu$97413 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661: $auto$alumacc.cc:485:replace_alu$97418 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657: $auto$alumacc.cc:485:replace_alu$97429 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024: $auto$alumacc.cc:485:replace_alu$97434 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024: $auto$alumacc.cc:485:replace_alu$97445 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993: $auto$alumacc.cc:485:replace_alu$97456 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281: $auto$alumacc.cc:485:replace_alu$97469 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4277: $auto$alumacc.cc:485:replace_alu$97474 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:828$4246: $auto$alumacc.cc:485:replace_alu$97485 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:827$4243: $auto$alumacc.cc:485:replace_alu$97496 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:826$4240: $auto$alumacc.cc:485:replace_alu$97507 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4238: $auto$alumacc.cc:485:replace_alu$97518 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233: $auto$alumacc.cc:485:replace_alu$97529 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990, $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997: $auto$alumacc.cc:485:replace_alu$97534 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304: $auto$alumacc.cc:485:replace_alu$97543 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303: $auto$alumacc.cc:485:replace_alu$97552 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279: $auto$alumacc.cc:485:replace_alu$97561 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:830$4252: $auto$alumacc.cc:485:replace_alu$97570 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:829$4249: $auto$alumacc.cc:485:replace_alu$97583 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:820$4232: $auto$alumacc.cc:485:replace_alu$97596 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222: $auto$alumacc.cc:485:replace_alu$97609 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221: $auto$alumacc.cc:485:replace_alu$97618 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994: $auto$alumacc.cc:485:replace_alu$97627 + creating $alu cell for $add$ulx3s_packet_top.sv:21$159: $auto$alumacc.cc:485:replace_alu$97636 + creating $alu cell for $flatten\bridge.\utx.$add$uart_tx.sv:58$4380: $auto$alumacc.cc:485:replace_alu$97639 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430: $auto$alumacc.cc:485:replace_alu$97642 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350: $auto$alumacc.cc:485:replace_alu$97645 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351: $auto$alumacc.cc:485:replace_alu$97648 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045: $auto$alumacc.cc:485:replace_alu$97651 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204: $auto$alumacc.cc:485:replace_alu$97654 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215: $auto$alumacc.cc:485:replace_alu$97657 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226: $auto$alumacc.cc:485:replace_alu$97660 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227: $auto$alumacc.cc:485:replace_alu$97663 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228: $auto$alumacc.cc:485:replace_alu$97666 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229: $auto$alumacc.cc:485:replace_alu$97669 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230: $auto$alumacc.cc:485:replace_alu$97672 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231: $auto$alumacc.cc:485:replace_alu$97675 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285: $auto$alumacc.cc:485:replace_alu$97678 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237: $auto$alumacc.cc:485:replace_alu$97681 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276: $auto$alumacc.cc:485:replace_alu$97684 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087: $auto$alumacc.cc:485:replace_alu$97687 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096: $auto$alumacc.cc:485:replace_alu$97690 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078: $auto$alumacc.cc:485:replace_alu$97693 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028: $auto$alumacc.cc:485:replace_alu$97696 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908: $auto$alumacc.cc:485:replace_alu$97699 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483: $auto$alumacc.cc:485:replace_alu$97702 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484: $auto$alumacc.cc:485:replace_alu$97705 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145: $auto$alumacc.cc:485:replace_alu$97708 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136: $auto$alumacc.cc:485:replace_alu$97711 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087: $auto$alumacc.cc:485:replace_alu$97714 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096: $auto$alumacc.cc:485:replace_alu$97717 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078: $auto$alumacc.cc:485:replace_alu$97720 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028: $auto$alumacc.cc:485:replace_alu$97723 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908: $auto$alumacc.cc:485:replace_alu$97726 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660: $auto$alumacc.cc:485:replace_alu$97729 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705: $auto$alumacc.cc:485:replace_alu$97732 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700: $auto$alumacc.cc:485:replace_alu$97735 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279: $auto$alumacc.cc:485:replace_alu$97738 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315: $auto$alumacc.cc:485:replace_alu$97741 + creating $alu cell for $flatten\bridge.\utx.$add$uart_tx.sv:55$4379: $auto$alumacc.cc:485:replace_alu$97744 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190: $auto$alumacc.cc:485:replace_alu$97747 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209: $auto$alumacc.cc:485:replace_alu$97750 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220: $auto$alumacc.cc:485:replace_alu$97753 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228: $auto$alumacc.cc:485:replace_alu$97756 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267: $auto$alumacc.cc:485:replace_alu$97759 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287: $auto$alumacc.cc:485:replace_alu$97762 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305: $auto$alumacc.cc:485:replace_alu$97765 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993: $auto$alumacc.cc:485:replace_alu$97768 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995: $auto$alumacc.cc:485:replace_alu$97771 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716: $auto$alumacc.cc:485:replace_alu$97774 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817: $auto$alumacc.cc:485:replace_alu$97777 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719: $auto$alumacc.cc:485:replace_alu$97780 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730: $auto$alumacc.cc:485:replace_alu$97783 + creating $alu cell for $flatten\bridge.\urx.$add$uart_rx.sv:69$4414: $auto$alumacc.cc:485:replace_alu$97786 + creating $alu cell for $flatten\bridge.\urx.$add$uart_rx.sv:86$4433: $auto$alumacc.cc:485:replace_alu$97789 + creating $alu cell for $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422: $auto$alumacc.cc:485:replace_alu$97792 + creating $alu cell for $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420: $auto$alumacc.cc:485:replace_alu$97795 + created 103 $alu and 2 $macc cells. + +26.23. Executing OPT pass (performing simple optimizations). + +26.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$95660: { $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y $auto$alumacc.cc:501:replace_alu$97535 $auto$alumacc.cc:502:replace_alu$97536 [7] $auto$rtlil.cc:2401:Not$93451 $auto$rtlil.cc:2401:Not$93833 $auto$rtlil.cc:2401:Not$93839 $auto$rtlil.cc:2401:Not$93841 $auto$rtlil.cc:2401:Not$93843 $auto$rtlil.cc:2401:Not$93845 $auto$rtlil.cc:2401:Not$93847 $auto$rtlil.cc:2401:Not$93849 $auto$rtlil.cc:2401:Not$93851 $auto$rtlil.cc:2401:Not$93853 $auto$rtlil.cc:2401:Not$93855 $auto$rtlil.cc:2401:Not$93857 $auto$rtlil.cc:2401:Not$93859 $auto$rtlil.cc:2401:Not$95628 $auto$rtlil.cc:2401:Not$95634 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$91485: { $auto$alumacc.cc:501:replace_alu$97239 $auto$rtlil.cc:2401:Not$91483 $auto$rtlil.cc:2405:ReduceOr$97246 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$logic_and$../../asic_core/rtl/lsc1_packet_tx.sv:93$1796_Y } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$91459: { $auto$alumacc.cc:501:replace_alu$97239 $auto$rtlil.cc:2405:ReduceOr$97246 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$logic_and$../../asic_core/rtl/lsc1_packet_tx.sv:93$1796_Y } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 3 changes. + +26.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.23.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 9 unused cells and 80 unused wires. + + +26.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.23.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.23.16. Finished OPT passes. (There is nothing left to do.) + +26.24. Executing MEMORY pass. + +26.24.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +26.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 2 transformations. + +26.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address write port 0. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address write port 1. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value write port 0. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value write port 1. + +26.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +26.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_address'[0] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_address'[1] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_value'[0] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_value'[1] in module `\ulx3s_packet_top': no output FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_address'[0] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_address'[1] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_value'[0] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_value'[1] in module `\ulx3s_packet_top': no address FF found. + +26.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address by address: + Merging ports 0, 1 (address 1'1). +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address by address: +Consolidating read ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value by address: + Merging ports 0, 1 (address 1'1). +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value by address: +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address using sat-based resource sharing: + Checking group clocked with posedge \bridge.clk, width 32: ports 0, 1. + Common input cone for all EN signals: 88 cells. + Size of unconstrained SAT problem: 2798 variables, 6514 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value using sat-based resource sharing: + Checking group clocked with posedge \bridge.clk, width 128: ports 0, 1. + Common input cone for all EN signals: 88 cells. + Size of unconstrained SAT problem: 2798 variables, 6514 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. + +26.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +26.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +26.25. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). +using FF mapping for memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address +using FF mapping for memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value + + +26.27. Executing TECHMAP pass (map to technology primitives). + +26.27.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/lutrams_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +26.27.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/brams_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ECP5_DP16KD_'. +Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. +Successfully finished Verilog frontend. + +26.27.3. Continuing TECHMAP pass. +No more expansions possible. + + +26.28. Executing OPT pass (performing simple optimizations). + +26.28.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.28.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 209 cells. + +26.28.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$95371 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\n_deferred[31:0], Q = \bridge.g_packet.asic.packet_core.n_deferred, rval = 0). +Adding SRST signal on $auto$ff.cc:266:slice$94940 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\deferred_target[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_target, rval = 0). +Adding SRST signal on $auto$ff.cc:266:slice$94895 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\deferred_local[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_local, rval = 0). + +26.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 41 unused cells and 1950 unused wires. + + +26.28.5. Rerunning OPT passes. (Removed registers in this run.) + +26.28.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.28.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.28.8. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$91491 ($dffe) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [188:0], Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [189:1], rval = 189'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $auto$ff.cc:266:slice$91491 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:124$1658_Y, Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [0], rval = 1'0). + +26.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 1 unused cells and 6 unused wires. + + +26.28.10. Rerunning OPT passes. (Removed registers in this run.) + +26.28.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.28.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.28.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.28.15. Finished fast OPT passes. + +26.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \bridge.g_packet.asic.packet_core.staged_write_address in module \ulx3s_packet_top: + created 2 $dff cells and 0 static cells of width 32. + read interface: 0 $dff and 0 $mux cells. + write interface: 4 write mux blocks. +Mapping memory \bridge.g_packet.asic.packet_core.staged_write_value in module \ulx3s_packet_top: + created 2 $dff cells and 0 static cells of width 128. + read interface: 0 $dff and 0 $mux cells. + write interface: 4 write mux blocks. + +26.30. Executing OPT pass (performing simple optimizations). + +26.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 2 cells. + +26.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$12987: + Old ports: A=4'0011, B=4'1011, Y=$auto$wreduce.cc:461:run$97095 [3:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97095 [3] + New connections: $auto$wreduce.cc:461:run$97095 [2:0] = 3'011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13129: + Old ports: A=4'0111, B=4'1111, Y=$auto$wreduce.cc:461:run$97094 [3:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97094 [3] + New connections: $auto$wreduce.cc:461:run$97094 [2:0] = 3'111 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 12'000000000001 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 12'000000000010 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [15:0] + New ports: A={ 2'01 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 2'10 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [5:0] + New connections: $auto$wreduce.cc:461:run$97093 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16945: + Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:461:run$97083 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97083 [1] + New connections: $auto$wreduce.cc:461:run$97083 [0] = 1'0 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17206: + Old ports: A={ 6'000000 $auto$wreduce.cc:461:run$97083 [1:0] }, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] + New ports: A=$auto$wreduce.cc:461:run$97083 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24082: + Old ports: A={ 31'0000000000000000000000000000000 $auto$wreduce.cc:461:run$97087 [0] }, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] + New ports: A=$auto$wreduce.cc:461:run$97087 [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29049: + Old ports: A=8'00000000, B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71676: + Old ports: A=6'010011, B=6'100011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0] + New ports: A=2'01, B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:4] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [3:0] = 4'0011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739: + Old ports: A={ 10'0000000000 $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0] }, B=16'0000000000100111, Y=$auto$wreduce.cc:461:run$97086 [15:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0], B=6'100111, Y=$auto$wreduce.cc:461:run$97086 [5:0] + New connections: $auto$wreduce.cc:461:run$97086 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75588: + Old ports: A=6'011011, B=6'100011, Y=$auto$wreduce.cc:461:run$97063 [5:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] } + New connections: { $auto$wreduce.cc:461:run$97063 [4] $auto$wreduce.cc:461:run$97063 [2:0] } = { $auto$wreduce.cc:461:run$97063 [3] 3'011 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97063 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97080 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97080 [5:0] + New connections: $auto$wreduce.cc:461:run$97080 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97063 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97058 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97058 [5:0] + New connections: $auto$wreduce.cc:461:run$97058 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80194: + Old ports: A=6'011011, B=6'100011, Y=$auto$wreduce.cc:461:run$97046 [5:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97046 [5] $auto$wreduce.cc:461:run$97046 [3] } + New connections: { $auto$wreduce.cc:461:run$97046 [4] $auto$wreduce.cc:461:run$97046 [2:0] } = { $auto$wreduce.cc:461:run$97046 [3] 3'011 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97046 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97102 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97046 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97102 [5:0] + New connections: $auto$wreduce.cc:461:run$97102 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078: + Old ports: A=8'10001100, B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [1] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096: + Old ports: A=8'10000111, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y + New ports: A=2'01, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [3:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114: + Old ports: A=8'10000001, B=8'10000110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y + New ports: A=2'01, B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143: + Old ports: A=8'10001100, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [2:1] } = { 5'10001 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176: + Old ports: A=8'10001010, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [2:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194: + Old ports: A=8'10001100, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [2:1] } = { 5'10001 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204: + Old ports: A=8'10001101, B=8'10010000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y + New ports: A=2'01, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [3:1] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255: + Old ports: A=8'00000010, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [3:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] 6'000010 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262: + Old ports: A=8'10010010, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [3:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] 6'000010 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273: + Old ports: A=8'10000110, B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [7:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291: + Old ports: A=8'00000011, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [7] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [6:0] = 7'0000011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323: + Old ports: A=8'00000000, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335: + Old ports: A=8'00000000, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [7:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363: + Old ports: A=8'00000000, B=8'10001101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126: + Old ports: A={ 6'000000 $auto$wreduce.cc:461:run$97114 [1:0] }, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y + New ports: A=$auto$wreduce.cc:461:run$97114 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447: + Old ports: A=8'00000010, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y + New ports: A=2'10, B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808: + Old ports: A=8'00000000, B={ 6'000000 $auto$wreduce.cc:461:run$97117 [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y + New ports: A=2'00, B=$auto$wreduce.cc:461:run$97117 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826: + Old ports: A=8'00000000, B={ 6'000000 $auto$wreduce.cc:461:run$97116 [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y + New ports: A=2'00, B=$auto$wreduce.cc:461:run$97116 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873: + Old ports: A=8'00000000, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [7:1] = { 6'000000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906: + Old ports: A=8'00000000, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [7:1] = { 6'000000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298: + Old ports: A=5'10000, B=5'00101, Y=$auto$wreduce.cc:461:run$97110 [4:0] + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97110 [4] $auto$wreduce.cc:461:run$97110 [0] } + New connections: $auto$wreduce.cc:461:run$97110 [3:1] = { 1'0 $auto$wreduce.cc:461:run$97110 [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301: + Old ports: A=16'0000000000000101, B={ 11'00000000000 $auto$wreduce.cc:461:run$97110 [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y + New ports: A=5'00101, B=$auto$wreduce.cc:461:run$97110 [4:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305: + Old ports: A=5'00101, B=5'10000, Y=$auto$wreduce.cc:461:run$97111 [4:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97111 [4] $auto$wreduce.cc:461:run$97111 [0] } + New connections: $auto$wreduce.cc:461:run$97111 [3:1] = { 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316: + Old ports: A=4'0101, B=4'1110, Y=$auto$wreduce.cc:461:run$97112 [3:0] + New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:461:run$97112 [1:0] + New connections: $auto$wreduce.cc:461:run$97112 [3:2] = { $auto$wreduce.cc:461:run$97112 [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319: + Old ports: A=16'0000000000000101, B={ 12'000000000000 $auto$wreduce.cc:461:run$97112 [3:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y + New ports: A=4'0101, B=$auto$wreduce.cc:461:run$97112 [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334: + Old ports: A=5'10100, B=5'00101, Y=$auto$wreduce.cc:461:run$97113 [4:0] + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97113 [4] $auto$wreduce.cc:461:run$97113 [0] } + New connections: $auto$wreduce.cc:461:run$97113 [3:1] = 3'010 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97090 [5:0] }, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y + New ports: A=$auto$wreduce.cc:461:run$97090 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365: + Old ports: A=2'11, B=2'01, Y=$auto$wreduce.cc:461:run$97114 [1:0] + New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$97114 [1] + New connections: $auto$wreduce.cc:461:run$97114 [0] = 1'1 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7609_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3\core_rx_valid[0:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868: + Old ports: A=3'000, B=3'100, Y=$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y [2] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y [1:0] = 2'00 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3\core_rx_valid[0:0] + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491: { $auto$opt_reduce.cc:134:opt_pmux$98364 $auto$opt_reduce.cc:134:opt_pmux$98362 } + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640: + Old ports: A=4'0000, B=12'000111111000, Y=$auto$wreduce.cc:461:run$97122 [3:0] + New ports: A=3'000, B=9'001111100, Y={ $auto$wreduce.cc:461:run$97122 [3] $auto$wreduce.cc:461:run$97122 [1:0] } + New connections: $auto$wreduce.cc:461:run$97122 [2] = $auto$wreduce.cc:461:run$97122 [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97124 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98156 [120] + New connections: $auto$wreduce.cc:461:run$97124 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97128 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98150 [120] + New connections: $auto$wreduce.cc:461:run$97128 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.state [4] + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491: { $auto$opt_reduce.cc:134:opt_pmux$98368 $auto$opt_reduce.cc:134:opt_pmux$98366 } + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640: + Old ports: A=4'0000, B=12'000111111000, Y=$auto$wreduce.cc:461:run$97130 [3:0] + New ports: A=3'000, B=9'001111100, Y={ $auto$wreduce.cc:461:run$97130 [3] $auto$wreduce.cc:461:run$97130 [1:0] } + New connections: $auto$wreduce.cc:461:run$97130 [2] = $auto$wreduce.cc:461:run$97130 [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97132 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98153 [120] + New connections: $auto$wreduce.cc:461:run$97132 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12397: $auto$opt_reduce.cc:134:opt_pmux$98370 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12473: \bridge.g_packet.asic.packet_core.receiver.state [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580: + Old ports: A=8'10000101, B=8'10000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [1:0] } = 7'1000001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1595: + Old ports: A={ 25'0111111111111111111111111 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7:1] }, B={ 25'1001001001000111011111001 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] $auto$opt_expr.cc:205:group_cell_inputs$98231 [0] $auto$opt_expr.cc:205:group_cell_inputs$98227 [5:1] }, Y={ $auto$wreduce.cc:461:run$97133 [30:0] $auto$wreduce.cc:461:run$97137 [0] } + New ports: A={ 2'01 $auto$opt_expr.cc:205:group_cell_inputs$98227 [6] }, B={ 2'10 $auto$opt_expr.cc:205:group_cell_inputs$98231 [0] }, Y={ $auto$wreduce.cc:461:run$97133 [30] $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [4] } + New connections: { $auto$wreduce.cc:461:run$97133 [29:8] $auto$wreduce.cc:461:run$97133 [6:5] $auto$wreduce.cc:461:run$97133 [3:0] $auto$wreduce.cc:461:run$97137 [0] } = { $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 3'111 $auto$wreduce.cc:461:run$97133 [7] 5'11111 $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] $auto$opt_expr.cc:205:group_cell_inputs$98227 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 [12:11] $auto$wreduce.cc:461:run$97133 [28] $auto$opt_expr.cc:205:group_cell_inputs$98235 [10:9] $auto$wreduce.cc:461:run$97133 [25] $auto$opt_expr.cc:205:group_cell_inputs$98235 [8:7] $auto$wreduce.cc:461:run$97133 [22] $auto$opt_expr.cc:205:group_cell_inputs$98235 [6:4] $auto$wreduce.cc:461:run$97133 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98235 [3] $auto$wreduce.cc:461:run$97133 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98235 [2:1] $auto$wreduce.cc:461:run$97133 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98235 [0] $auto$wreduce.cc:461:run$97133 [4:0] }, Y={ $auto$wreduce.cc:461:run$97134 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:29] $auto$wreduce.cc:461:run$97133 [27:26] $auto$wreduce.cc:461:run$97133 [24:23] $auto$wreduce.cc:461:run$97133 [21:19] $auto$wreduce.cc:461:run$97133 [15] $auto$wreduce.cc:461:run$97133 [9:8] $auto$wreduce.cc:461:run$97133 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 }, Y={ $auto$wreduce.cc:461:run$97134 [30:28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New connections: { $auto$wreduce.cc:461:run$97134 [27] $auto$wreduce.cc:461:run$97134 [24] $auto$wreduce.cc:461:run$97134 [21] $auto$wreduce.cc:461:run$97134 [17:15] $auto$wreduce.cc:461:run$97134 [13:9] $auto$wreduce.cc:461:run$97134 [6:5] $auto$wreduce.cc:461:run$97134 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599_Y [0] } = { $auto$wreduce.cc:461:run$97133 [28] $auto$wreduce.cc:461:run$97133 [25] $auto$wreduce.cc:461:run$97133 [22] $auto$wreduce.cc:461:run$97133 [18:16] $auto$wreduce.cc:461:run$97133 [14:10] $auto$wreduce.cc:461:run$97133 [7:6] $auto$wreduce.cc:461:run$97133 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 [12:11] $auto$wreduce.cc:461:run$97134 [28] $auto$opt_expr.cc:205:group_cell_inputs$98239 [10:9] $auto$wreduce.cc:461:run$97134 [25] $auto$opt_expr.cc:205:group_cell_inputs$98239 [8:7] $auto$wreduce.cc:461:run$97134 [22] $auto$opt_expr.cc:205:group_cell_inputs$98239 [6:4] $auto$wreduce.cc:461:run$97134 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98239 [3] $auto$wreduce.cc:461:run$97134 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98239 [2:1] $auto$wreduce.cc:461:run$97134 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98239 [0] $auto$wreduce.cc:461:run$97134 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [27:26] $auto$wreduce.cc:461:run$97134 [24:23] $auto$wreduce.cc:461:run$97134 [21:19] $auto$wreduce.cc:461:run$97134 [15] $auto$wreduce.cc:461:run$97134 [9:8] $auto$wreduce.cc:461:run$97134 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603_Y [0] } = { $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [25] $auto$wreduce.cc:461:run$97134 [22] $auto$wreduce.cc:461:run$97134 [18:16] $auto$wreduce.cc:461:run$97134 [14:10] $auto$wreduce.cc:461:run$97134 [7:6] $auto$wreduce.cc:461:run$97134 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98243 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98243 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98243 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98243 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98243 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98243 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97135 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: { $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $auto$wreduce.cc:461:run$97135 [17:15] $auto$wreduce.cc:461:run$97135 [13:9] $auto$wreduce.cc:461:run$97135 [6:5] $auto$wreduce.cc:461:run$97135 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 [12:11] $auto$wreduce.cc:461:run$97135 [28] $auto$opt_expr.cc:205:group_cell_inputs$98247 [10:9] $auto$wreduce.cc:461:run$97135 [25] $auto$opt_expr.cc:205:group_cell_inputs$98247 [8:7] $auto$wreduce.cc:461:run$97135 [22] $auto$opt_expr.cc:205:group_cell_inputs$98247 [6:4] $auto$wreduce.cc:461:run$97135 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98247 [3] $auto$wreduce.cc:461:run$97135 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98247 [2:1] $auto$wreduce.cc:461:run$97135 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98247 [0] $auto$wreduce.cc:461:run$97135 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27:26] $auto$wreduce.cc:461:run$97135 [24:23] $auto$wreduce.cc:461:run$97135 [21:19] $auto$wreduce.cc:461:run$97135 [15] $auto$wreduce.cc:461:run$97135 [9:8] $auto$wreduce.cc:461:run$97135 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611_Y [0] } = { $auto$wreduce.cc:461:run$97135 [28] $auto$wreduce.cc:461:run$97135 [25] $auto$wreduce.cc:461:run$97135 [22] $auto$wreduce.cc:461:run$97135 [18:16] $auto$wreduce.cc:461:run$97135 [14:10] $auto$wreduce.cc:461:run$97135 [7:6] $auto$wreduce.cc:461:run$97135 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98251 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98251 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98251 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98251 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98251 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98251 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98255 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98255 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98255 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98255 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98255 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98255 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1623: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98259 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98259 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98259 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98259 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98259 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98259 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.receiver.crc [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98266 [12:11] \bridge.g_packet.asic.packet_core.receiver.crc [29] $auto$opt_expr.cc:205:group_cell_inputs$98266 [10:9] \bridge.g_packet.asic.packet_core.receiver.crc [26] $auto$opt_expr.cc:205:group_cell_inputs$98266 [8:7] \bridge.g_packet.asic.packet_core.receiver.crc [23] $auto$opt_expr.cc:205:group_cell_inputs$98266 [6:4] \bridge.g_packet.asic.packet_core.receiver.crc [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98266 [3] \bridge.g_packet.asic.packet_core.receiver.crc [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98266 [2:1] \bridge.g_packet.asic.packet_core.receiver.crc [8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7] $auto$opt_expr.cc:205:group_cell_inputs$98266 [0] $auto$opt_expr.cc:205:group_cell_inputs$98263 [5:1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.receiver.crc [31:30] \bridge.g_packet.asic.packet_core.receiver.crc [28:27] \bridge.g_packet.asic.packet_core.receiver.crc [25:24] \bridge.g_packet.asic.packet_core.receiver.crc [22:20] \bridge.g_packet.asic.packet_core.receiver.crc [16] \bridge.g_packet.asic.packet_core.receiver.crc [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98263 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98266 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628_Y [0] } = { \bridge.g_packet.asic.packet_core.receiver.crc [29] \bridge.g_packet.asic.packet_core.receiver.crc [26] \bridge.g_packet.asic.packet_core.receiver.crc [23] \bridge.g_packet.asic.packet_core.receiver.crc [19:17] \bridge.g_packet.asic.packet_core.receiver.crc [15:11] \bridge.g_packet.asic.packet_core.receiver.crc [8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7] $auto$opt_expr.cc:205:group_cell_inputs$98263 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98270 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98270 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98270 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98270 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98270 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98270 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98270 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98270 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98274 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98274 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98274 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98274 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98274 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98274 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98274 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98274 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98278 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98278 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98278 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98278 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98278 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98278 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98278 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98278 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98282 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98282 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98282 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98282 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98282 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98282 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98282 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98282 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98286 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98286 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98286 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98286 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98286 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98286 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98286 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97136 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98286 }, Y={ $auto$wreduce.cc:461:run$97136 [30:28] $auto$wreduce.cc:461:run$97136 [26:25] $auto$wreduce.cc:461:run$97136 [23:22] $auto$wreduce.cc:461:run$97136 [20:18] $auto$wreduce.cc:461:run$97136 [14] $auto$wreduce.cc:461:run$97136 [8:7] $auto$wreduce.cc:461:run$97136 [4] } + New connections: { $auto$wreduce.cc:461:run$97136 [27] $auto$wreduce.cc:461:run$97136 [24] $auto$wreduce.cc:461:run$97136 [21] $auto$wreduce.cc:461:run$97136 [17:15] $auto$wreduce.cc:461:run$97136 [13:9] $auto$wreduce.cc:461:run$97136 [6:5] $auto$wreduce.cc:461:run$97136 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97136 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98290 [12:11] $auto$wreduce.cc:461:run$97136 [28] $auto$opt_expr.cc:205:group_cell_inputs$98290 [10:9] $auto$wreduce.cc:461:run$97136 [25] $auto$opt_expr.cc:205:group_cell_inputs$98290 [8:7] $auto$wreduce.cc:461:run$97136 [22] $auto$opt_expr.cc:205:group_cell_inputs$98290 [6:4] $auto$wreduce.cc:461:run$97136 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98290 [3] $auto$wreduce.cc:461:run$97136 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98290 [2:1] $auto$wreduce.cc:461:run$97136 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98290 [0] $auto$wreduce.cc:461:run$97136 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97136 [30:29] $auto$wreduce.cc:461:run$97136 [27:26] $auto$wreduce.cc:461:run$97136 [24:23] $auto$wreduce.cc:461:run$97136 [21:19] $auto$wreduce.cc:461:run$97136 [15] $auto$wreduce.cc:461:run$97136 [9:8] $auto$wreduce.cc:461:run$97136 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98290 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652_Y [0] } = { $auto$wreduce.cc:461:run$97136 [28] $auto$wreduce.cc:461:run$97136 [25] $auto$wreduce.cc:461:run$97136 [22] $auto$wreduce.cc:461:run$97136 [18:16] $auto$wreduce.cc:461:run$97136 [14:10] $auto$wreduce.cc:461:run$97136 [7:6] $auto$wreduce.cc:461:run$97136 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1656: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98294 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98294 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98294 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98294 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98294 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98294 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98294 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98294 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4789: + Old ports: A=8'00000000, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4852: + Old ports: A=2'00, B=2'11, Y=$auto$wreduce.cc:461:run$97142 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97142 [0] + New connections: $auto$wreduce.cc:461:run$97142 [1] = $auto$wreduce.cc:461:run$97142 [0] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98160 [12:11] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [29] $auto$opt_expr.cc:205:group_cell_inputs$98160 [10:9] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [26] $auto$opt_expr.cc:205:group_cell_inputs$98160 [8:7] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [23] $auto$opt_expr.cc:205:group_cell_inputs$98160 [6:4] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98160 [3] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98160 [2:1] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7] $auto$opt_expr.cc:205:group_cell_inputs$98160 [0] $auto$opt_expr.cc:205:group_cell_inputs$98157 [5:1] }, Y={ $auto$wreduce.cc:461:run$97162 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [31:30] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [28:27] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [25:24] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [22:20] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [16] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98157 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98160 }, Y={ $auto$wreduce.cc:461:run$97162 [30:28] $auto$wreduce.cc:461:run$97162 [26:25] $auto$wreduce.cc:461:run$97162 [23:22] $auto$wreduce.cc:461:run$97162 [20:18] $auto$wreduce.cc:461:run$97162 [14] $auto$wreduce.cc:461:run$97162 [8:7] $auto$wreduce.cc:461:run$97162 [4] } + New connections: { $auto$wreduce.cc:461:run$97162 [27] $auto$wreduce.cc:461:run$97162 [24] $auto$wreduce.cc:461:run$97162 [21] $auto$wreduce.cc:461:run$97162 [17:15] $auto$wreduce.cc:461:run$97162 [13:9] $auto$wreduce.cc:461:run$97162 [6:5] $auto$wreduce.cc:461:run$97162 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] } = { \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [29] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [26] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [23] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [19:17] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [15:11] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7] $auto$opt_expr.cc:205:group_cell_inputs$98157 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97162 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98164 [12:11] $auto$wreduce.cc:461:run$97162 [28] $auto$opt_expr.cc:205:group_cell_inputs$98164 [10:9] $auto$wreduce.cc:461:run$97162 [25] $auto$opt_expr.cc:205:group_cell_inputs$98164 [8:7] $auto$wreduce.cc:461:run$97162 [22] $auto$opt_expr.cc:205:group_cell_inputs$98164 [6:4] $auto$wreduce.cc:461:run$97162 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98164 [3] $auto$wreduce.cc:461:run$97162 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98164 [2:1] $auto$wreduce.cc:461:run$97162 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98164 [0] $auto$wreduce.cc:461:run$97162 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97162 [30:29] $auto$wreduce.cc:461:run$97162 [27:26] $auto$wreduce.cc:461:run$97162 [24:23] $auto$wreduce.cc:461:run$97162 [21:19] $auto$wreduce.cc:461:run$97162 [15] $auto$wreduce.cc:461:run$97162 [9:8] $auto$wreduce.cc:461:run$97162 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98164 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] } = { $auto$wreduce.cc:461:run$97162 [28] $auto$wreduce.cc:461:run$97162 [25] $auto$wreduce.cc:461:run$97162 [22] $auto$wreduce.cc:461:run$97162 [18:16] $auto$wreduce.cc:461:run$97162 [14:10] $auto$wreduce.cc:461:run$97162 [7:6] $auto$wreduce.cc:461:run$97162 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98168 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98168 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98168 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98168 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98168 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98168 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98168 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98168 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98172 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98172 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98172 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98172 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98172 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98172 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98172 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98172 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98176 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98176 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98176 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98176 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98176 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98176 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98176 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98176 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98180 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98180 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98180 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98180 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98180 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98180 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98180 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97163 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98180 }, Y={ $auto$wreduce.cc:461:run$97163 [30:28] $auto$wreduce.cc:461:run$97163 [26:25] $auto$wreduce.cc:461:run$97163 [23:22] $auto$wreduce.cc:461:run$97163 [20:18] $auto$wreduce.cc:461:run$97163 [14] $auto$wreduce.cc:461:run$97163 [8:7] $auto$wreduce.cc:461:run$97163 [4] } + New connections: { $auto$wreduce.cc:461:run$97163 [27] $auto$wreduce.cc:461:run$97163 [24] $auto$wreduce.cc:461:run$97163 [21] $auto$wreduce.cc:461:run$97163 [17:15] $auto$wreduce.cc:461:run$97163 [13:9] $auto$wreduce.cc:461:run$97163 [6:5] $auto$wreduce.cc:461:run$97163 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97163 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98184 [12:11] $auto$wreduce.cc:461:run$97163 [28] $auto$opt_expr.cc:205:group_cell_inputs$98184 [10:9] $auto$wreduce.cc:461:run$97163 [25] $auto$opt_expr.cc:205:group_cell_inputs$98184 [8:7] $auto$wreduce.cc:461:run$97163 [22] $auto$opt_expr.cc:205:group_cell_inputs$98184 [6:4] $auto$wreduce.cc:461:run$97163 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98184 [3] $auto$wreduce.cc:461:run$97163 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98184 [2:1] $auto$wreduce.cc:461:run$97163 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98184 [0] $auto$wreduce.cc:461:run$97163 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97163 [30:29] $auto$wreduce.cc:461:run$97163 [27:26] $auto$wreduce.cc:461:run$97163 [24:23] $auto$wreduce.cc:461:run$97163 [21:19] $auto$wreduce.cc:461:run$97163 [15] $auto$wreduce.cc:461:run$97163 [9:8] $auto$wreduce.cc:461:run$97163 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98184 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] } = { $auto$wreduce.cc:461:run$97163 [28] $auto$wreduce.cc:461:run$97163 [25] $auto$wreduce.cc:461:run$97163 [22] $auto$wreduce.cc:461:run$97163 [18:16] $auto$wreduce.cc:461:run$97163 [14:10] $auto$wreduce.cc:461:run$97163 [7:6] $auto$wreduce.cc:461:run$97163 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98188 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98188 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98188 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98188 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98188 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98188 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98188 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98188 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98195 [12:11] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [29] $auto$opt_expr.cc:205:group_cell_inputs$98195 [10:9] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [26] $auto$opt_expr.cc:205:group_cell_inputs$98195 [8:7] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [23] $auto$opt_expr.cc:205:group_cell_inputs$98195 [6:4] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98195 [3] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98195 [2:1] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7] $auto$opt_expr.cc:205:group_cell_inputs$98195 [0] $auto$opt_expr.cc:205:group_cell_inputs$98192 [5:1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [31:30] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [28:27] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [25:24] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [22:20] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [16] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98192 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98195 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] } = { \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [29] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [26] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [23] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [19:17] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [15:11] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7] $auto$opt_expr.cc:205:group_cell_inputs$98192 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98199 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98199 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98199 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98199 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98199 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98199 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98199 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98199 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98203 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98203 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98203 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98203 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98203 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98203 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98203 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98203 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98207 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98207 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98207 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98207 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98207 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98207 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98207 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98207 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98211 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98211 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98211 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98211 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98211 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98211 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98211 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98211 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98215 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98215 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98215 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98215 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98215 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98215 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98215 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98215 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98219 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98219 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98219 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98219 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98219 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98219 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98219 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98219 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98223 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98223 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98223 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98223 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98223 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98223 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98223 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98223 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4:0] } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$98361: { \bridge.g_packet.asic.packet_core.adapter.datapath.state [9] \bridge.g_packet.asic.packet_core.adapter.datapath.state [7] \bridge.g_packet.asic.packet_core.adapter.datapath.state [3:1] } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$98365: { \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [9] \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [7] \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [3:1] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 2'01 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 2'10 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [5:0] + New ports: A={ 1'1 $auto$wreduce.cc:461:run$97095 [3] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$97094 [3] 1'1 }, Y=$auto$wreduce.cc:461:run$97093 [4:2] + New connections: { $auto$wreduce.cc:461:run$97093 [5] $auto$wreduce.cc:461:run$97093 [1:0] } = { $auto$wreduce.cc:461:run$97093 [2] 2'11 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18214: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24484: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29181: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0], B=8'10010100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$60678: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97090 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97090 [5:2] + New connections: $auto$wreduce.cc:461:run$97090 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0], B=6'100111, Y=$auto$wreduce.cc:461:run$97086 [5:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:4] 1'0 }, B=3'101, Y={ $auto$wreduce.cc:461:run$97086 [5:4] $auto$wreduce.cc:461:run$97086 [2] } + New connections: { $auto$wreduce.cc:461:run$97086 [3] $auto$wreduce.cc:461:run$97086 [1:0] } = 3'011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97080 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97080 [5:2] + New connections: $auto$wreduce.cc:461:run$97080 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97058 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97058 [5:2] + New connections: $auto$wreduce.cc:461:run$97058 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245: + Old ports: A=$auto$wreduce.cc:461:run$97046 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97102 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97046 [5] $auto$wreduce.cc:461:run$97046 [3] $auto$wreduce.cc:461:run$97046 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97102 [5:2] + New connections: $auto$wreduce.cc:461:run$97102 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y + New ports: A=5'00111, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [3:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] }, B=4'0110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [4:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [2] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y, B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 1'0 }, B=3'101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [6:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [1] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y + New ports: A=3'101, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [3:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276: + Old ports: A=8'10000001, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y + New ports: A=3'101, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [2] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [1] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [3:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y, B=8'10010000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] }, B=3'110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [3:1] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126: + Old ports: A=$auto$wreduce.cc:461:run$97114 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0] + New ports: A=$auto$wreduce.cc:461:run$97114 [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811: + Old ports: A=8'00000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y + New ports: A=2'00, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y, B={ 6'000000 \bridge.g_packet.asic.packet_core.blake_retire_mismatch_detail [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [1:0], B=\bridge.g_packet.asic.packet_core.blake_retire_mismatch_detail [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270: + Old ports: A=16'0000000000000101, B=$auto$wreduce.cc:461:run$97093 [15:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y + New ports: A=6'000101, B=$auto$wreduce.cc:461:run$97093 [5:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301: + Old ports: A=5'00101, B=$auto$wreduce.cc:461:run$97110 [4:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0] + New ports: A=2'01, B={ $auto$wreduce.cc:461:run$97110 [4] $auto$wreduce.cc:461:run$97110 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y, B={ 11'00000000000 $auto$wreduce.cc:461:run$97111 [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0], B={ $auto$wreduce.cc:461:run$97111 [4] 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 $auto$wreduce.cc:461:run$97111 [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319: + Old ports: A=4'0101, B=$auto$wreduce.cc:461:run$97112 [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0] + New ports: A=2'01, B=$auto$wreduce.cc:461:run$97112 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366: + Old ports: A=$auto$wreduce.cc:461:run$97086 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y + New ports: A=$auto$wreduce.cc:461:run$97086 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378: + Old ports: A=$auto$wreduce.cc:461:run$97080 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y + New ports: A=$auto$wreduce.cc:461:run$97080 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396: + Old ports: A=$auto$wreduce.cc:461:run$97058 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y + New ports: A=$auto$wreduce.cc:461:run$97058 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406: + Old ports: A=$auto$wreduce.cc:461:run$97102 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y + New ports: A=$auto$wreduce.cc:461:run$97102 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y, B=8'10000100, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [2] 1'1 }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [1] } = 6'100000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4888: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] }, B=2'11, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [7:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [2:1] } = { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4942: + Old ports: A=$auto$wreduce.cc:461:run$97142 [1:0], B=2'00, Y=$auto$wreduce.cc:461:run$97141 [1:0] + New ports: A=$auto$wreduce.cc:461:run$97142 [0], B=1'0, Y=$auto$wreduce.cc:461:run$97141 [0] + New connections: $auto$wreduce.cc:461:run$97141 [1] = $auto$wreduce.cc:461:run$97141 [0] + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18295: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0], B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24993: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0], B=8'10000110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [0] }, B=4'0110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y, B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] }, B=3'001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [1] } = 5'10001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y + New ports: A=2'10, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y + New ports: A=6'100111, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [3:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1:0] }, B=3'111, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] }, B=5'10110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [4:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [2] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270: + Old ports: A=6'000101, B=$auto$wreduce.cc:461:run$97093 [5:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] + New ports: A=5'00010, B={ $auto$wreduce.cc:461:run$97093 [2] $auto$wreduce.cc:461:run$97093 [4:2] 1'1 }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y, B=16'0000000001111010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] }, B=7'1111010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [6:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [15:7] = 9'000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0], B={ $auto$wreduce.cc:461:run$97111 [4] 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 $auto$wreduce.cc:461:run$97111 [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] }, B={ $auto$wreduce.cc:461:run$97111 [4] $auto$wreduce.cc:461:run$97111 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325: + Old ports: A=16'0000000000000101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y + New ports: A=4'0101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345: + Old ports: A=$auto$wreduce.cc:461:run$97090 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97090 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366: + Old ports: A=$auto$wreduce.cc:461:run$97086 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97086 [5:4] $auto$wreduce.cc:461:run$97086 [2] 1'1 }, B=4'0010, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [2:1] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [0] } = 2'01 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378: + Old ports: A=$auto$wreduce.cc:461:run$97080 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97080 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396: + Old ports: A=$auto$wreduce.cc:461:run$97058 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97058 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406: + Old ports: A=$auto$wreduce.cc:461:run$97102 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97102 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590: + Old ports: A=8'10000000, B={ 8'10000011 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y + New ports: A=3'000, B={ 3'011 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y [2:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y [7:3] = 5'10000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4972: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0], B=8'10001000, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] }, B=3'110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [2:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15046: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=4'1110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17032: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=5'01111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [7:5] = { $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17459: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18832: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$23806: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=5'01100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [7:5] = { $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26380: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=4'1101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$28929: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0], B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [4:0], B=5'00011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1:0] }, B=3'011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [2:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [7:3] = 5'10000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y, B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [4:0] }, B=6'100101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] }, B=4'1001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [1] } = 4'0001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y + New ports: A=3'110, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [6:0], B=7'0000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y [6:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y [15:7] = 9'000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] }, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325: + Old ports: A=4'0101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0] + New ports: A=2'01, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5041: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0], B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] }, B=4'1001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [2] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15202: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17290: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [4:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17720: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [4:0] }, B=6'110101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19123: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$21154: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] }, B=4'1101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24220: + Old ports: A=8'10001001, B=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] + New ports: A=6'101001, B={ $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26530: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2:0] }, B=4'1110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [4:0] }, B=6'100011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1:0] }, B=4'1011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [2:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [6:3] = 4'0000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5095: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] + New ports: A=5'10110, B={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [3:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14093: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18133: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19548: + Old ports: A=8'00000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] + New ports: A=2'00, B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$21586: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26674: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5134: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0], B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [3:0] }, B=5'10011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [3:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14345: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0], B=8'10001110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [4:0] }, B=6'101110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18373: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [4:0] }, B=6'101111, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$22989: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26812: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0], B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [4:0] }, B=6'110001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5164: + Old ports: A=8'10000010, B=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0], Y=\bridge.g_packet.asic.packet_core.request_fault_status + New ports: A=5'10010, B={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [3:0] }, Y={ \bridge.g_packet.asic.packet_core.request_fault_status [7] \bridge.g_packet.asic.packet_core.request_fault_status [3:0] } + New connections: \bridge.g_packet.asic.packet_core.request_fault_status [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14744: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18607: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [4:0] }, B=6'110110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$25434: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26944: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0], B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [4:0] }, B=6'110001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14971: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18907: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [4:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$27609: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15720: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0], B={ 6'000000 \bridge.g_packet.asic.packet_core.request_fault_detail [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [1:0], B=\bridge.g_packet.asic.packet_core.request_fault_detail [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19617: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [1:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$22131: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [1:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24867: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$27189: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0], B=\bridge.g_packet.asic.packet_core.request_fault_status, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] }, B={ \bridge.g_packet.asic.packet_core.request_fault_status [7] 1'0 \bridge.g_packet.asic.packet_core.request_fault_status [3:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] }, B=6'000000, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [4:0] }, B={ 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [4:0] }, B=6'000001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [4:0] }, B={ 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [2] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y, B=\bridge.g_packet.asic.packet_core.request_fault_status, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.request_fault_status [7] 1'0 \bridge.g_packet.asic.packet_core.request_fault_status [3:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [4:0] }, B={ 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [4:0] }, B=6'100011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [2] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [7] 5'00011 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 247 changes. + +26.30.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 3 cells. + +26.30.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 49 unused wires. + + +26.30.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 1'1 $auto$wreduce.cc:461:run$97094 [3] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$97094 [3] 1'1 }, Y={ $auto$wreduce.cc:461:run$97093 [4:3] $auto$wreduce.cc:461:run$97093 [5] } + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97093 [4] $auto$wreduce.cc:461:run$97093 [5] } + New connections: $auto$wreduce.cc:461:run$97093 [3] = $auto$wreduce.cc:461:run$97094 [3] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:29] 1'1 $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97133 [29] 2'11 $auto$wreduce.cc:461:run$97133 [29] $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 }, Y={ $auto$wreduce.cc:461:run$97134 [30:28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30] 1'1 $auto$wreduce.cc:461:run$97133 [29] $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98374 [1] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98374 [0] $auto$opt_expr.cc:205:group_cell_inputs$98374 [2] }, Y={ $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New connections: { $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] } = { $auto$wreduce.cc:461:run$97134 [7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [7] $auto$wreduce.cc:461:run$97134 [8] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [23] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [20:19] 2'11 $auto$wreduce.cc:461:run$97134 [8] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97135 [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [3] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [23] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [20:19] $auto$wreduce.cc:461:run$97134 [8] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98378 [6:3] $auto$opt_expr.cc:205:group_cell_inputs$98378 [7] $auto$opt_expr.cc:205:group_cell_inputs$98378 [2:0] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [3] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97135 [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20] $auto$wreduce.cc:461:run$97135 [3] $auto$wreduce.cc:461:run$97135 [3] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97134 [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] 2'11 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97134 [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98382 [6:5] $auto$opt_expr.cc:205:group_cell_inputs$98382 [9] $auto$opt_expr.cc:205:group_cell_inputs$98382 [4] $auto$opt_expr.cc:205:group_cell_inputs$98382 [8] $auto$opt_expr.cc:205:group_cell_inputs$98382 [3] $auto$opt_expr.cc:205:group_cell_inputs$98382 [7] $auto$opt_expr.cc:205:group_cell_inputs$98382 [2:1] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98382 [0] $auto$opt_expr.cc:205:group_cell_inputs$98382 [10] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: $auto$wreduce.cc:461:run$97135 [14] = $auto$wreduce.cc:461:run$97135 [8] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 4 changes. + +26.30.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.30.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_value[1]$98343 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [335:208], Q = \bridge.g_packet.asic.packet_core.staged_write_value[1]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_value[0]$98341 ($dff) from module ulx3s_packet_top (D = $memory\bridge.g_packet.asic.packet_core.staged_write_value$wrmux[0][1][0]$y$98352, Q = \bridge.g_packet.asic.packet_core.staged_write_value[0]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_address[1]$98315 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.staged_access[7], Q = \bridge.g_packet.asic.packet_core.staged_write_address[1]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_address[0]$98313 ($dff) from module ulx3s_packet_top (D = $memory\bridge.g_packet.asic.packet_core.staged_write_address$wrmux[0][1][0]$y$98328, Q = \bridge.g_packet.asic.packet_core.staged_write_address[0]). +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. + +26.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 2 unused cells and 22 unused wires. + + +26.30.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134: + Old ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 4'0000 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 2'00 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296: + Old ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 4'0000 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 2'00 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 [12:11] $auto$opt_expr.cc:205:group_cell_inputs$98239 [9] $auto$opt_expr.cc:205:group_cell_inputs$98239 [7] $auto$opt_expr.cc:205:group_cell_inputs$98239 [10] $auto$opt_expr.cc:205:group_cell_inputs$98239 [5:4] $auto$opt_expr.cc:205:group_cell_inputs$98239 [1] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [13] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98411 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98411 [4] $auto$opt_expr.cc:205:group_cell_inputs$98411 [1:0] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [13] } + New connections: { $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] } = { $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [6] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] 1'1 $auto$wreduce.cc:461:run$97135 [13] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 [12:4] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98243 [1:0] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [7] $auto$wreduce.cc:461:run$97135 [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] 1'1 $auto$wreduce.cc:461:run$97135 [13] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98413 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98413 [5] $auto$opt_expr.cc:205:group_cell_inputs$98413 [1:0] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98413 [4] $auto$opt_expr.cc:205:group_cell_inputs$98413 [6] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: { $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] } = { $auto$wreduce.cc:461:run$97135 [20:19] $auto$wreduce.cc:461:run$97135 [20:19] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y, B={ 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [4:0] }, B={ 2'10 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 6 changes. + +26.30.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.30.20. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. + +26.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 3 unused wires. + + +26.30.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.23. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27:26] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97134 [28] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 [12:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98247 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [12] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [2] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97134 [28] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98416 [6:4] $auto$opt_expr.cc:205:group_cell_inputs$98416 [1] $auto$opt_expr.cc:205:group_cell_inputs$98416 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98416 [8] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98416 [0] $auto$opt_expr.cc:205:group_cell_inputs$98416 [7] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [12] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [2] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98251 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98418 [6:5] $auto$opt_expr.cc:205:group_cell_inputs$98418 [9] $auto$opt_expr.cc:205:group_cell_inputs$98418 [4:3] $auto$opt_expr.cc:205:group_cell_inputs$98418 [8] $auto$opt_expr.cc:205:group_cell_inputs$98418 [2:1] $auto$opt_expr.cc:205:group_cell_inputs$98418 [10] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98418 [0] $auto$opt_expr.cc:205:group_cell_inputs$98418 [7] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 2 changes. + +26.30.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.27. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.30.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.30. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:9] $auto$opt_expr.cc:205:group_cell_inputs$98251 [7] $auto$opt_expr.cc:205:group_cell_inputs$98251 [8] $auto$opt_expr.cc:205:group_cell_inputs$98251 [5:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98251 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98420 [5:4] $auto$opt_expr.cc:205:group_cell_inputs$98420 [8] $auto$opt_expr.cc:205:group_cell_inputs$98420 [3] $auto$opt_expr.cc:205:group_cell_inputs$98420 [7] $auto$opt_expr.cc:205:group_cell_inputs$98420 [1] $auto$opt_expr.cc:205:group_cell_inputs$98420 [2] $auto$opt_expr.cc:205:group_cell_inputs$98420 [9] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98420 [0] $auto$opt_expr.cc:205:group_cell_inputs$98420 [6] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97133 [29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $auto$wreduce.cc:461:run$97135 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97133 [29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $auto$wreduce.cc:461:run$97135 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98422 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98422 [1] $auto$opt_expr.cc:205:group_cell_inputs$98422 [5] $auto$opt_expr.cc:205:group_cell_inputs$98422 [0] $auto$opt_expr.cc:205:group_cell_inputs$98422 [4:3] $auto$opt_expr.cc:205:group_cell_inputs$98422 [9] $auto$opt_expr.cc:205:group_cell_inputs$98422 [10] $auto$opt_expr.cc:205:group_cell_inputs$98422 [2] $auto$opt_expr.cc:205:group_cell_inputs$98422 [8] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] } = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 2 changes. + +26.30.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.34. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.30.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.37. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1623: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $auto$wreduce.cc:461:run$97135 [18] $auto$wreduce.cc:461:run$97134 [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $auto$wreduce.cc:461:run$97135 [18] $auto$wreduce.cc:461:run$97134 [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98424 [8:7] $auto$opt_expr.cc:205:group_cell_inputs$98424 [3] $auto$opt_expr.cc:205:group_cell_inputs$98424 [6] $auto$opt_expr.cc:205:group_cell_inputs$98424 [2:1] $auto$opt_expr.cc:205:group_cell_inputs$98424 [5] $auto$opt_expr.cc:205:group_cell_inputs$98424 [9] $auto$opt_expr.cc:205:group_cell_inputs$98424 [10] $auto$opt_expr.cc:205:group_cell_inputs$98424 [11] $auto$opt_expr.cc:205:group_cell_inputs$98424 [4] $auto$opt_expr.cc:205:group_cell_inputs$98424 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [23] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [20] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 1 changes. + +26.30.40. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.41. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 1 unused wires. + + +26.30.43. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.30.44. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.30.47. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.48. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.49. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.30.50. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.30.51. Finished OPT passes. (There is nothing left to do.) + +26.31. Executing TECHMAP pass (map to technology primitives). + +26.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/arith_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ecp5_alu'. +Successfully finished Verilog frontend. + +26.31.3. Continuing TECHMAP pass. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ecp5_alu for cells of type $alu. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $lut. +Using extmapper simplemap for cells of type $sdff. +Using template $paramod$3e6013394447b9f5655f40d9b082bb75de6c7f0c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d66a711d7e97d14a7c7a9fd9e900c39b1fc36cfa\_80_ecp5_alu for cells of type $alu. +Using extmapper maccmap for cells of type $macc. + add \bridge.g_packet.asic.packet_core.response_payload_mux.payload_index [4:0] (5 bits, unsigned) + sub { $techmap97179$auto$share.cc:667:make_supercell$97173.Y [2:0] 2'00 } (5 bits, unsigned) + add 5'10001 (5 bits, unsigned) +Using extmapper simplemap for cells of type $mux. +Using template $paramod$constmap:f00043fc55daea38aef72d8e6295cbc9727d4528$paramod$b434c177fd0ba7b727bcf52e63869b1f5cb81d5c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$8b1a36ab2238111d2a0f4cb4ef2e14f2a55fc1f9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e20dd69394642b602af944fa966e099d5a6789a2\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:3d770d3f0e63622fe3434edb9a878b97222d5e2a$paramod$5d2a8dabb79f284440e8a72a1afb5894aff4d0d1\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$a460ba4831a5c553df03ee15bf45a690343e194f\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9a7f8f842c7d15a8f6b6820db3daba71c00239a1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f956edc9fe4df758d9fdb10bfc518a364c99e75e\_90_alu for cells of type $alu. +Using template $paramod$e95b69d3115bf069a0763f3951e78119084acbbc\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:b932cf6f5b744e7a22fe56014111479eed600561$paramod$6b401fce98938c3da90dba3992a2381126d14c86\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$f5ef69b350eb4888d7fd5599e5525777232de9ee\_80_ecp5_alu for cells of type $alu. +Using template $paramod$c78beacbbce872b25786db84eb9f11fc34f75ce1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9984296a4bb6718f9a1d83dbdd617d11d154c2d7\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:d3cca817093d0befd4513a92cfe48f9b2294495b$paramod$a33f210e9dfd7445c53aacb0e77dd047a12d9b6f\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$bee761d331fdedbd8626647f29f2ee65d35196da\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\_90_mod for cells of type $mod. +Using template $paramod$d90c3448203144d55644b597072d6cf1b3e54430\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\_90_div for cells of type $div. +Using template $paramod$fb7f6c42d84fe8fae89a359df55310f1e494c563\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3feadc943c245786557f92f999c9b43f572b6b8b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:da283fa03f54264b1ac64045e6b92c72b69afff5$paramod$3c22fa67685c4ece6d7a71e8c65fa1c930a7b26e\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$106402fc14ba87a4d8643cf9e9a3de5e7eff24e1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:dbc0e80e8b30c37248cdc71088745cad46c205c8$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. + add { $techmap97179$auto$share.cc:667:make_supercell$97173.Y 2'00 } (7 bits, unsigned) + add 16'0000000000101111 (16 bits, unsigned) +Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$29dcfde687ab76cd03c4ee062fb9520b20dbe845\_90_pmux for cells of type $pmux. +Using template $paramod$38e8498ccdc425801fe5312e427e3cf0d9089c58\_80_ecp5_alu for cells of type $alu. +Using template $paramod$72f7795a18b8bd21d2def9f98cbb7d0e4ff65a7f\_90_pmux for cells of type $pmux. +Using template $paramod$0f9ef3943735053e2437cb2dfebddb8617beb01b\_90_pmux for cells of type $pmux. +Using template $paramod$f42569e367821ad1b7d52f2d157a44ce80c766dc\_90_pmux for cells of type $pmux. +Using template $paramod$4f9ddb8bcc47f1c63c5307c488aaf2e8cb141a6c\_90_pmux for cells of type $pmux. +Using template $paramod$b8765a8123741d1543ecc993bbc61eeed6ca73ea\_90_pmux for cells of type $pmux. +Using template $paramod$0612aa82a8bdb3c60f7a2e5f068aa820e0b30027\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ecp5_alu for cells of type $alu. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$constmap:2609a5722a69691cd18f1ae36c23d1d8a273e785$paramod$ef0ec05b6682614df4f877d3cc76a5f45a4b7300\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using template $paramod$231afaec00e6fad0c71d9f677e0405124d548ad2\_90_pmux for cells of type $pmux. +Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. +Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. +Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. +Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. +Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. +Using template $paramod$e830d104b5de63a966ae948f6aff012e63986700\_90_pmux for cells of type $pmux. +Using template $paramod$70d30c21ff772b34d0d1da2801fbd781dc3c70e4\_90_pmux for cells of type $pmux. +Using template $paramod$b8a7a49af93c9972e4faced050a7ddb2a5968b70\_80_ecp5_alu for cells of type $alu. +Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:d3a9dbfbcdb01b8f2b0053b3a234a39cfa4a68b0$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 +Creating constmapped module `$paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx'. + +26.31.136. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$122515. + dead port 2/2 on $mux $procmux$122509. + dead port 2/2 on $mux $procmux$122503. + dead port 2/2 on $mux $procmux$122497. + dead port 2/2 on $mux $procmux$122491. + dead port 2/2 on $mux $procmux$122485. + dead port 2/2 on $mux $procmux$122479. + dead port 2/2 on $mux $procmux$122473. +Removed 8 multiplexer ports. + + +26.31.137. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx. + +Removed 0 unused cells and 13 unused wires. +Using template $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx for cells of type $shift. +Using template $paramod$7b16819b516a037d220ff7463dffc76498bbb23b\_90_alu for cells of type $alu. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Bit 10 of port B and bit 9 of port B are connected. + Bit 11 of port B and bit 9 of port B are connected. + Bit 12 of port B and bit 9 of port B are connected. + Bit 13 of port B and bit 9 of port B are connected. + Bit 14 of port B and bit 9 of port B are connected. + Bit 15 of port B and bit 9 of port B are connected. + Bit 16 of port B and bit 9 of port B are connected. + Bit 17 of port B and bit 9 of port B are connected. + Bit 18 of port B and bit 9 of port B are connected. + Bit 19 of port B and bit 9 of port B are connected. + Bit 20 of port B and bit 9 of port B are connected. + Bit 21 of port B and bit 9 of port B are connected. + Bit 22 of port B and bit 9 of port B are connected. + Bit 23 of port B and bit 9 of port B are connected. + Bit 24 of port B and bit 9 of port B are connected. + Bit 25 of port B and bit 9 of port B are connected. + Bit 26 of port B and bit 9 of port B are connected. + Bit 27 of port B and bit 9 of port B are connected. + Bit 28 of port B and bit 9 of port B are connected. + Bit 29 of port B and bit 9 of port B are connected. + Bit 30 of port B and bit 9 of port B are connected. + Bit 31 of port B and bit 9 of port B are connected. +Creating constmapped module `$paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx'. + +26.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$116161. + dead port 1/2 on $mux $procmux$116158. + dead port 2/2 on $mux $procmux$116158. + dead port 1/2 on $mux $procmux$116155. + dead port 1/2 on $mux $procmux$116152. + dead port 2/2 on $mux $procmux$116152. + dead port 1/2 on $mux $procmux$116149. + dead port 1/2 on $mux $procmux$116146. + dead port 2/2 on $mux $procmux$116146. + dead port 2/2 on $mux $procmux$116140. + dead port 2/2 on $mux $procmux$116134. + dead port 2/2 on $mux $procmux$116128. + dead port 2/2 on $mux $procmux$116122. + dead port 2/2 on $mux $procmux$116116. +Removed 14 multiplexer ports. + + +26.31.142. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx. + +Removed 45 unused cells and 62 unused wires. +Using template $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:6c39e690103f07a79a9a7bc3048d8f2f5e5d9d3c$paramod$f612e35060ae7fb18272569c570296f68e4cce8a\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:09a194da8e942924b0a9ba3642691e46c42a5672$paramod$ca10b04578db81bdaee95c919a49f80d9e62ba64\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:779758473956024271d76e132066ad805458a885$paramod$31bea9f4cbe46260fd6192157109a9aa617193fa\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. +Using template $paramod$fc16b9f758000d363d24f130038bd99b46b4fa1b\_90_pmux for cells of type $pmux. +Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$076c9a7a3f037230073fe14dd4865d470cb48917\_80_ecp5_alu for cells of type $alu. +Using template $paramod$bc5b76409c189dae1304578314e9d1ddd73fedb5\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9fd1289fe94899e73ba1836aa1d18f7f186f44e4\_80_ecp5_alu for cells of type $alu. +Using template $paramod$a34f5a54451e27e96d7c38bcd96183b90a0e2cf0\_80_ecp5_alu for cells of type $alu. +Using template $paramod$74ae009756a053357cf6867c0f5ef34bbd93f8bc\_80_ecp5_alu for cells of type $alu. +Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. +Using template $paramod$9dd2c168c92ea5e7211728a4dd85e9d07319b5c9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$081ba1a4a7201ecdb44563d3c3bd7013d1ebf4eb\_80_ecp5_alu for cells of type $alu. +Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fb2ccc7567b9f572f99303d62bd705e69acf8cd5\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $sdffce. +Using template $paramod$dd7e7d5c03aea134912316b6b5bb7a107010ead9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. +Using template $paramod$ebf89ea36a793f0f77858f212141d47c833068ad\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fdd20cfde6eff5e426e814d02912ca76c51febc9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. +Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f634e570cbc550b94014122ad284ced3e6dbf131\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ecp5_alu for cells of type $alu. +Using template $paramod$dde52db7035cb02b3cc5e73865788532339e3bcb\_80_ecp5_alu for cells of type $alu. +Using template $paramod$99501223b6f7e5af250351eeb57edb5403a5ad0b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:51fb3526f3621c6ba109a6fa670766d42e57f474$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx'. + +26.31.214. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$164768. + dead port 2/2 on $mux $procmux$164762. + dead port 2/2 on $mux $procmux$164756. + dead port 2/2 on $mux $procmux$164750. +Removed 4 multiplexer ports. + + +26.31.215. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000101 for cells of type $fa. +Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\$__div_mod_trunc for cells of type $__div_mod_trunc. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Running "alumacc" on wrapper $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $paramod\$__div_mod_u\WIDTH=32'00000000000000000000000000100000 for cells of type $__div_mod_u. +Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $paramod$789c344356a154d2afc7b832b41d1067dbc946ba\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e39069e3f4ee35c1eea86993bd74689959babaab\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d7aca3dc44b07ff19908fb1a3b606577588c15f1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f9e3a3c4b84f99cb56fad07743ec44ad55b11c8b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$dd5ba471f7dcf35707f23b88cfd15b9582f97277\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b7531bc0616f8d4cdd8159edd2237c9ddbb2ce01\_80_ecp5_alu for cells of type $alu. +Using template $paramod$ff8ba121d2f8e85b775c9f35ef677a1a276e7e1b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9a66d4bebbc4fab84566caffef9f094a1a467389\_80_ecp5_alu for cells of type $alu. +Using template $paramod$57bc309a5d8a948cec8981d26d896ee1cbf54d58\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f94cfdb8ad389f4fc4515bcb65bccd7e2d189e95\_80_ecp5_alu for cells of type $alu. +Using template $paramod$2a25669ccd39fe7c0fbfb2a4d17416fc78667f00\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d9397dfdf5f7cf5715aebc9527845402880218a0\_80_ecp5_alu for cells of type $alu. +Using template $paramod$acc477ace2583cc2ee0cf651c72a385d2bbbe9f1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$415abdcadc251df4f0f033b62b8f3296b8461b4e\_80_ecp5_alu for cells of type $alu. +Using template $paramod$6573c1c269218f299badf6e04ca86aa37fdb352c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$6a21b72c9c0b32e81b169c7e08a4d8b9c462448f\_80_ecp5_alu for cells of type $alu. +Using template $paramod$324e0706ebb77f1915b22f4a136962ec3fd1d7ff\_80_ecp5_alu for cells of type $alu. +Using template $paramod$461fc931d630cb01bec1fea87f37fbcc53f6f6a4\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fe074227b1c5fbaa1ea56076182c29dbcf3a782a\_80_ecp5_alu for cells of type $alu. +Using template $paramod$85502450775e62e9c6a2fe29020b3433d4335647\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e32c921f95fe0e2350204f4ecefc9e296355521b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$05d913fba320393c7e943e625bef3af776153b60\_80_ecp5_alu for cells of type $alu. +Using template $paramod$8e07e2c0a3efc148d2f3714f3901076678774ed1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$5b7e592b3c2951af6800b7fd597f66a79b72b91c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$90182783100594e2dd636a282c4723cfc9adaedd\_80_ecp5_alu for cells of type $alu. +Using template $paramod$851c5c9b30913ea2deae68e3ca9e9c4e649723bc\_80_ecp5_alu for cells of type $alu. +Using template $paramod$1445aacdb5f2a1ef9fedf1373097ffa45438211d\_80_ecp5_alu for cells of type $alu. +Using template $paramod$7add42b712fe5bbbba521e93062103d6bf78a453\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b6f86f6a0c43c26b22ee55f51e05d5951f0e6562\_80_ecp5_alu for cells of type $alu. +Using template $paramod$044fdceace8c449ec99f900b42120ac005ff4065\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b6b58933bcf3c8b9e3e5de18c2637bd0e12c7c47\_80_ecp5_alu for cells of type $alu. +No more expansions possible. + + +26.32. Executing OPT pass (performing simple optimizations). + +26.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 9955 cells. + +26.32.3. Executing OPT_DFF pass (perform DFF optimizations). + +26.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 19639 unused cells and 32416 unused wires. + + +26.32.5. Finished fast OPT passes. + +26.33. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +26.35. Executing TECHMAP pass (map to technology primitives). + +26.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +26.35.2. Continuing TECHMAP pass. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. +Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +26.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +26.38. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in ulx3s_packet_top. + +26.39. Executing ATTRMVCP pass (move or copy attributes). + +26.40. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 6 unused cells and 33530 unused wires. + + +26.41. Executing TECHMAP pass (map to technology primitives). + +26.41.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/latches_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +26.41.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42. Executing ABC9 pass. + +26.42.1. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.2. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.3. Executing SCC pass (detecting logic loops). +Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$103721 $auto$ff.cc:266:slice$144591 $auto$simplemap.cc:126:simplemap_reduce$100400 $auto$simplemap.cc:126:simplemap_reduce$100396 $auto$simplemap.cc:126:simplemap_reduce$100390 $auto$simplemap.cc:126:simplemap_reduce$100379 $auto$simplemap.cc:267:simplemap_mux$151506 $auto$ff.cc:266:slice$119395 $auto$simplemap.cc:126:simplemap_reduce$103723 $auto$simplemap.cc:126:simplemap_reduce$103720 $auto$ff.cc:266:slice$144201 $auto$simplemap.cc:126:simplemap_reduce$100402 +Found an SCC: $auto$ff.cc:266:slice$119266 $auto$simplemap.cc:126:simplemap_reduce$103714 $auto$simplemap.cc:126:simplemap_reduce$103712 $auto$simplemap.cc:225:simplemap_logbin$119201 $auto$simplemap.cc:225:simplemap_logbin$164196 +Found 2 SCCs in module ulx3s_packet_top. +Found 2 SCCs. + +26.42.4. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.5. Executing PROC pass (convert processes to netlists). + +26.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +26.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +26.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +26.42.5.4. Executing PROC_INIT pass (extract init attributes). + +26.42.5.5. Executing PROC_ARST pass (detect async resets in processes). + +26.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +26.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +26.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +26.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +26.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +26.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +26.42.5.12. Executing OPT_EXPR pass (perform const folding). + +26.42.6. Executing TECHMAP pass (map to technology primitives). + +26.42.6.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.42.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42.7. Executing OPT pass (performing simple optimizations). + +26.42.7.1. Executing OPT_EXPR pass (perform const folding). + +26.42.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +26.42.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +26.42.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +26.42.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +26.42.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +26.42.7.8. Executing OPT_EXPR pass (perform const folding). + +26.42.7.9. Finished OPT passes. (There is nothing left to do.) + +26.42.8. Executing TECHMAP pass (map to technology primitives). + +26.42.8.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +26.42.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42.9. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +26.42.10. Executing ABC9_OPS pass (helper functions for ABC9). + + +26.42.11. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.12. Executing ABC9_OPS pass (helper functions for ABC9). + + +26.42.13. Executing TECHMAP pass (map to technology primitives). + +26.42.13.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.42.13.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $or. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +26.42.14. Executing OPT pass (performing simple optimizations). + +26.42.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.42.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 2 cells. + +26.42.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +26.42.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.42.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.42.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 55 unused wires. + + +26.42.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.42.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.42.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +26.42.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.42.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.42.14.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.42.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.42.14.16. Finished OPT passes. (There is nothing left to do.) + +26.42.15. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_packet_top: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 2 $_OR_ + 2 $_XOR_ + 14 $_MUX_ + not replaced 3 cell types: + 31 $specify2 + 4 $_NOT_ + 4 $_AND_ + +26.42.16. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_packet_top: replaced 49747 cells with 308809 new cells, skipped 21329 cells. + replaced 3 cell types: + 13140 $_OR_ + 7422 $_XOR_ + 29185 $_MUX_ + not replaced 7 cell types: + 5022 $_NOT_ + 5733 $_AND_ + 1 MULT18X18D + 1 EHXPLLL + 7221 TRELLIS_FF + 3350 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + 1 $__ABC9_SCC_BREAKER + +26.42.16.1. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.16.2. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.16.3. Executing XAIGER backend. + +Extracted 128694 AND gates and 346594 wires from module `ulx3s_packet_top' to a netlist network with 7233 inputs and 8853 outputs. + +26.42.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +26.42.16.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 7233/ 8853 and = 114508 lev = 311 (17.77) mem = 2.17 MB box = 3350 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 7233/ 8853 and = 148895 lev = 63 (8.30) mem = 2.10 MB ch =20031 box = 806 bb = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no +ABC: Node = 148895. Ch = 17039. Total mem = 25.98 MB. Peak cut mem = 1.22 MB. +ABC: P: Del = 22659.00. Ar = 135334.0. Edge = 149273. Cut = 1640461. T = 0.46 sec +ABC: P: Del = 22532.00. Ar = 133587.0. Edge = 144083. Cut = 1600620. T = 0.47 sec +ABC: P: Del = 22532.00. Ar = 30136.0. Edge = 94304. Cut = 3442399. T = 0.89 sec +ABC: F: Del = 22532.00. Ar = 28710.0. Edge = 92343. Cut = 3310419. T = 0.87 sec +ABC: A: Del = 22532.00. Ar = 27598.0. Edge = 88719. Cut = 3338144. T = 2.29 sec +ABC: A: Del = 22532.00. Ar = 27529.0. Edge = 88679. Cut = 3324904. T = 2.35 sec +ABC: Total time = 7.34 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 7233/ 8853 and = 88404 lev = 59 (9.52) mem = 1.40 MB box = 785 bb = 0 +ABC: Mapping (K=7) : lut = 23076 edge = 86702 lev = 29 (5.21) levB = 89 mem = 0.94 MB +ABC: LUT = 23076 : 2=1054 4.6 % 3=7181 31.1 % 4=11359 49.2 % 5=3342 14.5 % 6=75 0.3 % 7=65 0.3 % Ave = 3.76 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 72.23 seconds, total: 72.23 seconds + +26.42.16.6. Executing AIGER frontend. + +Removed 132395 unused cells and 156371 unused wires. + +26.42.16.7. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 23150 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 785 +ABC RESULTS: input signals: 189 +ABC RESULTS: output signals: 8780 +Removing temp directory. + +26.42.17. Executing TECHMAP pass (map to technology primitives). + +26.42.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +26.42.17.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000010 for cells of type $__ABC9_SCC_BREAKER. +No more expansions possible. + +Removed 1642 unused cells and 345388 unused wires. + +26.43. Executing TECHMAP pass (map to technology primitives). + +26.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +26.43.2. Continuing TECHMAP pass. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. +Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. +Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. +Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. +Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. +Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. +Using template $paramod$fedcddf7a4357754b8c2c1b3c873f3560b924a39\$lut for cells of type $lut. +Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$b9f1cc075fd5e1dc13f6aa9fc152bf79a0f71ef7\$lut for cells of type $lut. +Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157\$lut for cells of type $lut. +Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut. +Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1\$lut for cells of type $lut. +Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. +Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. +Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. +Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut. +Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. +Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut. +Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. +Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut. +Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. +Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. +Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. +Using template $paramod$000bb7a035b5a5c1934ca0e20d202ab94a0e06c9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. +Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut. +Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. +Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. +Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a\$lut for cells of type $lut. +Using template $paramod$52d96bfa17866bab828b9f1286c638d27fce0ef0\$lut for cells of type $lut. +Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. +Using template $paramod$6a0faddbb1877e236e8eb8130711942937277f4e\$lut for cells of type $lut. +Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. +Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. +Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578\$lut for cells of type $lut. +Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. +Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. +Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut. +Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. +Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. +Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut. +Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. +Using template $paramod$1769b870d47911d7a8ec3b7224a7974dbc5fe069\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut. +Using template $paramod$549a24c0b77071744eefd28bf11342e15d6bc181\$lut for cells of type $lut. +Using template $paramod$c388bdf5bc34e848632d723db494e9a79bee28dd\$lut for cells of type $lut. +Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut. +Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. +Using template $paramod$adb3580ae7f1e000bff662054d4f52a48cec1e58\$lut for cells of type $lut. +Using template $paramod$c0b24172d263163a8e6b59024cdb9dfb57b52d61\$lut for cells of type $lut. +Using template $paramod$f056b3cf42701dfc7f540d463578d46c622fe830\$lut for cells of type $lut. +Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut. +Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut. +Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut. +Using template $paramod$0383ea234f9fd03480ea2f8696098da806b349de\$lut for cells of type $lut. +Using template $paramod$233b70872b0d11ad6386b65bc4d8864ac02395bb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut. +Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. +Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut. +Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut. +Using template $paramod$86d1a361297b330f6575bda7e44a0fcda00635d1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut. +Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. +Using template $paramod$a067ca065a0e8fdac308d6893e69914865d54ec4\$lut for cells of type $lut. +Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut. +Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. +Using template $paramod$bbb10333e84a7e80f65e1494ebbfbf3f28568fcd\$lut for cells of type $lut. +Using template $paramod$ffa1224fa26b3074d5175286833c5c7f95f6fb8b\$lut for cells of type $lut. +Using template $paramod$fe70bb3280659663b8fa2b45f42fda9ccf4ccfaa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. +Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. +Using template $paramod$7776c9f5ae2211fea85581af31384e8ba1fa501e\$lut for cells of type $lut. +Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. +Using template $paramod$8d41622da0aa87c171e3ad24745637a8e540bedc\$lut for cells of type $lut. +Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut. +Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut. +Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. +Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039\$lut for cells of type $lut. +Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394\$lut for cells of type $lut. +Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395\$lut for cells of type $lut. +Using template $paramod$96bf8e3dce66ee15df06137d7b93bf7e34b26863\$lut for cells of type $lut. +Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. +Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848\$lut for cells of type $lut. +Using template $paramod$53085fa3385a29b95b991d58be8f55774e1a4d92\$lut for cells of type $lut. +Using template $paramod$2a533b2b9ed36df203d5fca44a14d68feeb67362\$lut for cells of type $lut. +Using template $paramod$70e649cff31ac39ffa7544751d17e54df9788341\$lut for cells of type $lut. +Using template $paramod$a5810b3064bbc05b2c453025774af99926f05666\$lut for cells of type $lut. +Using template $paramod$5f3abb125a0361a143f12eec230ed33f6f988a00\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100001 for cells of type $lut. +Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e\$lut for cells of type $lut. +Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. +Using template $paramod$a2078492a93db2b736e3f44dc8f19641566d846d\$lut for cells of type $lut. +Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b\$lut for cells of type $lut. +Using template $paramod$810e0f22d547104f8208898922f6ac2444aeece7\$lut for cells of type $lut. +Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut. +Using template $paramod$29f1cd2a09b892eea21b26ecd16aa99574b3d6c4\$lut for cells of type $lut. +Using template $paramod$3b383aa74b05b60cb9cabc0ba0eca4dea92c2b33\$lut for cells of type $lut. +Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b\$lut for cells of type $lut. +Using template $paramod$9c8231ab3b30fd231c3be4df663c91e1a5781fa7\$lut for cells of type $lut. +Using template $paramod$c7b20ecfdd4b0c41f8ccf7e4154a4ad7dca4807c\$lut for cells of type $lut. +Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. +Using template $paramod$842028a23ac07055161965e8aace63da0714578f\$lut for cells of type $lut. +Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. +Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. +Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut. +Using template $paramod$f377b83bfd4274750d2cc48e6e3fa52263d09667\$lut for cells of type $lut. +Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e\$lut for cells of type $lut. +Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut. +Using template $paramod$2af3e003254181d08baef124757f4cecfb778e26\$lut for cells of type $lut. +Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut. +Using template $paramod$74a12c4d30e035eeda2d34c53b77373f2b2df37a\$lut for cells of type $lut. +Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut. +Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab\$lut for cells of type $lut. +Using template $paramod$9640380942618015231dc80e07fe9e6281ac216a\$lut for cells of type $lut. +Using template $paramod$c50bf79556f7c35c37bbd3d892f752a0609f21ca\$lut for cells of type $lut. +Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut. +Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99\$lut for cells of type $lut. +Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821\$lut for cells of type $lut. +Using template $paramod$90edad2b6a4dec5adef9ce6a532f7a1edb48db32\$lut for cells of type $lut. +Using template $paramod$011b9cadb5a2b1bb00b102aedec4f2cce186949e\$lut for cells of type $lut. +Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. +Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. +Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. +Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut. +Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. +Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut. +Using template $paramod$3070c1773f3a1b28a0a0b5f34a4a299b8a02055e\$lut for cells of type $lut. +Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut. +Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. +Using template $paramod$5a490b0e00aeb3aa961ff44c01138435d4948c4d\$lut for cells of type $lut. +Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut. +Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut. +Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c\$lut for cells of type $lut. +Using template $paramod$7a4cd79e1c19466b5946403ebacd15021cb8b814\$lut for cells of type $lut. +Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99\$lut for cells of type $lut. +Using template $paramod$3f0badb1a6257830a007d1166225fb9999e2000c\$lut for cells of type $lut. +Using template $paramod$61c4cbf8581170b67138b98e32863cf2de767f72\$lut for cells of type $lut. +Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. +Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut. +Using template $paramod$cfe658add7b49bc6805d629e0a88423d427de396\$lut for cells of type $lut. +Using template $paramod$32fb8371bd734b78a418ea9de39d47de7a9266da\$lut for cells of type $lut. +Using template $paramod$2b757c49dce94706e41b149d1a63f58eface8af9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011010 for cells of type $lut. +Using template $paramod$a59b6c8d81194b59764286a4118e90f9abac65dc\$lut for cells of type $lut. +Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. +Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$fbb57d8211f7406edbcbc7da6109c62aa6dcf0c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$5f99aa1a31b4f0c356281a67e16706e1e689d29f\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001010 for cells of type $lut. +Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. +Using template $paramod$43526719abd92ef1dcf092f5ae5632bfd65b96d8\$lut for cells of type $lut. +Using template $paramod$aa007bf717dd7ed8e7e12b31bda3917c395525ce\$lut for cells of type $lut. +Using template $paramod$b6508574947c9efbad5feaa6ee5d3e467e528885\$lut for cells of type $lut. +Using template $paramod$edcf01b6b14b71de1ef174d0767058217359b674\$lut for cells of type $lut. +Using template $paramod$f054a7d7ab239e8c6ce022005b59678182897bfe\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. +Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. +Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. +Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. +Using template $paramod$b80e608920ce9cfa1f5c7d21df7a72954e9b0a70\$lut for cells of type $lut. +Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut. +Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. +Using template $paramod$ef2d70b738add7194c07433b79aa092a92f6f1ea\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut. +Using template $paramod$ab802f374fd5db87cad46a1e7b287d7bfdd01aa7\$lut for cells of type $lut. +Using template $paramod$97da510a48140d987a9d50d2cc471e443af59783\$lut for cells of type $lut. +Using template $paramod$5107935b445e7ae7ab686f113b224ad25949eb1b\$lut for cells of type $lut. +Using template $paramod$90687826ecc50762f08b06e0c2f0be8f8b42044c\$lut for cells of type $lut. +Using template $paramod$eeed37ce45abdda29d3e180f2d1dfc0c4c376530\$lut for cells of type $lut. +Using template $paramod$63353a9cd99b0c49001cfade269881ffdd3905ee\$lut for cells of type $lut. +Using template $paramod$20eb354dbce30b5cbcf95731162faf3d60aac496\$lut for cells of type $lut. +Using template $paramod$a5e7a6e7aedf5438d458c5134b7c80da31bdbad3\$lut for cells of type $lut. +Using template $paramod$126a2bf227a5e24e40d623d3ec32202e0557c612\$lut for cells of type $lut. +Using template $paramod$0003932bde6e5d83aa0e3ebadf2bc95f80ff5c46\$lut for cells of type $lut. +Using template $paramod$02eefd9b74acf66558bff242fcbe62a514559f6a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$2f43819c0455a6eb10ff545f8331e5d7d67cb6a2\$lut for cells of type $lut. +Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. +Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. +Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut. +Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. +Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4\$lut for cells of type $lut. +Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. +Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. +Using template $paramod$e56967e4a5743f6ef12dfe7b1009bf8e0aa2fe0d\$lut for cells of type $lut. +Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. +Using template $paramod$a6ef2a845efd4ff0d96bc4fd2f06cc3516fa63ff\$lut for cells of type $lut. +Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. +Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. +Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut. +Using template $paramod$3be30a5a9f993377f0c44a54aadf0fabaaafa2c9\$lut for cells of type $lut. +Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut. +Using template $paramod$76af301ebe268bf10bfd5137e11ac427e045abf5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. +Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. +Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. +Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. +Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. +Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut. +Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. +Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. +Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. +Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. +Using template $paramod$2c95149d0c6ec8cb015c816ff2bb05269df37d88\$lut for cells of type $lut. +Using template $paramod$dbd6bfc0079f30bdbd8251243755394b48ae1fbb\$lut for cells of type $lut. +Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut. +Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut. +Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. +Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut. +Using template $paramod$37fffb60c4ed9143f4207129d4a64018994d852d\$lut for cells of type $lut. +Using template $paramod$dc80e74b9623b8a802ef4b5162559616e5ac1cef\$lut for cells of type $lut. +Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut. +Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut. +Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut. +Using template $paramod$723eb79ef8d5d376f3f196f4acfa8e347145a0fa\$lut for cells of type $lut. +Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. +Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e\$lut for cells of type $lut. +Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. +Using template $paramod$1de39b75a080bd0f6489e0fbdbfc12d8187bcf6f\$lut for cells of type $lut. +Using template $paramod$d47075a53ff1dff553bbe454ba83286b2e9de7dd\$lut for cells of type $lut. +Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut. +Using template $paramod$cba6b89907e1a68cc011c9a30e7e6cfab421f1a1\$lut for cells of type $lut. +Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. +Using template $paramod$a56a39c0f6a5a7dc6beed165205ecc9aaf916f10\$lut for cells of type $lut. +Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. +Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut. +Using template $paramod$b76eeafe3553c6220aebff28fb37e7d4bf1fb01a\$lut for cells of type $lut. +Using template $paramod$9c32fd119457e69e03a24d4d2698f238bf59d9d3\$lut for cells of type $lut. +Using template $paramod$37203517188e0e81c6d1574dd1c274ed56646adf\$lut for cells of type $lut. +Using template $paramod$a3077fa2cf8e48a37d410abdac8a7cce2583fbf3\$lut for cells of type $lut. +Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. +Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. +Using template $paramod$b28b4ecbaa07efdcc51c93348ccdc2395f8b41c1\$lut for cells of type $lut. +Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. +Using template $paramod$f096cbf7810c657d1faa5ebcdd247974deedeea6\$lut for cells of type $lut. +Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut. +Using template $paramod$fd20386aee979bc7d1fe84e4b6d9cb788fcf6275\$lut for cells of type $lut. +Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut. +Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. +Using template $paramod$64591bf347debff55b06eb75d4492bcbee74fc6b\$lut for cells of type $lut. +Using template $paramod$8e01928b484e04dfe17fd3fb8751c9b4f4d6b28e\$lut for cells of type $lut. +Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut. +Using template $paramod$f5c5f595015aee4de78d8a59fd7b7003b8956fde\$lut for cells of type $lut. +Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut. +Using template $paramod$a8cb2c06e172ce1c41ab3f6b96725153b1bfcd6a\$lut for cells of type $lut. +Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut. +Using template $paramod$3b3518232ab43bce2b5905ad42c85b24b1dbc08b\$lut for cells of type $lut. +Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. +Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut. +Using template $paramod$9c6fa709082a3074237b74172629c9b5608bfcac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$d98f7cae393e2fb5f134f7da3a0376cfdd41f123\$lut for cells of type $lut. +Using template $paramod$b4006828b803a36d06401e5093668a1907e825ca\$lut for cells of type $lut. +Using template $paramod$e5cad3f70ef8abd514139dd032da350013fc446a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. +Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. +Using template $paramod$7991e43c533565df3969b82a304afcde859daeba\$lut for cells of type $lut. +Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. +Using template $paramod$15b1be980a14edac79713e171a9494e1b4bd5060\$lut for cells of type $lut. +Using template $paramod$95994721d3c832b251cca338772f7ec207995711\$lut for cells of type $lut. +Using template $paramod$46a3c0240e7a0e1ba60e351b8dd1863f2b554f8b\$lut for cells of type $lut. +Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. +Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$430d9aae42a88b878b2a6ceac307a334dfa959c7\$lut for cells of type $lut. +Using template $paramod$7afde302ddf552f0fb7d1a62db4a89eaf7d351f0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. +Using template $paramod$378674974b3807d742e27f000a928a69cc15ff78\$lut for cells of type $lut. +Using template $paramod$ef23bc364ceee2a8dc5800c611734cfdf1fda657\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. +Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut. +Using template $paramod$175fdba264784436cc7fddca63446b9ae0bf4881\$lut for cells of type $lut. +Using template $paramod$812955f328f06a04a937e86a4a65f93c71c9dd61\$lut for cells of type $lut. +Using template $paramod$0aae27145afd1348566af63c85046495acb0e0d8\$lut for cells of type $lut. +Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. +Using template $paramod$dfdaea48b7611eab326be448302a98c04e3e259b\$lut for cells of type $lut. +Using template $paramod$edf0f1ca1d51bddab33b022d26d3da5ca2294e0d\$lut for cells of type $lut. +Using template $paramod$c1d19d26fc76dcae92dcb8d4cb83a61d66690ab8\$lut for cells of type $lut. +Using template $paramod$0331a4a399782662e6707b65e29e002ee5c3c2ad\$lut for cells of type $lut. +Using template $paramod$9b97a0ad7480907fc31589a8d320d2c7b5988f46\$lut for cells of type $lut. +Using template $paramod$ca2532991f2c847ac990e1deeca1e91108bc2da0\$lut for cells of type $lut. +Using template $paramod$859290076eb0ab5533d03769d9103e68d9252019\$lut for cells of type $lut. +Using template $paramod$16d276ea5dd24ebdbea76e6b5e97f981d6f732d4\$lut for cells of type $lut. +Using template $paramod$cced35221b5252719c37669ece663f2282e06857\$lut for cells of type $lut. +Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. +Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut. +Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc\$lut for cells of type $lut. +Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. +Using template $paramod$049f24bb0a60e88df65dcd16ca4d803000f3ec33\$lut for cells of type $lut. +Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut. +Using template $paramod$e2abc3b706ab86fd7c0d14a17f66f1e597465517\$lut for cells of type $lut. +Using template $paramod$0d94766b8f50ae8b32739d9cec096f2c5d44402a\$lut for cells of type $lut. +Using template $paramod$d61dc5ff3a9102f3e1b420770cb57c48730b6a64\$lut for cells of type $lut. +Using template $paramod$999f605d750567959edab1f1540f58f5f587176d\$lut for cells of type $lut. +Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. +Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000001 for cells of type $lut. +Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. +Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. +Using template $paramod$d2714c8e745a1556f41422d88e68656f7be2eb51\$lut for cells of type $lut. +Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. +Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376\$lut for cells of type $lut. +Using template $paramod$6b6ddc5b21698d9ced7db10b7c11cd0e0bbe1724\$lut for cells of type $lut. +Using template $paramod$93eb7afdb7ba444e94bb8ab99bb6e437294e72c5\$lut for cells of type $lut. +Using template $paramod$59e08c1819e5983704830c894d51357a44766911\$lut for cells of type $lut. +Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut. +Using template $paramod$8f8f3ed0dfbd822273417c0b66ef033f29ee6b95\$lut for cells of type $lut. +Using template $paramod$09452af5ff446506ce6933e409a1fd44c0b602cf\$lut for cells of type $lut. +Using template $paramod$f48bfbefa45c13216169eb3f6bfd33f86a743af6\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. +Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. +Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut. +Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. +Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. +Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. +Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. +Using template $paramod$35369ee2661bc6f22afa7fd33e082ebba93672ba\$lut for cells of type $lut. +Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. +Using template $paramod$8bb130805bdc6693bee1a55c66f5eb884b1589c8\$lut for cells of type $lut. +Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut. +Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut. +Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. +Using template $paramod$ececc55fe721b2d80098bfc00a6005f1af14b6e5\$lut for cells of type $lut. +Using template $paramod$3eb8805ccd6f91bad96dcbf190c2fb4f72f4634f\$lut for cells of type $lut. +Using template $paramod$04979dc4ef7042e984db9bc945cb489ee7f78f7a\$lut for cells of type $lut. +Using template $paramod$68b70f4e14df413658bd31cabb75ae13fe669a27\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. +Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut. +Using template $paramod$314f3c3dec7cf6ef51df1856bd63e6c4433257ff\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. +Using template $paramod$c53aa6fdec082f49347d41c5f71d8229b851ab6e\$lut for cells of type $lut. +Using template $paramod$81e1f78eaf1f9871e7a0d69382986cf21d267346\$lut for cells of type $lut. +Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. +Using template $paramod$5d3a75742a49186e20388443881a0a0917f692ec\$lut for cells of type $lut. +Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. +Using template $paramod$6c5ce7d614693d944f80092742f538498fb7dffc\$lut for cells of type $lut. +Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. +Using template $paramod$e5fa67e3abf5feee06fdd503a1d449e36f4bc6de\$lut for cells of type $lut. +Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. +Using template $paramod$5e15ae04a76125f3b517c457f68d762add482c29\$lut for cells of type $lut. +Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. +Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut. +Using template $paramod$05f73913e867143bcd43eab9e44b992e09d91590\$lut for cells of type $lut. +Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. +Using template $paramod$046677a75b0582b9c306f74453325906cb0a2362\$lut for cells of type $lut. +Using template $paramod$f66976b7a2c3a813b681ce6945edb10a3d232304\$lut for cells of type $lut. +Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. +Using template $paramod$755a25b60136c9f99207cadea9d10868cf2976eb\$lut for cells of type $lut. +Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. +Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut. +Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. +Using template $paramod$9d86735a665af3c1da46d993ca9fb8a1a8b4a873\$lut for cells of type $lut. +Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. +Using template $paramod$64977556c846e4e7f9ced3a7b7fe9d317e7a6b98\$lut for cells of type $lut. +Using template $paramod$43af8829d7b6b99a1d878f6f70b47d603b01581b\$lut for cells of type $lut. +Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. +Using template $paramod$d4aeb23fcfb2d027ae9345ab12ffffa58ef955b9\$lut for cells of type $lut. +Using template $paramod$0c60ec4482aeb729b020b7c47556a79f3cd19781\$lut for cells of type $lut. +Using template $paramod$d97c3b09adecfac2ca8a551bbe295665d430c156\$lut for cells of type $lut. +Using template $paramod$d8021370f0670d331038a0473505efae4dff2706\$lut for cells of type $lut. +Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae\$lut for cells of type $lut. +Using template $paramod$dc41e9665158f6caac97365e95c1c2f88dcb2656\$lut for cells of type $lut. +Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut. +Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut. +Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut. +Using template $paramod$d5b81050f4dde17d887b41d5503081be421dbab6\$lut for cells of type $lut. +Using template $paramod$b90d0bd825ef9aa143f3f391212f99bcd2d228dc\$lut for cells of type $lut. +Using template $paramod$8a6467e94c91f2ff2d68f9e1e4ae64482bde0370\$lut for cells of type $lut. +Using template $paramod$7227ea4800fccfe8973caa4fde61c413cc991170\$lut for cells of type $lut. +Using template $paramod$255b5b55b70a9f31c54d169ac13bc0391040bb53\$lut for cells of type $lut. +Using template $paramod$d2ef43814113ff73f9ebc73be6b7b228fcced45d\$lut for cells of type $lut. +Using template $paramod$81406f9d5ea793037b12f1f0a56a402afa7fbc64\$lut for cells of type $lut. +Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. +Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. +Using template $paramod$5c9402ac1f9624bebb844c6f1a2fa39fceb58fa6\$lut for cells of type $lut. +Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. +Using template $paramod$67ec9a31a0e23cc9bc3ec8cdbf560a93252ed7b7\$lut for cells of type $lut. +Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. +Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b\$lut for cells of type $lut. +Using template $paramod$6bbb754f7471a2fa1afcc5de924e8223eb328dca\$lut for cells of type $lut. +Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. +Using template $paramod$d894ffa1ba7cf53c4b1e0d5fd84aff28dfe71e96\$lut for cells of type $lut. +Using template $paramod$eaca67fb3817360f00958a66ab21b64eef766c33\$lut for cells of type $lut. +Using template $paramod$05bdebefca68d0e34a810cad2de0d2e5e9f7e5f6\$lut for cells of type $lut. +Using template $paramod$e9da3de86f237bcb085ba1689fb89690cf1237d9\$lut for cells of type $lut. +Using template $paramod$b2d762b3bb51b18915702c16c434bdbec4a25a4a\$lut for cells of type $lut. +Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. +Using template $paramod$65fb1d96ed353a5487bb4df51139b6105a246601\$lut for cells of type $lut. +Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut. +Using template $paramod$8f8dc162b887d52b83e5151ac53aec77083a5f6b\$lut for cells of type $lut. +Using template $paramod$a875f8d2599ac50ad4512ef7895d43899873516f\$lut for cells of type $lut. +Using template $paramod$dec948165935e60a7c91daec6fba305409bbb893\$lut for cells of type $lut. +Using template $paramod$241249d1d4c3f5d365d48855d52a4050c66b5508\$lut for cells of type $lut. +Using template $paramod$154d92943fca0a03a3c1537763a41af3e08c4957\$lut for cells of type $lut. +Using template $paramod$778cfa89a311116b4664a0be7522bd19e4c50232\$lut for cells of type $lut. +Using template $paramod$cf3d59690e35586ab717eef77fac309ee05c62c0\$lut for cells of type $lut. +Using template $paramod$e197e162644f13ba3d6def1b385f7543969ee569\$lut for cells of type $lut. +Using template $paramod$15deee21bfb7f6f9f3963bae01e1abc87728ceb1\$lut for cells of type $lut. +Using template $paramod$61cdb7b3beca9f8f70061c399b61d688c3f31426\$lut for cells of type $lut. +Using template $paramod$f4c73d849f7d47805ca1aefb950c4e26e4eae9d0\$lut for cells of type $lut. +Using template $paramod$b3443607fc1ff22fec48eb4559c7f22149c73850\$lut for cells of type $lut. +Using template $paramod$8eef681bdc083ca203a9548d7f7f1d9f218fed21\$lut for cells of type $lut. +Using template $paramod$2ed66c070898e6f5d3963fa62c6aed3c198b27ba\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut. +Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut. +Using template $paramod$2aae3f707bbf5bef51f256ca9ea2cff34ba32805\$lut for cells of type $lut. +Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut. +Using template $paramod$a73e5affe093cbfcf0d2b43eb8fbeac4ea474b24\$lut for cells of type $lut. +Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. +Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. +Using template $paramod$2413346fa47cf8a80719d09e44e1141a42fc9c2e\$lut for cells of type $lut. +Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut. +Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut. +Using template $paramod$16b79a5eba6e0c11d0283a95b16674705257a0eb\$lut for cells of type $lut. +Using template $paramod$437f3216c8a8575307ce60e7fe92b253b67b329d\$lut for cells of type $lut. +Using template $paramod$a53f5ca73ba0589d00065fc440f90f301dc78994\$lut for cells of type $lut. +Using template $paramod$158bf41561e34f496d0afe28c4ac547a36925821\$lut for cells of type $lut. +Using template $paramod$384e64758675daaf5330f45461f59a669167b732\$lut for cells of type $lut. +Using template $paramod$5708ac7a777fae8f9c9daa5e9a52c3f2588c942e\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. +Using template $paramod$157079f0ae4b31275bd0fd04027309ce6c2bb03d\$lut for cells of type $lut. +Using template $paramod$8701b6ee4399940a285292efbe9cceb7b706f778\$lut for cells of type $lut. +Using template $paramod$27f6c8873fe0bdf83df63bf8f11e3e13c46924b1\$lut for cells of type $lut. +Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut. +Using template $paramod$583578005113b28fdc769049949029c37251036c\$lut for cells of type $lut. +Using template $paramod$abac68f66a0af6ba506e4e6ed0564789f19d3056\$lut for cells of type $lut. +Using template $paramod$db1f16b3540819f8331a11890309aca8220a6666\$lut for cells of type $lut. +Using template $paramod$ab50f6fb413073986e8fac916d43b5751b6500aa\$lut for cells of type $lut. +Using template $paramod$4bb876346cbc5d13aef9f873277f12d388c5d51a\$lut for cells of type $lut. +Using template $paramod$640f0b255c4baeb1d5ed3ee07d5b4acf52609838\$lut for cells of type $lut. +Using template $paramod$6da36b00000992020b7b7eba5fbe42bbd326035f\$lut for cells of type $lut. +Using template $paramod$af12fcdb6d4167b15843baf81994cca157a7081f\$lut for cells of type $lut. +Using template $paramod$7fc326a07e1ca3332e6c50518f95d4ba681a1c4f\$lut for cells of type $lut. +Using template $paramod$8df3d57693e1fe1eb8939740ef44b31f69a48327\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod$3ec83cc0e0ec241030d7c40596e80d62c44c0f57\$lut for cells of type $lut. +Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\$lut for cells of type $lut. +Using template $paramod$36400b42aaf9adb061f1992c31e0ecb97c8d592b\$lut for cells of type $lut. +Using template $paramod$541493f767dfdad47f5523f3df4c2b5d41f262fa\$lut for cells of type $lut. +Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3\$lut for cells of type $lut. +Using template $paramod$76be5a5900f80a135961ac09b0cf70ec8308af2c\$lut for cells of type $lut. +Using template $paramod$e87f431398fe61dc3cef677df705fdf1c11aa0f7\$lut for cells of type $lut. +Using template $paramod$191987e4132f69ca46dd53dfa3f15f72d990cc0a\$lut for cells of type $lut. +Using template $paramod$0babebe51def8f4db6daaf70fa957a9414a7eb6e\$lut for cells of type $lut. +Using template $paramod$78b7f61776f7b3e82414706b5df5da710258defb\$lut for cells of type $lut. +Using template $paramod$d584fea2360dda8151932e9c7650815d06026aad\$lut for cells of type $lut. +Using template $paramod$da763b8130a28e1b216739f1a8785f84cdad4cc8\$lut for cells of type $lut. +Using template $paramod$da591023dfd122102746056e60cbd4335dee2967\$lut for cells of type $lut. +Using template $paramod$fecd70a3c12842afedfe0991d741483f4333befc\$lut for cells of type $lut. +Using template $paramod$48ccd01538754f822c4e0d1b7072b646dfab838e\$lut for cells of type $lut. +Using template $paramod$bd9bf3da00bf7305b997889fd74bf71914fe3b76\$lut for cells of type $lut. +Using template $paramod$a36df8cc99428717d44c2342ab2159150ec5d5d5\$lut for cells of type $lut. +Using template $paramod$01c954f3ccfb35914a3a738c89d5bf2cb57b50f6\$lut for cells of type $lut. +Using template $paramod$83f89089d8d50aea6704278132bab8dff4ae4634\$lut for cells of type $lut. +Using template $paramod$762dcdf49521c1aa2145fa6746ab6d57dd5df22e\$lut for cells of type $lut. +Using template $paramod$73d48bb02406b4c5f2ce0cd0a01e47009788eea6\$lut for cells of type $lut. +Using template $paramod$659a07cb052b531f6a26959304b909a63e9b19d9\$lut for cells of type $lut. +Using template $paramod$ed029e6c1e87a70cff2c1ea2f266e7c04d3c3742\$lut for cells of type $lut. +Using template $paramod$37988d71f70f8b382e293f926b32f5a20cfeb976\$lut for cells of type $lut. +Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. +Using template $paramod$d0e4f0cb614d58f16d39673a463165f3a53e05d1\$lut for cells of type $lut. +Using template $paramod$f85c9b2d5ed035cbe08436c409030da7e7effb9b\$lut for cells of type $lut. +Using template $paramod$8c469afba5eb89d974fdc046eae3ff1079e10df4\$lut for cells of type $lut. +Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut. +Using template $paramod$e84e4a245515000cd6930e0f4535753ed485f71e\$lut for cells of type $lut. +Using template $paramod$7593ee757eddab004dbe16f2eed5d381e66ab3f1\$lut for cells of type $lut. +Using template $paramod$360505de37fa7f3b097fcbc42bceab80083d3453\$lut for cells of type $lut. +Using template $paramod$dd55d80dc488f5a4ac45b94e2affc1a910c2c3e4\$lut for cells of type $lut. +Using template $paramod$4ac7f780adaaa22c08c8293c1e5f87245df90c92\$lut for cells of type $lut. +Using template $paramod$e582eabb72f618e7f43a74f48f19b24904765833\$lut for cells of type $lut. +Using template $paramod$08d200a0ce8385a41744a4f3b58fc12712eba5aa\$lut for cells of type $lut. +Using template $paramod$6353e02154629763bb936385ec889903cce366ba\$lut for cells of type $lut. +Using template $paramod$b42c71661456ab1f51df3cf9b706c5bfaf5033b4\$lut for cells of type $lut. +Using template $paramod$2314742bee32bcbcec3260491c4b270a378de401\$lut for cells of type $lut. +Using template $paramod$994df4878b93229fd396eb4dcca07bd1eadd5560\$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. +Using template $paramod$c7da182350c463dac9341b9202c767a484f2d529\$lut for cells of type $lut. +Using template $paramod$54ef21ccddfa27629768f219f304bb4163ac6894\$lut for cells of type $lut. +Using template $paramod$243fb93e736df5581df7bafa378886f2bdf5bea9\$lut for cells of type $lut. +Using template $paramod$a50983bc2d916c31a7d4beac5feb90028d16502d\$lut for cells of type $lut. +Using template $paramod$2af7fd5c408581c2b6e80048f54948ce05a232f8\$lut for cells of type $lut. +Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut. +Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut. +Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut. +Using template $paramod$f0773b2e1ec54f4b5730a332b99958a07b433091\$lut for cells of type $lut. +Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut. +Using template $paramod$e00d03686849cf5e50e9f0c13f0f78958ff5e7ae\$lut for cells of type $lut. +Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. +Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut. +Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. +Using template $paramod$f71cd4e12d252829a6db80287a07ec7f20c3e099\$lut for cells of type $lut. +Using template $paramod$dae8f9b502bd1460fd180a1c0b20d573cb3bdfaa\$lut for cells of type $lut. +Using template $paramod$60e0a526d5120cb853aa823aea6dcb02645a9f39\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010010 for cells of type $lut. +Using template $paramod$348e2e3c2386524c4c07656cb22e89d0405fecdc\$lut for cells of type $lut. +Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005\$lut for cells of type $lut. +Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut. +Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. +Using template $paramod$9c7a967a5dd69d8b7070c7493295b0c7b420660f\$lut for cells of type $lut. +Using template $paramod$792289623e28f7bc3d64dc7e2dfa26bc7f05ab4b\$lut for cells of type $lut. +Using template $paramod$026ce654ad9d4d9bd0be5200be74a4e269c217d5\$lut for cells of type $lut. +Using template $paramod$24ca0390b3c7866a19922039474de91afb9e77c2\$lut for cells of type $lut. +Using template $paramod$066c8b79539c6cc144c5af6a60f411ebf4e1a8d9\$lut for cells of type $lut. +Using template $paramod$2a53f1f183bcacb7879917d65d33616d9ae625bd\$lut for cells of type $lut. +Using template $paramod$64e53fd3a6f1160fc572afc2acdd7c1e160cb372\$lut for cells of type $lut. +Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut. +Using template $paramod$8749993695cb7da49450e673823d6cab088c25d0\$lut for cells of type $lut. +Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. +Using template $paramod$3d7aaf571d14e064fbd16f4b1c68734d6cf34112\$lut for cells of type $lut. +Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. +Using template $paramod$0f321fbc35ab60cc9b1f13bcbf4423cb3e15af29\$lut for cells of type $lut. +Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. +Using template $paramod$e7aa2f1c351872cafc7a537c79b7ddbfb688eb74\$lut for cells of type $lut. +Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4\$lut for cells of type $lut. +Using template $paramod$6dbbd23ebc1f6c14e7875f941d268d34f7f03613\$lut for cells of type $lut. +Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut. +Using template $paramod$250e9ed6c15020113b6b30a5ef7c8f11f208ca8e\$lut for cells of type $lut. +Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut. +Using template $paramod$b4d49db958e100f96eebdc703313cdb7c6da2d30\$lut for cells of type $lut. +Using template $paramod$f5c118b1371bfc24986fe89a9f3e936c05edfbc3\$lut for cells of type $lut. +Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut. +Using template $paramod$12801c6c97a78eae361d6725b3f112db891faf26\$lut for cells of type $lut. +Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. +Using template $paramod$edfdd002d369b276282ba114ad80081aeb01c009\$lut for cells of type $lut. +Using template $paramod$6f20c26c0721e8b3757ca7b9a77b6e1d35f0f91c\$lut for cells of type $lut. +Using template $paramod$48ed08ac863093cb81be5bfb1a860b60659d37e0\$lut for cells of type $lut. +Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. +Using template $paramod$f045317e24613b3327ba32c229fc29aecd46a578\$lut for cells of type $lut. +Using template $paramod$afb8959a93937986ded51b1cddcab9e31c6ea2ed\$lut for cells of type $lut. +Using template $paramod$b8c12e9f20286ec99dd92b2fd58c920f7e7cec0f\$lut for cells of type $lut. +Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut. +Using template $paramod$f8276d8043930bc37fe6e7aece4838ca8cbbed88\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011110 for cells of type $lut. +Using template $paramod$5d9bdb7f5954011ff004758709112a4f3d3263f1\$lut for cells of type $lut. +Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. +Using template $paramod$39b3ba6c949a044323f4c3d176cbbb241f762ca2\$lut for cells of type $lut. +Using template $paramod$2ffdd48c31fd3abb3756c8ed29b2777c7dc5fa83\$lut for cells of type $lut. +Using template $paramod$cba63f0d3ee9d49c25aa31a3006491d02c8ce45c\$lut for cells of type $lut. +Using template $paramod$16709c7277a90cf041bff64ab2ca758c41bc27be\$lut for cells of type $lut. +Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. +Using template $paramod$15884c19b49d782a8abfd3de481c24e2addb4014\$lut for cells of type $lut. +Using template $paramod$31355df6e553d8cd6fcd0bf57a837c84b61d1970\$lut for cells of type $lut. +Using template $paramod$8ff12d04a511f1681452a4f5ee3c51dba9cfce88\$lut for cells of type $lut. +Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. +Using template $paramod$5a3c42a1f10797f72f7dc04a8b3d2a4bed295e15\$lut for cells of type $lut. +Using template $paramod$c980dd261d6fb09bc841af11d4475dbcab25c466\$lut for cells of type $lut. +Using template $paramod$eecb66b63ca1b933f7cd7fb6f0e7840fa51bb9cd\$lut for cells of type $lut. +Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. +Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. +Using template $paramod$cd39481dd3aba995896cce486ea250f3438a3533\$lut for cells of type $lut. +Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut. +Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70\$lut for cells of type $lut. +Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593\$lut for cells of type $lut. +Using template $paramod$45d35c067ded9854bad436d064758afc38659286\$lut for cells of type $lut. +Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd\$lut for cells of type $lut. +Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. +Using template $paramod$fae6ca420eabd44e6c9fdca31474d250778770c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. +Using template $paramod$92dc953d4569c20cd5765a3ce5567d53a74e7bab\$lut for cells of type $lut. +Using template $paramod$498a44c299976466f23c7e4de76f60e6cc568478\$lut for cells of type $lut. +Using template $paramod$f1c808a575959b8e5fe662725b574608671d76e5\$lut for cells of type $lut. +Using template $paramod$83f8a77a82b30303d0d950f0eb545c79a45eece4\$lut for cells of type $lut. +Using template $paramod$7b0d2a2ffb3b8f28d614fe2eb48a97cfa46f63f9\$lut for cells of type $lut. +Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut. +Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. +Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018\$lut for cells of type $lut. +Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. +Using template $paramod$246ec991bdd99746c8a8bc3d7793b764df6ed8d7\$lut for cells of type $lut. +Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. +Using template $paramod$a70047793dbc7d59dc2bc31d6c4f156b9e13dcbd\$lut for cells of type $lut. +Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. +Using template $paramod$f1e658ef767025439b6a062b79969dc402e1d2ab\$lut for cells of type $lut. +Using template $paramod$0ff46acca3c504a56e28cebb7c80b4cf6727f8cb\$lut for cells of type $lut. +Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. +Using template $paramod$a1eb35ff1d6419b0fc78314211740ca314e2d3e1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. +Using template $paramod$ef2e713cf94754a85372c7c4eece657b7521f115\$lut for cells of type $lut. +Using template $paramod$342895d61650d958a2336ec313ba396bdba7b36d\$lut for cells of type $lut. +Using template $paramod$ee454ad2383885733a4273245816698f8443c10b\$lut for cells of type $lut. +Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut. +Using template $paramod$afdefd64f115cbb578c1cd4bf8426ecfef85ae91\$lut for cells of type $lut. +Using template $paramod$ce57c8604805f80ab07a0434d106bb987e82ae6c\$lut for cells of type $lut. +Using template $paramod$7dc80f6db7113f8d3efb3affd3151d83c6b5c052\$lut for cells of type $lut. +Using template $paramod$c4e4e438f53deb14c1ad728c967e8024f686836f\$lut for cells of type $lut. +Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut. +Using template $paramod$f919e2eb4f0ec7b3a3ece075b1a81cd1886359a9\$lut for cells of type $lut. +Using template $paramod$28c1b4eb2d2d71f05d2260a615cda612ac87485b\$lut for cells of type $lut. +Using template $paramod$b1ad3aa394426898eee56afdd1a015c08b8ec3ca\$lut for cells of type $lut. +Using template $paramod$44adbaeba8aebac00b5b76c0c821287bd76a54f4\$lut for cells of type $lut. +Using template $paramod$8cd5a5f75f43fffe243164dff2e5d4f1454af19a\$lut for cells of type $lut. +Using template $paramod$242599a6dd1ccb968650e97e72150d00ebb8ccfc\$lut for cells of type $lut. +Using template $paramod$8ee9afdaea0539b1dd0f1adf915c5c609a483c46\$lut for cells of type $lut. +Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut. +Using template $paramod$849eede967b3c8935808391f1a9ce50503aa897a\$lut for cells of type $lut. +Using template $paramod$a511f425a16be7369933baa8c17a62ec61a7d7bf\$lut for cells of type $lut. +Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. +Using template $paramod$52fff9e56e72ea7ba0438be276221256c87f3756\$lut for cells of type $lut. +Using template $paramod$68fe50ee5a60a0bed36b1b1843c805d7bc807f41\$lut for cells of type $lut. +Using template $paramod$949912d41b6703327b37a3cbe8a7a7bc923219b7\$lut for cells of type $lut. +Using template $paramod$20ac3f9f2cd752a746ad32213f9c4f07fd5930ff\$lut for cells of type $lut. +Using template $paramod$d96938b933811903763c8fc48238ba3a4fe3fe61\$lut for cells of type $lut. +Using template $paramod$0f31dbbdcf77bf9799eaa7f2770f351711caa9d7\$lut for cells of type $lut. +Using template $paramod$a34a1094e2d314048608fde4d3073e1293d36b6f\$lut for cells of type $lut. +Using template $paramod$4cef79c5dcf504d402cc91e8e17ad287350b8594\$lut for cells of type $lut. +Using template $paramod$98c396e6f215a5928f903721dfd7ad31ae8269ff\$lut for cells of type $lut. +Using template $paramod$085ac6daadd555b0f8cf8f603c7849f876be6cbc\$lut for cells of type $lut. +Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut. +Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut. +Using template $paramod$67f667c8a3d1d844698cdb7b2f5a5deab3d9409a\$lut for cells of type $lut. +Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut. +Using template $paramod$7a09c632ebd39a203628a04507a2df81de3ade57\$lut for cells of type $lut. +Using template $paramod$04037df916e752dc482342577e8299341aae51a4\$lut for cells of type $lut. +Using template $paramod$cd6ddbad0e2d34a9a4c4738962cbc71837b95c56\$lut for cells of type $lut. +Using template $paramod$d80a3e34243dd01a86cdf267e33e3f33845e0abb\$lut for cells of type $lut. +Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. +Using template $paramod$ec0df19840033c8b18208b7471309a53c2b25de8\$lut for cells of type $lut. +Using template $paramod$106a0e61e3103f1a5ff0d32c1eb749cff02adb43\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. +Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut. +Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut. +Using template $paramod$d8f3c716f81512daaf4db8814134a1981792e8a8\$lut for cells of type $lut. +Using template $paramod$948f2992d65cd45de16107a58830a18abac36467\$lut for cells of type $lut. +Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut. +Using template $paramod$f6499a512b57be5fed724a1220dd8b76f9cb276b\$lut for cells of type $lut. +Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. +Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut. +Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut. +Using template $paramod$14480a541c7accf2d8a8c2b8f162e571e737174d\$lut for cells of type $lut. +Using template $paramod$b63d17d6a4aca2801204553b213c0505b1dcfa61\$lut for cells of type $lut. +Using template $paramod$67be80acf92b4861aed3d8085a5bb296f128f875\$lut for cells of type $lut. +Using template $paramod$028e503861792ef2faa7a49f86896b8c441bfd8d\$lut for cells of type $lut. +Using template $paramod$9eed22699c2653b52e395b92910215456ca209e1\$lut for cells of type $lut. +Using template $paramod$79432275bae6ba3c8cd1f392a278d15c8c6d8c77\$lut for cells of type $lut. +Using template $paramod$ea474c71a7a9bb027676021008daefb4ecbb4eb1\$lut for cells of type $lut. +Using template $paramod$b49c34751da1b37066c4dedc23af15b0caf21eff\$lut for cells of type $lut. +Using template $paramod$15d3dd50cc31557057274aea687fe2a8296cd155\$lut for cells of type $lut. +Using template $paramod$d7c634c964a868577f926c0690c937ab5b147f6e\$lut for cells of type $lut. +Using template $paramod$af0c0e3aea5daa768aac0697b02a2a49301800b1\$lut for cells of type $lut. +Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. +Using template $paramod$d9f23974f72a3ab437d1a63d2f34fd3483a6f58d\$lut for cells of type $lut. +Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut. +Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut. +Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076\$lut for cells of type $lut. +Using template $paramod$d62fc140c26bd45d16de3ebed6da0aa258adf691\$lut for cells of type $lut. +Using template $paramod$823cc3693c093331e82006c402f318cfda9e9960\$lut for cells of type $lut. +Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut. +Using template $paramod$889dc7b17c448030eaa05f5eb6c645a7ac00212c\$lut for cells of type $lut. +Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. +Using template $paramod$0d5e420ccfc2dddc13533c0817d1e17e68a2c136\$lut for cells of type $lut. +Using template $paramod$61e71a6b219041f218388451735d309581e08c5a\$lut for cells of type $lut. +Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut. +Using template $paramod$e13515ff50e27c9008f50b05a66e5bcc5bfc830a\$lut for cells of type $lut. +Using template $paramod$9bc8328e11fe3fccdf86fc34790ac24d79f83988\$lut for cells of type $lut. +Using template $paramod$03f612cf47cd227bbcfebe52575115af80c7c16c\$lut for cells of type $lut. +Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. +Using template $paramod$70d7bf515ac9884ee9b23e71bf77b47f76d185ef\$lut for cells of type $lut. +Using template $paramod$5fc7b8a2c522f6d2673f42cd967352990b6c7262\$lut for cells of type $lut. +Using template $paramod$9e3dc3fff64456e2f7592466fa8d9168932a933b\$lut for cells of type $lut. +Using template $paramod$89c0f9d0c35e6d27b98a949543dd6ffb685c8494\$lut for cells of type $lut. +Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut. +Using template $paramod$3c014941563a279228df79e25630751fec86819c\$lut for cells of type $lut. +Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. +Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut. +Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut. +Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut. +Using template $paramod$de4e6a7b8a15f6a5473e5f664954e687cc29a030\$lut for cells of type $lut. +Using template $paramod$f0f848e7cfbbc6be3de026782b732eac78406dea\$lut for cells of type $lut. +Using template $paramod$d96e26d600b7afaf2bc32e15f141020b276413e7\$lut for cells of type $lut. +Using template $paramod$368d87bdae2d7c7edd4471a7544662ae1a87a1e6\$lut for cells of type $lut. +Using template $paramod$5084523aff77b31b8ebe7370c66eee056a7dfa8d\$lut for cells of type $lut. +Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. +Using template $paramod$0425f46a1444788a7d60572c26dbde5e7cb29de0\$lut for cells of type $lut. +Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut. +Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut. +Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. +Using template $paramod$ea74080f8ebc8f3ea8275fd61051fa8e4bd0300d\$lut for cells of type $lut. +Using template $paramod$bccd6a49db7603b1feab5a542c51ed065a930da8\$lut for cells of type $lut. +Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. +Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. +Using template $paramod$b31dd1d80549ddba3254da46cdcb07cc4ccccfbe\$lut for cells of type $lut. +Using template $paramod$daf647bf6403143068eea8188cee93c3147be893\$lut for cells of type $lut. +Using template $paramod$8c23cdf2a4f29c3245c8b87835fc4980076df069\$lut for cells of type $lut. +Using template $paramod$35039c9689735d0b61f44caa3553cfd5a2fbb4b7\$lut for cells of type $lut. +Using template $paramod$eb762d00edf4fa32a2d134b034b0b70d5545798c\$lut for cells of type $lut. +Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut. +Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. +Using template $paramod$8a98d1c91d920b5f0ab2d9972c6d6a50d9b3c6a0\$lut for cells of type $lut. +Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. +Using template $paramod$d1d6b5f05bbc9409db63d690a4e859de80aaf468\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod$66e741791413519a466d4f44240bc83d3a191818\$lut for cells of type $lut. +Using template $paramod$2615c96857d1544911b5f413e145132efdb858f4\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. +Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$91cf3b8946a6c260321b0156c1a86ce6a2bf132f\$lut for cells of type $lut. +Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. +Using template $paramod$ba318f6d3458908ac57d56e5fa81a962ff2ab52b\$lut for cells of type $lut. +Using template $paramod$8543f2365289954cda2d9c99ae041aa434eda106\$lut for cells of type $lut. +Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut. +Using template $paramod$4bf055ca8a75a6b2e0a7cc21f3141b6576bbc879\$lut for cells of type $lut. +Using template $paramod$07138df23ef575563a02de1d610b812cf677ab4c\$lut for cells of type $lut. +Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut. +Using template $paramod$26582a7543f385ddf0816d466b3062a20d272771\$lut for cells of type $lut. +Using template $paramod$dd82bdb82a639de3374fa55b64e3421389be06aa\$lut for cells of type $lut. +Using template $paramod$e0592112fe4ea0fcfc3950f3065219da5f87f992\$lut for cells of type $lut. +Using template $paramod$21f957a7073b1ba634cad0df400394ca323de2fc\$lut for cells of type $lut. +Using template $paramod$1380a7bce1312c754eede24e3ccb152531be4f52\$lut for cells of type $lut. +Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83\$lut for cells of type $lut. +Using template $paramod$414fd3c1d97526aa52c17e578c5aaa0e6063335b\$lut for cells of type $lut. +Using template $paramod$482996866aebe48dc155049098c96180706e5d91\$lut for cells of type $lut. +Using template $paramod$5cbc08fcae16eb4ba45340fd09ba55fbeee8fd1b\$lut for cells of type $lut. +Using template $paramod$88433ebfb4d698fe0a845fd0a518078e0471ea2e\$lut for cells of type $lut. +Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. +Using template $paramod$464c0ecb5e74ffed195f4d7c313e6e3ea55be670\$lut for cells of type $lut. +Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. +Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut. +Using template $paramod$351521e8b01efeb144a39a20c4d973eb0b1643fa\$lut for cells of type $lut. +Using template $paramod$1607ccad58d340fc93ee9777e1a8e09981196091\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. +Using template $paramod$2bbec90035bea8ace991b30dd6d61930d1c61b49\$lut for cells of type $lut. +Using template $paramod$b01a883499671a5425bc39f21c1d1e0278d16ad5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. +Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. +Using template $paramod$ab5aa5e59731bfdc24344a9d76ddb6d9330c36d8\$lut for cells of type $lut. +Using template $paramod$cab646641d68cefe20d4670d8440ba9c72e8a81d\$lut for cells of type $lut. +Using template $paramod$02b64df0c401f8e2ba178158bc5ce7175355234e\$lut for cells of type $lut. +Using template $paramod$08ae2f8c57e504d818c187980b1ee5d5ef6b1a53\$lut for cells of type $lut. +Using template $paramod$d2e99342926657515eaf7de0e0d6e0ab51c92111\$lut for cells of type $lut. +Using template $paramod$dc2c6712e2363e0ec4d02acb1b3c7aca5011dab3\$lut for cells of type $lut. +Using template $paramod$b738327f68fe6bf1555d8b2ce106aa85e35a6229\$lut for cells of type $lut. +Using template $paramod$6477682786f5d5e7389f71b44247ccc2d8ce5e8a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000010 for cells of type $lut. +Using template $paramod$3cbede9dc45aa7c93c185b8b3fb81d9b642a0901\$lut for cells of type $lut. +Using template $paramod$5e3c6f6e85a59d8f346a84209f5467e2836bf075\$lut for cells of type $lut. +Using template $paramod$8d5f7407b13422c8618a39f6e856e3fba0266b3e\$lut for cells of type $lut. +Using template $paramod$756411e77af623de7df7b1d1a9d7ff92c0454cde\$lut for cells of type $lut. +Using template $paramod$c5dfd15977aff7866c1f09b915c247bca50db8d6\$lut for cells of type $lut. +Using template $paramod$63e7f8842b2dc57884e28c60d852ac2425249fe5\$lut for cells of type $lut. +Using template $paramod$36a4c79e9812e72b3f6507c9dad3f12c6810002b\$lut for cells of type $lut. +Using template $paramod$3a394e8383b9e427703b747b908e336d98ac94af\$lut for cells of type $lut. +Using template $paramod$c5d52721a6fa5fa0cd6921002a3db881c9ac6b2d\$lut for cells of type $lut. +Using template $paramod$c44e11032e98972888a9936a4d39d6c205c8401e\$lut for cells of type $lut. +Using template $paramod$4af6c2eac05ebe3ee05e3a43b6cf864989a9a4d3\$lut for cells of type $lut. +Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut. +Using template $paramod$be65c6dd49b2d5e0cfc5bbae2439c0c6399f66e9\$lut for cells of type $lut. +Using template $paramod$d7af698a9225f22318e3e0624744afe3ade563d2\$lut for cells of type $lut. +Using template $paramod$4ff816b87f3f349eb9fc7f927f77fe55d27f31db\$lut for cells of type $lut. +Using template $paramod$cb3b4bc8731dc6a330664b5559c44ae895962c70\$lut for cells of type $lut. +Using template $paramod$73c16989abb0b6227357c782c6da9786372b6d01\$lut for cells of type $lut. +Using template $paramod$694260564f5128262db3caa34951c3359318f936\$lut for cells of type $lut. +Using template $paramod$2adae487a6026f8719510df993658c524e9de1a6\$lut for cells of type $lut. +Using template $paramod$c6e922301decb6dd7dc97e85b89e30d1e96329e6\$lut for cells of type $lut. +Using template $paramod$20664e4f19b19b225c7d14483ea396530f4bb055\$lut for cells of type $lut. +Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999\$lut for cells of type $lut. +Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. +Using template $paramod$b71fae56e3eab939c22ce153c13d4d14b5267148\$lut for cells of type $lut. +Using template $paramod$59441c2b025f9a3bc4e5c2f53a4be4bc145aef49\$lut for cells of type $lut. +Using template $paramod$01d346930d9890fc7de6387e6db51bcc29b39c35\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. +Using template $paramod$b956a90e2f7ebac67c9d1d9c6aeb80f6d973e2e4\$lut for cells of type $lut. +No more expansions possible. + + +26.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in ulx3s_packet_top. + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$94980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$59984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$58946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35271.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35019.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$34605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276770.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$10965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$11009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$11027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$29240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$30210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$30232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$31060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$32137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$33712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$44214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$47576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$47633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$48540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$49956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$49969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$52758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$57478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$58721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$63009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63407.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$64002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$66557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$275068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$75268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$75442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$78625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$78629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$78647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$78658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$78675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$82429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$82461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$83451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$83465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$83560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84445.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$85547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$89566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$94984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$95018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$95026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$abc9_ops.cc:595:break_scc$297311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$60672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$275068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7932_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$58148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70205.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$70093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$71381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$78690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$75627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) +Removed 0 unused cells and 53858 unused wires. + +26.45. Executing AUTONAME pass. +Renamed 4810507 objects in module ulx3s_packet_top (720 iterations). + + +26.46. Executing HIERARCHY pass (managing design hierarchy). + +26.46.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top + +26.46.2. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Removed 0 unused modules. + +26.47. Printing statistics. + +=== ulx3s_packet_top === + + Number of wires: 26458 + Number of wire bits: 78079 + Number of public wires: 26458 + Number of public wire bits: 78079 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 39206 + CCU2C 785 + EHXPLLL 1 + L6MUX21 270 + LUT4 27175 + MULT18X18D 1 + PFUMX 3753 + TRELLIS_FF 7221 + +26.48. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +27. Executing JSON backend. + +Warnings: 4 unique messages, 8 total +End of script. Logfile hash: 8292a81ada, CPU: user 273.93s system 4.01s, MEM: 1873.43 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 21% 1x abc9_exe (76 sec), 17% 1x autoname (63 sec), ... diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/SHA256SUMS b/evidence/lsc1-09-cleanroom/clean-build-2/SHA256SUMS new file mode 100644 index 00000000..96118384 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/SHA256SUMS @@ -0,0 +1,3 @@ +226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e ulx3s_lsc1_packet.bit +0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b ulx3s_lsc1_packet.config +0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee ulx3s_lsc1_packet.svf diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/SOURCE_MANIFEST.txt b/evidence/lsc1-09-cleanroom/clean-build-2/SOURCE_MANIFEST.txt new file mode 100644 index 00000000..2bda79c1 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/SOURCE_MANIFEST.txt @@ -0,0 +1,28 @@ +=== SOURCE PROVENANCE === +revision: adc3e2c5b86fb08e1b0225573486ae08af4ac194 +inputs-match-revision: yes +d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 asic_core/rtl/gf128_mul_bitstream.sv +4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 asic_core/rtl/gf2n_mul_bitstream.sv +192eddc1727d8976ea48db9a532f44893d06bdec7651c65a1b1b99502b5e70c5 asic_core/rtl/lean_silicon_lsc1.sv +774b239a6221619559c57f0e00aad4000b507fd7c941dc9da204c1e357d6ad90 asic_core/rtl/lean_silicon_lsc1_mincore.sv +bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b asic_core/rtl/leanvm_b_stream_alu.sv +37a01a30bfa5dd52e05854ec4f9c0cb11c0959d95d610d0fb383e5fdd08af4f9 asic_core/rtl/lsc1_blake3_alias_check.sv +af51a2f56073aee7ef95c183e06d0e7c0e0613a0c7193d9f883ed26b026986a8 asic_core/rtl/lsc1_blake3_lifecycle.sv +d89d5cef0c529810a8a456892aaf13134e3b7ce34894f4c45da43ba81c7e066d asic_core/rtl/lsc1_cell_alias_check.sv +5fafb0f5fe81ac5aaf32d0d9974d7d7d2e2b66dde05cdb707e2067ab516f5e05 asic_core/rtl/lsc1_field_encoder.sv +bbf7b0d27ccfb371b45a5b9627f1eb10257056ac7c4b1ba3ca1be1bdbeadac4d asic_core/rtl/lsc1_packet_frontend.sv +311d30b3bfb4603c6b722183fd289a62cc48ccad72adb792100cfd435397cff3 asic_core/rtl/lsc1_packet_rx.sv +8a9a1c80b85fbeb253f955e618dc1521aff6fb432698c8bb5eef743e1eefcb2e asic_core/rtl/lsc1_packet_tx.sv +0d0cee24aea05b1a2ae2691a1cc46518af79b79e6228b8bb41031394c15b8d4f asic_core/rtl/lsc1_request_validator.sv +8adab68bd187db1d8fee337e6c4487304d4ad61f57d62d63ce1173bbe9ae1a2a asic_core/rtl/lsc1_response_payload_mux.sv +41b68a8068f417ff8f0d33f0408405f4fae5a7b5e2fd60b482d11148e541e6c7 asic_core/rtl/lsc1_stream_adapter.sv +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +5a4a26710548d8bc7908cbfc33d611fad6de8f825cf5585bc94aed9ae6cfb804 fpga/ulx3s/build_packet_uart.sh +31f67a30da28cd68594e3e84ee9b44af08759a57990312c20a09d7a950569c97 fpga/ulx3s/uart_bridge.sv +042f81e94f1e7e45ca810b85ca90e3d8f11fd5d670718ccd0ae65db33cfccaf1 fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 fpga/ulx3s/uart_tx.sv +0d0d1e9821163e7289883bca7b9e16e81fa454079e1942f198ed9688d30576f3 fpga/ulx3s/ulx3s_core_pll.sv +89cbe328d101570ec2c8e874f61134d6cd293c5b39c47e53f34cef0e56d9089a fpga/ulx3s/ulx3s_packet_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/build.stderr b/evidence/lsc1-09-cleanroom/clean-build-2/build.stderr new file mode 100644 index 00000000..e69de29b diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/build.stdout b/evidence/lsc1-09-cleanroom/clean-build-2/build.stdout new file mode 100644 index 00000000..dbfbd48e --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/build.stdout @@ -0,0 +1,44 @@ +=== TOOL VERSIONS (LSC-1 PACKET UART) === +Yosys 0.33 (git sha1 2584903a060) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.11.1) +Project Trellis ecppack Version 1.4-2build4 +date: 2026-09-06T00:58:29Z +=== SOURCE PROVENANCE === +revision: adc3e2c5b86fb08e1b0225573486ae08af4ac194 +inputs-match-revision: yes +d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 asic_core/rtl/gf128_mul_bitstream.sv +4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 asic_core/rtl/gf2n_mul_bitstream.sv +192eddc1727d8976ea48db9a532f44893d06bdec7651c65a1b1b99502b5e70c5 asic_core/rtl/lean_silicon_lsc1.sv +774b239a6221619559c57f0e00aad4000b507fd7c941dc9da204c1e357d6ad90 asic_core/rtl/lean_silicon_lsc1_mincore.sv +bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b asic_core/rtl/leanvm_b_stream_alu.sv +37a01a30bfa5dd52e05854ec4f9c0cb11c0959d95d610d0fb383e5fdd08af4f9 asic_core/rtl/lsc1_blake3_alias_check.sv +af51a2f56073aee7ef95c183e06d0e7c0e0613a0c7193d9f883ed26b026986a8 asic_core/rtl/lsc1_blake3_lifecycle.sv +d89d5cef0c529810a8a456892aaf13134e3b7ce34894f4c45da43ba81c7e066d asic_core/rtl/lsc1_cell_alias_check.sv +5fafb0f5fe81ac5aaf32d0d9974d7d7d2e2b66dde05cdb707e2067ab516f5e05 asic_core/rtl/lsc1_field_encoder.sv +bbf7b0d27ccfb371b45a5b9627f1eb10257056ac7c4b1ba3ca1be1bdbeadac4d asic_core/rtl/lsc1_packet_frontend.sv +311d30b3bfb4603c6b722183fd289a62cc48ccad72adb792100cfd435397cff3 asic_core/rtl/lsc1_packet_rx.sv +8a9a1c80b85fbeb253f955e618dc1521aff6fb432698c8bb5eef743e1eefcb2e asic_core/rtl/lsc1_packet_tx.sv +0d0cee24aea05b1a2ae2691a1cc46518af79b79e6228b8bb41031394c15b8d4f asic_core/rtl/lsc1_request_validator.sv +8adab68bd187db1d8fee337e6c4487304d4ad61f57d62d63ce1173bbe9ae1a2a asic_core/rtl/lsc1_response_payload_mux.sv +41b68a8068f417ff8f0d33f0408405f4fae5a7b5e2fd60b482d11148e541e6c7 asic_core/rtl/lsc1_stream_adapter.sv +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +5a4a26710548d8bc7908cbfc33d611fad6de8f825cf5585bc94aed9ae6cfb804 fpga/ulx3s/build_packet_uart.sh +31f67a30da28cd68594e3e84ee9b44af08759a57990312c20a09d7a950569c97 fpga/ulx3s/uart_bridge.sv +042f81e94f1e7e45ca810b85ca90e3d8f11fd5d670718ccd0ae65db33cfccaf1 fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 fpga/ulx3s/uart_tx.sv +0d0d1e9821163e7289883bca7b9e16e81fa454079e1942f198ed9688d30576f3 fpga/ulx3s/ulx3s_core_pll.sv +89cbe328d101570ec2c8e874f61134d6cd293c5b39c47e53f34cef0e56d9089a fpga/ulx3s/ulx3s_packet_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf +ulx3s_lsc1_packet.bit: OK +ulx3s_lsc1_packet.config: OK +ulx3s_lsc1_packet.svf: OK +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +bitstream: /tmp/lean-silicon-lsc1-repair.qocLpF/run-2/results/ulx3s-lsc1-packet-20260726/ulx3s_lsc1_packet.bit +sha256: 226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/ecppack.log b/evidence/lsc1-09-cleanroom/clean-build-2/ecppack.log new file mode 100644 index 00000000..e69de29b diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/nextpnr.log b/evidence/lsc1-09-cleanroom/clean-build-2/nextpnr.log new file mode 100644 index 00000000..f6953b05 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/nextpnr.log @@ -0,0 +1,3442 @@ +Info: constraining clock net 'clk' to 25.00 MHz + +Info: Logic utilisation before packing: +Info: Total LUT4s: 28745/83640 34% +Info: logic LUTs: 27175/83640 32% +Info: carry LUTs: 1570/83640 1% +Info: RAM LUTs: 0/10455 0% +Info: RAMW LUTs: 0/20910 0% + +Info: Total DFFs: 7221/83640 8% + +Info: Packing IOs.. +Info: pin 'uart_tx$tr_io' constrained to Bel 'X0/Y56/PIOC'. +Info: pin 'uart_rx$tr_io' constrained to Bel 'X0/Y89/PIOB'. +Info: pin 'led$tr_io' constrained to Bel 'X0/Y35/PIOC'. +Info: pin 'clk$tr_io' constrained to Bel 'X0/Y47/PIOA'. +Info: placed PLL 'core_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL' +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 5684 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Promoting globals... +Info: promoting clock net core_clk to global network +Info: Checksum: 0xa96ca5f1 + +Info: Device utilisation: +Info: TRELLIS_IO: 4/ 365 1% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 208 0% +Info: MULT18X18D: 1/ 156 0% +Info: ALU54B: 0/ 78 0% +Info: EHXPLLL: 1/ 4 25% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 224 0% +Info: SIOLOGIC: 0/ 141 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 14 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 7221/ 83640 8% +Info: TRELLIS_COMB: 29127/ 83640 34% +Info: TRELLIS_RAMW: 0/ 10455 0% + +Info: Running Static placer... +Info: ⌁ bel grid 127x96, placer grid 127x95... +Info: ⌁ initialising bels... +Info: ⌁ initialising cells... +Info: ⌁ inserting spacers... +Info: ⌁ group COMB pre-spacer utilisation 34.82% (target 70.00%) +Info: ⌁ group COMB inserted a total of 29420 spacers +Info: ⌁ group FF pre-spacer utilisation 8.63% (target 70.00%) +Info: ⌁ group FF inserted a total of 51326 spacers +Info: ⌁ group RAM pre-spacer utilisation 0.00% (target 70.00%) +Info: ⌁ group RAM inserted a total of 145 spacers +Info: ⌁ group MUL pre-spacer utilisation 0.64% (target 70.00%) +Info: ⌁ group MUL inserted a total of 108 spacers +Info: initial density penalty: 0.000025 +Info: coord_dist: 0.000621 grad_dist: 0.000244 +Info: initial steplen=0.010000 next steplen = 2.542392 +Info: coord_dist: 0.000621 grad_dist: 0.000244 +Info: iter=0 steplen=2.542392 a=1.000000 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.00 +Info: system potential: 8514805.000000 hpwl: 20096.478516 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: Strict legalising 7 cells... +Info: HPWL after legalise: 20224.486328 (delta: 128.007812) +Info: coord_dist: 0.157905 grad_dist: 0.066841 +Info: iter=1 steplen=2.362397 a=1.618034 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.40 +Info: system potential: 8582809.000000 hpwl: 13807.583984 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.075696 grad_dist: 0.039319 +Info: iter=2 steplen=1.925172 a=2.193527 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.60 +Info: system potential: 8598067.000000 hpwl: 10372.306641 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.054848 grad_dist: 0.034262 +Info: iter=3 steplen=1.600815 a=2.749791 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.79 +Info: system potential: 8605408.000000 hpwl: 8136.815430 +Info: overlap: COMB=99.7%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035386 grad_dist: 0.022816 +Info: iter=4 steplen=1.550963 a=3.294880 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 0.94 +Info: system potential: 8609257.000000 hpwl: 6795.866699 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021060 grad_dist: 0.012018 +Info: iter=5 steplen=1.752297 a=3.832601 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.07 +Info: system potential: 8606709.000000 hpwl: 5815.658203 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016144 grad_dist: 0.007474 +Info: iter=6 steplen=2.159947 a=4.365079 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.17 +Info: system potential: 8597473.000000 hpwl: 5038.107422 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016653 grad_dist: 0.008327 +Info: iter=7 steplen=1.999925 a=4.893622 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.27 +Info: system potential: 8589082.000000 hpwl: 4389.816406 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018115 grad_dist: 0.011364 +Info: iter=8 steplen=1.594051 a=5.419099 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.38 +Info: system potential: 8582088.000000 hpwl: 3739.517578 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016821 grad_dist: 0.011320 +Info: iter=9 steplen=1.485981 a=5.942117 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.48 +Info: system potential: 8577730.000000 hpwl: 3270.938721 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012070 grad_dist: 0.007600 +Info: iter=10 steplen=1.588207 a=6.463116 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.59 +Info: system potential: 8571819.000000 hpwl: 2953.775391 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008682 grad_dist: 0.004639 +Info: iter=11 steplen=1.871586 a=6.982428 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.70 +Info: system potential: 8567021.000000 hpwl: 2721.067383 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007932 grad_dist: 0.004161 +Info: iter=12 steplen=1.906472 a=7.500307 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.83 +Info: system potential: 8563001.000000 hpwl: 2531.046875 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008403 grad_dist: 0.005095 +Info: iter=13 steplen=1.649297 a=8.016954 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 1.95 +Info: system potential: 8561013.000000 hpwl: 2338.870605 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008331 grad_dist: 0.005430 +Info: iter=14 steplen=1.534174 a=8.532532 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.08 +Info: system potential: 8558900.000000 hpwl: 2181.093506 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006953 grad_dist: 0.004373 +Info: iter=15 steplen=1.589933 a=9.047169 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.20 +Info: system potential: 8556616.000000 hpwl: 2067.925293 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005590 grad_dist: 0.003171 +Info: iter=16 steplen=1.762770 a=9.560975 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.32 +Info: system potential: 8552007.000000 hpwl: 1983.437378 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005148 grad_dist: 0.002826 +Info: iter=17 steplen=1.821740 a=10.074040 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.43 +Info: system potential: 8549572.000000 hpwl: 1910.777222 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005337 grad_dist: 0.003162 +Info: iter=18 steplen=1.687788 a=10.586441 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.54 +Info: system potential: 8549344.000000 hpwl: 1835.611328 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005431 grad_dist: 0.003400 +Info: iter=19 steplen=1.597300 a=11.098242 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.65 +Info: system potential: 8546717.000000 hpwl: 1767.199219 +Info: overlap: COMB=99.8%, FF=99.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005018 grad_dist: 0.003089 +Info: iter=20 steplen=1.624351 a=11.609499 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.76 +Info: system potential: 8544092.000000 hpwl: 1716.198486 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004486 grad_dist: 0.002603 +Info: iter=21 steplen=1.723353 a=12.120261 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.88 +Info: system potential: 8544484.000000 hpwl: 1680.581421 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004293 grad_dist: 0.002436 +Info: iter=22 steplen=1.762445 a=12.630569 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 2.98 +Info: system potential: 8543948.000000 hpwl: 1653.231567 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004402 grad_dist: 0.002599 +Info: iter=23 steplen=1.693478 a=13.140462 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.10 +Info: system potential: 8541987.000000 hpwl: 1626.857300 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004483 grad_dist: 0.002743 +Info: iter=24 steplen=1.634380 a=13.649971 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.22 +Info: system potential: 8540601.000000 hpwl: 1602.899780 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004320 grad_dist: 0.002626 +Info: iter=25 steplen=1.645450 a=14.159125 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.34 +Info: system potential: 8536555.000000 hpwl: 1586.517334 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004065 grad_dist: 0.002393 +Info: iter=26 steplen=1.698927 a=14.667951 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.47 +Info: system potential: 8535830.000000 hpwl: 1575.769775 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003949 grad_dist: 0.002297 +Info: iter=27 steplen=1.719671 a=15.176470 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.58 +Info: system potential: 8535099.000000 hpwl: 1568.298950 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003982 grad_dist: 0.002365 +Info: iter=28 steplen=1.683457 a=15.684704 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.70 +Info: system potential: 8533242.000000 hpwl: 1559.154297 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004000 grad_dist: 0.002426 +Info: iter=29 steplen=1.648507 a=16.192673 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.82 +Info: system potential: 8532322.000000 hpwl: 1550.568970 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003890 grad_dist: 0.002355 +Info: iter=30 steplen=1.652200 a=16.700390 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 3.93 +Info: system potential: 8531519.000000 hpwl: 1543.876099 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003722 grad_dist: 0.002217 +Info: iter=31 steplen=1.679111 a=17.207872 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.05 +Info: system potential: 8529541.000000 hpwl: 1540.543945 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003612 grad_dist: 0.002139 +Info: iter=32 steplen=1.688514 a=17.715136 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.17 +Info: system potential: 8529077.000000 hpwl: 1538.243408 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003571 grad_dist: 0.002139 +Info: iter=33 steplen=1.669522 a=18.222191 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.28 +Info: system potential: 8529539.000000 hpwl: 1536.187500 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003521 grad_dist: 0.002133 +Info: iter=34 steplen=1.650666 a=18.729050 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.40 +Info: system potential: 8527445.000000 hpwl: 1534.105103 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003412 grad_dist: 0.002065 +Info: iter=35 steplen=1.652514 a=19.235723 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.51 +Info: system potential: 8526462.000000 hpwl: 1533.675049 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003276 grad_dist: 0.001966 +Info: iter=36 steplen=1.666453 a=19.742220 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.63 +Info: system potential: 8525433.000000 hpwl: 1534.347412 +Info: overlap: COMB=99.8%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003171 grad_dist: 0.001897 +Info: iter=37 steplen=1.671391 a=20.248550 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.76 +Info: system potential: 8526380.000000 hpwl: 1535.843140 +Info: overlap: COMB=99.7%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003102 grad_dist: 0.001866 +Info: iter=38 steplen=1.662205 a=20.754723 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.87 +Info: system potential: 8526406.000000 hpwl: 1537.221680 +Info: overlap: COMB=99.7%, FF=99.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003035 grad_dist: 0.001835 +Info: iter=39 steplen=1.653676 a=21.260744 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 4.99 +Info: system potential: 8526979.000000 hpwl: 1539.255981 +Info: overlap: COMB=99.7%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002948 grad_dist: 0.001780 +Info: iter=40 steplen=1.656143 a=21.766623 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.11 +Info: system potential: 8525591.000000 hpwl: 1542.428101 +Info: overlap: COMB=99.8%, FF=99.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002857 grad_dist: 0.001717 +Info: iter=41 steplen=1.664403 a=22.272364 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.23 +Info: system potential: 8525118.000000 hpwl: 1546.994385 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002788 grad_dist: 0.001672 +Info: iter=42 steplen=1.667891 a=22.777975 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.35 +Info: system potential: 8523290.000000 hpwl: 1552.597778 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002744 grad_dist: 0.001648 +Info: iter=43 steplen=1.665321 a=23.283461 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.47 +Info: system potential: 8522112.000000 hpwl: 1559.111572 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002709 grad_dist: 0.001628 +Info: iter=44 steplen=1.663431 a=23.788830 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.59 +Info: system potential: 8519849.000000 hpwl: 1566.114624 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002676 grad_dist: 0.001605 +Info: iter=45 steplen=1.667239 a=24.294085 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.72 +Info: system potential: 8518502.000000 hpwl: 1573.757080 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002653 grad_dist: 0.001585 +Info: iter=46 steplen=1.673540 a=24.799229 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.84 +Info: system potential: 8517161.000000 hpwl: 1581.522461 +Info: overlap: COMB=99.7%, FF=99.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002650 grad_dist: 0.001580 +Info: iter=47 steplen=1.677325 a=25.304270 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 5.96 +Info: system potential: 8515713.000000 hpwl: 1589.523926 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002668 grad_dist: 0.001590 +Info: iter=48 steplen=1.677365 a=25.809210 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.07 +Info: system potential: 8515972.000000 hpwl: 1597.237549 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002698 grad_dist: 0.001608 +Info: iter=49 steplen=1.677481 a=26.314053 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.20 +Info: system potential: 8513372.000000 hpwl: 1604.944458 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002735 grad_dist: 0.001628 +Info: iter=50 steplen=1.679927 a=26.818802 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.32 +Info: system potential: 8511293.000000 hpwl: 1612.398926 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002781 grad_dist: 0.001652 +Info: iter=51 steplen=1.683222 a=27.323462 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.44 +Info: system potential: 8509669.000000 hpwl: 1620.124268 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002840 grad_dist: 0.001686 +Info: iter=52 steplen=1.684606 a=27.828035 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.57 +Info: system potential: 8511234.000000 hpwl: 1627.488037 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002910 grad_dist: 0.001728 +Info: iter=53 steplen=1.684033 a=28.332527 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.69 +Info: system potential: 8512777.000000 hpwl: 1635.078369 +Info: overlap: COMB=99.7%, FF=99.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.002986 grad_dist: 0.001774 +Info: iter=54 steplen=1.683441 a=28.836939 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.81 +Info: system potential: 8514427.000000 hpwl: 1642.497925 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003064 grad_dist: 0.001820 +Info: iter=55 steplen=1.683243 a=29.341272 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 6.92 +Info: system potential: 8512579.000000 hpwl: 1650.272949 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003145 grad_dist: 0.001867 +Info: iter=56 steplen=1.684613 a=29.845533 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.04 +Info: system potential: 8509419.000000 hpwl: 1657.951294 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003232 grad_dist: 0.001918 +Info: iter=57 steplen=1.685404 a=30.349722 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.16 +Info: system potential: 8507435.000000 hpwl: 1665.997192 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003325 grad_dist: 0.001974 +Info: iter=58 steplen=1.684822 a=30.853840 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.29 +Info: system potential: 8507813.000000 hpwl: 1673.851807 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003423 grad_dist: 0.002033 +Info: iter=59 steplen=1.683768 a=31.357891 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.40 +Info: system potential: 8505955.000000 hpwl: 1681.950195 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003521 grad_dist: 0.002092 +Info: iter=60 steplen=1.683519 a=31.861877 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.52 +Info: system potential: 8502002.000000 hpwl: 1689.939331 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003620 grad_dist: 0.002150 +Info: iter=61 steplen=1.684048 a=32.365799 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.65 +Info: system potential: 8500115.000000 hpwl: 1698.280029 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003723 grad_dist: 0.002211 +Info: iter=62 steplen=1.684241 a=32.869659 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.76 +Info: system potential: 8498147.000000 hpwl: 1706.541870 +Info: overlap: COMB=99.7%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003830 grad_dist: 0.002275 +Info: iter=63 steplen=1.683796 a=33.373463 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 7.88 +Info: system potential: 8496199.000000 hpwl: 1715.107666 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.003940 grad_dist: 0.002341 +Info: iter=64 steplen=1.683232 a=33.877209 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.01 +Info: system potential: 8494107.000000 hpwl: 1723.658203 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004051 grad_dist: 0.002407 +Info: iter=65 steplen=1.683157 a=34.380898 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.11 +Info: system potential: 8492958.000000 hpwl: 1732.588257 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004165 grad_dist: 0.002474 +Info: iter=66 steplen=1.683469 a=34.884533 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.23 +Info: system potential: 8492325.000000 hpwl: 1741.576660 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004281 grad_dist: 0.002543 +Info: iter=67 steplen=1.683365 a=35.388115 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.36 +Info: system potential: 8486891.000000 hpwl: 1750.923218 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004401 grad_dist: 0.002615 +Info: iter=68 steplen=1.683104 a=35.891647 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.46 +Info: system potential: 8482260.000000 hpwl: 1760.320557 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004524 grad_dist: 0.002688 +Info: iter=69 steplen=1.683297 a=36.395130 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.58 +Info: system potential: 8479875.000000 hpwl: 1770.121704 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004651 grad_dist: 0.002762 +Info: iter=70 steplen=1.683671 a=36.898563 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.70 +Info: system potential: 8478173.000000 hpwl: 1780.125366 +Info: overlap: COMB=99.7%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004782 grad_dist: 0.002840 +Info: iter=71 steplen=1.683787 a=37.401951 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.81 +Info: system potential: 8472433.000000 hpwl: 1790.523926 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.004917 grad_dist: 0.002921 +Info: iter=72 steplen=1.683692 a=37.905293 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 8.93 +Info: system potential: 8467401.000000 hpwl: 1801.082397 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005057 grad_dist: 0.003003 +Info: iter=73 steplen=1.683696 a=38.408588 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.05 +Info: system potential: 8464948.000000 hpwl: 1812.117432 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005200 grad_dist: 0.003088 +Info: iter=74 steplen=1.683964 a=38.911842 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.16 +Info: system potential: 8463548.000000 hpwl: 1823.383911 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005347 grad_dist: 0.003174 +Info: iter=75 steplen=1.684380 a=39.415054 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.27 +Info: system potential: 8461371.000000 hpwl: 1835.103516 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005500 grad_dist: 0.003265 +Info: iter=76 steplen=1.684658 a=39.918224 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.38 +Info: system potential: 8461066.000000 hpwl: 1847.145142 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005658 grad_dist: 0.003358 +Info: iter=77 steplen=1.684687 a=40.421356 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.50 +Info: system potential: 8458474.000000 hpwl: 1859.591431 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005821 grad_dist: 0.003455 +Info: iter=78 steplen=1.684895 a=40.924446 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.61 +Info: system potential: 8456665.000000 hpwl: 1872.411865 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.005988 grad_dist: 0.003553 +Info: iter=79 steplen=1.685361 a=41.427502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.72 +Info: system potential: 8459255.000000 hpwl: 1885.696899 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006160 grad_dist: 0.003655 +Info: iter=80 steplen=1.685378 a=41.930519 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.83 +Info: system potential: 8456068.000000 hpwl: 1899.391968 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006340 grad_dist: 0.003760 +Info: iter=81 steplen=1.686169 a=42.433502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 9.95 +Info: system potential: 8454533.000000 hpwl: 1913.641479 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006526 grad_dist: 0.003868 +Info: iter=82 steplen=1.686917 a=42.936447 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.06 +Info: system potential: 8461490.000000 hpwl: 1928.404541 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006720 grad_dist: 0.003983 +Info: iter=83 steplen=1.687244 a=43.439358 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.17 +Info: system potential: 8463342.000000 hpwl: 1943.686646 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.006924 grad_dist: 0.004103 +Info: iter=84 steplen=1.687602 a=43.942234 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.28 +Info: system potential: 8471180.000000 hpwl: 1959.590698 +Info: overlap: COMB=99.6%, FF=99.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007133 grad_dist: 0.004226 +Info: iter=85 steplen=1.688087 a=44.445080 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.40 +Info: system potential: 8467627.000000 hpwl: 1976.066406 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007351 grad_dist: 0.004353 +Info: iter=86 steplen=1.688851 a=44.947891 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.51 +Info: system potential: 8464463.000000 hpwl: 1993.311646 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007578 grad_dist: 0.004485 +Info: iter=87 steplen=1.689589 a=45.450672 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.62 +Info: system potential: 8463951.000000 hpwl: 2011.174194 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.007815 grad_dist: 0.004624 +Info: iter=88 steplen=1.690159 a=45.953423 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.73 +Info: system potential: 8459463.000000 hpwl: 2029.907959 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008062 grad_dist: 0.004768 +Info: iter=89 steplen=1.690795 a=46.456142 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.85 +Info: system potential: 8454278.000000 hpwl: 2049.376465 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008318 grad_dist: 0.004918 +Info: iter=90 steplen=1.691517 a=46.958832 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 10.97 +Info: system potential: 8451459.000000 hpwl: 2069.900146 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008584 grad_dist: 0.005073 +Info: iter=91 steplen=1.692062 a=47.461494 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.08 +Info: system potential: 8448445.000000 hpwl: 2091.127441 +Info: overlap: COMB=99.6%, FF=99.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.008860 grad_dist: 0.005234 +Info: iter=92 steplen=1.692882 a=47.964130 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.20 +Info: system potential: 8445511.000000 hpwl: 2113.532227 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009148 grad_dist: 0.005400 +Info: iter=93 steplen=1.694047 a=48.466736 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.32 +Info: system potential: 8435234.000000 hpwl: 2136.761230 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009449 grad_dist: 0.005575 +Info: iter=94 steplen=1.694966 a=48.969315 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.43 +Info: system potential: 8430420.000000 hpwl: 2161.344971 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.009764 grad_dist: 0.005759 +Info: iter=95 steplen=1.695576 a=49.471867 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.56 +Info: system potential: 8420643.000000 hpwl: 2186.796875 +Info: overlap: COMB=99.6%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010091 grad_dist: 0.005949 +Info: iter=96 steplen=1.696301 a=49.974392 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.68 +Info: system potential: 8414419.000000 hpwl: 2213.828369 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010430 grad_dist: 0.006145 +Info: iter=97 steplen=1.697423 a=50.476894 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.80 +Info: system potential: 8395722.000000 hpwl: 2241.787842 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.010782 grad_dist: 0.006348 +Info: iter=98 steplen=1.698540 a=50.979370 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 11.93 +Info: system potential: 8379563.500000 hpwl: 2271.525635 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011149 grad_dist: 0.006560 +Info: iter=99 steplen=1.699444 a=51.481823 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.05 +Info: system potential: 8368260.500000 hpwl: 2302.227783 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011530 grad_dist: 0.006782 +Info: iter=100 steplen=1.700242 a=51.984253 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.17 +Info: system potential: 8352019.000000 hpwl: 2334.883545 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.011925 grad_dist: 0.007009 +Info: iter=101 steplen=1.701323 a=52.486656 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.30 +Info: system potential: 8343772.500000 hpwl: 2368.516357 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012328 grad_dist: 0.007244 +Info: iter=102 steplen=1.701805 a=52.989037 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.43 +Info: system potential: 8329875.000000 hpwl: 2404.383545 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.012748 grad_dist: 0.007484 +Info: iter=103 steplen=1.703336 a=53.491394 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.56 +Info: system potential: 8316487.000000 hpwl: 2441.320068 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.013181 grad_dist: 0.007731 +Info: iter=104 steplen=1.704924 a=53.993732 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.69 +Info: system potential: 8301330.500000 hpwl: 2480.910645 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.013634 grad_dist: 0.007992 +Info: iter=105 steplen=1.705991 a=54.496048 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.84 +Info: system potential: 8281380.000000 hpwl: 2521.450195 +Info: overlap: COMB=99.5%, FF=98.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.014106 grad_dist: 0.008265 +Info: iter=106 steplen=1.706677 a=54.998341 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 12.97 +Info: system potential: 8260743.000000 hpwl: 2564.805420 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.014588 grad_dist: 0.008543 +Info: iter=107 steplen=1.707478 a=55.500614 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.11 +Info: system potential: 8239633.500000 hpwl: 2608.909180 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.015077 grad_dist: 0.008825 +Info: iter=108 steplen=1.708554 a=56.002865 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.26 +Info: system potential: 8210766.000000 hpwl: 2656.306885 +Info: overlap: COMB=99.5%, FF=98.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.015578 grad_dist: 0.009111 +Info: iter=109 steplen=1.709830 a=56.505096 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.41 +Info: system potential: 8188782.000000 hpwl: 2704.452637 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016091 grad_dist: 0.009406 +Info: iter=110 steplen=1.710742 a=57.007309 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.56 +Info: system potential: 8165506.000000 hpwl: 2756.184570 +Info: overlap: COMB=99.4%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.016617 grad_dist: 0.009708 +Info: iter=111 steplen=1.711671 a=57.509502 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.71 +Info: system potential: 8138830.500000 hpwl: 2808.476807 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.017146 grad_dist: 0.010015 +Info: iter=112 steplen=1.712127 a=58.011677 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 13.88 +Info: system potential: 8107955.000000 hpwl: 2864.552490 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.017684 grad_dist: 0.010322 +Info: iter=113 steplen=1.713264 a=58.513832 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.05 +Info: system potential: 8077053.500000 hpwl: 2920.982178 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018228 grad_dist: 0.010630 +Info: iter=114 steplen=1.714753 a=59.015968 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.21 +Info: system potential: 8044288.000000 hpwl: 2981.765137 +Info: overlap: COMB=99.5%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.018786 grad_dist: 0.010948 +Info: iter=115 steplen=1.715950 a=59.518085 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.39 +Info: system potential: 8009852.500000 hpwl: 3042.644531 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.019357 grad_dist: 0.011276 +Info: iter=116 steplen=1.716622 a=60.020187 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.56 +Info: system potential: 7973161.000000 hpwl: 3107.905273 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.019937 grad_dist: 0.011608 +Info: iter=117 steplen=1.717462 a=60.522270 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.75 +Info: system potential: 7947153.000000 hpwl: 3173.127686 +Info: overlap: COMB=99.5%, FF=98.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.020518 grad_dist: 0.011939 +Info: iter=118 steplen=1.718579 a=61.024338 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 14.94 +Info: system potential: 7918307.500000 hpwl: 3243.307617 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021108 grad_dist: 0.012272 +Info: iter=119 steplen=1.720080 a=61.526386 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.15 +Info: system potential: 7881625.500000 hpwl: 3313.404297 +Info: overlap: COMB=99.5%, FF=98.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.021711 grad_dist: 0.012613 +Info: iter=120 steplen=1.721361 a=62.028416 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.35 +Info: system potential: 7848025.000000 hpwl: 3388.735596 +Info: overlap: COMB=99.4%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.022331 grad_dist: 0.012964 +Info: iter=121 steplen=1.722475 a=62.530430 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.56 +Info: system potential: 7819774.500000 hpwl: 3463.793213 +Info: overlap: COMB=99.4%, FF=98.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.022962 grad_dist: 0.013321 +Info: iter=122 steplen=1.723732 a=63.032429 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 15.77 +Info: system potential: 7803936.000000 hpwl: 3544.241943 +Info: overlap: COMB=99.4%, FF=98.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.023604 grad_dist: 0.013682 +Info: iter=123 steplen=1.725162 a=63.534412 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.00 +Info: system potential: 7772771.500000 hpwl: 3624.341553 +Info: overlap: COMB=99.4%, FF=98.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.024249 grad_dist: 0.014051 +Info: iter=124 steplen=1.725753 a=64.036377 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.23 +Info: system potential: 7734660.500000 hpwl: 3709.754883 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.024898 grad_dist: 0.014421 +Info: iter=125 steplen=1.726456 a=64.538330 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.47 +Info: system potential: 7683216.500000 hpwl: 3794.507812 +Info: overlap: COMB=99.4%, FF=98.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.025540 grad_dist: 0.014787 +Info: iter=126 steplen=1.727227 a=65.040268 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.71 +Info: system potential: 7622771.000000 hpwl: 3884.712158 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.026176 grad_dist: 0.015150 +Info: iter=127 steplen=1.727807 a=65.542191 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 16.95 +Info: system potential: 7560831.500000 hpwl: 3973.969727 +Info: overlap: COMB=99.3%, FF=98.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.026805 grad_dist: 0.015513 +Info: iter=128 steplen=1.727903 a=66.044098 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.20 +Info: system potential: 7504115.500000 hpwl: 4068.275879 +Info: overlap: COMB=99.4%, FF=98.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.027419 grad_dist: 0.015869 +Info: iter=129 steplen=1.727766 a=66.545990 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.46 +Info: system potential: 7448961.500000 hpwl: 4161.238770 +Info: overlap: COMB=99.4%, FF=98.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.028011 grad_dist: 0.016213 +Info: iter=130 steplen=1.727689 a=67.047867 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 17.73 +Info: system potential: 7388779.000000 hpwl: 4259.378906 +Info: overlap: COMB=99.3%, FF=98.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.028584 grad_dist: 0.016544 +Info: iter=131 steplen=1.727765 a=67.549728 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.02 +Info: system potential: 7322618.500000 hpwl: 4356.195801 +Info: overlap: COMB=99.3%, FF=98.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.029145 grad_dist: 0.016868 +Info: iter=132 steplen=1.727790 a=68.051582 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.31 +Info: system potential: 7250014.500000 hpwl: 4458.327148 +Info: overlap: COMB=99.3%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.029699 grad_dist: 0.017189 +Info: iter=133 steplen=1.727787 a=68.553421 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.62 +Info: system potential: 7182640.500000 hpwl: 4558.850098 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.030246 grad_dist: 0.017507 +Info: iter=134 steplen=1.727680 a=69.055244 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 18.94 +Info: system potential: 7119545.500000 hpwl: 4664.079590 +Info: overlap: COMB=99.3%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.030790 grad_dist: 0.017821 +Info: iter=135 steplen=1.727712 a=69.557053 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.27 +Info: system potential: 7064553.000000 hpwl: 4767.367676 +Info: overlap: COMB=99.3%, FF=98.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.031330 grad_dist: 0.018132 +Info: iter=136 steplen=1.727878 a=70.058853 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.62 +Info: system potential: 7001991.500000 hpwl: 4875.217285 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.031872 grad_dist: 0.018444 +Info: iter=137 steplen=1.728110 a=70.560638 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 19.97 +Info: system potential: 6946372.000000 hpwl: 4980.763184 +Info: overlap: COMB=99.2%, FF=97.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.032417 grad_dist: 0.018757 +Info: iter=138 steplen=1.728230 a=71.062408 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 20.33 +Info: system potential: 6880503.500000 hpwl: 5090.250977 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.032961 grad_dist: 0.019072 +Info: iter=139 steplen=1.728226 a=71.564163 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 20.70 +Info: system potential: 6823283.500000 hpwl: 5197.462402 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.033502 grad_dist: 0.019384 +Info: iter=140 steplen=1.728340 a=72.065910 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.10 +Info: system potential: 6767464.000000 hpwl: 5308.474121 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.034035 grad_dist: 0.019691 +Info: iter=141 steplen=1.728468 a=72.567650 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.49 +Info: system potential: 6714823.500000 hpwl: 5417.166504 +Info: overlap: COMB=99.2%, FF=97.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.034566 grad_dist: 0.019995 +Info: iter=142 steplen=1.728731 a=73.069374 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 21.89 +Info: system potential: 6667323.000000 hpwl: 5529.572266 +Info: overlap: COMB=99.1%, FF=97.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035097 grad_dist: 0.020297 +Info: iter=143 steplen=1.729220 a=73.571083 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 22.30 +Info: system potential: 6621768.500000 hpwl: 5640.035156 +Info: overlap: COMB=99.1%, FF=97.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.035635 grad_dist: 0.020601 +Info: iter=144 steplen=1.729806 a=74.072784 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 22.73 +Info: system potential: 6580090.000000 hpwl: 5754.417480 +Info: overlap: COMB=99.1%, FF=97.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.036181 grad_dist: 0.020911 +Info: iter=145 steplen=1.730254 a=74.574471 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 23.15 +Info: system potential: 6537505.000000 hpwl: 5866.941895 +Info: overlap: COMB=99.1%, FF=97.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.036738 grad_dist: 0.021226 +Info: iter=146 steplen=1.730841 a=75.076149 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 23.58 +Info: system potential: 6489350.500000 hpwl: 5983.432129 +Info: overlap: COMB=99.1%, FF=97.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.037302 grad_dist: 0.021543 +Info: iter=147 steplen=1.731514 a=75.577812 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.03 +Info: system potential: 6446750.000000 hpwl: 6098.070312 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.037880 grad_dist: 0.021866 +Info: iter=148 steplen=1.732381 a=76.079468 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.49 +Info: system potential: 6407622.500000 hpwl: 6216.986328 +Info: overlap: COMB=99.0%, FF=97.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.038470 grad_dist: 0.022197 +Info: iter=149 steplen=1.733097 a=76.581108 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 24.96 +Info: system potential: 6374991.000000 hpwl: 6333.979004 +Info: overlap: COMB=99.0%, FF=97.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.039079 grad_dist: 0.022538 +Info: iter=150 steplen=1.733952 a=77.082741 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 25.44 +Info: system potential: 6334709.500000 hpwl: 6455.270508 +Info: overlap: COMB=99.0%, FF=97.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.039702 grad_dist: 0.022886 +Info: iter=151 steplen=1.734775 a=77.584366 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 25.93 +Info: system potential: 6294619.000000 hpwl: 6574.238770 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.040343 grad_dist: 0.023243 +Info: iter=152 steplen=1.735721 a=78.085976 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 26.44 +Info: system potential: 6256852.500000 hpwl: 6698.014160 +Info: overlap: COMB=98.9%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.041001 grad_dist: 0.023611 +Info: iter=153 steplen=1.736511 a=78.587578 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 26.94 +Info: system potential: 6222937.500000 hpwl: 6819.216797 +Info: overlap: COMB=98.9%, FF=96.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.041680 grad_dist: 0.023989 +Info: iter=154 steplen=1.737449 a=79.089165 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 27.45 +Info: system potential: 6179733.000000 hpwl: 6945.390625 +Info: overlap: COMB=99.0%, FF=97.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.042376 grad_dist: 0.024378 +Info: iter=155 steplen=1.738280 a=79.590744 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 27.96 +Info: system potential: 6143025.000000 hpwl: 7068.854492 +Info: overlap: COMB=98.9%, FF=96.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.043095 grad_dist: 0.024779 +Info: iter=156 steplen=1.739177 a=80.092316 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 28.45 +Info: system potential: 6104339.000000 hpwl: 7197.405762 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.043833 grad_dist: 0.025193 +Info: iter=157 steplen=1.739931 a=80.593872 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 28.95 +Info: system potential: 6063214.000000 hpwl: 7322.881836 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.044597 grad_dist: 0.025618 +Info: iter=158 steplen=1.740822 a=81.095421 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 29.42 +Info: system potential: 6025433.500000 hpwl: 7453.872559 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.045379 grad_dist: 0.026057 +Info: iter=159 steplen=1.741497 a=81.596962 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 29.89 +Info: system potential: 5979945.500000 hpwl: 7581.052246 +Info: overlap: COMB=98.9%, FF=96.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.046188 grad_dist: 0.026509 +Info: iter=160 steplen=1.742310 a=82.098495 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 30.35 +Info: system potential: 5933397.000000 hpwl: 7714.185547 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.047012 grad_dist: 0.026974 +Info: iter=161 steplen=1.742875 a=82.600021 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 30.80 +Info: system potential: 5891555.000000 hpwl: 7842.596191 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.047859 grad_dist: 0.027448 +Info: iter=162 steplen=1.743618 a=83.101532 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 31.26 +Info: system potential: 5838790.500000 hpwl: 7977.649414 +Info: overlap: COMB=98.8%, FF=96.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.048721 grad_dist: 0.027931 +Info: iter=163 steplen=1.744336 a=83.603035 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 31.70 +Info: system potential: 5796730.000000 hpwl: 8107.588379 +Info: overlap: COMB=98.8%, FF=96.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.049605 grad_dist: 0.028424 +Info: iter=164 steplen=1.745140 a=84.104530 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 32.14 +Info: system potential: 5759914.000000 hpwl: 8244.602539 +Info: overlap: COMB=98.8%, FF=96.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.050506 grad_dist: 0.028930 +Info: iter=165 steplen=1.745823 a=84.606018 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 32.58 +Info: system potential: 5727264.000000 hpwl: 8376.832031 +Info: overlap: COMB=98.7%, FF=96.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.051435 grad_dist: 0.029444 +Info: iter=166 steplen=1.746841 a=85.107498 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.00 +Info: system potential: 5694033.000000 hpwl: 8517.190430 +Info: overlap: COMB=98.7%, FF=95.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.052384 grad_dist: 0.029971 +Info: iter=167 steplen=1.747802 a=85.608963 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.43 +Info: system potential: 5656227.000000 hpwl: 8653.161133 +Info: overlap: COMB=98.6%, FF=95.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.053368 grad_dist: 0.030515 +Info: iter=168 steplen=1.748915 a=86.110420 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 33.85 +Info: system potential: 5610102.000000 hpwl: 8798.030273 +Info: overlap: COMB=98.7%, FF=96.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.054376 grad_dist: 0.031075 +Info: iter=169 steplen=1.749844 a=86.611870 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 34.27 +Info: system potential: 5566582.500000 hpwl: 8939.132812 +Info: overlap: COMB=98.6%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.055417 grad_dist: 0.031648 +Info: iter=170 steplen=1.751015 a=87.113312 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 34.67 +Info: system potential: 5528910.500000 hpwl: 9089.878906 +Info: overlap: COMB=98.5%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.056475 grad_dist: 0.032234 +Info: iter=171 steplen=1.752036 a=87.614746 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.08 +Info: system potential: 5487287.500000 hpwl: 9238.583008 +Info: overlap: COMB=98.6%, FF=95.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.057571 grad_dist: 0.032833 +Info: iter=172 steplen=1.753436 a=88.116173 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.49 +Info: system potential: 5452114.000000 hpwl: 9397.672852 +Info: overlap: COMB=98.5%, FF=95.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.058690 grad_dist: 0.033450 +Info: iter=173 steplen=1.754552 a=88.617592 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 35.90 +Info: system potential: 5417467.000000 hpwl: 9555.486328 +Info: overlap: COMB=98.5%, FF=95.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.059850 grad_dist: 0.034090 +Info: iter=174 steplen=1.755666 a=89.119003 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 36.29 +Info: system potential: 5372263.000000 hpwl: 9722.668945 +Info: overlap: COMB=98.5%, FF=95.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.061029 grad_dist: 0.034747 +Info: iter=175 steplen=1.756348 a=89.620407 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 36.67 +Info: system potential: 5330796.500000 hpwl: 9888.072266 +Info: overlap: COMB=98.4%, FF=95.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.062227 grad_dist: 0.035414 +Info: iter=176 steplen=1.757111 a=90.121803 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.05 +Info: system potential: 5294574.500000 hpwl: 10061.114258 +Info: overlap: COMB=98.4%, FF=95.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.063421 grad_dist: 0.036081 +Info: iter=177 steplen=1.757726 a=90.623192 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.41 +Info: system potential: 5255217.000000 hpwl: 10233.398438 +Info: overlap: COMB=98.4%, FF=95.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.064624 grad_dist: 0.036747 +Info: iter=178 steplen=1.758630 a=91.124573 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 37.78 +Info: system potential: 5216764.500000 hpwl: 10411.831055 +Info: overlap: COMB=98.3%, FF=94.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.065823 grad_dist: 0.037414 +Info: iter=179 steplen=1.759302 a=91.625946 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.16 +Info: system potential: 5174847.000000 hpwl: 10589.868164 +Info: overlap: COMB=98.3%, FF=94.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.067031 grad_dist: 0.038084 +Info: iter=180 steplen=1.760081 a=92.127312 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.57 +Info: system potential: 5124769.000000 hpwl: 10772.805664 +Info: overlap: COMB=98.4%, FF=94.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.068225 grad_dist: 0.038751 +Info: iter=181 steplen=1.760603 a=92.628670 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 38.99 +Info: system potential: 5072445.500000 hpwl: 10955.675781 +Info: overlap: COMB=98.3%, FF=94.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.069412 grad_dist: 0.039409 +Info: iter=182 steplen=1.761324 a=93.130020 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 39.45 +Info: system potential: 5026487.000000 hpwl: 11142.213867 +Info: overlap: COMB=98.3%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.070575 grad_dist: 0.040055 +Info: iter=183 steplen=1.761982 a=93.631363 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 39.94 +Info: system potential: 4978157.000000 hpwl: 11328.912109 +Info: overlap: COMB=98.3%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.071738 grad_dist: 0.040692 +Info: iter=184 steplen=1.762969 a=94.132698 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 40.46 +Info: system potential: 4932299.500000 hpwl: 11518.359375 +Info: overlap: COMB=98.2%, FF=94.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.072892 grad_dist: 0.041327 +Info: iter=185 steplen=1.763776 a=94.634026 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 41.01 +Info: system potential: 4892566.000000 hpwl: 11708.231445 +Info: overlap: COMB=98.2%, FF=94.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.074055 grad_dist: 0.041963 +Info: iter=186 steplen=1.764766 a=95.135345 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 41.60 +Info: system potential: 4852654.000000 hpwl: 11900.305664 +Info: overlap: COMB=98.2%, FF=94.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.075215 grad_dist: 0.042597 +Info: iter=187 steplen=1.765712 a=95.636665 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 42.21 +Info: system potential: 4817535.000000 hpwl: 12092.366211 +Info: overlap: COMB=98.1%, FF=94.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.076383 grad_dist: 0.043230 +Info: iter=188 steplen=1.766891 a=96.137978 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 42.87 +Info: system potential: 4783562.500000 hpwl: 12286.185547 +Info: overlap: COMB=98.1%, FF=94.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.077553 grad_dist: 0.043864 +Info: iter=189 steplen=1.768039 a=96.639275 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 43.55 +Info: system potential: 4749353.000000 hpwl: 12479.855469 +Info: overlap: COMB=98.1%, FF=94.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.078742 grad_dist: 0.044503 +Info: iter=190 steplen=1.769377 a=97.140572 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 44.26 +Info: system potential: 4715383.500000 hpwl: 12675.065430 +Info: overlap: COMB=98.0%, FF=93.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.079939 grad_dist: 0.045147 +Info: iter=191 steplen=1.770627 a=97.641861 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 45.00 +Info: system potential: 4679545.500000 hpwl: 12870.277344 +Info: overlap: COMB=98.0%, FF=93.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.081154 grad_dist: 0.045798 +Info: iter=192 steplen=1.771991 a=98.143143 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 45.76 +Info: system potential: 4647268.000000 hpwl: 13066.356445 +Info: overlap: COMB=97.9%, FF=93.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.082375 grad_dist: 0.046454 +Info: iter=193 steplen=1.773251 a=98.644417 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 46.53 +Info: system potential: 4612301.500000 hpwl: 13262.174805 +Info: overlap: COMB=97.9%, FF=93.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.083614 grad_dist: 0.047116 +Info: iter=194 steplen=1.774641 a=99.145683 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 47.34 +Info: system potential: 4580488.500000 hpwl: 13458.455078 +Info: overlap: COMB=97.9%, FF=93.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.084859 grad_dist: 0.047785 +Info: iter=195 steplen=1.775870 a=99.646942 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 48.14 +Info: system potential: 4545085.500000 hpwl: 13655.028320 +Info: overlap: COMB=97.8%, FF=93.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086123 grad_dist: 0.048462 +Info: iter=196 steplen=1.777140 a=100.148193 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 48.96 +Info: system potential: 4510969.000000 hpwl: 13851.360352 +Info: overlap: COMB=97.8%, FF=93.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.087392 grad_dist: 0.049143 +Info: iter=197 steplen=1.778311 a=100.649437 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 49.79 +Info: system potential: 4474014.000000 hpwl: 14047.770508 +Info: overlap: COMB=97.8%, FF=93.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088673 grad_dist: 0.049826 +Info: iter=198 steplen=1.779654 a=101.150681 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 50.63 +Info: system potential: 4442674.500000 hpwl: 14243.244141 +Info: overlap: COMB=97.8%, FF=93.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.089956 grad_dist: 0.050513 +Info: iter=199 steplen=1.780867 a=101.651917 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 51.45 +Info: system potential: 4409180.500000 hpwl: 14438.568359 +Info: overlap: COMB=97.7%, FF=92.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.091259 grad_dist: 0.051205 +Info: iter=200 steplen=1.782236 a=102.153145 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 52.29 +Info: system potential: 4376227.000000 hpwl: 14632.612305 +Info: overlap: COMB=97.7%, FF=92.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.092570 grad_dist: 0.051903 +Info: iter=201 steplen=1.783529 a=102.654366 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 53.11 +Info: system potential: 4341388.500000 hpwl: 14826.385742 +Info: overlap: COMB=97.7%, FF=92.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.093900 grad_dist: 0.052610 +Info: iter=202 steplen=1.784847 a=103.155586 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 53.92 +Info: system potential: 4301986.000000 hpwl: 15018.722656 +Info: overlap: COMB=97.6%, FF=92.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.095240 grad_dist: 0.053321 +Info: iter=203 steplen=1.786157 a=103.656799 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 54.73 +Info: system potential: 4263971.500000 hpwl: 15212.285156 +Info: overlap: COMB=97.6%, FF=92.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.096586 grad_dist: 0.054037 +Info: iter=204 steplen=1.787426 a=104.158005 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 55.55 +Info: system potential: 4224621.000000 hpwl: 15404.966797 +Info: overlap: COMB=97.6%, FF=92.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.097932 grad_dist: 0.054751 +Info: iter=205 steplen=1.788669 a=104.659203 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 56.35 +Info: system potential: 4191258.000000 hpwl: 15599.207031 +Info: overlap: COMB=97.6%, FF=92.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099280 grad_dist: 0.055460 +Info: iter=206 steplen=1.790098 a=105.160400 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 57.16 +Info: system potential: 4161082.000000 hpwl: 15793.301758 +Info: overlap: COMB=97.5%, FF=92.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.100630 grad_dist: 0.056167 +Info: iter=207 steplen=1.791609 a=105.661591 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 57.95 +Info: system potential: 4130626.250000 hpwl: 15989.558594 +Info: overlap: COMB=97.4%, FF=91.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.101993 grad_dist: 0.056880 +Info: iter=208 steplen=1.793143 a=106.162773 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 58.75 +Info: system potential: 4095690.750000 hpwl: 16186.119141 +Info: overlap: COMB=97.4%, FF=91.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.103365 grad_dist: 0.057598 +Info: iter=209 steplen=1.794572 a=106.663948 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 59.53 +Info: system potential: 4064890.750000 hpwl: 16385.292969 +Info: overlap: COMB=97.4%, FF=92.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.104738 grad_dist: 0.058316 +Info: iter=210 steplen=1.796050 a=107.165123 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 60.32 +Info: system potential: 4028955.000000 hpwl: 16584.988281 +Info: overlap: COMB=97.3%, FF=91.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106103 grad_dist: 0.059026 +Info: iter=211 steplen=1.797568 a=107.666290 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 61.09 +Info: system potential: 3989928.000000 hpwl: 16788.468750 +Info: overlap: COMB=97.3%, FF=91.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.107463 grad_dist: 0.059731 +Info: iter=212 steplen=1.799129 a=108.167450 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 61.87 +Info: system potential: 3953746.500000 hpwl: 16992.027344 +Info: overlap: COMB=97.2%, FF=91.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.108816 grad_dist: 0.060432 +Info: iter=213 steplen=1.800616 a=108.668602 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 62.64 +Info: system potential: 3918786.750000 hpwl: 17199.271484 +Info: overlap: COMB=97.1%, FF=91.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110162 grad_dist: 0.061128 +Info: iter=214 steplen=1.802154 a=109.169754 penalty=[0.00, 0.00, 0.00, 0.00] +Info: update_chains distance 63.44 +Info: system potential: 3884546.500000 hpwl: 17406.363281 +Info: overlap: COMB=97.0%, FF=91.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.111493 grad_dist: 0.061815 +Info: iter=215 steplen=1.803648 a=109.670898 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 64.22 +Info: system potential: 3852372.000000 hpwl: 17617.705078 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.112814 grad_dist: 0.062495 +Info: iter=216 steplen=1.805166 a=110.172035 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 65.03 +Info: system potential: 3820459.750000 hpwl: 17828.677734 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114119 grad_dist: 0.063168 +Info: iter=217 steplen=1.806606 a=110.673164 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 65.84 +Info: system potential: 3788681.500000 hpwl: 18043.574219 +Info: overlap: COMB=96.9%, FF=90.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.115413 grad_dist: 0.063833 +Info: iter=218 steplen=1.808050 a=111.174294 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 66.68 +Info: system potential: 3757345.500000 hpwl: 18258.994141 +Info: overlap: COMB=96.9%, FF=90.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.116685 grad_dist: 0.064490 +Info: iter=219 steplen=1.809337 a=111.675415 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 67.51 +Info: system potential: 3725131.500000 hpwl: 18477.525391 +Info: overlap: COMB=96.9%, FF=90.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.117941 grad_dist: 0.065139 +Info: iter=220 steplen=1.810611 a=112.176537 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 68.38 +Info: system potential: 3693135.500000 hpwl: 18697.146484 +Info: overlap: COMB=96.9%, FF=90.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.119168 grad_dist: 0.065776 +Info: iter=221 steplen=1.811729 a=112.677650 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 69.24 +Info: system potential: 3656854.750000 hpwl: 18918.423828 +Info: overlap: COMB=96.7%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.120374 grad_dist: 0.066400 +Info: iter=222 steplen=1.812859 a=113.178757 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 70.14 +Info: system potential: 3628093.250000 hpwl: 19142.156250 +Info: overlap: COMB=96.6%, FF=90.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.121543 grad_dist: 0.067009 +Info: iter=223 steplen=1.813817 a=113.679863 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 71.05 +Info: system potential: 3594067.250000 hpwl: 19366.810547 +Info: overlap: COMB=96.6%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.122686 grad_dist: 0.067601 +Info: iter=224 steplen=1.814853 a=114.180962 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 72.01 +Info: system potential: 3559474.750000 hpwl: 19594.535156 +Info: overlap: COMB=96.6%, FF=90.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.123788 grad_dist: 0.068174 +Info: iter=225 steplen=1.815769 a=114.682053 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 72.98 +Info: system potential: 3528440.500000 hpwl: 19822.343750 +Info: overlap: COMB=96.5%, FF=89.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.124856 grad_dist: 0.068728 +Info: iter=226 steplen=1.816655 a=115.183144 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 74.01 +Info: system potential: 3492570.250000 hpwl: 20053.828125 +Info: overlap: COMB=96.4%, FF=89.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.125878 grad_dist: 0.069258 +Info: iter=227 steplen=1.817527 a=115.684227 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 75.03 +Info: system potential: 3461786.750000 hpwl: 20284.755859 +Info: overlap: COMB=96.3%, FF=89.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126857 grad_dist: 0.069762 +Info: iter=228 steplen=1.818442 a=116.185310 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 76.11 +Info: system potential: 3429086.250000 hpwl: 20519.091797 +Info: overlap: COMB=96.3%, FF=89.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.127790 grad_dist: 0.070241 +Info: iter=229 steplen=1.819309 a=116.686386 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 77.16 +Info: system potential: 3398440.000000 hpwl: 20752.310547 +Info: overlap: COMB=96.4%, FF=88.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.128683 grad_dist: 0.070695 +Info: iter=230 steplen=1.820247 a=117.187462 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 78.28 +Info: system potential: 3364164.500000 hpwl: 20988.890625 +Info: overlap: COMB=96.3%, FF=88.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.129525 grad_dist: 0.071124 +Info: iter=231 steplen=1.821115 a=117.688530 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 79.38 +Info: system potential: 3334479.250000 hpwl: 21224.595703 +Info: overlap: COMB=96.3%, FF=88.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130321 grad_dist: 0.071526 +Info: iter=232 steplen=1.822006 a=118.189590 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 80.53 +Info: system potential: 3301195.250000 hpwl: 21463.806641 +Info: overlap: COMB=96.2%, FF=88.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131060 grad_dist: 0.071899 +Info: iter=233 steplen=1.822828 a=118.690651 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 81.66 +Info: system potential: 3268614.750000 hpwl: 21702.332031 +Info: overlap: COMB=96.1%, FF=87.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131747 grad_dist: 0.072243 +Info: iter=234 steplen=1.823666 a=119.191704 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 82.85 +Info: system potential: 3246746.250000 hpwl: 21944.130859 +Info: overlap: COMB=95.9%, FF=87.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132371 grad_dist: 0.072557 +Info: iter=235 steplen=1.824372 a=119.692749 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 84.01 +Info: system potential: 3216556.250000 hpwl: 22185.050781 +Info: overlap: COMB=95.9%, FF=87.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132947 grad_dist: 0.072840 +Info: iter=236 steplen=1.825202 a=120.193794 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 85.23 +Info: system potential: 3185128.500000 hpwl: 22430.900391 +Info: overlap: COMB=95.7%, FF=87.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133457 grad_dist: 0.073096 +Info: iter=237 steplen=1.825780 a=120.694832 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 86.40 +Info: system potential: 3153969.250000 hpwl: 22675.060547 +Info: overlap: COMB=95.6%, FF=87.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133913 grad_dist: 0.073325 +Info: iter=238 steplen=1.826284 a=121.195869 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 87.63 +Info: system potential: 3115736.750000 hpwl: 22925.292969 +Info: overlap: COMB=95.6%, FF=87.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134288 grad_dist: 0.073516 +Info: iter=239 steplen=1.826633 a=121.696899 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 88.81 +Info: system potential: 3086980.000000 hpwl: 23173.066406 +Info: overlap: COMB=95.6%, FF=87.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134584 grad_dist: 0.073667 +Info: iter=240 steplen=1.826935 a=122.197929 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 90.06 +Info: system potential: 3058013.750000 hpwl: 23427.605469 +Info: overlap: COMB=95.5%, FF=86.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134796 grad_dist: 0.073777 +Info: iter=241 steplen=1.827082 a=122.698952 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 91.27 +Info: system potential: 3030148.750000 hpwl: 23679.279297 +Info: overlap: COMB=95.6%, FF=86.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134935 grad_dist: 0.073847 +Info: iter=242 steplen=1.827222 a=123.199974 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 92.54 +Info: system potential: 3009162.250000 hpwl: 23939.556641 +Info: overlap: COMB=95.5%, FF=85.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134989 grad_dist: 0.073879 +Info: iter=243 steplen=1.827168 a=123.700989 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 93.77 +Info: system potential: 2981113.750000 hpwl: 24195.367188 +Info: overlap: COMB=95.4%, FF=85.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134974 grad_dist: 0.073870 +Info: iter=244 steplen=1.827181 a=124.201996 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 95.08 +Info: system potential: 2953028.500000 hpwl: 24461.812500 +Info: overlap: COMB=95.3%, FF=85.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134868 grad_dist: 0.073822 +Info: iter=245 steplen=1.826923 a=124.703003 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 96.35 +Info: system potential: 2927574.000000 hpwl: 24721.267578 +Info: overlap: COMB=95.0%, FF=85.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134684 grad_dist: 0.073733 +Info: iter=246 steplen=1.826634 a=125.204002 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 97.71 +Info: system potential: 2899663.000000 hpwl: 24993.507812 +Info: overlap: COMB=95.0%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134399 grad_dist: 0.073593 +Info: iter=247 steplen=1.826247 a=125.705002 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 99.04 +Info: system potential: 2867884.750000 hpwl: 25257.064453 +Info: overlap: COMB=94.9%, FF=85.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134023 grad_dist: 0.073402 +Info: iter=248 steplen=1.825880 a=126.205994 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 100.47 +Info: system potential: 2839718.250000 hpwl: 25536.142578 +Info: overlap: COMB=94.9%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.133545 grad_dist: 0.073163 +Info: iter=249 steplen=1.825295 a=126.706985 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 101.87 +Info: system potential: 2813498.250000 hpwl: 25805.027344 +Info: overlap: COMB=94.9%, FF=85.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132975 grad_dist: 0.072874 +Info: iter=250 steplen=1.824735 a=127.207970 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 103.38 +Info: system potential: 2787680.250000 hpwl: 26091.232422 +Info: overlap: COMB=94.9%, FF=85.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.132298 grad_dist: 0.072530 +Info: iter=251 steplen=1.824056 a=127.708954 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 104.85 +Info: system potential: 2757824.250000 hpwl: 26365.931641 +Info: overlap: COMB=94.8%, FF=85.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.131533 grad_dist: 0.072135 +Info: iter=252 steplen=1.823427 a=128.209930 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 106.40 +Info: system potential: 2725088.500000 hpwl: 26660.105469 +Info: overlap: COMB=94.6%, FF=84.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130661 grad_dist: 0.071695 +Info: iter=253 steplen=1.822443 a=128.710907 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 107.88 +Info: system potential: 2697391.500000 hpwl: 26940.792969 +Info: overlap: COMB=94.4%, FF=84.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.129690 grad_dist: 0.071206 +Info: iter=254 steplen=1.821338 a=129.211884 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 109.44 +Info: system potential: 2675123.500000 hpwl: 27242.322266 +Info: overlap: COMB=94.4%, FF=83.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.128599 grad_dist: 0.070654 +Info: iter=255 steplen=1.820114 a=129.712845 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 110.93 +Info: system potential: 2653252.500000 hpwl: 27530.800781 +Info: overlap: COMB=94.3%, FF=82.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.127415 grad_dist: 0.070046 +Info: iter=256 steplen=1.819010 a=130.213806 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 112.50 +Info: system potential: 2625045.250000 hpwl: 27842.980469 +Info: overlap: COMB=94.2%, FF=83.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126139 grad_dist: 0.069400 +Info: iter=257 steplen=1.817559 a=130.714767 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 114.02 +Info: system potential: 2598766.250000 hpwl: 28140.531250 +Info: overlap: COMB=94.2%, FF=83.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.124786 grad_dist: 0.068720 +Info: iter=258 steplen=1.815862 a=131.215714 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 115.62 +Info: system potential: 2568909.250000 hpwl: 28463.080078 +Info: overlap: COMB=94.0%, FF=82.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.123325 grad_dist: 0.067986 +Info: iter=259 steplen=1.813973 a=131.716660 penalty=[0.01, 0.01, 0.01, 0.01] +Info: update_chains distance 117.19 +Info: system potential: 2537531.000000 hpwl: 28769.453125 +Info: overlap: COMB=94.0%, FF=82.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.121755 grad_dist: 0.067190 +Info: iter=260 steplen=1.812117 a=132.217606 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 118.86 +Info: system potential: 2512710.500000 hpwl: 29102.195312 +Info: overlap: COMB=93.7%, FF=82.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.120073 grad_dist: 0.066335 +Info: iter=261 steplen=1.810103 a=132.718552 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 120.50 +Info: system potential: 2492911.000000 hpwl: 29416.316406 +Info: overlap: COMB=93.6%, FF=81.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.118310 grad_dist: 0.065429 +Info: iter=262 steplen=1.808219 a=133.219498 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 122.25 +Info: system potential: 2468728.250000 hpwl: 29756.978516 +Info: overlap: COMB=93.4%, FF=81.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.116471 grad_dist: 0.064478 +Info: iter=263 steplen=1.806364 a=133.720428 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 123.97 +Info: system potential: 2441460.500000 hpwl: 30078.949219 +Info: overlap: COMB=93.3%, FF=80.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114568 grad_dist: 0.063494 +Info: iter=264 steplen=1.804383 a=134.221359 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 125.78 +Info: system potential: 2413471.000000 hpwl: 30426.777344 +Info: overlap: COMB=93.3%, FF=80.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.112601 grad_dist: 0.062476 +Info: iter=265 steplen=1.802306 a=134.722290 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 127.53 +Info: system potential: 2386902.000000 hpwl: 30756.544922 +Info: overlap: COMB=93.3%, FF=80.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110568 grad_dist: 0.061418 +Info: iter=266 steplen=1.800251 a=135.223221 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 129.36 +Info: system potential: 2361020.500000 hpwl: 31109.386719 +Info: overlap: COMB=93.1%, FF=80.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.108474 grad_dist: 0.060322 +Info: iter=267 steplen=1.798242 a=135.724152 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 131.13 +Info: system potential: 2336535.500000 hpwl: 31447.740234 +Info: overlap: COMB=93.1%, FF=80.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106344 grad_dist: 0.059201 +Info: iter=268 steplen=1.796335 a=136.225067 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 132.96 +Info: system potential: 2313116.000000 hpwl: 31806.652344 +Info: overlap: COMB=92.8%, FF=79.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.104199 grad_dist: 0.058068 +Info: iter=269 steplen=1.794423 a=136.725983 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 134.74 +Info: system potential: 2288399.250000 hpwl: 32153.570312 +Info: overlap: COMB=92.6%, FF=79.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.102067 grad_dist: 0.056935 +Info: iter=270 steplen=1.792675 a=137.226898 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 136.59 +Info: system potential: 2262210.000000 hpwl: 32519.486328 +Info: overlap: COMB=92.5%, FF=79.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099951 grad_dist: 0.055810 +Info: iter=271 steplen=1.790908 a=137.727798 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 138.41 +Info: system potential: 2236369.500000 hpwl: 32875.203125 +Info: overlap: COMB=92.3%, FF=79.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.097881 grad_dist: 0.054700 +Info: iter=272 steplen=1.789409 a=138.228714 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 140.30 +Info: system potential: 2210155.500000 hpwl: 33248.867188 +Info: overlap: COMB=92.1%, FF=78.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.095867 grad_dist: 0.053612 +Info: iter=273 steplen=1.788166 a=138.729614 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 142.17 +Info: system potential: 2184050.750000 hpwl: 33613.546875 +Info: overlap: COMB=92.1%, FF=78.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.093942 grad_dist: 0.052559 +Info: iter=274 steplen=1.787376 a=139.230515 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 144.08 +Info: system potential: 2157209.500000 hpwl: 33995.226562 +Info: overlap: COMB=92.1%, FF=78.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.092127 grad_dist: 0.051558 +Info: iter=275 steplen=1.786858 a=139.731415 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 145.94 +Info: system potential: 2134231.500000 hpwl: 34369.488281 +Info: overlap: COMB=91.8%, FF=77.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.090470 grad_dist: 0.050626 +Info: iter=276 steplen=1.787026 a=140.232315 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 147.87 +Info: system potential: 2104992.750000 hpwl: 34760.445312 +Info: overlap: COMB=91.6%, FF=77.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088998 grad_dist: 0.049784 +Info: iter=277 steplen=1.787693 a=140.733200 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 149.74 +Info: system potential: 2079202.000000 hpwl: 35146.277344 +Info: overlap: COMB=91.4%, FF=76.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.087762 grad_dist: 0.049059 +Info: iter=278 steplen=1.788913 a=141.234085 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 151.65 +Info: system potential: 2053050.250000 hpwl: 35546.171875 +Info: overlap: COMB=91.2%, FF=76.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086790 grad_dist: 0.048471 +Info: iter=279 steplen=1.790570 a=141.734970 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 153.52 +Info: system potential: 2022814.000000 hpwl: 35944.484375 +Info: overlap: COMB=91.3%, FF=76.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086110 grad_dist: 0.048031 +Info: iter=280 steplen=1.792801 a=142.235855 penalty=[0.02, 0.02, 0.02, 0.02] +Info: update_chains distance 155.47 +Info: system potential: 1995800.125000 hpwl: 36355.667969 +Info: overlap: COMB=91.1%, FF=76.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.085749 grad_dist: 0.047751 +Info: iter=281 steplen=1.795767 a=142.736740 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 157.42 +Info: system potential: 1969756.375000 hpwl: 36766.609375 +Info: overlap: COMB=90.8%, FF=75.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.085747 grad_dist: 0.047650 +Info: iter=282 steplen=1.799525 a=143.237610 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 159.47 +Info: system potential: 1945184.125000 hpwl: 37191.394531 +Info: overlap: COMB=90.7%, FF=75.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086138 grad_dist: 0.047751 +Info: iter=283 steplen=1.803885 a=143.738480 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 161.48 +Info: system potential: 1918799.375000 hpwl: 37616.925781 +Info: overlap: COMB=90.5%, FF=74.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.086946 grad_dist: 0.048072 +Info: iter=284 steplen=1.808656 a=144.239349 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 163.55 +Info: system potential: 1892061.625000 hpwl: 38054.613281 +Info: overlap: COMB=90.4%, FF=74.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.088169 grad_dist: 0.048615 +Info: iter=285 steplen=1.813634 a=144.740219 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 165.59 +Info: system potential: 1868252.250000 hpwl: 38493.636719 +Info: overlap: COMB=90.1%, FF=74.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.089799 grad_dist: 0.049368 +Info: iter=286 steplen=1.818966 a=145.241074 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 167.69 +Info: system potential: 1843982.000000 hpwl: 38945.535156 +Info: overlap: COMB=89.8%, FF=73.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.091814 grad_dist: 0.050321 +Info: iter=287 steplen=1.824549 a=145.741928 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 169.75 +Info: system potential: 1817313.375000 hpwl: 39398.785156 +Info: overlap: COMB=89.7%, FF=72.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.094205 grad_dist: 0.051469 +Info: iter=288 steplen=1.830331 a=146.242783 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 171.88 +Info: system potential: 1791054.000000 hpwl: 39866.933594 +Info: overlap: COMB=89.6%, FF=72.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.096932 grad_dist: 0.052800 +Info: iter=289 steplen=1.835839 a=146.743637 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 173.97 +Info: system potential: 1762001.750000 hpwl: 40333.933594 +Info: overlap: COMB=89.5%, FF=72.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.099969 grad_dist: 0.054286 +Info: iter=290 steplen=1.841536 a=147.244492 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 176.15 +Info: system potential: 1738440.625000 hpwl: 40817.558594 +Info: overlap: COMB=89.5%, FF=73.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.103266 grad_dist: 0.055895 +Info: iter=291 steplen=1.847484 a=147.745331 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 178.32 +Info: system potential: 1714568.125000 hpwl: 41298.214844 +Info: overlap: COMB=89.3%, FF=73.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.106795 grad_dist: 0.057626 +Info: iter=292 steplen=1.853223 a=148.246185 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 180.60 +Info: system potential: 1688180.875000 hpwl: 41799.242188 +Info: overlap: COMB=88.9%, FF=72.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.110524 grad_dist: 0.059464 +Info: iter=293 steplen=1.858669 a=148.747025 penalty=[0.03, 0.03, 0.03, 0.03] +Info: update_chains distance 182.81 +Info: system potential: 1661179.250000 hpwl: 42293.519531 +Info: overlap: COMB=88.6%, FF=71.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.114387 grad_dist: 0.061367 +Info: iter=294 steplen=1.863985 a=149.247864 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 185.10 +Info: system potential: 1631940.375000 hpwl: 42811.039062 +Info: overlap: COMB=88.3%, FF=71.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.118327 grad_dist: 0.063305 +Info: iter=295 steplen=1.869168 a=149.748703 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 187.30 +Info: system potential: 1603837.375000 hpwl: 43318.074219 +Info: overlap: COMB=88.1%, FF=70.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.122296 grad_dist: 0.065255 +Info: iter=296 steplen=1.874123 a=150.249542 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 189.59 +Info: system potential: 1573837.000000 hpwl: 43851.621094 +Info: overlap: COMB=87.8%, FF=69.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.126255 grad_dist: 0.067197 +Info: iter=297 steplen=1.878870 a=150.750381 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 191.80 +Info: system potential: 1547659.250000 hpwl: 44367.437500 +Info: overlap: COMB=87.6%, FF=69.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.130176 grad_dist: 0.069107 +Info: iter=298 steplen=1.883693 a=151.251205 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 194.10 +Info: system potential: 1521394.375000 hpwl: 44915.273438 +Info: overlap: COMB=87.5%, FF=69.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.134012 grad_dist: 0.070977 +Info: iter=299 steplen=1.888108 a=151.752029 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 196.35 +Info: system potential: 1493733.250000 hpwl: 45437.484375 +Info: overlap: COMB=87.5%, FF=69.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.137734 grad_dist: 0.072797 +Info: iter=300 steplen=1.892036 a=152.252853 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 198.73 +Info: system potential: 1467182.500000 hpwl: 45995.589844 +Info: overlap: COMB=87.2%, FF=68.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.141300 grad_dist: 0.074533 +Info: iter=301 steplen=1.895801 a=152.753677 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 200.96 +Info: system potential: 1443358.000000 hpwl: 46522.445312 +Info: overlap: COMB=86.9%, FF=67.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.144675 grad_dist: 0.076171 +Info: iter=302 steplen=1.899343 a=153.254501 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 203.30 +Info: system potential: 1418588.625000 hpwl: 47090.300781 +Info: overlap: COMB=86.8%, FF=67.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.147843 grad_dist: 0.077714 +Info: iter=303 steplen=1.902407 a=153.755310 penalty=[0.04, 0.04, 0.04, 0.04] +Info: update_chains distance 205.58 +Info: system potential: 1394502.250000 hpwl: 47623.062500 +Info: overlap: COMB=86.6%, FF=66.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.150785 grad_dist: 0.079146 +Info: iter=304 steplen=1.905155 a=154.256119 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 207.98 +Info: system potential: 1365500.500000 hpwl: 48201.382812 +Info: overlap: COMB=86.3%, FF=66.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153450 grad_dist: 0.080447 +Info: iter=305 steplen=1.907472 a=154.756927 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 210.21 +Info: system potential: 1340192.125000 hpwl: 48738.648438 +Info: overlap: COMB=86.0%, FF=65.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.155833 grad_dist: 0.081600 +Info: iter=306 steplen=1.909713 a=155.257736 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 212.58 +Info: system potential: 1315067.000000 hpwl: 49325.710938 +Info: overlap: COMB=85.7%, FF=65.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157901 grad_dist: 0.082607 +Info: iter=307 steplen=1.911477 a=155.758545 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 214.85 +Info: system potential: 1288748.000000 hpwl: 49868.644531 +Info: overlap: COMB=85.5%, FF=64.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159681 grad_dist: 0.083474 +Info: iter=308 steplen=1.912943 a=156.259354 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 217.22 +Info: system potential: 1261813.000000 hpwl: 50462.695312 +Info: overlap: COMB=85.1%, FF=64.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161151 grad_dist: 0.084200 +Info: iter=309 steplen=1.913920 a=156.760162 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 219.41 +Info: system potential: 1236862.625000 hpwl: 51010.964844 +Info: overlap: COMB=84.7%, FF=63.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162316 grad_dist: 0.084781 +Info: iter=310 steplen=1.914537 a=157.260956 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 221.80 +Info: system potential: 1213856.500000 hpwl: 51613.265625 +Info: overlap: COMB=84.5%, FF=62.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163163 grad_dist: 0.085206 +Info: iter=311 steplen=1.914925 a=157.761749 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 224.07 +Info: system potential: 1189944.625000 hpwl: 52169.816406 +Info: overlap: COMB=84.2%, FF=61.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163717 grad_dist: 0.085473 +Info: iter=312 steplen=1.915428 a=158.262543 penalty=[0.05, 0.05, 0.05, 0.05] +Info: update_chains distance 226.46 +Info: system potential: 1163608.125000 hpwl: 52781.156250 +Info: overlap: COMB=84.0%, FF=61.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163983 grad_dist: 0.085611 +Info: iter=313 steplen=1.915442 a=158.763336 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 228.64 +Info: system potential: 1138379.375000 hpwl: 53347.023438 +Info: overlap: COMB=83.9%, FF=61.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164035 grad_dist: 0.085645 +Info: iter=314 steplen=1.915284 a=159.264130 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 230.99 +Info: system potential: 1117846.500000 hpwl: 53966.812500 +Info: overlap: COMB=83.7%, FF=60.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163860 grad_dist: 0.085574 +Info: iter=315 steplen=1.914846 a=159.764908 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 233.17 +Info: system potential: 1096324.625000 hpwl: 54541.125000 +Info: overlap: COMB=83.5%, FF=60.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163491 grad_dist: 0.085401 +Info: iter=316 steplen=1.914405 a=160.265686 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 235.49 +Info: system potential: 1071944.375000 hpwl: 55172.156250 +Info: overlap: COMB=82.9%, FF=59.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162967 grad_dist: 0.085135 +Info: iter=317 steplen=1.914223 a=160.766464 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 237.64 +Info: system potential: 1050678.750000 hpwl: 55759.777344 +Info: overlap: COMB=82.6%, FF=59.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162345 grad_dist: 0.084807 +Info: iter=318 steplen=1.914290 a=161.267242 penalty=[0.06, 0.06, 0.06, 0.06] +Info: update_chains distance 239.90 +Info: system potential: 1024486.625000 hpwl: 56405.390625 +Info: overlap: COMB=82.4%, FF=58.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161685 grad_dist: 0.084464 +Info: iter=319 steplen=1.914248 a=161.768021 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 241.98 +Info: system potential: 1000763.625000 hpwl: 57010.933594 +Info: overlap: COMB=82.1%, FF=57.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161070 grad_dist: 0.084133 +Info: iter=320 steplen=1.914476 a=162.268799 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 244.23 +Info: system potential: 977026.937500 hpwl: 57670.875000 +Info: overlap: COMB=81.6%, FF=56.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160506 grad_dist: 0.083819 +Info: iter=321 steplen=1.914912 a=162.769562 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 246.23 +Info: system potential: 954483.687500 hpwl: 58291.000000 +Info: overlap: COMB=81.4%, FF=56.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160041 grad_dist: 0.083535 +Info: iter=322 steplen=1.915852 a=163.270325 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 248.42 +Info: system potential: 933709.437500 hpwl: 58965.707031 +Info: overlap: COMB=81.1%, FF=55.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159742 grad_dist: 0.083303 +Info: iter=323 steplen=1.917602 a=163.771088 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 250.45 +Info: system potential: 911229.375000 hpwl: 59606.640625 +Info: overlap: COMB=80.4%, FF=54.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159685 grad_dist: 0.083178 +Info: iter=324 steplen=1.919800 a=164.271851 penalty=[0.07, 0.07, 0.07, 0.07] +Info: update_chains distance 252.64 +Info: system potential: 890168.250000 hpwl: 60303.453125 +Info: overlap: COMB=80.5%, FF=54.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159927 grad_dist: 0.083205 +Info: iter=325 steplen=1.922080 a=164.772614 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 254.67 +Info: system potential: 866066.125000 hpwl: 60964.828125 +Info: overlap: COMB=79.9%, FF=54.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160491 grad_dist: 0.083365 +Info: iter=326 steplen=1.925157 a=165.273376 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 256.83 +Info: system potential: 844353.000000 hpwl: 61680.906250 +Info: overlap: COMB=79.6%, FF=53.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161331 grad_dist: 0.083650 +Info: iter=327 steplen=1.928654 a=165.774139 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 258.73 +Info: system potential: 823618.125000 hpwl: 62362.546875 +Info: overlap: COMB=79.0%, FF=52.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162508 grad_dist: 0.084083 +Info: iter=328 steplen=1.932702 a=166.274887 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 260.84 +Info: system potential: 803165.750000 hpwl: 63099.886719 +Info: overlap: COMB=78.8%, FF=51.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164044 grad_dist: 0.084677 +Info: iter=329 steplen=1.937300 a=166.775635 penalty=[0.08, 0.08, 0.08, 0.08] +Info: update_chains distance 262.77 +Info: system potential: 780379.437500 hpwl: 63803.554688 +Info: overlap: COMB=78.8%, FF=51.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.165922 grad_dist: 0.085435 +Info: iter=330 steplen=1.942083 a=167.276382 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 264.82 +Info: system potential: 758608.062500 hpwl: 64562.277344 +Info: overlap: COMB=78.5%, FF=50.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168068 grad_dist: 0.086337 +Info: iter=331 steplen=1.946645 a=167.777130 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 266.60 +Info: system potential: 737945.375000 hpwl: 65285.960938 +Info: overlap: COMB=77.9%, FF=50.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.170422 grad_dist: 0.087333 +Info: iter=332 steplen=1.951404 a=168.277878 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 268.59 +Info: system potential: 715477.062500 hpwl: 66062.304688 +Info: overlap: COMB=77.6%, FF=49.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.172922 grad_dist: 0.088391 +Info: iter=333 steplen=1.956325 a=168.778625 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 270.32 +Info: system potential: 696568.062500 hpwl: 66806.648438 +Info: overlap: COMB=77.1%, FF=48.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175497 grad_dist: 0.089506 +Info: iter=334 steplen=1.960732 a=169.279373 penalty=[0.09, 0.09, 0.09, 0.09] +Info: update_chains distance 272.26 +Info: system potential: 678429.250000 hpwl: 67597.468750 +Info: overlap: COMB=76.8%, FF=47.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178140 grad_dist: 0.090633 +Info: iter=335 steplen=1.965511 a=169.780106 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 273.95 +Info: system potential: 658875.437500 hpwl: 68358.882812 +Info: overlap: COMB=76.6%, FF=47.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.180775 grad_dist: 0.091754 +Info: iter=336 steplen=1.970220 a=170.280838 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 275.82 +Info: system potential: 638048.875000 hpwl: 69166.671875 +Info: overlap: COMB=76.1%, FF=46.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.183355 grad_dist: 0.092888 +Info: iter=337 steplen=1.973946 a=170.781570 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 277.36 +Info: system potential: 619693.562500 hpwl: 69940.960938 +Info: overlap: COMB=75.8%, FF=45.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185773 grad_dist: 0.093972 +Info: iter=338 steplen=1.976902 a=171.282303 penalty=[0.10, 0.10, 0.10, 0.10] +Info: update_chains distance 279.21 +Info: system potential: 600167.687500 hpwl: 70754.695312 +Info: overlap: COMB=75.7%, FF=45.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.187938 grad_dist: 0.094910 +Info: iter=339 steplen=1.980159 a=171.783035 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 280.76 +Info: system potential: 580950.500000 hpwl: 71541.640625 +Info: overlap: COMB=75.2%, FF=45.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.189768 grad_dist: 0.095719 +Info: iter=340 steplen=1.982555 a=172.283768 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 282.54 +Info: system potential: 565097.000000 hpwl: 72362.726562 +Info: overlap: COMB=74.6%, FF=43.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.191311 grad_dist: 0.096419 +Info: iter=341 steplen=1.984170 a=172.784500 penalty=[0.11, 0.11, 0.11, 0.11] +Info: update_chains distance 284.08 +Info: system potential: 547988.687500 hpwl: 73155.093750 +Info: overlap: COMB=74.3%, FF=42.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.192572 grad_dist: 0.096954 +Info: iter=342 steplen=1.986207 a=173.285233 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 285.94 +Info: system potential: 530487.437500 hpwl: 73984.023438 +Info: overlap: COMB=74.2%, FF=42.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193492 grad_dist: 0.097353 +Info: iter=343 steplen=1.987526 a=173.785950 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 287.36 +Info: system potential: 514400.875000 hpwl: 74784.843750 +Info: overlap: COMB=73.5%, FF=41.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194132 grad_dist: 0.097659 +Info: iter=344 steplen=1.987869 a=174.286667 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 289.09 +Info: system potential: 499281.937500 hpwl: 75617.148438 +Info: overlap: COMB=73.1%, FF=41.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194490 grad_dist: 0.097812 +Info: iter=345 steplen=1.988407 a=174.787384 penalty=[0.12, 0.12, 0.12, 0.12] +Info: update_chains distance 290.56 +Info: system potential: 483101.250000 hpwl: 76424.062500 +Info: overlap: COMB=72.6%, FF=40.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194570 grad_dist: 0.097813 +Info: iter=346 steplen=1.989213 a=175.288101 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 292.31 +Info: system potential: 467811.843750 hpwl: 77264.601562 +Info: overlap: COMB=72.2%, FF=39.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194464 grad_dist: 0.097748 +Info: iter=347 steplen=1.989455 a=175.788818 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 293.61 +Info: system potential: 453081.750000 hpwl: 78078.945312 +Info: overlap: COMB=72.0%, FF=38.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194293 grad_dist: 0.097643 +Info: iter=348 steplen=1.989834 a=176.289536 penalty=[0.13, 0.13, 0.13, 0.13] +Info: update_chains distance 295.32 +Info: system potential: 438590.937500 hpwl: 78924.242188 +Info: overlap: COMB=71.7%, FF=37.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194063 grad_dist: 0.097482 +Info: iter=349 steplen=1.990756 a=176.790237 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 296.66 +Info: system potential: 424514.187500 hpwl: 79746.804688 +Info: overlap: COMB=71.1%, FF=37.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193885 grad_dist: 0.097309 +Info: iter=350 steplen=1.992480 a=177.290939 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 298.23 +Info: system potential: 411689.593750 hpwl: 80600.539062 +Info: overlap: COMB=71.0%, FF=36.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.193924 grad_dist: 0.097208 +Info: iter=351 steplen=1.994941 a=177.791641 penalty=[0.14, 0.14, 0.14, 0.14] +Info: update_chains distance 299.54 +Info: system potential: 396681.593750 hpwl: 81434.023438 +Info: overlap: COMB=70.6%, FF=35.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194336 grad_dist: 0.097258 +Info: iter=352 steplen=1.998150 a=178.292343 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 301.16 +Info: system potential: 383841.937500 hpwl: 82298.328125 +Info: overlap: COMB=69.8%, FF=33.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.195134 grad_dist: 0.097486 +Info: iter=353 steplen=2.001652 a=178.793045 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 302.47 +Info: system potential: 372050.937500 hpwl: 83141.179688 +Info: overlap: COMB=69.2%, FF=33.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.196381 grad_dist: 0.097876 +Info: iter=354 steplen=2.006425 a=179.293747 penalty=[0.15, 0.15, 0.15, 0.15] +Info: update_chains distance 304.13 +Info: system potential: 359683.625000 hpwl: 84015.070312 +Info: overlap: COMB=69.2%, FF=33.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.198135 grad_dist: 0.098462 +Info: iter=355 steplen=2.012306 a=179.794449 penalty=[0.16, 0.16, 0.16, 0.16] +Info: update_chains distance 305.48 +Info: system potential: 347710.968750 hpwl: 84872.898438 +Info: overlap: COMB=68.7%, FF=32.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.200480 grad_dist: 0.099322 +Info: iter=356 steplen=2.018480 a=180.295135 penalty=[0.16, 0.16, 0.16, 0.16] +Info: update_chains distance 307.18 +Info: system potential: 336445.093750 hpwl: 85756.796875 +Info: overlap: COMB=67.8%, FF=31.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.203356 grad_dist: 0.100436 +Info: iter=357 steplen=2.024739 a=180.795822 penalty=[0.17, 0.17, 0.17, 0.17] +Info: update_chains distance 308.51 +Info: system potential: 324542.343750 hpwl: 86623.015625 +Info: overlap: COMB=67.7%, FF=31.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.206619 grad_dist: 0.101723 +Info: iter=358 steplen=2.031179 a=181.296509 penalty=[0.17, 0.17, 0.17, 0.17] +Info: update_chains distance 310.14 +Info: system potential: 312635.031250 hpwl: 87510.164062 +Info: overlap: COMB=67.0%, FF=30.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.210204 grad_dist: 0.103137 +Info: iter=359 steplen=2.038094 a=181.797195 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 311.31 +Info: system potential: 301512.531250 hpwl: 88381.226562 +Info: overlap: COMB=66.5%, FF=30.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.214009 grad_dist: 0.104671 +Info: iter=360 steplen=2.044579 a=182.297882 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 312.78 +Info: system potential: 291503.687500 hpwl: 89267.609375 +Info: overlap: COMB=66.1%, FF=29.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.217943 grad_dist: 0.106290 +Info: iter=361 steplen=2.050451 a=182.798569 penalty=[0.18, 0.18, 0.18, 0.18] +Info: update_chains distance 313.81 +Info: system potential: 281322.093750 hpwl: 90133.203125 +Info: overlap: COMB=65.8%, FF=29.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.221825 grad_dist: 0.107905 +Info: iter=362 steplen=2.055740 a=183.299255 penalty=[0.19, 0.19, 0.19, 0.19] +Info: update_chains distance 315.25 +Info: system potential: 270961.968750 hpwl: 91010.453125 +Info: overlap: COMB=65.5%, FF=28.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.225480 grad_dist: 0.109441 +Info: iter=363 steplen=2.060297 a=183.799942 penalty=[0.19, 0.19, 0.19, 0.19] +Info: update_chains distance 316.17 +Info: system potential: 261459.531250 hpwl: 91865.335938 +Info: overlap: COMB=65.0%, FF=27.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.228811 grad_dist: 0.110850 +Info: iter=364 steplen=2.064144 a=184.300613 penalty=[0.20, 0.20, 0.20, 0.20] +Info: update_chains distance 317.60 +Info: system potential: 252832.500000 hpwl: 92729.960938 +Info: overlap: COMB=64.5%, FF=27.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.231696 grad_dist: 0.112101 +Info: iter=365 steplen=2.066837 a=184.801285 penalty=[0.20, 0.20, 0.20, 0.20] +Info: update_chains distance 318.61 +Info: system potential: 243646.656250 hpwl: 93571.406250 +Info: overlap: COMB=63.9%, FF=26.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.233996 grad_dist: 0.113145 +Info: iter=366 steplen=2.068113 a=185.301956 penalty=[0.21, 0.21, 0.21, 0.21] +Info: update_chains distance 320.10 +Info: system potential: 235145.687500 hpwl: 94411.390625 +Info: overlap: COMB=63.6%, FF=25.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.235624 grad_dist: 0.113899 +Info: iter=367 steplen=2.068708 a=185.802628 penalty=[0.21, 0.21, 0.21, 0.21] +Info: update_chains distance 321.10 +Info: system potential: 227244.468750 hpwl: 95229.593750 +Info: overlap: COMB=63.1%, FF=25.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236511 grad_dist: 0.114346 +Info: iter=368 steplen=2.068381 a=186.303299 penalty=[0.22, 0.22, 0.22, 0.22] +Info: update_chains distance 322.76 +Info: system potential: 219732.125000 hpwl: 96048.367188 +Info: overlap: COMB=62.7%, FF=24.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236709 grad_dist: 0.114516 +Info: iter=369 steplen=2.067029 a=186.803970 penalty=[0.22, 0.22, 0.22, 0.22] +Info: update_chains distance 323.87 +Info: system potential: 212239.125000 hpwl: 96844.976562 +Info: overlap: COMB=62.1%, FF=23.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.236205 grad_dist: 0.114398 +Info: iter=370 steplen=2.064773 a=187.304642 penalty=[0.23, 0.23, 0.23, 0.23] +Info: update_chains distance 325.69 +Info: system potential: 204744.640625 hpwl: 97643.000000 +Info: overlap: COMB=61.3%, FF=23.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.234998 grad_dist: 0.113984 +Info: iter=371 steplen=2.061675 a=187.805298 penalty=[0.24, 0.24, 0.24, 0.24] +Info: update_chains distance 326.90 +Info: system potential: 198011.515625 hpwl: 98423.070312 +Info: overlap: COMB=60.8%, FF=23.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.233191 grad_dist: 0.113292 +Info: iter=372 steplen=2.058322 a=188.305954 penalty=[0.24, 0.24, 0.24, 0.24] +Info: update_chains distance 328.73 +Info: system potential: 191483.531250 hpwl: 99198.187500 +Info: overlap: COMB=60.0%, FF=22.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.230912 grad_dist: 0.112360 +Info: iter=373 steplen=2.055102 a=188.806625 penalty=[0.25, 0.25, 0.25, 0.25] +Info: update_chains distance 330.08 +Info: system potential: 184948.656250 hpwl: 99965.906250 +Info: overlap: COMB=59.5%, FF=21.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.228308 grad_dist: 0.111277 +Info: iter=374 steplen=2.051703 a=189.307281 penalty=[0.25, 0.25, 0.25, 0.25] +Info: update_chains distance 332.06 +Info: system potential: 178557.078125 hpwl: 100726.929688 +Info: overlap: COMB=59.2%, FF=21.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.225539 grad_dist: 0.110108 +Info: iter=375 steplen=2.048338 a=189.807938 penalty=[0.26, 0.26, 0.26, 0.26] +Info: update_chains distance 333.53 +Info: system potential: 172487.750000 hpwl: 101479.609375 +Info: overlap: COMB=58.5%, FF=21.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.222671 grad_dist: 0.108872 +Info: iter=376 steplen=2.045260 a=190.308594 penalty=[0.27, 0.27, 0.27, 0.27] +Info: update_chains distance 335.60 +Info: system potential: 166894.953125 hpwl: 102226.578125 +Info: overlap: COMB=58.0%, FF=20.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.219845 grad_dist: 0.107597 +Info: iter=377 steplen=2.043225 a=190.809250 penalty=[0.27, 0.27, 0.27, 0.27] +Info: update_chains distance 337.19 +Info: system potential: 161279.000000 hpwl: 102970.515625 +Info: overlap: COMB=57.3%, FF=20.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.217169 grad_dist: 0.106368 +Info: iter=378 steplen=2.041681 a=191.309906 penalty=[0.28, 0.28, 0.28, 0.28] +Info: update_chains distance 339.44 +Info: system potential: 155802.593750 hpwl: 103711.406250 +Info: overlap: COMB=56.5%, FF=19.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.214793 grad_dist: 0.105267 +Info: iter=379 steplen=2.040449 a=191.810562 penalty=[0.29, 0.29, 0.29, 0.29] +Info: update_chains distance 341.20 +Info: system potential: 150498.265625 hpwl: 104446.226562 +Info: overlap: COMB=56.2%, FF=19.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.212696 grad_dist: 0.104296 +Info: iter=380 steplen=2.039359 a=192.311218 penalty=[0.29, 0.29, 0.29, 0.29] +Info: update_chains distance 343.51 +Info: system potential: 145335.875000 hpwl: 105173.234375 +Info: overlap: COMB=55.5%, FF=18.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.210897 grad_dist: 0.103417 +Info: iter=381 steplen=2.039293 a=192.811874 penalty=[0.30, 0.30, 0.30, 0.30] +Info: update_chains distance 345.37 +Info: system potential: 140392.140625 hpwl: 105894.343750 +Info: overlap: COMB=54.9%, FF=18.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.209296 grad_dist: 0.102653 +Info: iter=382 steplen=2.038863 a=193.312515 penalty=[0.31, 0.31, 0.31, 0.31] +Info: update_chains distance 347.73 +Info: system potential: 135629.656250 hpwl: 106607.250000 +Info: overlap: COMB=54.5%, FF=17.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.207949 grad_dist: 0.102002 +Info: iter=383 steplen=2.038689 a=193.813171 penalty=[0.32, 0.32, 0.32, 0.32] +Info: update_chains distance 349.60 +Info: system potential: 131015.070312 hpwl: 107311.093750 +Info: overlap: COMB=53.7%, FF=16.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.206685 grad_dist: 0.101407 +Info: iter=384 steplen=2.038161 a=194.313828 penalty=[0.33, 0.33, 0.33, 0.33] +Info: update_chains distance 352.01 +Info: system potential: 126618.726562 hpwl: 108003.328125 +Info: overlap: COMB=53.0%, FF=16.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.205471 grad_dist: 0.100842 +Info: iter=385 steplen=2.037562 a=194.814468 penalty=[0.33, 0.33, 0.33, 0.33] +Info: update_chains distance 353.98 +Info: system potential: 122386.031250 hpwl: 108682.906250 +Info: overlap: COMB=52.5%, FF=15.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.204164 grad_dist: 0.100271 +Info: iter=386 steplen=2.036124 a=195.315109 penalty=[0.34, 0.34, 0.34, 0.34] +Info: update_chains distance 356.38 +Info: system potential: 118249.070312 hpwl: 109350.492188 +Info: overlap: COMB=51.9%, FF=15.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.202711 grad_dist: 0.099638 +Info: iter=387 steplen=2.034483 a=195.815750 penalty=[0.35, 0.35, 0.35, 0.35] +Info: update_chains distance 358.33 +Info: system potential: 114335.875000 hpwl: 110005.562500 +Info: overlap: COMB=51.5%, FF=15.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.201074 grad_dist: 0.098903 +Info: iter=388 steplen=2.033053 a=196.316391 penalty=[0.36, 0.36, 0.36, 0.36] +Info: update_chains distance 360.75 +Info: system potential: 110647.929688 hpwl: 110651.945312 +Info: overlap: COMB=50.8%, FF=15.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.199362 grad_dist: 0.098100 +Info: iter=389 steplen=2.032222 a=196.817032 penalty=[0.37, 0.37, 0.37, 0.37] +Info: update_chains distance 362.74 +Info: system potential: 107072.109375 hpwl: 111284.757812 +Info: overlap: COMB=50.4%, FF=14.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.197669 grad_dist: 0.097306 +Info: iter=390 steplen=2.031423 a=197.317673 penalty=[0.38, 0.38, 0.38, 0.38] +Info: update_chains distance 365.12 +Info: system potential: 103568.851562 hpwl: 111911.562500 +Info: overlap: COMB=49.6%, FF=13.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.196034 grad_dist: 0.096556 +Info: iter=391 steplen=2.030267 a=197.818314 penalty=[0.39, 0.39, 0.39, 0.39] +Info: update_chains distance 367.01 +Info: system potential: 100274.101562 hpwl: 112519.062500 +Info: overlap: COMB=49.0%, FF=13.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.194428 grad_dist: 0.095817 +Info: iter=392 steplen=2.029151 a=198.318954 penalty=[0.40, 0.40, 0.40, 0.40] +Info: update_chains distance 369.34 +Info: system potential: 97043.343750 hpwl: 113120.484375 +Info: overlap: COMB=48.6%, FF=12.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.192884 grad_dist: 0.095057 +Info: iter=393 steplen=2.029152 a=198.819580 penalty=[0.41, 0.41, 0.41, 0.41] +Info: update_chains distance 371.21 +Info: system potential: 93935.687500 hpwl: 113708.820312 +Info: overlap: COMB=47.8%, FF=12.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.191468 grad_dist: 0.094342 +Info: iter=394 steplen=2.029504 a=199.320206 penalty=[0.42, 0.42, 0.42, 0.42] +Info: update_chains distance 373.54 +Info: system potential: 90887.273438 hpwl: 114293.242188 +Info: overlap: COMB=46.7%, FF=12.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.190291 grad_dist: 0.093753 +Info: iter=395 steplen=2.029708 a=199.820831 penalty=[0.43, 0.43, 0.43, 0.43] +Info: update_chains distance 375.44 +Info: system potential: 87905.085938 hpwl: 114861.625000 +Info: overlap: COMB=46.2%, FF=12.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.189314 grad_dist: 0.093260 +Info: iter=396 steplen=2.029961 a=200.321457 penalty=[0.44, 0.44, 0.44, 0.44] +Info: update_chains distance 377.79 +Info: system potential: 85076.875000 hpwl: 115429.484375 +Info: overlap: COMB=45.4%, FF=11.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.188445 grad_dist: 0.092823 +Info: iter=397 steplen=2.030155 a=200.822083 penalty=[0.45, 0.45, 0.45, 0.45] +Info: update_chains distance 379.64 +Info: system potential: 82382.820312 hpwl: 115976.492188 +Info: overlap: COMB=44.9%, FF=11.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.187585 grad_dist: 0.092411 +Info: iter=398 steplen=2.029904 a=201.322708 penalty=[0.46, 0.46, 0.46, 0.46] +Info: update_chains distance 381.95 +Info: system potential: 79758.531250 hpwl: 116521.320312 +Info: overlap: COMB=44.3%, FF=10.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.186713 grad_dist: 0.091988 +Info: iter=399 steplen=2.029758 a=201.823334 penalty=[0.47, 0.47, 0.47, 0.47] +Info: update_chains distance 383.77 +Info: system potential: 77215.046875 hpwl: 117045.218750 +Info: overlap: COMB=43.6%, FF=10.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185847 grad_dist: 0.091541 +Info: iter=400 steplen=2.030207 a=202.323944 penalty=[0.48, 0.48, 0.48, 0.48] +Info: update_chains distance 386.08 +Info: system potential: 74683.414062 hpwl: 117565.601562 +Info: overlap: COMB=43.0%, FF=10.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.185009 grad_dist: 0.091120 +Info: iter=401 steplen=2.030389 a=202.824554 penalty=[0.49, 0.49, 0.49, 0.49] +Info: update_chains distance 388.01 +Info: system potential: 72268.867188 hpwl: 118072.960938 +Info: overlap: COMB=42.6%, FF=9.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.184137 grad_dist: 0.090744 +Info: iter=402 steplen=2.029199 a=203.325180 penalty=[0.51, 0.51, 0.51, 0.51] +Info: update_chains distance 390.36 +Info: system potential: 69933.273438 hpwl: 118564.984375 +Info: overlap: COMB=41.8%, FF=9.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.183097 grad_dist: 0.090315 +Info: iter=403 steplen=2.027312 a=203.825790 penalty=[0.52, 0.52, 0.52, 0.52] +Info: update_chains distance 392.21 +Info: system potential: 67706.078125 hpwl: 119049.664062 +Info: overlap: COMB=41.4%, FF=8.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.181849 grad_dist: 0.089733 +Info: iter=404 steplen=2.026561 a=204.326401 penalty=[0.53, 0.53, 0.53, 0.53] +Info: update_chains distance 394.53 +Info: system potential: 65626.484375 hpwl: 119520.281250 +Info: overlap: COMB=40.7%, FF=8.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.180606 grad_dist: 0.089068 +Info: iter=405 steplen=2.027737 a=204.827011 penalty=[0.55, 0.55, 0.55, 0.55] +Info: update_chains distance 396.50 +Info: system potential: 63566.652344 hpwl: 119999.187500 +Info: overlap: COMB=40.2%, FF=7.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.179587 grad_dist: 0.088513 +Info: iter=406 steplen=2.028930 a=205.327621 penalty=[0.56, 0.56, 0.56, 0.56] +Info: update_chains distance 399.02 +Info: system potential: 61573.984375 hpwl: 120465.617188 +Info: overlap: COMB=39.8%, FF=7.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178953 grad_dist: 0.088148 +Info: iter=407 steplen=2.030138 a=205.828232 penalty=[0.57, 0.57, 0.57, 0.57] +Info: update_chains distance 401.10 +Info: system potential: 59590.441406 hpwl: 120939.812500 +Info: overlap: COMB=39.1%, FF=7.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178509 grad_dist: 0.087901 +Info: iter=408 steplen=2.030789 a=206.328842 penalty=[0.59, 0.59, 0.59, 0.59] +Info: update_chains distance 403.63 +Info: system potential: 57781.550781 hpwl: 121398.656250 +Info: overlap: COMB=38.6%, FF=7.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.178145 grad_dist: 0.087696 +Info: iter=409 steplen=2.031390 a=206.829453 penalty=[0.60, 0.60, 0.60, 0.60] +Info: update_chains distance 405.65 +Info: system potential: 55933.847656 hpwl: 121872.906250 +Info: overlap: COMB=38.0%, FF=7.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177842 grad_dist: 0.087486 +Info: iter=410 steplen=2.032812 a=207.330063 penalty=[0.62, 0.62, 0.62, 0.62] +Info: update_chains distance 408.09 +Info: system potential: 54024.042969 hpwl: 122333.304688 +Info: overlap: COMB=37.1%, FF=6.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177518 grad_dist: 0.087309 +Info: iter=411 steplen=2.033214 a=207.830658 penalty=[0.63, 0.63, 0.63, 0.63] +Info: update_chains distance 410.16 +Info: system potential: 52195.578125 hpwl: 122812.617188 +Info: overlap: COMB=36.5%, FF=6.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.177187 grad_dist: 0.087150 +Info: iter=412 steplen=2.033121 a=208.331253 penalty=[0.65, 0.65, 0.65, 0.65] +Info: update_chains distance 412.72 +Info: system potential: 50362.500000 hpwl: 123274.671875 +Info: overlap: COMB=35.9%, FF=6.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176810 grad_dist: 0.086920 +Info: iter=413 steplen=2.034171 a=208.831848 penalty=[0.67, 0.67, 0.67, 0.67] +Info: update_chains distance 414.80 +Info: system potential: 48573.363281 hpwl: 123760.976562 +Info: overlap: COMB=35.3%, FF=5.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176424 grad_dist: 0.086661 +Info: iter=414 steplen=2.035802 a=209.332443 penalty=[0.68, 0.68, 0.68, 0.68] +Info: update_chains distance 417.29 +Info: system potential: 46811.378906 hpwl: 124234.335938 +Info: overlap: COMB=34.8%, FF=6.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176070 grad_dist: 0.086467 +Info: iter=415 steplen=2.036277 a=209.833038 penalty=[0.70, 0.70, 0.70, 0.70] +Info: update_chains distance 419.35 +Info: system potential: 45118.382812 hpwl: 124728.085938 +Info: overlap: COMB=34.5%, FF=5.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175877 grad_dist: 0.086294 +Info: iter=416 steplen=2.038111 a=210.333633 penalty=[0.72, 0.72, 0.72, 0.72] +Info: update_chains distance 421.65 +Info: system potential: 43458.222656 hpwl: 125211.093750 +Info: overlap: COMB=34.1%, FF=5.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175830 grad_dist: 0.086128 +Info: iter=417 steplen=2.041507 a=210.834229 penalty=[0.73, 0.73, 0.73, 0.73] +Info: update_chains distance 423.78 +Info: system potential: 41741.523438 hpwl: 125719.406250 +Info: overlap: COMB=33.3%, FF=4.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175925 grad_dist: 0.086097 +Info: iter=418 steplen=2.043347 a=211.334824 penalty=[0.75, 0.75, 0.75, 0.75] +Info: update_chains distance 426.20 +Info: system potential: 40209.914062 hpwl: 126215.601562 +Info: overlap: COMB=32.9%, FF=4.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.176030 grad_dist: 0.086169 +Info: iter=419 steplen=2.042847 a=211.835419 penalty=[0.77, 0.77, 0.77, 0.77] +Info: update_chains distance 428.19 +Info: system potential: 38723.980469 hpwl: 126720.539062 +Info: overlap: COMB=32.3%, FF=4.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175996 grad_dist: 0.086109 +Info: iter=420 steplen=2.043875 a=212.336014 penalty=[0.79, 0.79, 0.79, 0.79] +Info: update_chains distance 430.43 +Info: system potential: 37195.742188 hpwl: 127220.273438 +Info: overlap: COMB=31.9%, FF=4.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175745 grad_dist: 0.085886 +Info: iter=421 steplen=2.046263 a=212.836594 penalty=[0.81, 0.81, 0.81, 0.81] +Info: update_chains distance 432.36 +Info: system potential: 35735.921875 hpwl: 127739.312500 +Info: overlap: COMB=31.4%, FF=4.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175517 grad_dist: 0.085701 +Info: iter=422 steplen=2.048010 a=213.337173 penalty=[0.83, 0.83, 0.83, 0.83] +Info: update_chains distance 434.49 +Info: system potential: 34291.511719 hpwl: 128245.851562 +Info: overlap: COMB=30.9%, FF=4.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175404 grad_dist: 0.085582 +Info: iter=423 steplen=2.049542 a=213.837753 penalty=[0.85, 0.85, 0.85, 0.85] +Info: update_chains distance 436.25 +Info: system potential: 32834.160156 hpwl: 128767.234375 +Info: overlap: COMB=30.2%, FF=4.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175250 grad_dist: 0.085442 +Info: iter=424 steplen=2.051092 a=214.338333 penalty=[0.87, 0.87, 0.87, 0.87] +Info: update_chains distance 438.10 +Info: system potential: 31396.417969 hpwl: 129274.796875 +Info: overlap: COMB=29.8%, FF=4.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.175059 grad_dist: 0.085265 +Info: iter=425 steplen=2.053112 a=214.838913 penalty=[0.89, 0.89, 0.89, 0.89] +Info: update_chains distance 439.38 +Info: system potential: 30121.751953 hpwl: 129795.484375 +Info: overlap: COMB=29.1%, FF=3.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174909 grad_dist: 0.085079 +Info: iter=426 steplen=2.055849 a=215.339493 penalty=[0.92, 0.92, 0.92, 0.92] +Info: update_chains distance 440.94 +Info: system potential: 28823.443359 hpwl: 130301.960938 +Info: overlap: COMB=28.5%, FF=3.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174824 grad_dist: 0.084937 +Info: iter=427 steplen=2.058291 a=215.840073 penalty=[0.94, 0.94, 0.94, 0.94] +Info: update_chains distance 442.14 +Info: system potential: 27537.847656 hpwl: 130823.562500 +Info: overlap: COMB=27.9%, FF=3.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174825 grad_dist: 0.084833 +Info: iter=428 steplen=2.060818 a=216.340652 penalty=[0.96, 0.96, 0.96, 0.96] +Info: update_chains distance 443.50 +Info: system potential: 26314.400391 hpwl: 131324.093750 +Info: overlap: COMB=27.9%, FF=3.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174813 grad_dist: 0.084746 +Info: iter=429 steplen=2.062794 a=216.841232 penalty=[0.99, 0.99, 0.99, 0.99] +Info: update_chains distance 444.61 +Info: system potential: 25083.455078 hpwl: 131837.171875 +Info: overlap: COMB=27.3%, FF=3.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174756 grad_dist: 0.084634 +Info: iter=430 steplen=2.064832 a=217.341812 penalty=[1.01, 1.01, 1.01, 1.01] +Info: update_chains distance 445.90 +Info: system potential: 23858.943359 hpwl: 132322.734375 +Info: overlap: COMB=26.8%, FF=3.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174600 grad_dist: 0.084484 +Info: iter=431 steplen=2.066663 a=217.842392 penalty=[1.04, 1.04, 1.04, 1.04] +Info: update_chains distance 446.61 +Info: system potential: 22709.591797 hpwl: 132817.859375 +Info: overlap: COMB=26.2%, FF=3.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.174214 grad_dist: 0.084306 +Info: iter=432 steplen=2.066452 a=218.342972 penalty=[1.06, 1.06, 1.06, 1.06] +Info: update_chains distance 447.59 +Info: system potential: 21630.294922 hpwl: 133277.156250 +Info: overlap: COMB=25.6%, FF=2.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.173573 grad_dist: 0.083995 +Info: iter=433 steplen=2.066476 a=218.843536 penalty=[1.09, 1.09, 1.09, 1.09] +Info: update_chains distance 448.18 +Info: system potential: 20663.419922 hpwl: 133741.781250 +Info: overlap: COMB=25.0%, FF=2.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.172700 grad_dist: 0.083503 +Info: iter=434 steplen=2.068194 a=219.344101 penalty=[1.12, 1.12, 1.12, 1.12] +Info: update_chains distance 449.10 +Info: system potential: 19734.441406 hpwl: 134183.781250 +Info: overlap: COMB=24.4%, FF=2.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.171834 grad_dist: 0.082981 +Info: iter=435 steplen=2.070770 a=219.844681 penalty=[1.15, 1.15, 1.15, 1.15] +Info: update_chains distance 449.57 +Info: system potential: 18867.146484 hpwl: 134626.671875 +Info: overlap: COMB=24.0%, FF=2.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.171048 grad_dist: 0.082572 +Info: iter=436 steplen=2.071513 a=220.345245 penalty=[1.17, 1.17, 1.17, 1.17] +Info: update_chains distance 450.31 +Info: system potential: 18020.859375 hpwl: 135047.687500 +Info: overlap: COMB=23.8%, FF=2.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.170332 grad_dist: 0.082199 +Info: iter=437 steplen=2.072185 a=220.845810 penalty=[1.20, 1.20, 1.20, 1.20] +Info: update_chains distance 450.66 +Info: system potential: 17237.900391 hpwl: 135457.640625 +Info: overlap: COMB=23.2%, FF=2.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.169588 grad_dist: 0.081754 +Info: iter=438 steplen=2.074370 a=221.346375 penalty=[1.23, 1.23, 1.23, 1.23] +Info: update_chains distance 451.43 +Info: system potential: 16498.933594 hpwl: 135856.750000 +Info: overlap: COMB=22.7%, FF=2.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168909 grad_dist: 0.081321 +Info: iter=439 steplen=2.077060 a=221.846939 penalty=[1.26, 1.26, 1.26, 1.26] +Info: update_chains distance 452.04 +Info: system potential: 15816.792969 hpwl: 136243.890625 +Info: overlap: COMB=22.0%, FF=2.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.168323 grad_dist: 0.081013 +Info: iter=440 steplen=2.077725 a=222.347504 penalty=[1.30, 1.30, 1.30, 1.30] +Info: update_chains distance 453.23 +Info: system potential: 15168.061523 hpwl: 136617.953125 +Info: overlap: COMB=21.8%, FF=2.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.167808 grad_dist: 0.080719 +Info: iter=441 steplen=2.078918 a=222.848068 penalty=[1.33, 1.33, 1.33, 1.33] +Info: update_chains distance 454.01 +Info: system potential: 14549.710938 hpwl: 136973.437500 +Info: overlap: COMB=21.2%, FF=2.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.167122 grad_dist: 0.080347 +Info: iter=442 steplen=2.079998 a=223.348633 penalty=[1.36, 1.36, 1.36, 1.36] +Info: update_chains distance 455.14 +Info: system potential: 14012.304688 hpwl: 137324.343750 +Info: overlap: COMB=20.8%, FF=2.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.166201 grad_dist: 0.079932 +Info: iter=443 steplen=2.079283 a=223.849197 penalty=[1.40, 1.40, 1.40, 1.40] +Info: update_chains distance 455.81 +Info: system potential: 13449.343750 hpwl: 137642.703125 +Info: overlap: COMB=20.7%, FF=1.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.165297 grad_dist: 0.079404 +Info: iter=444 steplen=2.081732 a=224.349762 penalty=[1.43, 1.43, 1.43, 1.43] +Info: update_chains distance 456.59 +Info: system potential: 12947.724609 hpwl: 137973.218750 +Info: overlap: COMB=20.4%, FF=1.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.164392 grad_dist: 0.078838 +Info: iter=445 steplen=2.085188 a=224.850327 penalty=[1.47, 1.47, 1.47, 1.47] +Info: update_chains distance 456.93 +Info: system potential: 12423.333008 hpwl: 138273.875000 +Info: overlap: COMB=20.1%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163911 grad_dist: 0.078440 +Info: iter=446 steplen=2.089653 a=225.350876 penalty=[1.50, 1.50, 1.50, 1.50] +Info: update_chains distance 457.68 +Info: system potential: 11962.882812 hpwl: 138600.062500 +Info: overlap: COMB=20.1%, FF=2.0%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163669 grad_dist: 0.078250 +Info: iter=447 steplen=2.091615 a=225.851425 penalty=[1.54, 1.54, 1.54, 1.54] +Info: update_chains distance 458.10 +Info: system potential: 11523.691406 hpwl: 138878.593750 +Info: overlap: COMB=19.7%, FF=1.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163421 grad_dist: 0.078133 +Info: iter=448 steplen=2.091591 a=226.351974 penalty=[1.58, 1.58, 1.58, 1.58] +Info: update_chains distance 458.95 +Info: system potential: 11112.025391 hpwl: 139188.718750 +Info: overlap: COMB=19.3%, FF=1.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.163086 grad_dist: 0.077852 +Info: iter=449 steplen=2.094835 a=226.852524 penalty=[1.62, 1.62, 1.62, 1.62] +Info: update_chains distance 459.56 +Info: system potential: 10695.295898 hpwl: 139448.859375 +Info: overlap: COMB=19.1%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162593 grad_dist: 0.077489 +Info: iter=450 steplen=2.098278 a=227.353073 penalty=[1.66, 1.66, 1.66, 1.66] +Info: update_chains distance 460.60 +Info: system potential: 10314.656250 hpwl: 139763.062500 +Info: overlap: COMB=18.8%, FF=1.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.162129 grad_dist: 0.077241 +Info: iter=451 steplen=2.099002 a=227.853622 penalty=[1.70, 1.70, 1.70, 1.70] +Info: update_chains distance 461.25 +Info: system potential: 9902.566406 hpwl: 140011.531250 +Info: overlap: COMB=18.4%, FF=1.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161913 grad_dist: 0.076991 +Info: iter=452 steplen=2.103029 a=228.354172 penalty=[1.74, 1.74, 1.74, 1.74] +Info: update_chains distance 461.91 +Info: system potential: 9538.675781 hpwl: 140323.812500 +Info: overlap: COMB=18.1%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161786 grad_dist: 0.076729 +Info: iter=453 steplen=2.108548 a=228.854721 penalty=[1.79, 1.79, 1.79, 1.79] +Info: update_chains distance 462.48 +Info: system potential: 9133.239258 hpwl: 140578.937500 +Info: overlap: COMB=17.8%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161871 grad_dist: 0.076684 +Info: iter=454 steplen=2.110883 a=229.355270 penalty=[1.83, 1.83, 1.83, 1.83] +Info: update_chains distance 463.35 +Info: system potential: 8760.636719 hpwl: 140894.234375 +Info: overlap: COMB=17.4%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161743 grad_dist: 0.076727 +Info: iter=455 steplen=2.108043 a=229.855820 penalty=[1.88, 1.88, 1.88, 1.88] +Info: update_chains distance 463.91 +Info: system potential: 8430.484375 hpwl: 141135.718750 +Info: overlap: COMB=17.3%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.161242 grad_dist: 0.076449 +Info: iter=456 steplen=2.109155 a=230.356369 penalty=[1.92, 1.92, 1.92, 1.92] +Info: update_chains distance 464.53 +Info: system potential: 8101.475098 hpwl: 141441.859375 +Info: overlap: COMB=17.0%, FF=1.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.160544 grad_dist: 0.075857 +Info: iter=457 steplen=2.116397 a=230.856918 penalty=[1.97, 1.97, 1.97, 1.97] +Info: update_chains distance 465.08 +Info: system potential: 7765.088867 hpwl: 141703.937500 +Info: overlap: COMB=16.6%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159941 grad_dist: 0.075492 +Info: iter=458 steplen=2.118638 a=231.357468 penalty=[2.02, 2.02, 2.02, 2.02] +Info: update_chains distance 465.67 +Info: system potential: 7434.513672 hpwl: 142017.578125 +Info: overlap: COMB=16.3%, FF=1.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.159570 grad_dist: 0.075390 +Info: iter=459 steplen=2.116598 a=231.858002 penalty=[2.07, 2.07, 2.07, 2.07] +Info: update_chains distance 466.33 +Info: system potential: 7129.029785 hpwl: 142272.234375 +Info: overlap: COMB=16.1%, FF=1.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.158951 grad_dist: 0.075050 +Info: iter=460 steplen=2.117938 a=232.358536 penalty=[2.12, 2.12, 2.12, 2.12] +Info: update_chains distance 467.25 +Info: system potential: 6845.776855 hpwl: 142581.718750 +Info: overlap: COMB=15.8%, FF=1.1%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157981 grad_dist: 0.074435 +Info: iter=461 steplen=2.122388 a=232.859070 penalty=[2.18, 2.18, 2.18, 2.18] +Info: update_chains distance 468.16 +Info: system potential: 6588.242676 hpwl: 142842.734375 +Info: overlap: COMB=15.4%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.157232 grad_dist: 0.073915 +Info: iter=462 steplen=2.127196 a=233.359604 penalty=[2.23, 2.23, 2.23, 2.23] +Info: update_chains distance 469.41 +Info: system potential: 6301.302246 hpwl: 143155.875000 +Info: overlap: COMB=15.7%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156984 grad_dist: 0.073639 +Info: iter=463 steplen=2.131798 a=233.860138 penalty=[2.29, 2.29, 2.29, 2.29] +Info: update_chains distance 470.54 +Info: system potential: 6057.123535 hpwl: 143425.281250 +Info: overlap: COMB=15.4%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156727 grad_dist: 0.073522 +Info: iter=464 steplen=2.131715 a=234.360672 penalty=[2.34, 2.34, 2.34, 2.34] +Info: update_chains distance 471.61 +Info: system potential: 5776.902344 hpwl: 143725.671875 +Info: overlap: COMB=15.1%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.156326 grad_dist: 0.073320 +Info: iter=465 steplen=2.132102 a=234.861206 penalty=[2.40, 2.40, 2.40, 2.40] +Info: update_chains distance 472.30 +Info: system potential: 5557.244141 hpwl: 143986.046875 +Info: overlap: COMB=14.8%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.155186 grad_dist: 0.072834 +Info: iter=466 steplen=2.130677 a=235.361740 penalty=[2.46, 2.46, 2.46, 2.46] +Info: update_chains distance 473.63 +Info: system potential: 5319.213379 hpwl: 144268.250000 +Info: overlap: COMB=14.0%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.154075 grad_dist: 0.072111 +Info: iter=467 steplen=2.136635 a=235.862274 penalty=[2.52, 2.52, 2.52, 2.52] +Info: update_chains distance 474.89 +Info: system potential: 5082.393066 hpwl: 144528.281250 +Info: overlap: COMB=13.8%, FF=1.3%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153111 grad_dist: 0.071433 +Info: iter=468 steplen=2.143432 a=236.362808 penalty=[2.59, 2.59, 2.59, 2.59] +Info: update_chains distance 476.11 +Info: system potential: 4869.984863 hpwl: 144809.843750 +Info: overlap: COMB=13.4%, FF=1.2%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152972 grad_dist: 0.071160 +Info: iter=469 steplen=2.149685 a=236.863342 penalty=[2.65, 2.65, 2.65, 2.65] +Info: update_chains distance 476.98 +Info: system potential: 4643.716309 hpwl: 145067.109375 +Info: overlap: COMB=13.2%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153304 grad_dist: 0.071225 +Info: iter=470 steplen=2.152397 a=237.363861 penalty=[2.72, 2.72, 2.72, 2.72] +Info: update_chains distance 477.85 +Info: system potential: 4461.454590 hpwl: 145326.531250 +Info: overlap: COMB=13.0%, FF=0.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153390 grad_dist: 0.071300 +Info: iter=471 steplen=2.151330 a=237.864380 penalty=[2.79, 2.79, 2.79, 2.79] +Info: update_chains distance 478.07 +Info: system potential: 4268.108398 hpwl: 145554.406250 +Info: overlap: COMB=12.7%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153334 grad_dist: 0.071096 +Info: iter=472 steplen=2.156715 a=238.364914 penalty=[2.86, 2.86, 2.86, 2.86] +Info: update_chains distance 478.78 +Info: system potential: 4078.253174 hpwl: 145787.968750 +Info: overlap: COMB=12.5%, FF=0.9%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153043 grad_dist: 0.070766 +Info: iter=473 steplen=2.162667 a=238.865433 penalty=[2.93, 2.93, 2.93, 2.93] +Info: update_chains distance 479.41 +Info: system potential: 3917.518799 hpwl: 146010.359375 +Info: overlap: COMB=12.3%, FF=0.8%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152932 grad_dist: 0.070660 +Info: iter=474 steplen=2.164347 a=239.365952 penalty=[3.00, 3.00, 3.00, 3.00] +Info: update_chains distance 480.25 +Info: system potential: 3758.513428 hpwl: 146219.406250 +Info: overlap: COMB=11.9%, FF=0.6%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153350 grad_dist: 0.070560 +Info: iter=475 steplen=2.173333 a=239.866470 penalty=[3.07, 3.07, 3.07, 3.07] +Info: update_chains distance 481.13 +Info: system potential: 3619.491699 hpwl: 146431.187500 +Info: overlap: COMB=11.8%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153576 grad_dist: 0.070573 +Info: iter=476 steplen=2.176136 a=240.366989 penalty=[3.15, 3.15, 3.15, 3.15] +Info: update_chains distance 482.62 +Info: system potential: 3508.918945 hpwl: 146631.578125 +Info: overlap: COMB=11.5%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153543 grad_dist: 0.070685 +Info: iter=477 steplen=2.172205 a=240.867508 penalty=[3.23, 3.23, 3.23, 3.23] +Info: update_chains distance 483.21 +Info: system potential: 3374.741211 hpwl: 146804.765625 +Info: overlap: COMB=11.2%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.153227 grad_dist: 0.070396 +Info: iter=478 steplen=2.176660 a=241.368027 penalty=[3.31, 3.31, 3.31, 3.31] +Info: update_chains distance 484.26 +Info: system potential: 3255.671875 hpwl: 146994.984375 +Info: overlap: COMB=11.0%, FF=0.7%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152323 grad_dist: 0.069792 +Info: iter=479 steplen=2.182525 a=241.868546 penalty=[3.39, 3.39, 3.39, 3.39] +Info: update_chains distance 485.27 +Info: system potential: 3144.638672 hpwl: 147172.062500 +Info: overlap: COMB=10.9%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151657 grad_dist: 0.069385 +Info: iter=480 steplen=2.185716 a=242.369064 penalty=[3.48, 3.48, 3.48, 3.48] +Info: update_chains distance 486.61 +Info: system potential: 3011.866699 hpwl: 147366.593750 +Info: overlap: COMB=10.7%, FF=0.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151521 grad_dist: 0.069117 +Info: iter=481 steplen=2.192243 a=242.869583 penalty=[3.57, 3.57, 3.57, 3.57] +Info: update_chains distance 487.51 +Info: system potential: 2905.388428 hpwl: 147543.781250 +Info: overlap: COMB=10.4%, FF=0.4%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151530 grad_dist: 0.068924 +Info: iter=482 steplen=2.198524 a=243.370102 penalty=[3.65, 3.65, 3.65, 3.65] +Info: update_chains distance 489.26 +Info: system potential: 2802.557129 hpwl: 147748.046875 +Info: overlap: COMB=10.2%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.151931 grad_dist: 0.068858 +Info: iter=483 steplen=2.206452 a=243.870621 penalty=[3.75, 3.75, 3.75, 3.75] +Info: update_chains distance 490.59 +Info: system potential: 2689.866699 hpwl: 147929.328125 +Info: overlap: COMB=10.0%, FF=0.5%, RAM=0.0%, MUL=0.0% +Info: coord_dist: 0.152483 grad_dist: 0.068981 +Info: iter=484 steplen=2.210502 a=244.371124 penalty=[3.84, 3.84, 3.84, 3.84] +Info: update_chains distance 492.25 +Info: system potential: 2593.473633 hpwl: 148131.437500 +Info: overlap: COMB=10.0%, FF=0.6%, RAM=0.0%, MUL=0.0% +Info: Strict legalising 24792 cells... +Info: HPWL after legalise: 159214.000000 (delta: 11082.562500) + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 159011 +Info: at iteration #5: temp = 0.000000, timing cost = 0, wirelen = 148373 +Info: at iteration #10: temp = 0.000000, timing cost = 0, wirelen = 146766 +Info: at iteration #15: temp = 0.000000, timing cost = 0, wirelen = 146348 +Info: at iteration #20: temp = 0.000000, timing cost = 0, wirelen = 146242 +Info: at iteration #23: temp = 0.000000, timing cost = 0, wirelen = 146233 +Info: SA placement time 44.88s + +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) + +Info: Max delay -> posedge $glbnet$core_clk: 3.52 ns +Info: Max delay posedge $glbnet$core_clk -> : 9.48 ns + +Info: Slack histogram: +Info: legend: * represents 36 endpoint(s) +Info: + represents [1,36) endpoint(s) +Info: [ 25523, 29209) |***+ +Info: [ 29209, 32895) |+ +Info: [ 32895, 36581) | +Info: [ 36581, 40267) | +Info: [ 40267, 43953) | +Info: [ 43953, 47639) | +Info: [ 47639, 51325) | +Info: [ 51325, 55011) |+ +Info: [ 55011, 58697) |*********+ +Info: [ 58697, 62383) |**************************************+ +Info: [ 62383, 66069) |******************************+ +Info: [ 66069, 69755) |*******+ +Info: [ 69755, 73441) |*+ +Info: [ 73441, 77127) |*************+ +Info: [ 77127, 80813) |***************************************************+ +Info: [ 80813, 84499) |************************************************************ +Info: [ 84499, 88185) |******************************************************+ +Info: [ 88185, 91871) |**********************************+ +Info: [ 91871, 95557) |*****************+ +Info: [ 95557, 99243) |**+ +Info: Checksum: 0xd4f9c64c +Info: Routing globals... +Info: routing clock net $glbnet$core_clk using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 111218 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 0 999 | 0 999 | 110219| 2.07 2.07| +Info: 2000 | 0 1999 | 0 1000 | 109219| 0.40 2.47| +Info: 3000 | 0 2999 | 0 1000 | 108219| 0.42 2.90| +Info: 4000 | 3 3996 | 3 997 | 107224| 0.41 3.30| +Info: 5000 | 4 4995 | 1 999 | 106225| 0.41 3.72| +Info: 6000 | 16 5983 | 12 988 | 105277| 0.48 4.19| +Info: 7000 | 32 6967 | 16 984 | 104294| 0.42 4.62| +Info: 8000 | 53 7946 | 21 979 | 103333| 0.47 5.09| +Info: 9000 | 56 8943 | 3 997 | 102349| 0.40 5.49| +Info: 10000 | 66 9933 | 10 990 | 101382| 0.44 5.93| +Info: 11000 | 69 10930 | 3 997 | 100392| 0.41 6.33| +Info: 12000 | 78 11921 | 9 991 | 99410| 0.64 6.98| +Info: 13000 | 82 12917 | 4 996 | 98418| 0.46 7.44| +Info: 14000 | 93 13906 | 11 989 | 97435| 0.52 7.96| +Info: 15000 | 112 14887 | 19 981 | 96475| 0.55 8.51| +Info: 16000 | 125 15874 | 13 987 | 95495| 0.63 9.14| +Info: 17000 | 149 16850 | 24 976 | 94537| 0.55 9.69| +Info: 18000 | 173 17826 | 24 976 | 93583| 0.51 10.21| +Info: 19000 | 187 18812 | 14 986 | 92609| 0.54 10.74| +Info: 20000 | 217 19782 | 30 970 | 91682| 0.53 11.28| +Info: 21000 | 251 20748 | 34 966 | 90736| 0.70 11.98| +Info: 22000 | 308 21691 | 57 943 | 89903| 1.00 12.98| +Info: 23000 | 342 22657 | 34 966 | 88962| 0.66 13.64| +Info: 24000 | 408 23591 | 66 934 | 88119| 0.62 14.26| +Info: 25000 | 487 24512 | 79 921 | 87318| 0.84 15.10| +Info: 26000 | 575 25424 | 88 912 | 86561| 0.68 15.78| +Info: 27000 | 658 26341 | 83 917 | 85860| 0.63 16.40| +Info: 28000 | 768 27231 | 110 890 | 85094| 0.80 17.20| +Info: 29000 | 850 28149 | 82 918 | 84271| 0.62 17.83| +Info: 30000 | 987 29012 | 137 863 | 83573| 0.97 18.79| +Info: 31000 | 1104 29895 | 117 883 | 82891| 0.81 19.61| +Info: 32000 | 1194 30805 | 90 910 | 82097| 0.68 20.29| +Info: 33000 | 1312 31687 | 118 882 | 81364| 0.72 21.01| +Info: 34000 | 1398 32601 | 86 914 | 80496| 0.63 21.64| +Info: 35000 | 1530 33469 | 132 868 | 79771| 0.84 22.48| +Info: 36000 | 1683 34316 | 153 847 | 79110| 0.96 23.44| +Info: 37000 | 1794 35205 | 111 889 | 78356| 0.67 24.11| +Info: 38000 | 1948 36051 | 154 846 | 77671| 0.97 25.08| +Info: 39000 | 2112 36887 | 164 836 | 77049| 0.96 26.04| +Info: 40000 | 2309 37690 | 197 803 | 76517| 1.10 27.13| +Info: 41000 | 2405 38594 | 96 904 | 75710| 0.66 27.79| +Info: 42000 | 2575 39424 | 170 830 | 75021| 0.90 28.69| +Info: 43000 | 2741 40258 | 166 834 | 74388| 0.97 29.66| +Info: 44000 | 3006 40993 | 265 735 | 73977| 1.24 30.91| +Info: 45000 | 3109 41890 | 103 897 | 73144| 0.74 31.65| +Info: 46000 | 3220 42779 | 111 889 | 72327| 0.77 32.42| +Info: 47000 | 3404 43595 | 184 816 | 71645| 0.87 33.29| +Info: 48000 | 3543 44456 | 139 861 | 70931| 0.73 34.02| +Info: 49000 | 3679 45320 | 136 864 | 70198| 0.90 34.92| +Info: 50000 | 3893 46031 | 214 711 | 69611| 1.04 35.96| +Info: 51000 | 4183 46715 | 290 684 | 69286| 1.53 37.49| +Info: 52000 | 4280 47527 | 97 812 | 68466| 0.79 38.27| +Info: 53000 | 4484 48289 | 204 762 | 67948| 1.10 39.37| +Info: 54000 | 4673 49094 | 189 805 | 67375| 1.38 40.75| +Info: 55000 | 4780 49966 | 107 872 | 66588| 0.87 41.62| +Info: 56000 | 4895 50849 | 115 883 | 65765| 0.92 42.55| +Info: 57000 | 5238 51502 | 343 653 | 65489| 2.25 44.80| +Info: 58000 | 5460 52273 | 222 771 | 64954| 1.40 46.20| +Info: 59000 | 5598 53123 | 138 850 | 64153| 0.89 47.09| +Info: 60000 | 5814 53902 | 216 779 | 63562| 1.08 48.18| +Info: 61000 | 5994 54722 | 180 820 | 62859| 0.95 49.13| +Info: 62000 | 6216 55496 | 222 774 | 62305| 1.23 50.35| +Info: 63000 | 6365 56345 | 149 849 | 61528| 0.87 51.23| +Info: 64000 | 6482 57222 | 117 877 | 60822| 0.84 52.07| +Info: 65000 | 6670 58030 | 188 808 | 60269| 0.96 53.02| +Info: 66000 | 6821 58872 | 151 842 | 59576| 0.97 53.99| +Info: 67000 | 6967 59707 | 146 835 | 58793| 0.76 54.76| +Info: 68000 | 7138 60497 | 171 790 | 58132| 0.95 55.70| +Info: 69000 | 7304 61284 | 166 787 | 57353| 0.87 56.57| +Info: 70000 | 7556 61988 | 252 704 | 56847| 1.49 58.06| +Info: 71000 | 8015 62529 | 459 541 | 56915| 2.76 60.82| +Info: 72000 | 8317 63199 | 302 670 | 56447| 1.52 62.34| +Info: 73000 | 8431 64022 | 114 823 | 55623| 0.66 62.99| +Info: 74000 | 8686 64735 | 255 713 | 55061| 1.39 64.38| +Info: 75000 | 8837 65563 | 151 828 | 54405| 1.01 65.39| +Info: 76000 | 9067 66307 | 230 744 | 53811| 1.25 66.64| +Info: 77000 | 9233 67105 | 166 798 | 53038| 0.82 67.47| +Info: 78000 | 9343 67987 | 110 882 | 52242| 0.90 68.37| +Info: 79000 | 9554 68769 | 211 782 | 51762| 1.30 69.67| +Info: 80000 | 9741 69573 | 187 804 | 51029| 1.04 70.72| +Info: 81000 | 9872 70430 | 131 857 | 50254| 0.86 71.57| +Info: 82000 | 10174 71122 | 302 692 | 49835| 1.99 73.56| +Info: 83000 | 10436 71845 | 262 723 | 49406| 1.66 75.22| +Info: 84000 | 10577 72695 | 141 850 | 48657| 1.07 76.29| +Info: 85000 | 10728 73538 | 151 843 | 47963| 1.11 77.40| +Info: 86000 | 10824 74437 | 96 899 | 47191| 0.71 78.11| +Info: 87000 | 10897 75359 | 73 922 | 46280| 0.52 78.64| +Info: 88000 | 10970 76278 | 73 919 | 45410| 0.54 79.17| +Info: 89000 | 11111 77130 | 141 852 | 44600| 0.74 79.91| +Info: 90000 | 11225 77964 | 114 834 | 43717| 0.57 80.49| +Info: 91000 | 11336 78792 | 111 828 | 42863| 0.66 81.15| +Info: 92000 | 11489 79530 | 153 738 | 42057| 0.67 81.82| +Info: 93000 | 11805 80214 | 316 684 | 42030| 2.17 83.99| +Info: 94000 | 12016 80923 | 211 709 | 41309| 0.96 84.95| +Info: 95000 | 12251 81655 | 235 732 | 40713| 1.31 86.27| +Info: 96000 | 12442 82418 | 191 763 | 39952| 0.78 87.05| +Info: 97000 | 12629 83199 | 187 781 | 39171| 0.77 87.82| +Info: 98000 | 13104 83724 | 475 525 | 39187| 2.96 90.78| +Info: 99000 | 13445 84369 | 341 645 | 38741| 1.98 92.76| +Info: 100000 | 13827 84983 | 382 614 | 38519| 2.28 95.04| +Info: 101000 | 14150 85653 | 323 670 | 38049| 1.54 96.58| +Info: 102000 | 14415 86376 | 265 723 | 37521| 1.39 97.97| +Info: 103000 | 14637 87120 | 222 744 | 36847| 1.26 99.23| +Info: 104000 | 14738 87971 | 101 851 | 35950| 0.58 99.81| +Info: 105000 | 14803 88803 | 65 832 | 35027| 0.53 100.34| +Info: 106000 | 14904 89643 | 101 840 | 34215| 0.86 101.20| +Info: 107000 | 14964 90474 | 60 831 | 33293| 0.64 101.84| +Info: 108000 | 15033 91322 | 69 848 | 32379| 0.59 102.42| +Info: 109000 | 15094 92200 | 61 878 | 31515| 0.59 103.01| +Info: 110000 | 15165 93038 | 71 838 | 30623| 0.63 103.65| +Info: 111000 | 15250 93825 | 85 787 | 29742| 0.63 104.28| +Info: 112000 | 15334 94563 | 84 738 | 28858| 0.67 104.95| +Info: 113000 | 15416 95303 | 82 740 | 27995| 0.57 105.52| +Info: 114000 | 15472 96069 | 56 766 | 27071| 0.52 106.04| +Info: 115000 | 15537 96894 | 65 825 | 26137| 0.52 106.56| +Info: 116000 | 15595 97710 | 58 816 | 25215| 0.52 107.08| +Info: 117000 | 15659 98505 | 64 795 | 24279| 0.54 107.62| +Info: 118000 | 15729 99299 | 70 794 | 23358| 0.67 108.29| +Info: 119000 | 15787 100125 | 58 826 | 22420| 0.50 108.79| +Info: 120000 | 15852 100956 | 65 831 | 21678| 0.58 109.37| +Info: 121000 | 15937 101754 | 85 798 | 20813| 0.65 110.02| +Info: 122000 | 16005 102629 | 68 875 | 19901| 0.61 110.62| +Info: 123000 | 16086 103514 | 81 885 | 18988| 0.60 111.23| +Info: 124000 | 16190 104389 | 104 875 | 18111| 0.67 111.90| +Info: 125000 | 16291 105194 | 101 805 | 17235| 0.65 112.55| +Info: 126000 | 16376 105980 | 85 786 | 16331| 0.63 113.19| +Info: 127000 | 16504 106762 | 128 782 | 15495| 0.79 113.98| +Info: 128000 | 16607 107604 | 103 842 | 14604| 0.69 114.67| +Info: 129000 | 16726 108424 | 119 820 | 13730| 0.69 115.36| +Info: 130000 | 16825 109281 | 99 857 | 12833| 0.66 116.02| +Info: 131000 | 16904 110145 | 79 864 | 11912| 0.60 116.61| +Info: 132000 | 17032 110980 | 128 835 | 11063| 0.73 117.35| +Info: 133000 | 17110 111881 | 78 901 | 10149| 0.66 118.00| +Info: 134000 | 17163 112749 | 53 868 | 9209| 0.58 118.59| +Info: 135000 | 17237 113573 | 74 824 | 8294| 0.57 119.15| +Info: 136000 | 17304 114453 | 67 880 | 7372| 0.56 119.71| +Info: 137000 | 17531 115226 | 227 773 | 6744| 1.18 120.89| +Info: 138000 | 17793 115964 | 262 738 | 6018| 0.81 121.70| +Info: 139000 | 18042 116715 | 249 751 | 5287| 0.76 122.46| +Info: 140000 | 18340 117417 | 298 702 | 4783| 1.31 123.77| +Info: 141000 | 18603 118154 | 263 737 | 4109| 0.93 124.70| +Info: 142000 | 18878 118879 | 275 725 | 3492| 1.04 125.74| +Info: 143000 | 19135 119622 | 257 743 | 2775| 0.77 126.51| +Info: 144000 | 19407 120350 | 272 728 | 2048| 0.70 127.21| +Info: 145000 | 19638 121113 | 231 763 | 1282| 0.66 127.87| +Info: 146000 | 19645 121745 | 7 632 | 291| 0.43 128.29| +Info: 146290 | 19645 121917 | 0 172 | 0| 0.34 128.64| +Info: Routing complete. +Info: Router1 time 128.64s +Info: Checksum: 0x323f3232 + +Info: Critical path report for clock '$glbnet$core_clk' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_TRELLIS_FF_Q.Q +Info: routing 5.85 6.37 Net bridge.por_shift[7] (9,8) -> (32,83) +Info: Sink bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_LUT4_D.D +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: uart_tx.sv:11.23-11.28 +Info: uart_bridge.sv:59.7-66.6 +Info: logic 0.24 6.61 Source bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.rst_n_LUT4_D.F +Info: routing 2.64 9.25 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_D[0] (32,83) -> (76,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 9.49 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.F +Info: routing 1.20 10.69 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_COUT_CCU2C_CIN_S0_PFUMX_Z_BLUT_LUT4_Z_B[1] (76,77) -> (80,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B.B +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 10.92 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B.F +Info: routing 0.00 10.92 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_B_Z (80,77) -> (80,77) +Info: Sink bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C.F1 +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:133.22-133.24 +Info: logic 0.17 11.09 Source bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C.OFX +Info: routing 1.16 12.24 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_A1_S0_LUT4_Z_C_PFUMX_Z_C0[3] (80,77) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 12.69 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.69 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.69 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.69 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.76 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.76 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.83 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.83 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (81,74) -> (81,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.83 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.83 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (81,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.90 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.90 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 12.98 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 12.98 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 12.98 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 12.98 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 13.05 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 13.05 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 13.05 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 13.05 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:74.29-74.45 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: uart_bridge.sv:172.31-176.14 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 13.12 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 13.12 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (82,74) -> (82,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 13.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 1.38 14.90 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0[0] (82,74) -> (85,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 15.35 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 15.35 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN (85,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 15.42 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 15.42 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 15.42 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 15.42 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0_CIN (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 15.86 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.22 16.08 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_A1_LUT4_Z_D[1] (86,73) -> (86,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 16.32 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.91 17.23 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (86,73) -> (87,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 17.67 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 17.67 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1_CIN (87,72) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 17.75 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 17.75 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_FCI_INT (88,72) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 18.15 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 1.14 19.29 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_S0[1] (88,72) -> (86,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 19.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 1.03 20.56 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1[1] (86,74) -> (85,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 21.00 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 21.00 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (85,74) -> (85,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 21.00 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 21.00 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (85,74) -> (86,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 21.44 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 22.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (86,74) -> (85,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 22.61 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.88 23.49 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (85,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 23.94 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 23.94 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (84,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 24.01 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 24.01 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (84,75) -> (84,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 24.41 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.80 25.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_S0[1] (84,75) -> (85,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 25.44 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 0.89 26.34 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[1] (85,75) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 26.78 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 26.78 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (85,76) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 26.78 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 26.78 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (85,76) -> (85,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 27.23 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.80 28.02 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (85,76) -> (86,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 28.26 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0_LUT4_Z.F +Info: routing 1.03 29.29 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A0[1] (86,76) -> (88,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 29.73 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 29.73 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (88,76) -> (88,76) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 30.14 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.67 30.80 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (88,76) -> (87,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 31.04 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 1.04 32.08 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[1] (87,75) -> (89,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 32.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 32.53 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (89,75) -> (89,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 32.97 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.66 33.63 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (89,75) -> (90,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 33.87 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 0.89 34.76 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (90,75) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 35.21 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 35.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (90,74) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 35.28 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 35.28 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (90,74) -> (90,74) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 35.68 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.88 36.56 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (90,74) -> (90,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 36.79 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z.F +Info: routing 1.12 37.91 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[1] (90,73) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 38.36 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 38.36 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_FCI_INT (90,71) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 38.36 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 38.36 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (90,71) -> (90,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 38.80 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 39.73 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_A1_LUT4_Z_C[2] (90,71) -> (89,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 39.97 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_Z.F +Info: routing 1.12 41.09 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1[1] (89,72) -> (88,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 41.53 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 41.53 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN (88,73) -> (89,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 41.61 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 41.61 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_FCI_INT (89,73) -> (89,73) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.40 42.01 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1$CCU2_COMB1.F +Info: routing 0.93 42.94 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[1] (89,73) -> (88,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 43.18 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 1.12 44.30 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1[1] (88,72) -> (84,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.45 44.75 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 44.75 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN (84,72) -> (85,72) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.44 45.19 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.93 46.12 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[2] (85,72) -> (87,71) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 46.35 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C.F +Info: routing 0.87 47.22 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z (87,71) -> (87,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1$CCU2_COMB1.B +Info: logic 0.45 47.67 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1$CCU2_COMB1.FCO +Info: routing 0.00 47.67 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT (87,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.74 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.74 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.74 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.74 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.81 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.81 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.81 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.81 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.88 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.88 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.88 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.88 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 47.96 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 47.96 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (88,69) -> (88,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 47.96 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 47.96 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (88,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.03 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.03 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.03 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.03 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.10 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.10 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.10 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.10 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.17 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.17 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.17 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.17 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.24 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (89,69) -> (89,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.24 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (89,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.31 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.31 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.31 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.31 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.38 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.45 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.45 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.45 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.45 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.52 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (90,69) -> (90,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.52 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.52 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (90,69) -> (91,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /usr/bin/../share/yosys/techmap.v:331.28-331.64 +Info: /usr/bin/../share/yosys/techmap.v:368.4-373.3 +Info: /usr/bin/../share/yosys/techmap.v:428.4-432.3 +Info: uart_bridge.sv:172.31-176.14 +Info: ../../asic_core/rtl/lsc1_packet_frontend.sv:272.31-307.6 +Info: ../../asic_core/rtl/lsc1_response_payload_mux.sv:75.22-75.43 +Info: ../../asic_core/rtl/lean_silicon_lsc1.sv:14.26-19.6 +Info: ulx3s_packet_top.sv:14.60-17.6 +Info: /usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4 +Info: /usr/bin/../share/yosys/ecp5/cells_sim.v:82.9-82.13 +Info: logic 0.07 48.59 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO +Info: routing 0.00 48.59 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (91,69) -> (91,69) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI +Info: logic 0.00 48.59 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO +Info: routing 0.00 48.59 Net $nextpnr_CCU2C_145$CIN (91,69) -> (91,69) +Info: Sink $nextpnr_CCU2C_145$CCU2_COMB0.FCI +Info: logic 0.44 49.04 Source $nextpnr_CCU2C_145$CCU2_COMB0.F +Info: routing 1.11 50.15 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT[6] (91,69) -> (97,64) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_C.D +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 50.38 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_3_D_LUT4_Z_A_LUT4_Z_C_LUT4_C_1_Z_CCU2C_S0_CIN_CCU2C_COUT_S0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S0_CIN_CCU2C_COUT_A1_LUT4_C_Z_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_C.F +Info: routing 2.47 52.85 Net bridge.g_packet.asic.packet_core.last_status_TRELLIS_FF_Q_7_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_CCU2C_S0_S1_PFUMX_Z_BLUT_LUT4_Z_B_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_PFUMX_C0_Z[5] (97,64) -> (77,50) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 53.11 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 1.11 54.21 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z_C[1] (77,50) -> (77,53) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z.C +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 54.45 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_Z.F +Info: routing 1.69 56.14 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_SD[5] (77,53) -> (81,63) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 56.40 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.65 57.05 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_SD[5] (81,63) -> (82,66) +Info: Sink bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 57.31 Source bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 1.67 58.98 Net bridge.g_packet.asic.packet_core.staged_write_count_LUT4_A_Z_LUT4_Z_2_B_LUT4_B_2_Z[6] (82,66) -> (72,75) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 59.24 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.97 60.21 Net bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] (72,75) -> (73,78) +Info: Sink bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_A.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 60.47 Source bridge.g_packet.asic.packet_core.state_valid_LUT4_A_Z_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_C_Z_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_D_2_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_A.OFX +Info: routing 0.97 61.44 Net bridge.tx_data_q_TRELLIS_FF_Q_2_DI_LUT4_Z_C[4] (73,78) -> (71,81) +Info: Sink bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 61.69 Source bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 1.23 62.93 Net bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (71,81) -> (69,88) +Info: Sink bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C.C +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.24 63.16 Source bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C.F +Info: routing 0.94 64.11 Net bridge.tx_data_q_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_Z[5] (69,88) -> (67,86) +Info: Sink bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI_PFUMX_Z_BLUT_LUT4_Z.M +Info: Defined in: +Info: /usr/bin/../share/yosys/ecp5/cells_map.v:108.23-108.24 +Info: logic 0.26 64.36 Source bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.92 65.28 Net bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8_DI (67,86) -> (67,85) +Info: Sink bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8.M +Info: setup 0.00 65.28 Source bridge.g_packet.asic.packet_core.transmitter.payload_crc_TRELLIS_FF_Q_8.M +Info: 19.53 ns logic, 45.75 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$core_clk': +Info: type curr total name +Info: source 0.00 0.00 Source uart_rx$tr_io.O +Info: routing 2.30 2.30 Net uart_rx$TRELLIS_IO_IN (0,89) -> (33,89) +Info: Sink bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: Defined in: +Info: ulx3s_packet_top.sv:6.17-6.24 +Info: setup 0.00 2.30 Source bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: 0.00 ns logic, 2.30 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$core_clk' -> '': +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source bridge.utx.tx_serial_TRELLIS_FF_Q.Q +Info: routing 5.74 6.27 Net uart_tx$TRELLIS_IO_OUT (65,87) -> (0,56) +Info: Sink uart_tx$tr_io.I +Info: Defined in: +Info: ulx3s_packet_top.sv:7.17-7.24 +Info: 0.52 ns logic, 5.74 ns routing + +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) + +Info: Max delay -> posedge $glbnet$core_clk: 2.30 ns +Info: Max delay posedge $glbnet$core_clk -> : 6.27 ns + +Info: Slack histogram: +Info: legend: * represents 44 endpoint(s) +Info: + represents [1,44) endpoint(s) +Info: [ 34721, 37938) |**+ +Info: [ 37938, 41155) |+ +Info: [ 41155, 44372) | +Info: [ 44372, 47589) | +Info: [ 47589, 50806) | +Info: [ 50806, 54023) | +Info: [ 54023, 57240) | +Info: [ 57240, 60457) | +Info: [ 60457, 63674) |****+ +Info: [ 63674, 66891) |*************+ +Info: [ 66891, 70108) |******************+ +Info: [ 70108, 73325) |*****************************+ +Info: [ 73325, 76542) |******+ +Info: [ 76542, 79759) |+ +Info: [ 79759, 82976) |*************+ +Info: [ 82976, 86193) |**********************************+ +Info: [ 86193, 89410) |************************************************************ +Info: [ 89410, 92627) |**********************************************+ +Info: [ 92627, 95844) |********************************+ +Info: [ 95844, 99061) |**+ + +Info: Program finished normally. diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/timing.txt b/evidence/lsc1-09-cleanroom/clean-build-2/timing.txt new file mode 100644 index 00000000..a3a0974f --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/timing.txt @@ -0,0 +1,6 @@ +Info: Input frequency of PLL 'core_pll.pll_i' is constrained to 25.0 MHz +Info: Derived frequency constraint of 10.0 MHz for net core_clk +Info: Max frequency for clock '$glbnet$core_clk': 13.43 MHz (PASS at 10.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz) +Info: Slack histogram: diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/tool_versions.txt b/evidence/lsc1-09-cleanroom/clean-build-2/tool_versions.txt new file mode 100644 index 00000000..a7f82e9c --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/tool_versions.txt @@ -0,0 +1,5 @@ +=== TOOL VERSIONS (LSC-1 PACKET UART) === +Yosys 0.33 (git sha1 2584903a060) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.11.1) +Project Trellis ecppack Version 1.4-2build4 +date: 2026-09-06T00:58:29Z diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.bit b/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.bit new file mode 100644 index 0000000000000000000000000000000000000000..c4a699369d754237f7a4bddbd39be7a8d45f67df GIT binary patch literal 1927725 zcmeFa37i~9c{cubZ_jM+cx8H5BY7-@sTr@nmO-4U8I9zTEMO#LFa*d*UW055 zNV3Uia@LMk@>&R32?549VI+hjJ0^%L2f0SV*ut0~bA=>?D3I`lBpf+N@<9^+pX%8j z?P|BXdYo$iouBH}s=K!-g@hZ{j1>$z*nm21jZ ztzJowKmPb1eiDbrUr0pX#{cqAX-xrVj{ocMzj@%QAK>&9k}p5<_)`cCpuFBPfTB~x zFci&?(IFK-h9Sd{ngP`v#ts>VR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-x zR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!XjSd-xR1B!X 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zUta?utBj|l`cU2XHe8&*`$Dw_Z5b|WCd-g{IkLn7RSTjH3wgCR3Jg?}hTfKBplb20 zM2My%{L1=b|9_6l>O+g5M+RP(;e*H+g=_4}mxziM=eQ5G$kI-7)C8paP}(+uo#S lNy*|LH6LsJtpN_u`? literal 0 HcmV?d00001 diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.config b/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.config new file mode 100644 index 00000000..0b0dc4d2 --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.config @@ -0,0 +1,496803 @@ +.device LFE5U-85F + +.comment Part: LFE5U-85F-6CABGA381 + +.tile CIB_R10C39:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C40:CIB_DSP +arc: N1_V02N0501 S1_V02N0401 + +.tile CIB_R10C41:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R10C42:CIB_DSP +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 N1_V02S0301 + +.tile CIB_R10C43:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 V01N0001 + +.tile CIB_R10C44:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 + +.tile CIB_R10C45:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R10C46:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R10C47:CIB_DSP +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 + +.tile CIB_R10C48:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 V01N0001 + +.tile CIB_R10C49:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 S1_V02N0201 + +.tile CIB_R10C50:CIB_DSP +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0401 V01N0001 + +.tile CIB_R10C51:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R10C52:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 + +.tile CIB_R10C54:CIB_DSP +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R10C7:CIB_DSP +arc: N1_V02N0201 N3_V06S0103 + +.tile CIB_R11C1:CIB_LR +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R13C1:CIB_LR +arc: N1_V02N0301 S3_V06N0003 + +.tile CIB_R17C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R19C1:CIB_LR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R22C100:CIB_EBR +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 + +.tile CIB_R22C101:CIB_EBR +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C102:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R22C103:CIB_EBR +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R22C104:CIB_EBR +arc: E1_H02E0301 V06N0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R22C105:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 E3_H06W0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R22C106:CIB_EBR +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R22C107:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R22C108:CIB_EBR +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R22C109:CIB_EBR +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R22C110:CIB_EBR +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C111:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R22C112:CIB_EBR +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C113:CIB_EBR +arc: W3_H06W0103 V06N0103 + +.tile CIB_R22C14:CIB_EBR +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 + +.tile CIB_R22C16:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R22C18:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0201 N1_V02S0701 + +.tile CIB_R22C19:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R22C20:CIB_EBR +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 + +.tile CIB_R22C21:CIB_EBR +arc: N1_V02N0501 H02W0501 + +.tile CIB_R22C22:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 S3_V06N0303 + +.tile CIB_R22C23:CIB_EBR +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 + +.tile CIB_R22C24:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 + +.tile CIB_R22C25:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R22C33:CIB_EBR +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0100 N3_V06S0303 + +.tile CIB_R22C34:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C35:CIB_EBR +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 + +.tile CIB_R22C36:CIB_EBR +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0401 N3_V06S0203 + +.tile CIB_R22C37:CIB_EBR +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 + +.tile CIB_R22C38:CIB_EBR +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N1_V01S0000 + +.tile CIB_R22C39:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 + +.tile CIB_R22C40:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C41:CIB_EBR +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R22C42:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 + +.tile CIB_R22C43:CIB_EBR +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06E0303 + +.tile CIB_R22C44:CIB_EBR +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R22C45:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R22C46:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R22C47:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R22C48:CIB_EBR +arc: E1_H02E0001 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R22C49:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R22C50:CIB_EBR +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 + +.tile CIB_R22C51:CIB_EBR +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R22C52:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R22C53:CIB_EBR +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 + +.tile CIB_R22C54:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0401 S3_V06N0203 + +.tile CIB_R22C55:CIB_EBR +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R22C56:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 V06S0003 + +.tile CIB_R22C57:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R22C58:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R22C59:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C60:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C61:CIB_EBR +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R22C62:CIB_EBR +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C63:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0201 V02S0201 + +.tile CIB_R22C64:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C65:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C66:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C67:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R22C68:CIB_EBR +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C69:CIB_EBR +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R22C70:CIB_EBR +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C71:CIB_EBR +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C72:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C73:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R22C74:CIB_EBR +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C75:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E1_H02W0301 + +.tile CIB_R22C76:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C77:CIB_EBR +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 + +.tile CIB_R22C78:CIB_EBR +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R22C79:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V01N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R22C80:CIB_EBR +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V02S0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 V01N0101 + +.tile CIB_R22C81:CIB_EBR +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R22C82:CIB_EBR +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 + +.tile CIB_R22C83:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R22C84:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R22C85:CIB_EBR +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R22C86:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R22C87:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 + +.tile CIB_R22C88:CIB_EBR +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 + +.tile CIB_R22C89:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R22C90:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0401 E3_H06W0203 + +.tile CIB_R22C91:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E3_H06W0303 + +.tile CIB_R22C92:CIB_EBR +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C93:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 + +.tile CIB_R22C94:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C95:CIB_EBR +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 + +.tile CIB_R22C96:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C97:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C98:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R22C99:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R23C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R25C1:CIB_LR +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R29C1:CIB_LR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R31C1:CIB_LR +arc: N3_V06N0203 S1_V02N0701 + +.tile CIB_R33C1:CIB_LR +arc: N1_V02N0701 E1_H02W0701 + +.tile CIB_R34C100:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C101:CIB_DSP +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C102:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C103:CIB_DSP +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R34C104:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C105:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R34C106:CIB_DSP +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R34C107:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C108:CIB_DSP +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R34C109:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C110:CIB_DSP +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R34C111:CIB_DSP +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C112:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C113:CIB_DSP +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C114:CIB_DSP +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0401 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R34C115:CIB_DSP +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 + +.tile CIB_R34C116:CIB_DSP +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0201 S3_V06N0103 + +.tile CIB_R34C14:CIB_DSP +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 N1_V02S0501 + +.tile CIB_R34C15:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R34C16:CIB_DSP +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0301 N1_V01S0100 + +.tile CIB_R34C17:CIB_DSP +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 + +.tile CIB_R34C18:CIB_DSP +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0601 + +.tile CIB_R34C19:CIB_DSP +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R34C20:CIB_DSP +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R34C21:CIB_DSP +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C22:CIB_DSP +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R34C23:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 + +.tile CIB_R34C24:CIB_DSP +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R34C25:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 + +.tile CIB_R34C26:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 E1_H02W0401 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R34C27:CIB_DSP +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H02E0601 + +.tile CIB_R34C28:CIB_DSP +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R34C29:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R34C30:CIB_DSP +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 + +.tile CIB_R34C31:CIB_DSP +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0101 H02W0101 + +.tile CIB_R34C32:CIB_DSP +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C33:CIB_DSP +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0103 N3_V06S0103 + +.tile CIB_R34C34:CIB_DSP +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 + +.tile CIB_R34C35:CIB_DSP +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R34C36:CIB_DSP +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R34C37:CIB_DSP +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C38:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R34C39:CIB_DSP +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 + +.tile CIB_R34C40:CIB_DSP +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C41:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R34C42:CIB_DSP +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C43:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R34C44:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N3_V06S0303 + +.tile CIB_R34C45:CIB_DSP +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C46:CIB_DSP +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 + +.tile CIB_R34C47:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C48:CIB_DSP +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C49:CIB_DSP +arc: E1_H02E0601 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R34C50:CIB_DSP +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R34C51:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R34C52:CIB_DSP +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R34C53:CIB_DSP +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R34C54:CIB_DSP +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R34C55:CIB_DSP +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R34C56:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R34C57:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 + +.tile CIB_R34C58:CIB_DSP +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 + +.tile CIB_R34C59:CIB_DSP +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R34C60:CIB_DSP +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 + +.tile CIB_R34C61:CIB_DSP +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C62:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R34C63:CIB_DSP +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0601 H06E0303 + +.tile CIB_R34C64:CIB_DSP +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R34C65:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0301 V06S0003 + +.tile CIB_R34C66:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R34C67:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C68:CIB_DSP +arc: E1_H02E0001 V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 V01N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C69:CIB_DSP +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C70:CIB_DSP +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R34C71:CIB_DSP +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C72:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 + +.tile CIB_R34C73:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C74:CIB_DSP +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R34C75:CIB_DSP +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C76:CIB_DSP +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R34C77:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C78:CIB_DSP +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R34C79:CIB_DSP +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R34C80:CIB_DSP +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R34C81:CIB_DSP +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 V02S0501 + +.tile CIB_R34C82:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R34C83:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile CIB_R34C84:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02W0701 + +.tile CIB_R34C85:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R34C86:CIB_DSP +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R34C87:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R34C88:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 + +.tile CIB_R34C89:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02S0501 + +.tile CIB_R34C90:CIB_DSP +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 + +.tile CIB_R34C91:CIB_DSP +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R34C92:CIB_DSP +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R34C93:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R34C94:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H01W0000 + +.tile CIB_R34C95:CIB_DSP +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C96:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 + +.tile CIB_R34C97:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C98:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R34C99:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R35C1:CIB_LR +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 + +.tile CIB_R37C1:CIB_LR +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R3C1:CIB_LR +arc: V01S0100 S3_V06N0303 + +.tile CIB_R41C1:CIB_LR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R46C100:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C101:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R46C102:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R46C103:CIB_EBR +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C104:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C105:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C106:CIB_EBR +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R46C107:CIB_EBR +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06S0203 + +.tile CIB_R46C108:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C109:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R46C110:CIB_EBR +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R46C111:CIB_EBR +arc: N1_V02N0601 V01N0001 + +.tile CIB_R46C112:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S1_V02N0201 + +.tile CIB_R46C113:CIB_EBR +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R46C116:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R46C20:CIB_EBR +arc: N1_V02N0201 N3_V06S0103 + +.tile CIB_R46C21:CIB_EBR +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 + +.tile CIB_R46C22:CIB_EBR +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C23:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R46C24:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 + +.tile CIB_R46C25:CIB_EBR +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R46C26:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R46C27:CIB_EBR +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 + +.tile CIB_R46C28:CIB_EBR +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 + +.tile CIB_R46C29:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R46C30:CIB_EBR +arc: N1_V02N0301 H02E0301 + +.tile CIB_R46C31:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 + +.tile CIB_R46C32:CIB_EBR +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 + +.tile CIB_R46C33:CIB_EBR +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H02W0601 + +.tile CIB_R46C34:CIB_EBR +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C35:CIB_EBR +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 V01N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C36:CIB_EBR +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R46C37:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R46C38:CIB_EBR +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0701 N3_V06S0203 + +.tile CIB_R46C39:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 N3_V06S0003 + +.tile CIB_R46C40:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C41:CIB_EBR +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 + +.tile CIB_R46C42:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C43:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R46C44:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C45:CIB_EBR +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R46C46:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C47:CIB_EBR +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R46C48:CIB_EBR +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C49:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R46C50:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C51:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C52:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0501 V02N0501 + +.tile CIB_R46C53:CIB_EBR +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R46C54:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 + +.tile CIB_R46C55:CIB_EBR +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 + +.tile CIB_R46C56:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C57:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 + +.tile CIB_R46C58:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C59:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C60:CIB_EBR +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 + +.tile CIB_R46C61:CIB_EBR +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R46C62:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C63:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0601 + +.tile CIB_R46C64:CIB_EBR +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R46C65:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C66:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E1_H02W0001 + +.tile CIB_R46C67:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C68:CIB_EBR +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C69:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V01S0000 S3_V06N0103 + +.tile CIB_R46C70:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0601 S3_V06N0303 + +.tile CIB_R46C71:CIB_EBR +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 + +.tile CIB_R46C72:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 + +.tile CIB_R46C73:CIB_EBR +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R46C74:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C75:CIB_EBR +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 V01N0101 + +.tile CIB_R46C76:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W3_H06E0303 + +.tile CIB_R46C77:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02N0601 + +.tile CIB_R46C78:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 + +.tile CIB_R46C79:CIB_EBR +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C80:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C81:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C82:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R46C83:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 + +.tile CIB_R46C84:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V01N0101 + +.tile CIB_R46C85:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 V02N0601 + +.tile CIB_R46C86:CIB_EBR +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R46C87:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C88:CIB_EBR +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0701 W3_H06E0203 + +.tile CIB_R46C89:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R46C90:CIB_EBR +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R46C91:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0003 + +.tile CIB_R46C92:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R46C93:CIB_EBR +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C94:CIB_EBR +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C95:CIB_EBR +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R46C96:CIB_EBR +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0201 + +.tile CIB_R46C97:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R46C98:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R46C99:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R47C1:CIB_LR +arc: N3_V06N0303 JF5 + +.tile CIB_R4C1:CIB_PLL0 +arc: E3_H06E0103 JQ2 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: JA4 N1_V01S0100 +arc: JB1 V02N0301 +arc: JB4 E1_H02W0301 +arc: JC2 H00L0000 +arc: JC4 V00T0000 +arc: JCLK1 V02N0701 +arc: JD2 V02N0001 +arc: JD3 H00R0000 +arc: JD4 V02N0401 +arc: JLSR0 V00B0100 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: PLLCSOUT_PLLREFCS CLK1_PLLREFCS + +.tile CIB_R58C100:CIB_DSP +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 V01N0001 + +.tile CIB_R58C101:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C107:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 + +.tile CIB_R58C110:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C113:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C116:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R58C1:CIB_LR_S +arc: JA0 H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R58C22:CIB_DSP +arc: N3_V06N0203 E3_H06W0203 + +.tile CIB_R58C23:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R58C25:CIB_DSP +arc: N3_V06N0203 H06W0203 + +.tile CIB_R58C26:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R58C28:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C29:CIB_DSP +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0701 V06N0203 + +.tile CIB_R58C2:CIB_DSP +arc: W1_H02W0501 N1_V01S0100 + +.tile CIB_R58C30:CIB_DSP +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 + +.tile CIB_R58C31:CIB_DSP +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0601 E3_H06W0303 + +.tile CIB_R58C32:CIB_DSP +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R58C33:CIB_DSP +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 + +.tile CIB_R58C34:CIB_DSP +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R58C35:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R58C36:CIB_DSP +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 V06N0203 + +.tile CIB_R58C37:CIB_DSP +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C38:CIB_DSP +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0103 V06S0103 + +.tile CIB_R58C39:CIB_DSP +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C40:CIB_DSP +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C41:CIB_DSP +arc: E1_H02E0201 S3_V06N0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C42:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0003 V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C43:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C44:CIB_DSP +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H02E0601 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 + +.tile CIB_R58C45:CIB_DSP +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C46:CIB_DSP +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R58C47:CIB_DSP +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C48:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 + +.tile CIB_R58C49:CIB_DSP +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C50:CIB_DSP +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R58C51:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C52:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C53:CIB_DSP +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02E0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C54:CIB_DSP +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C55:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C56:CIB_DSP +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile CIB_R58C57:CIB_DSP +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile CIB_R58C58:CIB_DSP +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C59:CIB_DSP +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 + +.tile CIB_R58C60:CIB_DSP +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C61:CIB_DSP +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0303 H06E0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C62:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0103 V06N0103 + +.tile CIB_R58C63:CIB_DSP +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 + +.tile CIB_R58C64:CIB_DSP +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R58C65:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C66:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R58C67:CIB_DSP +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C68:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R58C69:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V01N0001 + +.tile CIB_R58C70:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 + +.tile CIB_R58C71:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C72:CIB_DSP +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C73:CIB_DSP +arc: E1_H01E0001 JF4 +arc: E1_H01E0101 JF7 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 JF6 +arc: JB4 W1_H02E0101 +arc: JCE2 H00R0000 +arc: JCE3 H00L0000 +arc: JD5 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 JF5 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 JF4 +arc: W3_H06W0303 V01N0101 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 + +.tile CIB_R58C74:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 JF0 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R58C75:CIB_DSP +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0000 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02W0401 +arc: W3_H06W0003 E1_H02W0001 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R58C76:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R58C77:CIB_DSP +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C78:CIB_DSP +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C79:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 E1_H01W0100 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R58C80:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C81:CIB_DSP +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R58C82:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 + +.tile CIB_R58C83:CIB_DSP +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 E1_H02W0001 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R58C84:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R58C85:CIB_DSP +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C86:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R58C87:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R58C88:CIB_DSP +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 H06E0303 + +.tile CIB_R58C89:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 + +.tile CIB_R58C90:CIB_DSP +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 + +.tile CIB_R58C91:CIB_DSP +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C92:CIB_DSP +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C93:CIB_DSP +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R58C94:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C95:CIB_DSP +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R58C96:CIB_DSP +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 V02N0201 + +.tile CIB_R58C97:CIB_DSP +arc: E1_H02E0301 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R58C98:CIB_DSP +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile CIB_R58C99:CIB_DSP +arc: N1_V02N0301 W1_H02E0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 N1_V01S0000 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 + +.tile CIB_R5C125:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C101:CIB_EBR +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R70C107:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C110:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C113:CIB_EBR +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R70C116:CIB_EBR +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R70C28:CIB_EBR +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R70C29:CIB_EBR +arc: N1_V02N0501 N1_V01S0100 + +.tile CIB_R70C30:CIB_EBR +arc: E1_H02E0001 V06S0003 + +.tile CIB_R70C31:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 + +.tile CIB_R70C32:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 N1_V02S0401 + +.tile CIB_R70C33:CIB_EBR +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: W1_H02W0201 S1_V02N0201 + +.tile CIB_R70C34:CIB_EBR +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 + +.tile CIB_R70C35:CIB_EBR +arc: W1_H02W0101 V06S0103 + +.tile CIB_R70C36:CIB_EBR +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 + +.tile CIB_R70C37:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 + +.tile CIB_R70C38:CIB_EBR +arc: N1_V02N0101 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0601 + +.tile CIB_R70C39:CIB_EBR +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 N3_V06S0003 + +.tile CIB_R70C40:CIB_EBR +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 V06N0303 + +.tile CIB_R70C41:CIB_EBR +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R70C42:CIB_EBR +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 + +.tile CIB_R70C43:CIB_EBR +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V06N0203 + +.tile CIB_R70C44:CIB_EBR +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 V01N0101 + +.tile CIB_R70C45:CIB_EBR +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N1_V02S0601 + +.tile CIB_R70C46:CIB_EBR +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 + +.tile CIB_R70C47:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R70C48:CIB_EBR +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N1_V01S0000 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R70C49:CIB_EBR +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0701 N1_V02S0701 + +.tile CIB_R70C50:CIB_EBR +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R70C51:CIB_EBR +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N1_V01S0000 + +.tile CIB_R70C52:CIB_EBR +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C53:CIB_EBR +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0501 N1_V02S0501 + +.tile CIB_R70C54:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R70C55:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0101 N1_V01S0100 + +.tile CIB_R70C56:CIB_EBR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 S3_V06N0003 + +.tile CIB_R70C57:CIB_EBR +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V01N0001 + +.tile CIB_R70C58:CIB_EBR +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0301 V02S0301 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C59:CIB_EBR +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 + +.tile CIB_R70C60:CIB_EBR +arc: E1_H02E0001 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 + +.tile CIB_R70C61:CIB_EBR +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 N1_V01S0100 + +.tile CIB_R70C62:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R70C63:CIB_EBR +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 + +.tile CIB_R70C64:CIB_EBR +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R70C65:CIB_EBR +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0701 S3_V06N0203 + +.tile CIB_R70C66:CIB_EBR +arc: E1_H02E0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R70C67:CIB_EBR +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 + +.tile CIB_R70C68:CIB_EBR +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0301 N1_V01S0100 + +.tile CIB_R70C69:CIB_EBR +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R70C70:CIB_EBR +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R70C71:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile CIB_R70C72:CIB_EBR +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R70C73:CIB_EBR +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile CIB_R70C74:CIB_EBR +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S3_V06N0003 + +.tile CIB_R70C75:CIB_EBR +arc: E1_H02E0101 V06S0103 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 + +.tile CIB_R70C76:CIB_EBR +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0201 H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R70C77:CIB_EBR +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06W0203 + +.tile CIB_R70C78:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 + +.tile CIB_R70C79:CIB_EBR +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 + +.tile CIB_R70C80:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 + +.tile CIB_R70C81:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 S3_V06N0303 + +.tile CIB_R70C82:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 V01N0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R70C83:CIB_EBR +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0201 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 + +.tile CIB_R70C84:CIB_EBR +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R70C85:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0101 H02W0101 + +.tile CIB_R70C86:CIB_EBR +arc: E3_H06E0203 H01E0001 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0101 V06S0103 + +.tile CIB_R70C87:CIB_EBR +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0601 + +.tile CIB_R70C88:CIB_EBR +arc: W3_H06W0003 V06S0003 + +.tile CIB_R70C89:CIB_EBR +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06E0203 + +.tile CIB_R70C90:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 + +.tile CIB_R70C91:CIB_EBR +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0303 V01N0101 + +.tile CIB_R70C92:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R70C93:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 + +.tile CIB_R70C94:CIB_EBR +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 + +.tile CIB_R7C1:CIB_LR +arc: N1_V02N0101 H06W0103 + +.tile CIB_R82C35:CIB_EBR +arc: E1_H02E0101 V06S0103 + +.tile CIB_R82C36:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H06W0003 + +.tile CIB_R82C37:CIB_EBR +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 + +.tile CIB_R82C38:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 S1_V02N0601 + +.tile CIB_R82C39:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 + +.tile CIB_R82C40:CIB_EBR +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 N1_V02S0201 + +.tile CIB_R82C41:CIB_EBR +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 V06N0103 + +.tile CIB_R82C42:CIB_EBR +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R82C43:CIB_EBR +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0601 S1_V02N0601 + +.tile CIB_R82C47:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R82C48:CIB_EBR +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 + +.tile CIB_R82C49:CIB_EBR +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 + +.tile CIB_R82C50:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0401 + +.tile CIB_R82C51:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 N1_V02S0101 + +.tile CIB_R82C52:CIB_EBR +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 + +.tile CIB_R82C53:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0701 V02S0701 + +.tile CIB_R82C54:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R82C55:CIB_EBR +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 + +.tile CIB_R82C56:CIB_EBR +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 V06S0303 + +.tile CIB_R82C57:CIB_EBR +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0301 V01N0101 + +.tile CIB_R82C58:CIB_EBR +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 + +.tile CIB_R82C59:CIB_EBR +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 V01N0001 + +.tile CIB_R82C60:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 + +.tile CIB_R82C61:CIB_EBR +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 W3_H06E0003 + +.tile CIB_R82C62:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 + +.tile CIB_R82C63:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V01S0000 + +.tile CIB_R82C64:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0501 V01N0101 + +.tile CIB_R82C65:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 + +.tile CIB_R82C66:CIB_EBR +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0301 H06W0003 +arc: W1_H02W0401 E1_H02W0101 + +.tile CIB_R82C67:CIB_EBR +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R82C68:CIB_EBR +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 + +.tile CIB_R82C69:CIB_EBR +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R82C70:CIB_EBR +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N1_V02S0601 + +.tile CIB_R82C71:CIB_EBR +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0001 N1_V02S0001 + +.tile CIB_R82C72:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 E1_H02W0601 + +.tile CIB_R82C73:CIB_EBR +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0501 N1_V02S0501 + +.tile CIB_R82C74:CIB_EBR +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0601 S1_V02N0601 + +.tile CIB_R82C75:CIB_EBR +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0201 H06W0103 + +.tile CIB_R82C76:CIB_EBR +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N3_V06S0303 + +.tile CIB_R82C77:CIB_EBR +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0001 S1_V02N0501 +arc: W1_H02W0401 V06S0203 + +.tile CIB_R82C78:CIB_EBR +arc: E1_H02E0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0103 N3_V06S0103 + +.tile CIB_R82C79:CIB_EBR +arc: N1_V02N0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 N1_V01S0100 + +.tile CIB_R82C82:CIB_EBR +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 + +.tile CIB_R89C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R94C123:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C46:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C47:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C48:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C49:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C50:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C51:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C52:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C53:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C54:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C55:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C56:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C57:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R94C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C71:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C72:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C73:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C74:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C75:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C76:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C77:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C78:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C79:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R94C80:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C81:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C82:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R9C1:CIB_LR +arc: N3_V06N0303 S1_V02N0601 + +.tile MIB_R0C67:TMID_0 +arc: G_TDCC0CLKI G_JULCPLL0CLKOP + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R22C113:EBR_SPINE_UR2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C12:EBR_SPINE_UL2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C30:EBR_SPINE_UL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C57:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C67:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R22C68:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R22C77:EBR_SPINE_UR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C95:EBR_SPINE_UR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R36C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R47C0:PICL0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R48C0:PICL1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R4C0:PLL0_UL +arc: E1_CLKFB E1_CLKINTFB +arc: E1_REFCLK1 E1_JREFCLK1_0 + +.tile MIB_R57C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.DRIVE 4 + +.tile MIB_R58C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R70C113:EBR_SPINE_LR2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C30:EBR_SPINE_LL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C57:EBR_SPINE_LL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C67:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R70C68:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R70C77:EBR_SPINE_LR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R70C95:EBR_SPINE_LR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R89C0:PICL0_DQS2 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R90C0:PICL1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOB.PULLMODE UP + +.tile MIB_R95C101:PICB0 +unknown: F0B1 + +.tile MIB_R95C102:PICB1 +unknown: F0B1 + +.tile MIB_R95C103:PICB0 +unknown: F0B1 + +.tile MIB_R95C104:PICB1 +unknown: F0B1 + +.tile MIB_R95C105:PICB0 +unknown: F0B1 + +.tile MIB_R95C106:PICB1 +unknown: F0B1 + +.tile MIB_R95C107:PICB0 +unknown: F0B1 + +.tile MIB_R95C108:PICB1 +unknown: F0B1 + +.tile MIB_R95C110:PICB0 +unknown: F0B1 + +.tile MIB_R95C111:PICB1 +unknown: F0B1 + +.tile MIB_R95C112:PICB0 +unknown: F0B1 + +.tile MIB_R95C113:PICB1 +unknown: F0B1 + +.tile MIB_R95C114:PICB0 +unknown: F0B1 + +.tile MIB_R95C115:PICB1 +unknown: F0B1 + +.tile MIB_R95C116:PICB0 +unknown: F0B1 + +.tile MIB_R95C117:PICB1 +unknown: F0B1 + +.tile MIB_R95C119:PICB0 +unknown: F0B1 + +.tile MIB_R95C120:PICB1 +unknown: F0B1 + +.tile MIB_R95C121:PICB0 +unknown: F0B1 + +.tile MIB_R95C122:PICB1 +unknown: F0B1 + +.tile MIB_R95C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R95C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R95C96:PICB0 +unknown: F0B1 + +.tile MIB_R95C97:PICB1 +unknown: F0B1 + +.tile MIB_R95C98:PICB0 +unknown: F0B1 + +.tile MIB_R95C99:PICB1 +unknown: F0B1 + +.tile R11C38:PLC2 +arc: E1_H01E0001 E3_H06W0003 + +.tile R11C39:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 + +.tile R11C3:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R11C40:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0101 H02W0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0010001110101111 +word: SLICEC.K0.INIT 0010001110101111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000101110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A4 N1_V01N0101 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1100111000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C42:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02S0601 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C43:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 H02W0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +word: SLICED.K0.INIT 1111000001100110 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1100111000000010 +word: SLICEB.K1.INIT 1100111000000010 +word: SLICEC.K1.INIT 1010001110101100 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B4 H02W0101 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M3 H02W0201 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C45:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 N1_V02S0501 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR0 H02E0301 +arc: M0 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C46:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B6 H02W0301 +arc: C0 F4 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 W1_H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +word: SLICEB.K0.INIT 1110101001001000 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K0.INIT 1000101110111000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C47:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H00L0000 +arc: B6 V02N0501 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1110101001100000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1010111000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C48:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 V02N0501 +arc: A0 H02W0701 +arc: A3 N1_V02S0701 +arc: A4 W1_H02E0701 +arc: B0 N1_V02S0301 +arc: B2 H01W0100 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 E1_H02W0601 +arc: C6 W1_H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R11C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q2 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101110000010000 +word: SLICEB.K1.INIT 1100110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C50:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C4 V00T0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R11C52:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V02N0401 +arc: B0 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: F0 F5A_SLICE +arc: M0 H02W0601 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R11C53:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 + +.tile R12C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B3 E1_H01W0100 +arc: B7 E1_H02W0301 +arc: C1 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: D0 V00T0100 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: V00T0100 F1 +arc: V01S0000 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R12C40:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 H01E0001 +arc: V00B0100 V02S0101 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: A3 F7 +arc: A5 V00T0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0401 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1100110000001100 +word: SLICEA.K0.INIT 0000101001101010 +word: SLICEA.K1.INIT 0000110000111100 +word: SLICEB.K0.INIT 0001111100100000 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 0000110001101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 V02S0101 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0301 +arc: B3 V02N0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R12C42:PLC2 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A6 H02E0701 +arc: B0 V02S0101 +arc: B3 W1_H02E0101 +arc: B7 F3 +arc: C0 F6 +arc: C1 F6 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: N3_V06N0303 F6 +arc: S1_V02S0501 F5 +arc: V01S0100 F7 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1010001110101100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0011111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R12C43:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0000 +arc: A1 W1_H02E0701 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: B6 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D6 V02N0401 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1101100011011000 +word: SLICED.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R12C44:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 E1_H01W0100 + +.tile R12C45:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q6 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1010000010101100 +word: SLICEA.K1.INIT 1010111110101100 +word: SLICEB.K0.INIT 1100000011001010 +word: SLICEB.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C46:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: M0 E1_H02W0601 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F0 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111111000110010 +word: SLICEB.K1.INIT 1100110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C47:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 W1_H02E0501 +arc: B0 W1_H02E0301 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C4 H02E0601 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C48:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02E0101 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0100 +arc: A2 H02E0501 +arc: A6 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: V00B0100 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1110110001100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C49:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: B2 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0401 F6 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1101110010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1110110001100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R12C50:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: A0 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 W1_H02E0101 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R12C51:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 E1_H02W0201 +arc: A0 W1_H02E0701 +arc: A2 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 V00B0100 +arc: D4 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C52:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 H01E0001 +arc: V00T0100 V02S0501 +arc: A0 H02E0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: H01W0000 Q4 +arc: LSR0 V00T0100 +arc: M0 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C53:PLC2 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 + +.tile R12C54:PLC2 +arc: N1_V02N0601 W3_H06E0303 + +.tile R13C101:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R13C104:PLC2 +arc: S1_V02S0501 N3_V06S0303 + +.tile R13C107:PLC2 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C17:PLC2 +arc: E3_H06E0303 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile R13C23:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R13C29:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R13C35:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E3_H06E0203 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEB.K0.INIT 1010111110100011 +word: SLICEB.K1.INIT 0101010000000000 +word: SLICEC.K0.INIT 1100000001000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 0000000000000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R13C40:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V01N0101 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A5 H02E0501 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 H02W0301 +arc: B7 F1 +arc: C0 F4 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 Q7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 Q7 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q7 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000000011101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000000010011 +word: SLICEA.K0.INIT 1111111101001111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R13C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: V01S0000 F6 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +word: SLICED.K0.INIT 0101010100010001 +word: SLICEC.K0.INIT 0011001000100010 +word: SLICEA.K0.INIT 0000001100000000 +word: SLICEA.K1.INIT 1010101110101010 +word: SLICED.K1.INIT 0000000001001100 +word: SLICEC.K1.INIT 0101010101010100 +word: SLICEB.K0.INIT 1111110111001100 +word: SLICEB.K1.INIT 0011000100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R13C42:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 V00T0000 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H00R0100 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02N0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: M4 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 F7 +arc: V00B0100 F7 +arc: V00T0000 Q2 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q7 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0000000001110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111100010001000 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110101010101010 +word: SLICEB.K1.INIT 0000000000101010 +word: SLICEB.K0.INIT 1111111110001000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R13C43:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02E0601 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 H01E0101 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B2 E1_H02W0301 +arc: B3 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: N1_V02N0401 F4 +arc: N3_V06N0203 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0000001100000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 0101111101010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R13C44:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V02N0101 +arc: A0 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C45:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 + +.tile R13C46:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q6 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICEA.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C47:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1011000110100000 +word: SLICEA.K1.INIT 1111010111100100 +word: SLICEB.K0.INIT 1000110110001000 +word: SLICEB.K1.INIT 1101110111011000 +word: SLICEC.K0.INIT 1111001000000010 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C48:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100110000001010 +word: SLICEB.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICEC.K1.INIT 1100110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C49:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 H02E0301 +arc: B2 H00R0100 +arc: C0 E1_H01W0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: LSR1 V00T0000 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C50:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 H01E0001 +arc: A0 H02E0701 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V01S0100 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R13C51:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 + +.tile R13C52:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H06E0303 + +.tile R13C53:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C56:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R13C59:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C62:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C65:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C68:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 + +.tile R13C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C72:PLC2 +arc: S3_V06S0103 H01E0101 + +.tile R13C77:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C83:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C89:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C95:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C96:PLC2 +arc: S1_V02S0701 S3_V06N0203 + +.tile R13C97:PLC2 +arc: S1_V02S0701 S3_V06N0203 + +.tile R14C15:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R14C18:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R14C33:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R14C35:PLC2 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0103 E3_H06W0103 + +.tile R14C38:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R14C39:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0201 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: A1 F5 +arc: B1 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: C1 F4 +arc: C4 V00T0000 +arc: C5 V02S0001 +arc: D1 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R14C40:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0701 +arc: V00B0000 H02E0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B7 H02W0301 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 0000001100000101 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 1100110011011100 +word: SLICEA.K0.INIT 1000100011111111 +word: SLICEA.K1.INIT 0000000010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R14C41:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B5 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 0000110100000000 +word: SLICEB.K0.INIT 0000111100001110 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 1111101011111010 +word: SLICEC.K1.INIT 1100101000001010 +word: SLICED.K0.INIT 0000000011110101 +word: SLICED.K1.INIT 0000000001110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R14C42:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 V02N0601 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 E1_H01W0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0111000001110111 +word: SLICEA.K1.INIT 1111000011100000 +word: SLICED.K0.INIT 1111000000110000 +word: SLICEB.K0.INIT 0000000001110000 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICEC.K1.INIT 1000100010001100 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C43:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V01N0001 +arc: A0 H00L0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 F7 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H01E0001 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 0000110000000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111110010101010 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1011001100110011 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R14C44:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06E0203 + +.tile R14C45:PLC2 +arc: H00R0000 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B7 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R14C46:PLC2 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R14C47:PLC2 +arc: N1_V02N0401 V01N0001 + +.tile R14C48:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R14C50:PLC2 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0601 V01N0001 + +.tile R14C51:PLC2 +arc: S1_V02S0701 H06W0203 + +.tile R14C52:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0601 E1_H01W0000 + +.tile R14C53:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: V00B0100 V02N0301 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 1111001111100010 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R14C54:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C7 H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111100100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICEC.K0.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R14C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 H02W0001 +arc: H00L0100 W1_H02E0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02N0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0101 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: D5 F0 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0100 F5 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111101011001010 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000110100001000 +word: SLICEC.K1.INIT 1010111110101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R14C56:PLC2 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R14C58:PLC2 +arc: S1_V02S0301 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 + +.tile R14C59:PLC2 +arc: V00B0000 S1_V02N0201 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R14C60:PLC2 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: A0 E1_H02W0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C61:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R14C62:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H00L0000 +arc: A2 F7 +arc: A3 F7 +arc: A5 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02W0401 +arc: C7 V00T0100 +arc: D0 V00T0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00T0000 +arc: V00T0000 F0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010110011111111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 1111000011100000 +word: SLICEB.K1.INIT 0000000011100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C63:PLC2 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 H02E0501 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 V01N0001 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEB.K0.INIT 1110111011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R14C64:PLC2 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 + +.tile R14C65:PLC2 +arc: S1_V02S0501 H06W0303 + +.tile R14C66:PLC2 +arc: S3_V06S0303 N3_V06S0303 +arc: B3 H02W0101 +arc: C3 V02N0601 +arc: D3 S1_V02N0001 +arc: F3 F3_SLICE +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0011000000111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R14C67:PLC2 +arc: A0 V02N0501 +arc: A3 F5 +arc: A5 S1_V02N0301 +arc: B0 H02W0301 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C3 E1_H01W0000 +arc: C5 V02N0001 +arc: D0 E1_H02W0001 +arc: D3 F0 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICEA.K0.INIT 0000111000000100 +word: SLICEB.K1.INIT 1111001111100010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C68:PLC2 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 V01N0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 F0 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: V00B0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 0011001000000010 +word: SLICED.K0.INIT 1111101111001000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R14C69:PLC2 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V01N0101 + +.tile R14C70:PLC2 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 + +.tile R14C81:PLC2 +arc: S1_V02S0101 S3_V06N0103 + +.tile R14C89:PLC2 +arc: E3_H06E0303 S3_V06N0303 + +.tile R14C95:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R14C98:PLC2 +arc: S3_V06S0003 H06E0003 + +.tile R15C100:PLC2 +arc: S1_V02S0601 S3_V06N0303 + +.tile R15C104:PLC2 +arc: S1_V02S0501 N1_V02S0501 + +.tile R15C105:PLC2 +arc: S1_V02S0301 S3_V06N0003 +arc: W3_H06W0003 S3_V06N0003 + +.tile R15C106:PLC2 +arc: S1_V02S0301 S3_V06N0003 + +.tile R15C107:PLC2 +arc: S1_V02S0501 N1_V02S0501 + +.tile R15C23:PLC2 +arc: S3_V06S0103 E3_H06W0103 + +.tile R15C26:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R15C29:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R15C32:PLC2 +arc: S3_V06S0003 H06W0003 + +.tile R15C35:PLC2 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0203 E3_H06W0203 +arc: D0 V02S0001 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: S3_V06S0003 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R15C36:PLC2 +arc: S1_V02S0501 E1_H01W0100 + +.tile R15C37:PLC2 +arc: H00L0000 V02N0001 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 H02W0401 +arc: A0 H00L0000 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 0101110100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C38:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R15C39:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: S3_V06S0303 E1_H01W0100 +arc: A1 N1_V02S0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111110011 +word: SLICEA.K1.INIT 0101010111110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R15C40:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 N1_V01S0100 +arc: B0 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 N1_V02S0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +word: SLICEA.K0.INIT 0000000010110000 +word: SLICEA.K1.INIT 0101000011110000 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 0101000000010000 +word: SLICEC.K0.INIT 0111011100000000 +word: SLICEC.K1.INIT 0000100000001100 +word: SLICED.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 H01E0101 +arc: A0 H02E0501 +arc: A1 H02E0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 H02W0701 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C5 N1_V02S0201 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 N1_V02S0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: S1_V02S0001 F0 +arc: V01S0100 F4 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0101111100000000 +word: SLICEA.K1.INIT 0000110000000100 +word: SLICEB.K0.INIT 0010101000101010 +word: SLICEB.K1.INIT 0000000010001010 +word: SLICEC.K0.INIT 0111011100000000 +word: SLICEC.K1.INIT 0000110100000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R15C42:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q5 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0111001001010000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1010110000001100 +word: SLICED.K0.INIT 1111101011111010 +word: SLICED.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C43:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0501 +arc: A2 H01E0001 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: B0 F1 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C2 H02E0401 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0401 F6 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0000000000001100 +word: SLICEA.K0.INIT 1100111011001100 +word: SLICEC.K0.INIT 0000000001010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R15C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F7 +arc: H01W0100 F5 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110010001000100 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 0000111100001010 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICEC.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R15C45:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 V02S0501 +arc: A2 H01E0001 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 0011011100001000 +word: SLICEB.K0.INIT 0111011100000111 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICED.K1.INIT 0000000000101000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C46:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000001000001010 +word: SLICEA.K0.INIT 0000101011110000 +word: SLICEA.K1.INIT 0010100011001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011101110000000 +word: SLICEC.K0.INIT 0011001000100010 +word: SLICEC.K1.INIT 0000000001100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C47:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B7 H02E0301 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C7 V00T0000 +arc: D1 W1_H02E0001 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N1_V01N0001 F7 +arc: N1_V02N0101 F3 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F1 +word: SLICEB.K0.INIT 0000001000100010 +word: SLICED.K1.INIT 0000001000100010 +word: SLICEA.K1.INIT 0000001000100010 +word: SLICEB.K1.INIT 0000001000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C48:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: A2 E1_H01E0001 +arc: B2 H01W0100 +arc: C2 E1_H02W0401 +arc: D2 E1_H02W0001 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100000011010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R15C49:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 + +.tile R15C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 F7 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0101000101000000 +word: SLICEB.K0.INIT 1110111011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011100000000000 +word: SLICEA.K1.INIT 1011100011111111 +word: SLICEB.K1.INIT 1010100000100000 +word: SLICEC.K0.INIT 1111111000110010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R15C51:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICED.K0.INIT 0000000011011000 +word: SLICEC.K1.INIT 0000000010100011 +word: SLICED.K1.INIT 0000000000010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C52:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: A0 H02E0501 +arc: A2 V02N0701 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R15C53:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 H00L0000 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C54:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0201 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R15C55:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 W1_H02E0301 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C56:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C57:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 F5 +arc: B0 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02E0201 +arc: D3 F0 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 1100100000001000 +word: SLICEA.K0.INIT 0100000001010001 +word: SLICED.K0.INIT 0000000011100000 +word: SLICEB.K0.INIT 0000111100110011 +word: SLICEB.K1.INIT 0000000000010101 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C58:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 V01N0101 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEC.K1.INIT 1111110010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 0000110000001010 +word: SLICED.K1.INIT 1111111000110010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C59:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 W3_H06E0103 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: V00T0000 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 1100111111001010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C60:PLC2 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H02W0601 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D3 H02W0001 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C61:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A4 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: B4 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D4 V00B0000 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000011010001 +word: SLICEA.K0.INIT 0000000011100000 +word: SLICED.K0.INIT 0000000000010101 +word: SLICEA.K1.INIT 0000000100010001 +word: SLICEC.K0.INIT 0000110100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R15C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0100 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101111110001111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101001100000000 +word: SLICED.K0.INIT 0000000011111110 +word: SLICED.K1.INIT 0000000000110010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C63:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 H01E0101 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0601 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 0010001100100000 +word: SLICED.K0.INIT 0000001000000111 +word: SLICEC.K1.INIT 0000000100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R15C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 0000110100001000 +word: SLICEC.K1.INIT 1111111000001110 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R15C66:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0501 +arc: W1_H02W0301 H01E0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 E1_H02W0101 +arc: B6 F3 +arc: C0 W1_H02E0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: N1_V01N0101 F4 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111100010 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICED.K0.INIT 1111010111100100 +word: SLICEC.K0.INIT 1111000011101110 +word: SLICEC.K1.INIT 0101000001011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R15C67:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 S1_V02N0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F6 +arc: V00T0100 F1 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 0000111000000100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 1101100011111111 +word: SLICED.K0.INIT 0000110100001000 +word: SLICED.K1.INIT 1111110110101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R15C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02N0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V00B0100 F7 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R15C69:PLC2 +arc: H01W0100 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: A2 H02W0701 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C70:PLC2 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R15C71:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 + +.tile R15C74:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R15C77:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R15C80:PLC2 +arc: E1_H02E0501 V02N0501 + +.tile R15C81:PLC2 +arc: E1_H02E0101 V02S0101 + +.tile R15C82:PLC2 +arc: A0 H02W0701 +arc: A2 E1_H02W0701 +arc: A6 W1_H02E0501 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R15C83:PLC2 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R15C84:PLC2 +arc: S1_V02S0101 H01E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 V02N0701 + +.tile R15C88:PLC2 +arc: E3_H06E0203 S3_V06N0203 + +.tile R15C89:PLC2 +arc: E3_H06E0003 S3_V06N0003 + +.tile R15C93:PLC2 +arc: S1_V02S0101 E3_H06W0103 + +.tile R15C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: V01S0100 S3_V06N0303 + +.tile R15C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0301 W3_H06E0003 + +.tile R15C96:PLC2 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 H01E0001 + +.tile R15C97:PLC2 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 + +.tile R15C99:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R16C100:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 H02E0701 +arc: A6 V02N0301 +arc: B0 V02N0301 +arc: B1 H02W0101 +arc: B3 F1 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C3 F6 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D3 F0 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C101:PLC2 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 V02N0701 + +.tile R16C102:PLC2 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: W1_H02W0601 S1_V02N0601 + +.tile R16C103:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C104:PLC2 +arc: S3_V06S0103 W3_H06E0103 + +.tile R16C105:PLC2 +arc: S1_V02S0301 H06W0003 + +.tile R16C106:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 H06E0303 + +.tile R16C107:PLC2 +arc: V00B0000 S1_V02N0001 +arc: A0 V02S0501 +arc: A3 H02W0501 +arc: A4 V00B0000 +arc: B2 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C108:PLC2 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: F0 F0_SLICE +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C33:PLC2 +arc: S3_V06S0303 H06W0303 + +.tile R16C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R16C37:PLC2 +arc: E1_H02E0201 H01E0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B6 V02N0701 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C38:PLC2 +arc: H00R0100 H02E0501 +arc: V00T0000 V02N0401 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR1 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0111001101000000 +word: SLICEB.K1.INIT 0101000011001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C39:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: S3_V06S0203 H06W0203 + +.tile R16C40:PLC2 +arc: E1_H02E0301 V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0303 E1_H02W0501 + +.tile R16C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0401 S1_V02N0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 F5 +arc: A5 V02S0101 +arc: B2 E1_H02W0301 +arc: B5 V02S0701 +arc: C2 E1_H02W0401 +arc: C5 V02S0201 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F2 +arc: W1_H02W0201 F2 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICEB.K0.INIT 0000000000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R16C42:PLC2 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A1 E1_H02W0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0501 +arc: A6 V02S0301 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 W1_H02E0301 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +arc: V01S0100 Q3 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100110000001100 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000101011111010 +word: SLICEC.K0.INIT 0000000011111010 +word: SLICEA.K1.INIT 0001000100110001 +word: SLICEB.K0.INIT 1111001111111111 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R16C43:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0701 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: A0 F5 +arc: A1 V02S0701 +arc: A3 V00B0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B3 V02S0101 +arc: B5 V02S0501 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 Q0 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +word: SLICED.K1.INIT 1010001000100010 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 0111111100000000 +word: SLICED.K0.INIT 0001001100110011 +word: SLICEA.K0.INIT 0010111100101111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1100101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C44:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0000001100000111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0111011100000000 +word: SLICEB.K0.INIT 0001000000000000 +word: SLICEB.K1.INIT 1111111000110010 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R16C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 H02E0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A7 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 0000000010001011 +word: SLICEC.K0.INIT 0010001100100000 +word: SLICEA.K1.INIT 1111111000001110 +word: SLICED.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R16C47:PLC2 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1111001110111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C48:PLC2 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E3_H06W0303 + +.tile R16C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B5 H02W0301 +arc: B7 V00B0100 +arc: C5 V02S0201 +arc: C7 V02N0201 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICEC.K1.INIT 0011000100000001 +word: SLICED.K1.INIT 0000000100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C50:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEC.K1.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R16C51:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111011110010 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C52:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 W3_H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V02N0701 F7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000101100001000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C53:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: B0 H02W0301 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C54:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0501 +arc: A3 V01N0101 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000110100000001 +word: SLICED.K0.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R16C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: A3 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 Q2 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q2 +arc: V00B0100 F7 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEC.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R16C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0101000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R16C57:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B4 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C4 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R16C59:PLC2 +arc: H00L0000 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02S0101 +arc: A4 S1_V02N0301 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F7 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000010101100 +word: SLICED.K1.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 H02W0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V01N0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: D0 V00T0100 +arc: D1 H00R0000 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000111000000010 +word: SLICEA.K1.INIT 1111111111001010 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R16C61:PLC2 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 V02S0401 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000101000001000 +word: SLICEA.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111111111001010 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1111111001010100 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1111001110111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C62:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A0 V02N0701 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B7 V02N0501 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C63:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D3 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R16C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C65:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V02S0201 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R16C66:PLC2 +arc: E1_H02E0301 V01N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 F7 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B5 F3 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 0011000100100000 +word: SLICEC.K0.INIT 1111001111100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R16C67:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: A3 V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D4 V01N0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H01E0101 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1101100011011000 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1011100011111111 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 1111111110111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C68:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 S3_V06N0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: A4 H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D4 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0001 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R16C69:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C70:PLC2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 H02W0401 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C71:PLC2 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V01N0001 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C72:PLC2 +arc: W1_H02W0101 V01N0101 + +.tile R16C73:PLC2 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02N0101 + +.tile R16C75:PLC2 +arc: E3_H06E0103 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: V01S0000 S3_V06N0103 + +.tile R16C80:PLC2 +arc: N1_V02N0501 S1_V02N0401 + +.tile R16C81:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C82:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 S1_V02N0601 + +.tile R16C83:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: A3 S1_V02N0501 +arc: A5 V00B0000 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 V02N0301 +arc: B4 V02N0701 +arc: B6 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R16C84:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: W1_H02W0301 S1_V02N0301 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C85:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: S1_V02S0301 W1_H02E0301 + +.tile R16C87:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C88:PLC2 +arc: E1_H02E0201 S1_V02N0201 + +.tile R16C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R16C90:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: S1_V02S0701 H02E0701 + +.tile R16C91:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C92:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06E0203 + +.tile R16C93:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 + +.tile R16C94:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 + +.tile R16C95:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 + +.tile R16C96:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 E1_H02W0101 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 F5 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0701 +arc: B7 F3 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 F6 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R16C97:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02E0701 + +.tile R16C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 + +.tile R16C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 + +.tile R17C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D2 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 F0 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: V00B0000 F4 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C101:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 W1_H02E0501 +arc: A2 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B4 V00B0100 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0000 F5 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile R17C103:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 H01E0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 S3_V06N0103 + +.tile R17C104:PLC2 +arc: H00L0000 E1_H02W0201 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A1 H00L0000 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D2 F0 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C105:PLC2 +arc: E1_H02E0701 V01N0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0101 E1_H01W0100 +arc: B0 V02S0301 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C106:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0701 V02N0701 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C107:PLC2 +arc: N1_V02N0501 H01E0101 +arc: V00T0000 W1_H02E0001 +arc: A0 S1_V02N0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 H02E0701 +arc: B2 H02E0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C108:PLC2 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 V06N0203 +arc: B2 S1_V02N0101 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 F0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R17C109:PLC2 +arc: W1_H02W0601 S3_V06N0303 + +.tile R17C35:PLC2 +arc: E1_H02E0301 N1_V02S0301 + +.tile R17C36:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: V00T0000 E1_H02W0001 +arc: A5 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B6 N1_V02S0501 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C37:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A6 N1_V01S0100 +arc: B6 V02S0501 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D6 V02S0401 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0401 Q6 +arc: S1_V02S0001 F0 +arc: S1_V02S0601 Q6 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0010001011110000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R17C38:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C39:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R17C3:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R17C40:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 H06E0103 + +.tile R17C41:PLC2 +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0401 + +.tile R17C42:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0701 W3_H06E0203 + +.tile R17C43:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 E1_H01W0100 +arc: B3 H02E0301 +arc: C0 H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111111111111100 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEB.K1.INIT 0000111011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R17C44:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A3 H02W0701 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B5 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C3 V02S0601 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F7 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C45:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A6 E1_H01W0000 +arc: B6 V00T0000 +arc: C6 V02S0201 +arc: D6 H02W0001 +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 0000000011100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C46:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02N0101 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 W1_H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C47:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: A2 H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C48:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R17C49:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: A3 H01E0001 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C50:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A2 W1_H02E0701 +arc: A4 H02E0501 +arc: A6 V02S0101 +arc: B1 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 0000010010101110 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K0.INIT 0101000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C51:PLC2 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 F7 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICED.K0.INIT 1010100000100000 +word: SLICED.K1.INIT 0000000011100010 +word: SLICEC.K0.INIT 1111000011101110 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R17C52:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: B1 H02W0101 +arc: B2 S1_V02N0101 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R17C53:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 0000010010101110 +word: SLICED.K1.INIT 0100111001001110 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: A1 E1_H01E0001 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B7 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0011000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C55:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 V01N0001 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: A6 N1_V02S0301 +arc: B0 H02E0101 +arc: B2 N1_V02S0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D5 F2 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1111101011011000 +word: SLICED.K0.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C56:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 F6 +arc: C4 F6 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 F4 +arc: S1_V02S0401 Q6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000101001001110 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R17C57:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0000 V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C58:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A2 H02W0501 +arc: A5 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B5 V02N0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C5 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C59:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A6 V00T0100 +arc: B2 H00R0000 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R17C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C61:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C62:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H02W0501 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0000000010101100 +word: SLICEB.K1.INIT 0000000000110101 +word: SLICEC.K1.INIT 0000001000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C63:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C64:PLC2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0201 S3_V06N0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C65:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C66:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: A3 S1_V02N0501 +arc: A6 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0010011100100010 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C67:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: B1 Q1 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R17C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: B1 Q1 +arc: C0 H02W0601 +arc: C2 H00L0000 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C69:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F7 +arc: A7 Q7 +arc: C3 E1_H02W0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R17C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 H02W0401 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R17C71:PLC2 +arc: H00R0000 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A3 E1_H02W0501 +arc: A7 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C0 V02N0601 +arc: C5 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R17C72:PLC2 +arc: H00R0000 H02E0601 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q5 +arc: M0 H02W0601 +arc: M2 E1_H02W0601 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 0101010100001100 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001111110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C73:PLC2 +arc: N1_V02N0101 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 + +.tile R17C74:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0103 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C75:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V01N0101 +arc: A5 Q5 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C76:PLC2 +arc: E3_H06E0303 H01E0101 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C78:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0303 E3_H06W0303 + +.tile R17C79:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: H01W0000 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 V02N0401 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: B0 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B6 V00T0000 +arc: C0 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 F6 +arc: C6 H02E0401 +arc: D0 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R17C80:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0401 F6 +arc: V00B0000 F4 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C81:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 W3_H06E0303 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C82:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 + +.tile R17C83:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 + +.tile R17C84:PLC2 +arc: E1_H02E0601 V01N0001 +arc: A6 N1_V02S0101 +arc: B6 N1_V01S0000 +arc: C6 V02N0201 +arc: D6 E1_H02W0001 +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C85:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A2 S1_V02N0701 +arc: A5 V02N0301 +arc: B0 V02S0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C86:PLC2 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 W3_H06E0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: F0 F0_SLICE +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R17C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 + +.tile R17C88:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 + +.tile R17C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 S3_V06N0103 + +.tile R17C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: B1 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R17C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 W1_H02E0101 +arc: C1 V02S0401 +arc: C3 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N1_V01N0101 F0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C92:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R17C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 W1_H02E0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C94:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 + +.tile R17C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A6 H02W0701 +arc: B1 H02W0101 +arc: B3 V02N0301 +arc: B6 S1_V02N0701 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C6 V00T0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R17C96:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0100 +arc: A1 H01E0001 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0301 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R17C97:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S3_V06S0003 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B5 F3 +arc: B6 H02E0101 +arc: C2 F6 +arc: C3 H00R0100 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F2 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R17C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F5 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: B0 F3 +arc: B1 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 F4 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00T0100 F1 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R18C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: D0 S1_V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D5 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R18C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 E1_H02W0501 +arc: A3 N1_V02S0501 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 E1_H02W0501 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: D0 N1_V02S0001 +arc: D2 H02W0201 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 F0 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 F3 +arc: H01W0100 F6 +arc: N1_V01N0101 F4 +arc: V00B0100 F5 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C102:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 F1 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F4 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000100000100010 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C103:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 F7 +arc: A2 H00L0100 +arc: A7 H02E0701 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C7 V02S0001 +arc: D1 F2 +arc: D2 H00R0000 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C104:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A4 F7 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0301 +arc: B4 F1 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D4 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C105:PLC2 +arc: H00L0000 E1_H02W0201 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A2 F7 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C106:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 V02N0601 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C107:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R18C108:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R18C109:PLC2 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile R18C110:PLC2 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0103 E1_H02W0201 + +.tile R18C111:PLC2 +arc: W3_H06W0003 S3_V06N0003 + +.tile R18C112:PLC2 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 + +.tile R18C113:PLC2 +arc: W3_H06W0103 S3_V06N0103 + +.tile R18C32:PLC2 +arc: S3_V06S0003 E3_H06W0003 + +.tile R18C35:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H06W0003 + +.tile R18C37:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02S0001 +arc: B4 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: D0 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R18C38:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: A0 H02E0701 +arc: B0 V02S0101 +arc: C0 H02E0601 +arc: D0 V02S0201 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: S3_V06S0003 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0010000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R18C39:PLC2 +arc: E1_H02E0601 V06S0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R18C40:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V06S0203 +arc: S1_V02S0001 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V06S0203 + +.tile R18C41:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0001 Q6 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1011101100001010 +word: SLICEA.K1.INIT 1000101000001010 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 1011000010111010 +word: SLICEC.K1.INIT 1000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C43:PLC2 +arc: E1_H02E0401 S1_V02N0401 + +.tile R18C44:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: A2 H02W0701 +arc: B2 H00R0000 +arc: C2 H02E0401 +arc: D2 S1_V02N0001 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEB.K0.INIT 0000010100010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R18C45:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A5 S1_V02N0301 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D5 V02N0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q4 +arc: F5 F5_SLICE +arc: H01W0000 Q7 +arc: M4 H02W0401 +arc: M7 E1_H01W0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C46:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0601 +arc: V01S0100 S3_V06N0303 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B3 F1 +arc: B4 H01E0101 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 V02S0601 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 W1_H02E0301 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C47:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 V02S0301 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C48:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: A0 H01E0001 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A4 F7 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0010001100100000 +word: SLICEA.K1.INIT 1110111111101100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1111001111100010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000101010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C50:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: A1 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C1 F4 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICED.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C51:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0100010011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C52:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: A3 F5 +arc: A5 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D3 S1_V02N0201 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 W1_H02E0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C53:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B7 S1_V02N0501 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C54:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H01E0001 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 Q4 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C55:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B3 H00R0000 +arc: B7 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 V02S0401 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R18C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 F5 +arc: A5 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 N1_V02S0001 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR1 V00T0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: B1 V00B0000 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V00B0000 Q6 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0111011101000100 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R18C58:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 V00T0100 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R18C59:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 W1_H02E0001 +arc: D3 V01S0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R18C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0701 +arc: B0 F3 +arc: B3 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 S1_V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q6 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C61:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V01N0101 +arc: A5 V02N0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 V02N0101 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0601 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R18C62:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011000011111100 +word: SLICEB.K1.INIT 0011000011111100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 H02W0501 +arc: B0 V02N0101 +arc: B5 H02W0301 +arc: C0 S1_V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V01N0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0010001100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C64:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C5 W1_H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D5 E1_H02W0001 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEA.K1.INIT 0011000011111100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111111001010 +word: SLICED.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R18C65:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0010111000101110 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0101010000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C66:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 W1_H02E0701 +arc: A5 V00T0100 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 W1_H02E0001 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M1 H00R0000 +arc: M2 E1_H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0100010101000000 +word: SLICEB.K1.INIT 1110111111101010 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C67:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 S1_V02N0701 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A4 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B7 H02W0101 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 E1_H01W0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1101000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R18C68:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V01N0101 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 V02N0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C69:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02E0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q1 +arc: S1_V02S0601 F4 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C70:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 H06W0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H02E0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B3 F1 +arc: C0 H02E0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 N1_V02S0001 +arc: D5 E1_H02W0201 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R18C71:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0501 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 F3 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B5 F1 +arc: B6 V02S0701 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 Q7 +arc: S1_V02S0701 Q7 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0010011100100010 +word: SLICED.K1.INIT 0101000011111010 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R18C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011101000111010 +word: SLICEB.K0.INIT 0000110000101110 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0100010011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R18C73:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F2 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R18C74:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H01W0100 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C75:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: B0 H01W0100 +arc: B5 S1_V02N0501 +arc: C0 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 W1_H02E0101 +arc: B2 V02S0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C2 H00L0000 +arc: C6 H02W0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 H02E0201 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R18C77:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A5 Q5 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V00B0100 F7 +arc: V01S0000 Q5 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C78:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C79:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C4 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 F7 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C80:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 W1_H02E0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 H02E0101 +arc: B4 F3 +arc: C1 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 F2 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: S1_V02S0601 F4 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R18C81:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V01N0101 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C82:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H02E0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C84:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C85:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 + +.tile R18C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: A1 H00L0000 +arc: B1 S1_V02N0101 +arc: C1 V02N0401 +arc: D1 E1_H02W0201 +arc: F1 F1_SLICE +arc: S1_V02S0301 F1 +word: SLICEA.K1.INIT 1000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: A6 W1_H02E0701 +arc: B6 V02N0501 +arc: C6 H02W0601 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: V01S0000 F6 +word: SLICED.K0.INIT 1000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C90:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A7 H02E0501 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: S1_V02S0601 F6 +arc: S3_V06S0203 F4 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001101010101 +word: SLICEC.K0.INIT 0011111101011111 +word: SLICEC.K1.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C91:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A3 N1_V02S0501 +arc: A4 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: S1_V02S0501 F5 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1101010100000000 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEC.K0.INIT 1101010100000000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 1000111100000000 +word: SLICEA.K1.INIT 1000000010101010 +word: SLICEC.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R18C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A4 S1_V02N0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 H02W0101 +arc: C1 H02E0601 +arc: C2 W1_H02E0601 +arc: C3 F4 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D1 V02S0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: V01S0000 F3 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1011001100000000 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K1.INIT 0000000000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R18C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A2 H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 E1_H02W0401 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A6 H02W0701 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D5 V02S0401 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +word: SLICEB.K0.INIT 0000000000101010 +word: SLICEB.K1.INIT 1111111100101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A6 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B5 S1_V02N0501 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 F0 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: S1_V02S0401 F6 +arc: V01S0000 F3 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000100000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C96:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 V00B0000 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 W1_H02E0301 +arc: B3 H00R0100 +arc: B4 W1_H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 V00B0100 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0401 F6 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R18C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 V02S0501 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D0 V02S0201 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 F0 +arc: D5 F2 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100001100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R18C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0101 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0011001101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R18C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000110000111111 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 E1_H02W0501 +arc: A2 V02S0701 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0001 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 F2 +arc: D5 N1_V02S0601 +arc: D6 V02S0401 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 F4 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: V00T0100 F3 +arc: V01S0000 F1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R19C102:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C103:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H00L0100 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C104:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 V02N0501 +arc: A5 V02N0101 +arc: A7 H02E0701 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B6 V02N0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R19C105:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H02W0701 +arc: A5 V02N0301 +arc: B3 V02S0101 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: C3 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: D3 H02W0201 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R19C106:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C107:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 H01E0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C108:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C109:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 V01N0101 +arc: A0 H02E0701 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 S1_V02N0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C110:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 S1_V02N0501 +arc: S1_V02S0501 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H01E0001 +arc: B0 H00R0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C111:PLC2 +arc: W1_H02W0101 V01N0101 + +.tile R19C112:PLC2 +arc: W3_H06W0203 N1_V01S0000 + +.tile R19C113:PLC2 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R19C15:PLC2 +arc: V01S0000 S3_V06N0103 + +.tile R19C17:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R19C18:PLC2 +arc: S1_V02S0101 S3_V06N0103 + +.tile R19C21:PLC2 +arc: S1_V02S0201 S3_V06N0103 +arc: V01S0000 S3_V06N0103 + +.tile R19C33:PLC2 +arc: S1_V02S0301 E1_H02W0301 + +.tile R19C34:PLC2 +arc: B5 E1_H02W0101 +arc: D5 V02N0401 +arc: F5 F5_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R19C35:PLC2 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: B1 E1_H02W0301 +arc: D1 E1_H02W0001 +arc: F1 F1_SLICE +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R19C36:PLC2 +arc: H00L0000 H02W0001 +arc: A3 N1_V02S0501 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: S3_V06S0003 F3 +arc: V01S0000 F2 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R19C37:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: C0 H00R0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C7 E1_H01E0101 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 F0 +arc: D5 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: S1_V02S0001 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000000001010101 +word: SLICEA.K0.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R19C38:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 F1 +arc: B4 F1 +arc: C1 V02S0601 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F0 +arc: V01S0000 F6 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R19C39:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0601 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A6 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: LSR0 H02E0301 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1011101100001010 +word: SLICEA.K1.INIT 1000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: LSR0 H02W0301 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C41:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: A0 H02W0701 +arc: A1 H01E0001 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F1 +arc: S1_V02S0001 F0 +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010100000000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010111100100010 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICED.K0.INIT 1111010100110000 +word: SLICED.K1.INIT 1101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C42:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0301 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B3 H02E0101 +arc: B5 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R19C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 H00L0000 +arc: A6 E1_H02W0501 +arc: B0 V00B0000 +arc: C0 H02E0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 W1_H02E0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C44:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A1 F5 +arc: A5 Q5 +arc: B1 S1_V02N0301 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: N1_V02N0401 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 1111111111100010 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1111111000001110 +word: SLICEC.K0.INIT 0000110100001000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R19C46:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: A1 W1_H02E0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: A7 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101110001011100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101001101011111 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEC.K1.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R19C47:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q2 +arc: N1_V02N0701 Q7 +arc: S1_V02S0501 Q7 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R19C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: A0 F5 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0011111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R19C49:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A4 F7 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: A0 S1_V02N0501 +arc: A3 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: C1 H00L0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 N1_V01S0000 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: B6 V02N0501 +arc: B7 H01E0101 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 H02E0001 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H01E0001 +arc: A2 F5 +arc: A5 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0301 Q3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0101000001011100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C53:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0101000001011100 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R19C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H00L0100 +arc: A7 H02E0501 +arc: B2 H00R0100 +arc: B5 H02W0101 +arc: B7 V02N0701 +arc: C2 H02E0401 +arc: C5 V00T0100 +arc: C7 V02N0001 +arc: D2 H00R0000 +arc: D5 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0101001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R19C55:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0701 +arc: B0 V01N0001 +arc: B2 H00R0000 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F4 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 0011000000111010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 V06N0203 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C57:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A2 H02W0701 +arc: A3 F7 +arc: A5 E1_H01W0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 W1_H02E0301 +arc: B7 V00B0100 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F4 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000111101000100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C58:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 F7 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 F4 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000001110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C59:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B4 V02N0501 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C2 F6 +arc: C3 V02S0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C60:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: B1 H02E0101 +arc: B3 F1 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C61:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0301 W1_H02E0301 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0701 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R19C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V02N0501 +arc: A6 V02N0301 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B3 E1_H02W0301 +arc: B5 F1 +arc: B6 F1 +arc: B7 F1 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0011001100001010 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C64:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C4 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR0 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0000111100100010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0100010001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C65:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 N1_V02S0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: V01S0000 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICEB.K1.INIT 1111111110101100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C66:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A5 H02W0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0101111101010000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C67:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H02W0701 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B5 F3 +arc: C0 V02N0401 +arc: C2 N1_V01N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02S0101 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C2 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: S1_V02S0501 Q5 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 0100010001110100 +word: SLICEB.K1.INIT 0111011101000100 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C69:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B6 V01S0000 +arc: C0 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C70:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A4 W1_H02E0701 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B5 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0000110000101110 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C71:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A6 H02E0701 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 H01W0000 +arc: D6 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 H02E0601 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F3 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C72:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F5 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C73:PLC2 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A4 V02N0101 +arc: A6 V02S0101 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N1_V01N0101 F0 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R19C74:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A5 V02S0101 +arc: B0 H02W0101 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1011101100000000 +word: SLICED.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 H01E0001 +arc: H00L0100 V02S0101 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F5 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C76:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 V01N0001 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C77:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 V01N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B4 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R19C78:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B4 F3 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0401 +arc: C4 F6 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C80:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 V02S0501 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R19C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B4 H01E0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C83:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H02W0701 +arc: A1 H02E0501 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C84:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 E1_H01E0001 +arc: A1 F5 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 F2 +arc: D2 H02W0001 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C85:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: C0 H02W0601 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 H02W0701 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F4 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1000110010001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 + +.tile R19C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: B0 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R19C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B7 S1_V02N0501 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000000001001100 +word: SLICEB.K1.INIT 1111111101001100 +word: SLICEC.K0.INIT 0011111100111111 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V02S0401 +arc: C3 S1_V02N0401 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0001000110111011 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A2 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 V02N0701 +arc: C1 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000011100000000 +word: SLICEC.K1.INIT 1111011111110000 +word: SLICED.K0.INIT 0101111101011111 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R19C92:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V01S0000 +arc: C1 V02N0401 +arc: C3 H02E0601 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 F2 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 0001000100010011 +word: SLICEC.K1.INIT 1111011111110000 +word: SLICEC.K0.INIT 0000011100000000 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEB.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0010001000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R19C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 F4 +arc: C7 V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000010001000100 +word: SLICEA.K1.INIT 1010111011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R19C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0501 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 V02N0701 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R19C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 V00T0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: V01S0000 F5 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000011110000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R19C96:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C97:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 V02S0501 +arc: B5 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: D2 F0 +arc: D3 E1_H02W0001 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R19C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R19C99:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 V02S0001 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICEA.K1.INIT 1100111011101110 +word: SLICEA.K0.INIT 0000001000100010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0301 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 W1_H02E0101 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 V00T0100 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: A6 H02E0501 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C102:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C103:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 N1_V02S0101 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: D0 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V02N0301 F3 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C104:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 S1_V02N0701 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 N1_V02S0001 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C106:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A4 F7 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C107:PLC2 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A3 H02W0701 +arc: A5 Q5 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C108:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C109:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C110:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0203 V01N0001 +arc: A1 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 N1_V01S0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 F3 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1100111100000000 +word: SLICEB.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C111:PLC2 +arc: S3_V06S0003 H01E0001 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02N0701 +arc: A5 E1_H01W0000 +arc: B0 V00T0000 +arc: B5 V02N0701 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1011101100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C112:PLC2 +arc: H00R0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 V02N0701 +arc: B0 V01N0001 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C113:PLC2 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile R20C13:PLC2 +arc: E3_H06E0303 S3_V06N0303 + +.tile R20C14:PLC2 +arc: E1_H02E0501 V02N0501 + +.tile R20C15:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 + +.tile R20C16:PLC2 +arc: S1_V02S0301 S3_V06N0003 +arc: V01S0100 S3_V06N0303 +arc: A0 V02N0501 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR1 W1_H02E0501 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C18:PLC2 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0601 E1_H02W0601 +arc: B0 V00B0000 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H00L0000 F0 +arc: LSR0 E1_H02W0501 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C19:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: B0 V02N0101 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: E1_H02E0601 Q6 +arc: F0 F5A_SLICE +arc: LSR0 H02W0501 +arc: M0 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C20:PLC2 +arc: E1_H02E0501 V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: B0 E1_H01W0100 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: LSR1 V00T0100 +arc: M0 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C21:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C22:PLC2 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V02N0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: F0 F5A_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: LSR0 W1_H02E0501 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V00T0100 Q3 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C25:PLC2 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 + +.tile R20C33:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R20C34:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0201 H02W0201 +arc: V00T0000 V02N0601 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A7 H02W0701 +arc: B1 H00R0100 +arc: B3 H02W0101 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C5 H02W0601 +arc: C7 V00T0000 +arc: D0 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R20C35:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 E1_H02W0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A7 H02W0701 +arc: B2 F1 +arc: B3 H00R0100 +arc: B5 E1_H02W0301 +arc: B7 V00B0100 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0001 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +arc: V01S0100 F7 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEC.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R20C36:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02W0401 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: B4 F3 +arc: B6 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F1 +arc: S3_V06S0303 F6 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000110000001100 +word: SLICEA.K1.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R20C37:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A3 V02N0701 +arc: A4 F5 +arc: B3 V02N0101 +arc: B5 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D4 H00R0100 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0201 F0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0000 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICEB.K1.INIT 0010001000100010 +word: SLICEC.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R20C38:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0401 +arc: C4 H01E0001 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K1.INIT 0100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C39:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: B4 V02N0501 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 F0 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R20C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1101010111000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R20C41:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0203 V01N0001 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 H02E0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C42:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02E0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 S1_V02N0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICED.K0.INIT 1011101100001010 +word: SLICED.K1.INIT 1011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C43:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0101 V06S0103 +arc: A0 F7 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D4 V02N0601 +arc: D7 H02E0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C44:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V06N0003 +arc: A0 V01N0101 +arc: A2 V02S0501 +arc: A3 E1_H01E0001 +arc: B1 Q1 +arc: B3 V02N0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: A0 F7 +arc: A2 V02S0501 +arc: A4 V02N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 F6 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 0101000101000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000111000000010 +word: SLICEA.K0.INIT 1111001111100010 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R20C46:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V01N0001 +arc: A0 H02W0501 +arc: A3 V02N0701 +arc: A7 E1_H01W0000 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D7 S1_V02N0601 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R20C47:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: M0 V00B0000 +arc: M1 H02E0001 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F2 +arc: V00B0100 Q5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 S1_V02N0701 +arc: A1 V01N0101 +arc: A2 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 N1_V02S0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A3 H02W0501 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: B1 V00B0000 +arc: B4 V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q7 +arc: V00B0000 F6 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C50:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F7 +arc: A3 S1_V02N0701 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 H01W0100 +arc: B3 V01N0001 +arc: B5 V02S0501 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C5 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 V01S0100 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010000010001000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C51:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 N1_V02S0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011000000111010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R20C52:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A5 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B6 S1_V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F6 +arc: S1_V02S0401 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R20C53:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06S0203 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H00R0000 +arc: B1 V00B0000 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B7 V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R20C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0701 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000000001110111 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H02E0501 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C1 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000111101000100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C57:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0501 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R20C58:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A4 F7 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 H02E0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 F6 +arc: C5 F6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 F7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 0001000100110011 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R20C59:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: B0 N1_V02S0101 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: C0 N1_V02S0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C60:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 V01N0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R20C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 V02N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 H02W0701 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: C0 F4 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C62:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 F7 +arc: A7 H00R0000 +arc: B1 H01W0100 +arc: B2 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F2 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R20C63:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0501 +arc: A3 V00T0000 +arc: A5 S1_V02N0301 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B5 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F7 +arc: V00T0000 Q0 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R20C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 E1_H02W0601 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 F1 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q7 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 0101010000000100 +word: SLICED.K1.INIT 1111111001010100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000000010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: A3 H02W0501 +arc: A4 W1_H02E0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: V00T0100 F3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M1 H02E0001 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000000001110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEC.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C67:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0100110001001100 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 H02W0201 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A3 S1_V02N0701 +arc: A5 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEB.K0.INIT 1011111110001100 +word: SLICEB.K1.INIT 1010111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R20C69:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B1 V00T0000 +arc: B4 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: S3_V06S0303 F6 +arc: V00B0000 F6 +arc: V00B0100 F5 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R20C70:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B5 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R20C71:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 H01E0001 +arc: A4 W1_H02E0501 +arc: A7 H02W0501 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B7 V02N0701 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 W1_H02E0401 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 Q3 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R20C72:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A7 H02W0701 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: V00B0100 F7 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R20C73:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A4 V00T0000 +arc: B1 V00B0000 +arc: B4 H02E0101 +arc: C0 F4 +arc: C1 V02N0401 +arc: C4 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R20C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 V01N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: C0 H00R0100 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V06S0103 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 F7 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B1 V00B0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 F0 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F1 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C76:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: E1_H02E0001 Q2 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 Q5 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: S1_V02S0401 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C78:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A6 V02S0101 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 F7 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICED.K1.INIT 1111000000110000 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R20C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 V02S0501 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 F1 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R20C80:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0601 F6 +arc: V00B0000 F4 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C81:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F7 +arc: A2 V01N0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: V01S0000 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B6 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 Q6 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C84:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 E1_H01W0000 + +.tile R20C85:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C86:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D4 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V02S0001 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C88:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0101000011110000 +word: SLICEA.K0.INIT 0000000001110000 +word: SLICEA.K1.INIT 1111111101110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C89:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0001000001010000 +word: SLICEA.K1.INIT 1011101011111010 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICEB.K0.INIT 0001000001010000 +word: SLICEB.K1.INIT 1011101011111010 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R20C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 N1_V02S0701 +arc: A2 V00T0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0101 +arc: B4 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 F0 +arc: D4 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000001010111 +word: SLICEB.K0.INIT 0101011100000000 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0011011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C91:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A1 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 0101111100000000 +word: SLICEB.K1.INIT 0001101100011011 +word: SLICED.K1.INIT 1000000011001100 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEC.K0.INIT 0100010001001100 +word: SLICEB.K0.INIT 0011001111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R20C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H00R0000 +arc: A3 F7 +arc: A4 V02S0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 H02W0701 +arc: B1 E1_H02W0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 W1_H02E0401 +arc: C3 F6 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0001 +arc: D5 N1_V02S0601 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R20C93:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 V00B0000 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C1 V02S0601 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F2 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000110000 +word: SLICED.K1.INIT 1101000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R20C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 V01N0101 +arc: C7 F6 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F4 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1010010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 F7 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02S0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 F2 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100001100000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000010010000100 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R20C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 F4 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R20C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A0 F5 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: A3 V00B0000 +arc: A4 F7 +arc: A5 V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R20C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H02W0301 +arc: A1 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 H02E0401 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: S1_V02S0201 F0 +arc: V00B0100 F7 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R20C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 W1_H02E0701 +arc: A7 N1_V02S0101 +arc: B1 V00T0000 +arc: B3 H01W0100 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C1 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D1 V00T0100 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02S0501 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0101 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: N1_V01N0001 F7 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 V00B0100 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 N1_V02S0701 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C1 H02E0401 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0000001111001111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100001100000000 +word: SLICEA.K0.INIT 0011001111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R21C103:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: V01S0100 F3 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C104:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A2 F7 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C105:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 H02E0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 F7 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B3 F1 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C7 H02W0601 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 F0 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C106:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A6 N1_V02S0101 +arc: B0 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0701 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: C0 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C107:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H01E0001 +arc: A2 H02W0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D1 F2 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C108:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V01N0001 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C109:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R21C110:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 H02W0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H06W0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A7 N1_V01S0100 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 F0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R21C111:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R21C112:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C113:PLC2 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile R21C114:PLC2 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 S3_V06N0103 + +.tile R21C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: A0 V02N0701 +arc: B0 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011101000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C15:PLC2 +arc: H00L0100 E1_H02W0301 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: A0 H00L0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1100110001011010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R21C16:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0101 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1011111000010100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1000100010111000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C17:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A7 N1_V01N0101 +arc: B0 H02E0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: S3_V06S0003 Q3 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C18:PLC2 +arc: H00L0000 H02E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A4 N1_V01S0100 +arc: A6 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 W1_H02E0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1000100011011000 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1000100011011000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C19:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A4 N1_V01S0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V01S0000 +arc: C0 F4 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C20:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010000010101100 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICEB.K0.INIT 1010000011100100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C21:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C22:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C23:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H02W0201 +arc: M4 H02E0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0201 Q2 +arc: W1_H02W0101 Q3 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K0.INIT 1111010000000100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C24:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0000 H02W0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00R0000 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 Q7 +arc: B0 E1_H01W0100 +arc: B2 H02E0301 +arc: C0 V02N0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C25:PLC2 +arc: H00L0100 W1_H02E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H02E0501 +arc: A4 S1_V02N0101 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 F0 +arc: LSR0 V00B0100 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1101000111100010 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C26:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0701 S1_V02N0701 + +.tile R21C29:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R21C32:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: S3_V06S0103 N3_V06S0003 + +.tile R21C33:PLC2 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0701 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 H02W0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A6 N1_V02S0301 +arc: B0 F3 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C34:PLC2 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F7 +arc: A4 V00T0000 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1000100011111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A3 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: C0 V02N0601 +arc: C2 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D4 H01W0000 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R21C36:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02E0201 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 Q1 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000001010000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C37:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B3 S1_V02N0301 +arc: B5 H00L0000 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 F4 +arc: C2 H00R0100 +arc: C3 V02S0601 +arc: C4 N1_V02S0001 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R21C38:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 F2 +arc: V01S0100 F1 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000010000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R21C39:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A7 V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100111000001010 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R21C40:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H00L0100 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A6 F5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1100111000001010 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02S0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q4 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1000100011111000 +word: SLICEC.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C42:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 E1_H01W0000 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 V02S0701 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C43:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00R0000 +arc: A4 W1_H02E0701 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 F6 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H01W0000 +arc: D5 N1_V02S0601 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C44:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0701 +arc: A1 F5 +arc: A2 H02E0701 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICED.K0.INIT 0000111101110111 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C45:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 H01E0001 +arc: A5 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1110010011101110 +word: SLICEA.K1.INIT 1011101111110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C46:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: B1 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0401 F4 +arc: S1_V02S0401 F6 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06N0303 +arc: A0 H02E0501 +arc: A1 E1_H02W0501 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B3 F1 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D3 H02E0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M1 W1_H02E0001 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0401 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0501 +arc: A1 H01E0001 +arc: A5 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C2 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 Q7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0101001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C49:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 V02N0501 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 Q5 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICEA.K1.INIT 1011100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C50:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C51:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: A3 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: V01S0100 F1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001100010011 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R21C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: S1_V02S0001 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000101010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R21C53:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A7 V00T0100 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0111011101000100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R21C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEA.K0.INIT 1111001110101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 V02S0601 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0601 F6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C56:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 S1_V02N0501 +arc: A3 V00T0000 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: S1_V02S0201 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1110001011111111 +word: SLICEA.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C57:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A6 F7 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 1111111001010100 +word: SLICED.K0.INIT 0000000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C58:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A6 V00T0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 H02E0601 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q3 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 F5 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C60:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: S3_V06S0203 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0010001001110010 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: B0 H02E0301 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: C0 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 Q4 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R21C62:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B7 N1_V02S0701 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V01S0100 Q1 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C63:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H01E0001 +arc: A5 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V02N0101 F1 +arc: S1_V02S0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110001011100010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C64:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C0 F4 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H00R0100 Q5 +arc: H01W0100 F6 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1011100010111000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101100011011000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A5 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0301 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 V02S0601 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 H00R0100 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B6 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0100 Q5 +arc: H01W0100 Q3 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 0001010110111111 +word: SLICED.K0.INIT 0001001100010011 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C68:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: W1_H02W0401 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1110001011111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R21C69:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEA.K1.INIT 1101110111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0101 +arc: B3 V02S0101 +arc: B7 W1_H02E0301 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0501 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C71:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A6 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: C0 H00L0000 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F5 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C72:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 V02S0101 +arc: A7 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0011111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C73:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A5 H02E0501 +arc: B0 V02N0301 +arc: B5 H00L0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R21C74:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: C0 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R21C75:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A3 H02W0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B7 N1_V01S0000 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0401 +arc: C7 F4 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 S1_V02N0401 +arc: D7 H01W0000 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0101 F1 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1010000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C76:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0001 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 N1_V01S0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: C0 W1_H02E0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C77:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 F4 +arc: C3 F4 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 N1_V02S0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B5 H02W0101 +arc: C0 H00L0000 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R21C79:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B5 V02N0701 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C3 F6 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H02W0701 +arc: A1 H00R0000 +arc: A3 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C1 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C81:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V02S0701 +arc: A5 E1_H02W0701 +arc: A6 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C82:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: A0 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 W1_H02E0301 +arc: B4 V02S0501 +arc: B6 H02W0301 +arc: C1 H02E0401 +arc: C2 F6 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D6 V02S0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R21C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 H02E0701 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B6 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 H01E0101 +arc: D4 H02W0201 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 F5 +arc: A5 H02W0701 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B5 V02S0701 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V02N0001 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEB.K0.INIT 1100111100000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001010000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R21C85:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 V06S0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A6 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C6 E1_H02W0401 +arc: D1 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M0 H02E0601 +arc: S1_V02S0201 F0 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C86:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 N1_V02S0001 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H02W0501 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0501 +arc: B5 S1_V02N0701 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V00B0100 F7 +arc: V00T0100 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R21C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R21C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 V00T0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F4 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101010100000000 +word: SLICEB.K1.INIT 0000000000000011 +word: SLICED.K1.INIT 1000000011001100 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R21C89:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 V02N0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A7 W1_H02E0701 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICEB.K0.INIT 0101111100111111 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICED.K0.INIT 0011111100111111 +word: SLICED.K1.INIT 0001110100011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R21C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A5 V02N0301 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0001010100000000 +word: SLICEB.K1.INIT 1011111110101010 +word: SLICEC.K0.INIT 0011111100111111 +word: SLICEC.K1.INIT 0100011101000111 +word: SLICED.K0.INIT 0000000001001100 +word: SLICED.K1.INIT 1111111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R21C91:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V02N0301 +arc: A6 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000001100010011 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000110000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R21C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D2 F0 +arc: D3 H01E0101 +arc: D4 N1_V02S0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001010000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R21C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H01W0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1011101100001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R21C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C1 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 F7 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A5 H02E0701 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C4 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: N3_V06N0303 F5 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R21C96:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A6 W1_H02E0501 +arc: A7 N1_V01S0100 +arc: B0 F1 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 V02S0601 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: D0 E1_H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F0 +arc: N3_V06N0103 F1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R21C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C1 N1_V01N0001 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C7 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 V02S0201 +arc: D1 N1_V02S0001 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B4 H02W0301 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: C0 E1_H02W0601 +arc: C1 H00R0100 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F4 +arc: V00T0000 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C101:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R23C102:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 H02E0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 N1_V02S0701 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0701 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V00B0100 +arc: C2 W1_H02E0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 F6 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +arc: S1_V02S0501 F5 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C103:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A2 H00L0100 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 S1_V02N0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C2 V02S0601 +arc: C5 V01N0101 +arc: C6 N1_V02S0201 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: N1_V01N0001 F6 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C104:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: C5 H02E0401 +arc: D0 V00T0100 +arc: D5 V02S0601 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 F5 +arc: A5 S1_V02N0301 +arc: A6 V02S0101 +arc: A7 E1_H02W0701 +arc: B0 H02E0301 +arc: B3 H00R0100 +arc: B4 F3 +arc: B5 V02S0501 +arc: B7 N1_V02S0501 +arc: C0 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C106:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0501 +arc: A1 F5 +arc: A3 H02E0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B1 F3 +arc: B3 H02E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 W1_H02E0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D3 N1_V01S0000 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0101 F1 +arc: S1_V02S0001 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C107:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0101 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V02N0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C108:PLC2 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1000001011000011 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R23C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H01E0001 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C110:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C111:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A3 N1_V02S0501 +arc: B0 V00B0000 +arc: C0 S1_V02N0401 +arc: C3 H02W0601 +arc: D0 E1_H02W0201 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: M0 V00T0000 +arc: V01S0000 F0 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C112:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F6 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C113:PLC2 +arc: H00L0000 H02E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C114:PLC2 +arc: N1_V02N0401 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C13:PLC2 +arc: S1_V02S0501 E1_H02W0501 + +.tile R23C14:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A4 E1_H02W0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C15:PLC2 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A2 V02N0501 +arc: A4 H02W0701 +arc: B0 V00B0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: C0 H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C16:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0501 Q7 +arc: V01S0000 F4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C17:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 V02N0601 +arc: A0 V01N0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: B4 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: LSR1 H02W0501 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 F0 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111011000000110 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C18:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 N1_V02S0501 +arc: A6 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1011111000010100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C19:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A6 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B4 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C20:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 H02E0501 +arc: A2 V00T0000 +arc: A4 H02W0701 +arc: B0 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H01E0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C21:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A2 V00T0000 +arc: A4 V00T0000 +arc: A6 V02N0101 +arc: B0 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: V01S0000 F6 +arc: V01S0100 Q5 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C22:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q3 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C23:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B4 H00L0000 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K0.INIT 1111010000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C24:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 E1_H01E0001 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B4 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100111000000010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C25:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: V01S0100 F4 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100110001011010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C26:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 H01E0101 +arc: A0 H01E0001 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C31:PLC2 +arc: S3_V06S0003 E3_H06W0003 + +.tile R23C32:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 + +.tile R23C33:PLC2 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 E1_H02W0701 +arc: A0 F5 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: C0 N1_V01S0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 N1_V02S0201 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C34:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 F4 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1011001110100000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C35:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B5 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C36:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A2 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C5 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 N1_V02S0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1010000010100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R23C37:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A4 F5 +arc: A6 H00L0000 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 H00L0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C38:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A6 F5 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: B1 F3 +arc: B2 H00L0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 N1_V02S0201 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110001010000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100000011101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C39:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A0 F5 +arc: A1 F7 +arc: A2 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000100011111000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K0.INIT 1101010111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C3:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R23C40:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A0 F7 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C41:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: B5 H02E0101 +arc: B6 N1_V02S0501 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D6 W1_H02E0201 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C42:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06S0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 V02S0501 +arc: A1 H01E0001 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 N1_V02S0601 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: W1_H02W0101 F3 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C43:PLC2 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 F5 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: M0 H02W0601 +arc: M1 H02W0001 +arc: M2 H02W0601 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0601 F4 +arc: V00B0100 Q7 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C44:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A3 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B4 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICED.K0.INIT 0000011111110111 +word: SLICED.K1.INIT 0101001101011111 +word: SLICEA.K1.INIT 1101111110001010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C45:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEC.K0.INIT 1010100000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICEB.K1.INIT 0101001101011111 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R23C46:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000001100110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R23C47:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H02W0101 +arc: B4 V02N0501 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: N3_V06N0303 F6 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C48:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 F7 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B1 E1_H01W0100 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H01E0001 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B3 F1 +arc: B5 H00R0000 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 E1_H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: N3_V06N0203 F7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: A0 S1_V02N0501 +arc: A1 H02E0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 V02N0301 +arc: B4 F1 +arc: B5 F1 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A0 F7 +arc: A1 H00L0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C52:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B2 H02W0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C53:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02W0701 +arc: A3 F7 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F7 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0100 Q7 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0001010110111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H01E0001 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 V00B0000 +arc: B2 V02N0101 +arc: B3 N1_V02S0101 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: C0 E1_H01W0000 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F6 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0011001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C55:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: A1 H02W0501 +arc: A2 F7 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 N1_V02S0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H01E0101 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1000100010100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A3 H02W0701 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: V00T0100 Q1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0101010000000100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B7 V00B0100 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C58:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A2 E1_H01E0001 +arc: A5 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 N1_V01S0100 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R23C59:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R23C60:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B0 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: B0 F3 +arc: B2 S1_V02N0301 +arc: B3 V02S0301 +arc: C0 H02E0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +word: SLICEB.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1101111111010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M4 E1_H02W0401 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0601 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C63:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 S1_V02N0501 +arc: A3 V02S0701 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B7 N1_V02S0701 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D7 H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C64:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A5 N1_V02S0101 +arc: A6 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F4 +arc: N3_V06N0103 F1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C65:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0301 +arc: C0 V02S0401 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q7 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001101101011111 +word: SLICEA.K0.INIT 0000110100001000 +word: SLICEA.K1.INIT 1110111111101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C66:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C67:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H00L0000 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B6 F1 +arc: B7 V02N0701 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M5 E1_H02W0001 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 F6 +arc: V00B0100 Q5 +arc: W1_H02W0101 F3 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R23C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 N1_V02S0101 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B5 H02E0301 +arc: B6 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 F4 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F2 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000011111110111 +word: SLICEA.K1.INIT 1010111111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R23C69:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: N1_V02N0501 F7 +arc: W1_H02W0001 F0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R23C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: B3 V01N0001 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0100 Q7 +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A7 E1_H02W0501 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C5 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: V01S0000 F6 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000010010101110 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R23C72:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A5 H02E0501 +arc: B3 V02N0101 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 H02E0601 +arc: N1_V01N0001 F5 +arc: N1_V02N0701 F7 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C73:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 S1_V02N0101 +arc: A7 H02E0501 +arc: B2 E1_H02W0301 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C2 N1_V01N0001 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D2 V00T0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N3_V06N0303 F5 +arc: V01S0000 F2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C74:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B1 H02W0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 F4 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V01N0101 F0 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001000100110011 +word: SLICEA.K0.INIT 0101000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R23C75:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 F5 +arc: A4 S1_V02N0301 +arc: A5 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C1 H00R0100 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 H02E0401 +arc: D1 H01E0101 +arc: D4 N1_V02S0401 +arc: D5 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: S3_V06S0003 F0 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C76:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 V00B0100 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C77:PLC2 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H02W0501 +arc: A7 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C78:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: B0 E1_H02W0301 +arc: B1 V02S0301 +arc: B2 N1_V02S0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R23C79:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C80:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C81:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A4 V02N0101 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K0.INIT 1100000011110000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R23C82:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1111000001010000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B4 V01S0000 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V02S0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R23C84:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A6 F5 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 F4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: A1 V02S0501 +arc: A4 H02W0501 +arc: A5 V02N0301 +arc: A6 F5 +arc: B1 H00R0100 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: B6 E1_H02W0101 +arc: C1 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: D1 W1_H02E0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 F0 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 H02W0601 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 F1 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C7 V01N0101 +arc: D0 E1_H02W0001 +arc: D1 F0 +arc: D2 H02W0201 +arc: D4 F2 +arc: D5 V01N0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C87:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 F6 +arc: C4 H02W0601 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R23C88:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 H02W0501 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 V02S0401 +arc: C1 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0501 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: V01S0000 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0101010100110011 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICED.K0.INIT 0001000001010000 +word: SLICED.K1.INIT 1101110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: S1_V02S0501 F7 +arc: V01S0000 F0 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02W0501 +arc: A2 N1_V02S0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: B0 V00B0000 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: C2 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1100010001000100 +word: SLICEA.K0.INIT 0000000000100010 +word: SLICEC.K1.INIT 0000000101010101 +word: SLICEB.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R23C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V02N0301 +arc: B2 H02W0301 +arc: B4 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 V00T0100 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D4 H00L0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K0.INIT 1000111100000000 +word: SLICED.K0.INIT 0000000000001100 +word: SLICEB.K0.INIT 0000000001010111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R23C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0000 +arc: A5 F7 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 F3 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C7 W1_H02E0401 +arc: D0 N1_V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 H02W0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C7 H01E0001 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F0 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C94:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A4 E1_H02W0501 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 E1_H02W0701 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02S0401 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R23C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 E1_H02W0301 +arc: B6 F1 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V01N0101 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 H02W0701 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: D0 V02S0001 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R23C97:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 F7 +arc: A2 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: S3_V06S0003 F3 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R23C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0701 +arc: A3 E1_H01E0001 +arc: A4 W1_H02E0701 +arc: A5 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: N1_V02N0501 F5 +arc: V01S0000 F0 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: B0 W1_H02E0301 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 F4 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0501 +arc: B0 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 V02N0701 +arc: C0 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0101 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 F5 +arc: B1 V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 F4 +arc: D1 H01E0101 +arc: D3 H02W0001 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: M2 V00B0100 +arc: N1_V02N0601 F6 +arc: S3_V06S0203 F7 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C103:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 H00R0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1001000010010000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R24C104:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 S1_V02N0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 S1_V02N0401 +arc: D5 V02S0401 +arc: D6 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R24C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V01S0100 +arc: A5 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 H01E0101 +arc: B5 W1_H02E0101 +arc: B7 V00B0000 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 H00R0000 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 F5 +arc: B0 H00R0100 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 F3 +arc: C0 H00L0100 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 F4 +arc: D0 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C107:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 V02N0501 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 V00T0000 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: D1 W1_H02E0001 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: S1_V02S0201 F0 +arc: V00B0100 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C108:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: S1_V02S0201 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R24C109:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: A5 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 F7 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C110:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 E1_H02W0501 +arc: A2 V02S0701 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C111:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C112:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A1 V02S0501 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1011101100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C113:PLC2 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 V01N0101 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1111000001010000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C114:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V01N0101 +arc: B0 V02N0101 +arc: B3 E1_H01W0100 +arc: C0 H00L0000 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C115:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C117:PLC2 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 + +.tile R24C13:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: M0 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C14:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C15:PLC2 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C16:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 Q5 +arc: B0 H02W0301 +arc: B1 H01W0100 +arc: B2 H02W0101 +arc: B4 E1_H02W0301 +arc: C0 V02N0601 +arc: C2 V02N0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: S1_V02S0301 Q1 +arc: V00T0000 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C17:PLC2 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V06S0003 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C18:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: C0 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C19:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C20:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B6 E1_H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V02N0701 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C21:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 H01E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A6 W1_H02E0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C22:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 V02N0301 +arc: A6 E1_H02W0701 +arc: B0 V01N0001 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: C0 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H02E0001 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q1 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C23:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A6 V02N0301 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 Q0 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C24:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A2 V02S0501 +arc: B2 V02N0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: LSR1 V00T0000 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C25:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: B6 H01E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q7 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C26:PLC2 +arc: N1_V02N0301 H02E0301 + +.tile R24C31:PLC2 +arc: S3_V06S0103 E3_H06W0103 + +.tile R24C32:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V02S0301 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 E1_H01W0000 + +.tile R24C33:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: A0 N1_V02S0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111010001000100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010000011101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C34:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: A0 E1_H01E0001 +arc: A1 F7 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: S1_V02S0301 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C35:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 S1_V02N0501 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 F7 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C37:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 H01E0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 H00L0100 +arc: A5 H02E0501 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C38:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 S1_V02N0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 F4 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1010000011101100 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111010001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C39:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 H01E0001 +arc: C0 V02S0401 +arc: C2 S1_V02N0401 +arc: C5 V00T0000 +arc: D0 V02S0201 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R24C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 V01N0101 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A7 N1_V01S0100 +arc: B0 F1 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 F6 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D6 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: S1_V02S0601 F6 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C41:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 V02S0301 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B3 E1_H02W0101 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 V02S0601 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111000001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V01S0000 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: C6 F4 +arc: C7 H01E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000010000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C43:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 F3 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F4 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C44:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A3 H00L0100 +arc: B3 V02N0101 +arc: C3 H02W0401 +arc: D3 V02S0201 +arc: F3 F3_SLICE +arc: N1_V02N0301 F3 +word: SLICEB.K1.INIT 0101001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C45:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0601 F6 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C46:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B6 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D4 F0 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +word: SLICEC.K0.INIT 1000110010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C47:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: B2 V02S0101 +arc: C1 H02W0601 +arc: C2 H00R0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R24C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V06N0203 +arc: A1 H00R0000 +arc: A4 V02N0101 +arc: A5 H02W0501 +arc: A7 E1_H01W0000 +arc: B2 V02S0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C1 V02N0401 +arc: C3 W1_H02E0401 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: A7 V00T0100 +arc: B0 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C3 H02E0601 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D3 H02E0001 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: N1_V01N0101 F0 +arc: N1_V02N0701 F7 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F6 +arc: S1_V02S0201 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1110110001001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1010000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C51:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 W1_H02E0501 +arc: A1 H01E0001 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 E1_H02W0101 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R24C52:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 S1_V02N0701 +arc: B6 V02S0501 +arc: C0 F6 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C53:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 E1_H02W0101 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 W1_H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C54:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C55:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C56:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F1 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 0011010100111111 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000011100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C57:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H01E0001 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M0 H02E0601 +arc: M1 W1_H02E0001 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F5 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R24C58:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02E0701 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0103 F2 +arc: S1_V02S0201 Q2 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V00T0000 +arc: A7 H02E0701 +arc: B1 V02N0101 +arc: B2 H01W0100 +arc: B4 H02W0101 +arc: B5 S1_V02N0501 +arc: B7 V02N0501 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F4 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 0001000011011100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R24C60:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A4 E1_H01W0000 +arc: A5 H02E0501 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H01W0000 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F6 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R24C61:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0701 +arc: A3 F5 +arc: A4 F5 +arc: A5 V00T0100 +arc: B1 V00B0000 +arc: B4 V00B0100 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 0100011101110111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C62:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0501 +arc: A5 S1_V02N0101 +arc: B1 H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M0 V00T0000 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F5 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C63:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 N1_V02S0301 +arc: B1 V00B0000 +arc: B5 V02N0501 +arc: C1 H02W0601 +arc: C5 N1_V02S0201 +arc: D1 V00B0100 +arc: D5 H02E0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C64:PLC2 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1111001111100010 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C65:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R24C66:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A3 H02W0501 +arc: A6 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: C1 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 1110010000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEA.K0.INIT 1110111001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C67:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A3 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 V02N0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1110001011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 F6 +arc: V00T0000 F2 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1110001011111111 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 F0 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C70:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 W1_H02E0701 +arc: A3 V02S0501 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A7 E1_H01W0000 +arc: B3 H02E0101 +arc: B5 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F5 +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R24C71:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 S1_V02N0701 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A6 H02W0501 +arc: B1 E1_H02W0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C1 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H01E0101 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: V01S0100 Q5 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010001010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C72:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 H02E0501 +arc: A6 S1_V02N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0303 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R24C73:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A3 V02N0501 +arc: B0 F3 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: C0 H00L0100 +arc: C3 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C74:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 F1 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0601 +arc: C2 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 F0 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C75:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: H00L0100 V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 H02E0701 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B2 H02W0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C2 S1_V02N0401 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: D2 V00B0100 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R24C76:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A4 V00T0000 +arc: A6 S1_V02N0301 +arc: B1 Q1 +arc: B4 V02S0701 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D4 W1_H02E0001 +arc: D6 V00B0000 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C77:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 H02E0501 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 F1 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D7 N1_V02S0601 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C78:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A4 V02S0301 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C79:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C80:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q4 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C81:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 V00T0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B7 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D7 H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C82:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 V02N0101 +arc: B3 H02W0301 +arc: C0 H02E0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0701 V06S0203 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B4 F1 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 H02E0701 +arc: A6 W1_H02E0701 +arc: B0 H02E0101 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H01W0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 H02W0501 +arc: A4 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B2 E1_H02W0101 +arc: B4 H00L0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 S1_V02N0401 +arc: C4 F6 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D2 H02W0001 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 N3_V06S0103 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 N1_V02S0701 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0101 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B7 V02N0501 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C7 V02N0001 +arc: D1 H02E0001 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C87:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0000 +arc: A3 V00B0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0601 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V01N0001 +arc: A4 S1_V02N0101 +arc: B0 V00B0000 +arc: B4 V02S0701 +arc: C0 V02N0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02S0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R24C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 S1_V02N0701 +arc: A2 V02N0701 +arc: B1 H01W0100 +arc: B3 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C7 V02S0201 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICED.K1.INIT 0011111100000000 +word: SLICEB.K0.INIT 0101111101011111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06N0303 +arc: A1 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C3 S1_V02N0401 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D6 F0 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: N3_V06N0203 F4 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 0000000000100010 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICED.K1.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06N0203 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 H02E0301 +arc: C2 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: D0 W1_H02E0201 +arc: D1 H01E0101 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F6 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0001000111011101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R24C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0701 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000100001000100 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0101010100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R24C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 W1_H02E0101 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 S1_V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F7 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: A1 H01E0001 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: B4 H00L0000 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: C1 V02S0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0601 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 N1_V02S0001 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F1 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R24C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0001 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D5 H01W0000 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0100 F7 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R24C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 F4 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 E1_H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: V01S0000 F6 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 N1_V02S0101 +arc: B1 V01N0001 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 N1_V02S0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R24C99:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0101000001010000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 V02N0701 +arc: A2 F7 +arc: A3 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02S0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C102:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H01E0001 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: B6 V00B0100 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: D0 H02W0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: N1_V02N0301 F1 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000001000000000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C103:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 F7 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 V01S0100 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R25C104:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: B1 H02W0101 +arc: C1 H00R0100 +arc: D1 E1_H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C105:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R25C106:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A7 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C107:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: B5 H02E0301 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 N1_V01S0100 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R25C108:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B7 N1_V01S0000 +arc: C1 H02W0601 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C109:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: B1 H02E0101 +arc: B2 H02W0301 +arc: B4 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 F1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C110:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C111:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B7 V02N0701 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0701 Q7 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C112:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 H01E0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R25C113:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1101110100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C114:PLC2 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C115:PLC2 +arc: N1_V02N0401 S1_V02N0101 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 S3_V06N0303 + +.tile R25C13:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: A0 E1_H02W0701 +arc: A2 N1_V02S0501 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02E0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C15:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 H01E0101 +arc: A0 H02W0501 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A6 V02N0101 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: B4 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C16:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1101000111100010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C17:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V01N0101 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0401 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0601 Q4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C18:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 V02N0701 +arc: B6 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q7 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000010101100 +word: SLICED.K0.INIT 1101100011011000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C19:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0000 +arc: A2 N1_V02S0501 +arc: B0 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C0 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010001110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C20:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0101 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q7 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000110110001000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C21:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 E1_H01W0000 +arc: A2 E1_H02W0701 +arc: B0 H02W0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0501 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C22:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C23:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B4 V02S0501 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C24:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 H02W0701 +arc: B0 V02S0301 +arc: B2 H00L0000 +arc: C0 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V01N0101 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C25:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H01E0101 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C26:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: W1_H02W0701 S1_V02N0701 + +.tile R25C27:PLC2 +arc: W1_H02W0401 W3_H06E0203 + +.tile R25C32:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 + +.tile R25C33:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: H00L0000 H02E0001 +arc: H00R0100 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 F5 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 N1_V02S0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C34:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H02W0501 +arc: A1 H01E0001 +arc: A2 F7 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010000011101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C35:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 H01E0001 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q4 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010000011101100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1011101000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C36:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C37:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 F7 +arc: A3 H02E0701 +arc: B0 V00T0000 +arc: B5 H02E0101 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C5 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V00T0100 +arc: D5 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C38:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: A0 V01N0101 +arc: A1 H00L0000 +arc: A3 H02E0701 +arc: A5 H02E0501 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 H02E0601 +arc: C5 W1_H02E0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D3 V02S0001 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C39:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 H02W0501 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1101100011011000 +word: SLICEB.K1.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C40:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 E1_H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H01E0101 +arc: B6 V02N0701 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000111110001000 +word: SLICED.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 F3 +arc: B2 H02W0301 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C42:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: A0 N1_V02S0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B7 N1_V02S0701 +arc: C0 W1_H02E0601 +arc: C1 F4 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 H02W0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V02N0301 F1 +arc: V01S0000 F3 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C43:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H00L0100 +arc: B3 S1_V02N0101 +arc: C3 W1_H02E0401 +arc: D3 H02E0201 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C44:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F7 +arc: A2 H02E0501 +arc: A4 H02W0701 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B2 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C2 V02N0401 +arc: C4 V02N0201 +arc: C7 H02E0601 +arc: D0 E1_H02W0001 +arc: D2 H00R0000 +arc: D4 F2 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F0 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R25C45:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R25C46:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B3 H02W0301 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: S3_V06S0203 Q4 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C47:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: A4 E1_H01W0000 +arc: B3 H02W0301 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 Q3 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R25C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: A7 H02E0701 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: V00B0000 F6 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R25C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A6 W1_H02E0501 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F2 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1010100000100000 +word: SLICEB.K0.INIT 1010110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C50:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 V02S0301 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1101111111010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C51:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V00T0000 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 Q4 +arc: E1_H02E0501 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0601 F4 +arc: V00T0100 F3 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEB.K1.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C53:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A7 H00R0000 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 N1_V02S0501 +arc: B7 S1_V02N0501 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H01E0001 +arc: C5 V01N0101 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D7 H00L0100 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: S1_V02S0401 F4 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0101000001000100 +word: SLICEB.K1.INIT 1111111010101110 +word: SLICED.K1.INIT 0011001000010000 +word: SLICEC.K1.INIT 1111111000110010 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R25C54:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02E0301 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02E0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V02S0001 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D6 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: N1_V02N0301 F1 +arc: N3_V06N0003 F0 +arc: V00B0000 F6 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0010001000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C55:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: B0 V00T0000 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C56:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 E1_H01W0000 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0601 F6 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0101000001011100 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D1 F2 +arc: D2 V02N0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R25C58:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A5 H02W0501 +arc: B0 V01N0001 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0101001101011111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R25C59:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 F5 +arc: A2 V02S0701 +arc: A5 V00T0100 +arc: B3 S1_V02N0101 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C60:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: C0 F4 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0011111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R25C61:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A3 H02E0701 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C62:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A6 N1_V01S0100 +arc: B3 H02W0101 +arc: C0 H02W0401 +arc: C3 N1_V01S0100 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0301 F3 +arc: S1_V02S0601 Q4 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A3 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R25C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A6 H02W0501 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C65:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: B0 S1_V02N0301 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R25C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: A4 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V01N0101 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 F3 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0000101001001110 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 1100000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C68:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 N1_V02S0501 +arc: A5 N1_V02S0101 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C5 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D5 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00R0100 F5 +arc: H01W0100 F5 +arc: M0 V00B0000 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C69:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 E1_H02W0501 +arc: A5 V02S0301 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B7 E1_H02W0101 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 H02E0601 +arc: M6 H02E0401 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 0001101101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0011010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C70:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0101 +arc: B3 F1 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0100 Q3 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K0.INIT 0000010010101110 +word: SLICED.K1.INIT 0100010011101110 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C71:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B3 V02S0101 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D5 V02S0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R25C72:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A5 V02N0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B3 V02S0101 +arc: B5 F1 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q1 +arc: V01S0000 F1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C73:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02E0501 +arc: B1 E1_H02W0101 +arc: C1 H02E0401 +arc: D1 V02N0201 +arc: F1 F1_SLICE +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C74:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A6 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 N1_V02S0401 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: V01S0000 F3 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C75:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 V02S0401 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C77:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R25C78:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H02W0701 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B6 V02N0701 +arc: C0 S1_V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C79:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 E1_H02W0701 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 F3 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C80:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A7 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R25C81:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A6 F7 +arc: A7 V02N0301 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B6 F3 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 V02N0001 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0401 F6 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A6 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B4 V02N0701 +arc: B6 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101110100001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 H01E0101 +arc: B6 S1_V02N0501 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 F4 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F5 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 N1_V02S0501 +arc: A1 F7 +arc: A2 H02W0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0001 F0 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D1 W1_H02E0001 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R25C87:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 F0 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C88:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: A6 H02W0701 +arc: B4 V02N0701 +arc: C4 V00T0100 +arc: C6 V00T0000 +arc: D4 E1_H02W0201 +arc: D6 N1_V02S0401 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R25C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V01N0101 +arc: B6 H02W0101 +arc: C6 S1_V02N0001 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 1100111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R25C90:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: C7 W1_H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: V01S0000 F4 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICEC.K0.INIT 0011001111111111 +word: SLICEC.K1.INIT 0000110000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R25C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H00R0000 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 F3 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C2 F4 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F2 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001000100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R25C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: B0 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: C0 V02N0601 +arc: C6 V02N0201 +arc: D0 W1_H02E0201 +arc: D4 V02S0401 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R25C93:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 H02W0301 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R25C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A4 S1_V02N0301 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B4 V02S0701 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: C4 V02S0001 +arc: C6 V01N0101 +arc: C7 N1_V02S0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 H02E0201 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F4 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R25C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D1 W1_H02E0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R25C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0701 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C1 N1_V01S0100 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 W1_H02E0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: V01S0100 F3 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R25C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 F4 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: V00T0000 F2 +arc: V01S0000 F3 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 E1_H02W0701 +arc: B0 F3 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 H02W0001 +arc: D3 W1_H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F1 +arc: V01S0100 F4 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C101:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D3 V02S0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A2 F7 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B2 H01W0100 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 H01E0001 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: D0 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F6 +arc: S1_V02S0201 F2 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICED.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C103:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02S0101 +arc: B4 V02S0501 +arc: C4 V00T0100 +arc: D4 H02W0001 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C104:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 F5 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 V00T0100 +arc: B3 V01N0001 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D5 V00B0000 +arc: D6 E1_H02W0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 0000000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0100 F4 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C106:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 F5 +arc: A5 H02W0501 +arc: A7 W1_H02E0701 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B5 V00B0100 +arc: B7 N1_V02S0501 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D5 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C107:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C108:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0501 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 W1_H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: S3_V06S0003 Q0 +arc: V01S0000 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C109:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H02W0501 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 F1 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02S0001 +arc: D0 N1_V02S0001 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D5 N1_V02S0601 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C110:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06S0203 +arc: A0 F5 +arc: A1 V02N0501 +arc: A2 N1_V02S0701 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0301 +arc: A6 F7 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 N1_V02S0001 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D6 F2 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C111:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V02S0301 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C112:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02S0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D5 V01N0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C113:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F3 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1101000011010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C114:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C115:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: B0 V02N0101 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C116:PLC2 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile R26C117:PLC2 +arc: W1_H02W0401 S1_V02N0401 + +.tile R26C13:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: A0 V01N0101 +arc: B0 E1_H01W0100 +arc: B1 V01N0001 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: M0 V00B0100 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R26C14:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: A0 S1_V02N0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C15:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0100 +arc: A4 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C16:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A6 V02N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 F4 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000101110111000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1101111000010010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C17:PLC2 +arc: E1_H02E0601 V02S0601 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: A2 H00L0100 +arc: A4 N1_V02S0101 +arc: B0 W1_H02E0101 +arc: B4 H02E0301 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D5 H00R0100 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C18:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1110001011100010 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C19:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 + +.tile R26C20:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: A0 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C21:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V01S0000 F6 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A6 H02E0701 +arc: B0 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q7 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1101111000010010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C23:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 V06N0203 +arc: A0 H02E0501 +arc: A2 W1_H02E0501 +arc: A4 H02W0701 +arc: A6 W1_H02E0501 +arc: B0 V01N0001 +arc: B2 V02S0301 +arc: B4 H01E0101 +arc: C0 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C24:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A6 S1_V02N0101 +arc: B0 H02E0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 W1_H02E0301 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1000101110111000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C25:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 1101111000010010 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1101111000010010 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C26:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V02N0701 + +.tile R26C31:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: S1_V02S0501 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C32:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: B7 H02W0301 +arc: C0 F6 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000010001010100 +word: SLICEA.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C33:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H00R0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 V02N0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D5 H02W0001 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 0000001000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C34:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A6 F5 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: D0 W1_H02E0001 +arc: D2 E1_H02W0001 +arc: D3 F0 +arc: D4 F2 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C35:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: B1 H02E0101 +arc: B7 V02S0701 +arc: C1 S1_V02N0601 +arc: C7 E1_H01E0101 +arc: D1 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R26C36:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 + +.tile R26C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V01S0000 S3_V06N0103 + +.tile R26C38:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 N3_V06S0003 +arc: A0 W1_H02E0501 +arc: A1 F7 +arc: A3 H02E0701 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 V02S0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D1 F0 +arc: D3 V02S0001 +arc: D7 W1_H02E0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 S1_V02N0501 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0701 +arc: A4 V00T0100 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C41:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V02S0501 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0203 F7 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C42:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 F7 +arc: A7 N1_V02S0301 +arc: B1 V00B0000 +arc: B4 V02S0501 +arc: B7 S1_V02N0501 +arc: C1 H02E0601 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C7 H01E0001 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C43:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 V06N0103 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 N1_V02S0701 +arc: A4 E1_H02W0501 +arc: A5 V02S0101 +arc: A6 V02N0301 +arc: A7 F5 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02E0101 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 W1_H02E0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 W1_H02E0201 +arc: D6 F2 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000001110010 +word: SLICEB.K0.INIT 0000000000111010 +word: SLICED.K0.INIT 0101000001010001 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C44:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: A6 W1_H02E0501 +arc: B0 H02W0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 H02W0401 +arc: C4 V02S0201 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A5 W1_H02E0501 +arc: A7 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 F1 +arc: B5 V02S0701 +arc: B7 V00B0000 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D7 H02E0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N3_V06N0003 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEB.K1.INIT 1010100000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C46:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F7 +arc: A5 S1_V02N0101 +arc: A7 Q7 +arc: B5 V00B0100 +arc: C0 H00R0100 +arc: C1 V02S0401 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D5 S1_V02N0401 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 W1_H02E0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 F7 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C47:PLC2 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C48:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00T0000 +arc: A4 S1_V02N0301 +arc: A6 H02W0501 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 F6 +arc: C6 H02E0601 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000011111110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R26C49:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100101011111010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C50:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00R0000 +arc: A7 V02N0101 +arc: B1 E1_H01W0100 +arc: B6 V02N0701 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C51:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 F1 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1110010011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1110010000000000 +word: SLICEC.K1.INIT 1110010011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C52:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 V02N0501 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 F1 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 0000000010111000 +word: SLICEC.K1.INIT 1111111001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C54:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0100 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R26C55:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A3 H02W0501 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: M2 H02E0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q0 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C56:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 H02E0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B3 N1_V02S0301 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0011010100111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R26C59:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 F3 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEB.K0.INIT 1111000011101110 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R26C61:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +word: SLICEB.K0.INIT 0000110100001000 +word: SLICEB.K1.INIT 1111110111111000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111111000001110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICED.K1.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1101110110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V01N0101 +arc: A1 F7 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 F3 +arc: B2 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0203 F4 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 1001000010011001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICEA.K1.INIT 1011111110110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C64:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 1011100011111100 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEA.K1.INIT 1110111000101110 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEB.K1.INIT 1101110111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEC.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C66:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 Q3 +arc: V00T0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q3 +word: SLICEC.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C67:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 H02E0501 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: B0 V00B0000 +arc: B2 H02E0101 +arc: B4 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: C0 E1_H01W0000 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C69:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B7 V02N0501 +arc: C1 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R26C70:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 F7 +arc: A4 H02E0701 +arc: A7 Q7 +arc: B1 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F4 +arc: V01S0100 Q7 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C71:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 N1_V02S0701 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B3 S1_V02N0301 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D3 E1_H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V02N0501 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R26C73:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 V02S0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A3 H00L0100 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0101000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R26C74:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A3 F5 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: B0 V02N0101 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: C0 H00R0100 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: D0 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100000000110000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C75:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: B1 V02S0301 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: C1 H00L0100 +arc: C4 V01N0101 +arc: C5 E1_H02W0601 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F5 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C76:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 W1_H02E0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 N1_V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 N1_V01S0100 +arc: B4 N1_V01S0000 +arc: C4 V02S0201 +arc: D4 H00R0100 +arc: F4 F4_SLICE +arc: V01S0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R26C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 H02E0501 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 F3 +arc: B7 H02E0101 +arc: C1 N1_V02S0401 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: V01S0000 F0 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C79:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 H01W0100 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C80:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 V06S0303 +arc: A1 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C81:PLC2 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 H02E0301 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 V00T0000 +arc: B0 H02W0101 +arc: B2 V02N0301 +arc: B3 H02E0301 +arc: B5 S1_V02N0501 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C5 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: D5 F2 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C82:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0303 E1_H02W0601 + +.tile R26C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B2 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C5 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 F0 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R26C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 S1_V02N0101 +arc: B2 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010010100000000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R26C85:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 F5 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R26C86:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0701 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 F3 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F5 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C87:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: B1 V00T0000 +arc: B2 H02W0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: C0 V02N0601 +arc: C1 F4 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000100000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R26C88:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06S0003 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02S0501 +arc: A1 H02W0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: D0 H01E0101 +arc: D1 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 0100010001001100 +word: SLICEA.K1.INIT 0011011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0501 N3_V06S0303 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B5 N1_V01S0000 +arc: C1 H00L0100 +arc: C5 S1_V02N0001 +arc: D0 V02S0201 +arc: D1 H02W0201 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111001111 +word: SLICEC.K1.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R26C91:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 W1_H02E0601 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: D0 H02E0001 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: N1_V02N0301 F1 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1100001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R26C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D2 F0 +arc: D3 F2 +arc: D4 E1_H01W0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: D6 F0 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0303 F6 +arc: S3_V06S0103 F1 +arc: V01S0000 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R26C94:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 W1_H02E0401 +arc: C2 H00L0100 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: D2 E1_H02W0201 +arc: D5 H02W0001 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +arc: V00T0000 F2 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R26C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B1 H00R0100 +arc: B3 F1 +arc: B6 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C3 E1_H01W0000 +arc: C6 S1_V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D6 S1_V02N0601 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F6 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000010000000 +word: SLICEA.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R26C96:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 H02W0701 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 W1_H02E0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R26C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 H00R0000 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F3 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B0 F3 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 W1_H02E0601 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R26C99:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: A7 E1_H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 F0 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0101 F1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0501 +arc: A7 F5 +arc: B0 W1_H02E0301 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 F1 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 H02W0401 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 F2 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C101:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 W1_H02E0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 W1_H02E0301 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 F4 +arc: D0 F2 +arc: D1 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A4 V00T0000 +arc: A7 V02S0301 +arc: B1 H02W0101 +arc: B4 E1_H02W0301 +arc: B7 V02N0701 +arc: C1 V02N0401 +arc: C4 N1_V02S0201 +arc: C7 E1_H02W0601 +arc: D1 V02S0001 +arc: D4 N1_V02S0401 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C103:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A4 V02N0101 +arc: A6 N1_V02S0101 +arc: B0 H02W0101 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +arc: C0 S1_V02N0401 +arc: C4 V02S0201 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: D0 H02W0201 +arc: D4 H02E0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R27C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0101 +arc: B3 V02N0101 +arc: B4 F3 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V02N0501 F7 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C105:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 H02E0701 +arc: B0 W1_H02E0101 +arc: B3 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: D0 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00L0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R27C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00B0000 +arc: A5 H02W0501 +arc: B2 V02N0301 +arc: B5 S1_V02N0501 +arc: C2 N1_V02S0601 +arc: C5 V00B0100 +arc: D2 V01S0100 +arc: D5 H00R0100 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C107:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 S1_V02N0501 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 E1_H02W0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F3 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R27C108:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 H00R0100 +arc: B1 N1_V02S0101 +arc: B2 V02N0101 +arc: B3 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 F1 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 V00B0100 +arc: D0 H02E0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0100 F3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C109:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H01E0001 +arc: A5 V02S0101 +arc: A7 F5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C110:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C111:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F7 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C112:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0303 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1010001001010001 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R27C113:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C114:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0101 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 W1_H02E0001 +arc: D4 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C115:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: B0 H02E0101 +arc: B1 E1_H01W0100 +arc: B4 V02N0701 +arc: C0 S1_V02N0401 +arc: C1 V02N0401 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEC.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C116:PLC2 +arc: S1_V02S0501 H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R27C117:PLC2 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06S0203 + +.tile R27C12:PLC2 +arc: E1_H02E0701 E1_H01W0100 + +.tile R27C13:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0301 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C14:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 V00B0000 +arc: B2 H00L0000 +arc: B4 V02S0701 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C15:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02W0501 +arc: B0 V00B0000 +arc: B2 N1_V02S0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C16:PLC2 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A6 V02S0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010001110100000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1010110010101100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C17:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 H01E0001 +arc: A0 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C4 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V00B0100 +arc: D6 V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 W1_H02E0401 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1101100011011000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C18:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1000100011011000 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1000100011011000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C19:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 N1_V01S0100 + +.tile R27C20:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V02S0501 +arc: A4 H02E0501 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C21:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A6 N1_V01N0101 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C22:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A6 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C23:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C24:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q1 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000110110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C25:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C26:PLC2 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H01E0001 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: F0 F5A_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +word: SLICEA.K0.INIT 1010001110101100 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R27C27:PLC2 +arc: W1_H02W0201 S1_V02N0201 + +.tile R27C28:PLC2 +arc: W1_H02W0501 S1_V02N0501 + +.tile R27C29:PLC2 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R27C30:PLC2 +arc: E1_H02E0601 S1_V02N0601 + +.tile R27C31:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: A0 H00L0000 +arc: A7 H00L0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C32:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 H01E0001 +arc: A2 F7 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 F7 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 H01E0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: D0 N1_V02S0201 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 0001001100010000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEA.K1.INIT 0000000011001101 +word: SLICEC.K1.INIT 0000000010101011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C33:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 V02N0701 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0001000101010000 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C34:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02W0401 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A6 V02N0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C4 N1_V02S0001 +arc: C6 V00T0000 +arc: D4 V00B0000 +arc: D6 E1_H02W0001 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: A2 F7 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C36:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A5 N1_V02S0101 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B2 H02E0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F6 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C37:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A3 V02N0501 +arc: A7 V00T0100 +arc: B3 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V00T0100 F3 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C38:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 S1_V02N0601 + +.tile R27C39:PLC2 +arc: E1_H02E0001 V06N0003 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D0 S1_V02N0201 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: N1_V01N0101 F0 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEA.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C40:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEB.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICEA.K0.INIT 0000001100100010 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C42:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A2 S1_V02N0501 +arc: A3 V02N0701 +arc: A6 H02E0701 +arc: B0 V02N0301 +arc: B2 F3 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: C0 H02E0601 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: D0 H02W0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: V00B0000 F4 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEB.K0.INIT 0001000100110011 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C43:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 F7 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 F5 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +arc: V00B0100 F5 +arc: V00T0000 Q0 +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: A5 N1_V02S0301 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C7 H01E0001 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D2 V02S0001 +arc: D3 F0 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: S3_V06S0303 F5 +arc: V00B0000 F4 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 0000000001110010 +word: SLICEB.K0.INIT 0000001100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C45:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F6 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C46:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A1 N1_V02S0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A7 H02E0701 +arc: B4 V02N0501 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C1 H00R0100 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F5 +arc: V00B0100 Q7 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02S0501 +arc: A6 N1_V01N0101 +arc: B0 V02S0301 +arc: B6 V00T0000 +arc: C0 H02W0401 +arc: C3 H02E0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q7 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0201 Q0 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1000110010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A7 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C3 F6 +arc: C4 Q4 +arc: C6 H02E0601 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 F5 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B5 H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1010100000100000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101010000000100 +word: SLICEB.K1.INIT 1111111011001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 E1_H02W0701 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0100 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1101110111110101 +word: SLICED.K1.INIT 1010100000100000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C51:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 F7 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 W1_H02E0301 +arc: B3 E1_H01W0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C53:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A3 S1_V02N0501 +arc: A7 V02N0101 +arc: B0 F3 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02N0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C54:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02E0301 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0000 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R27C55:PLC2 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: B1 N1_V02S0101 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C56:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A6 H02E0701 +arc: B0 S1_V02N0301 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0000001100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R27C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 V02N0101 +arc: A6 V02S0301 +arc: B0 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B6 N1_V01S0000 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C4 H02E0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1010000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R27C58:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICEA.K0.INIT 1101100011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C59:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02S0501 +arc: A4 V00B0000 +arc: A7 H00R0000 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 V02S0501 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C60:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 S1_V02N0301 +arc: B0 V02N0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R27C61:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H01E0001 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 F1 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C62:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: B0 H02W0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011111110000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R27C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A7 H02E0701 +arc: B1 H02W0101 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 V02N0601 +arc: C4 H02E0401 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 N1_V02S0201 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0011010100111111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1101000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C64:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: C3 H02E0601 +arc: C5 V02S0001 +arc: D2 W1_H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 V02N0401 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C65:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H02E0501 +arc: A3 F7 +arc: A6 N1_V02S0301 +arc: A7 N1_V01N0101 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D3 H00R0000 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: N3_V06N0303 F6 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: C0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: M0 H02W0601 +arc: M5 H02W0001 +arc: MUXCLK2 CLK0 +word: SLICEA.K0.INIT 0101010100110000 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C67:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K0.INIT 1101100011011000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R27C68:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02W0501 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C4 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D4 V02S0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1000100010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C69:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 F7 +arc: B7 H02W0301 +arc: C1 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: M0 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R27C70:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02W0701 +arc: A7 E1_H01W0000 +arc: C2 H02W0401 +arc: C7 H02W0401 +arc: D2 N1_V01S0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICEB.K0.INIT 0000000001011111 +word: SLICED.K1.INIT 0000000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C71:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 V06N0303 +arc: A1 N1_V02S0501 +arc: A3 S1_V02N0701 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C72:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: B0 H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 F1 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: V01S0100 F1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C73:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0203 E3_H06W0103 + +.tile R27C74:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 N1_V02S0101 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 F3 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0601 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C75:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D2 N1_V02S0201 +arc: D3 H02W0001 +arc: D4 F2 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C76:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V01N0101 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H02E0301 +arc: B4 V02N0701 +arc: B6 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 W1_H02E0401 +arc: C4 H02E0601 +arc: C6 F4 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 S1_V02N0401 +arc: D6 H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0000 +arc: S1_V02S0201 F0 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C77:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 N3_V06S0003 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C7 N1_V02S0001 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F7 +arc: S1_V02S0301 F3 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C78:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A1 W1_H02E0501 +arc: A2 V02S0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 W1_H02E0301 +arc: B6 F3 +arc: B7 V02S0501 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 N1_V02S0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 N1_V02S0201 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02E0601 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C79:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 F7 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 H00R0100 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 F3 +arc: B6 F1 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 F0 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R27C80:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 W1_H02E0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B7 F3 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0701 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010010100000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C81:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: A1 E1_H02W0501 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0201 +arc: D7 H00R0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C82:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 W1_H02E0501 +arc: A2 H02W0501 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 F7 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B4 W1_H02E0301 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C85:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V01N0101 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 W1_H02E0301 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F7 +word: SLICED.K1.INIT 0000110000001100 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C86:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0301 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 F0 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D6 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C88:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000001110000 +word: SLICEB.K1.INIT 1111111101110000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEA.K1.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 H02W0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B6 N1_V01S0000 +arc: C1 H00L0100 +arc: C3 W1_H02E0401 +arc: C6 V00T0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D6 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICED.K0.INIT 1000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0501 +arc: A2 V01N0101 +arc: A3 V02S0701 +arc: A5 N1_V02S0301 +arc: A6 V00T0100 +arc: A7 F5 +arc: B0 W1_H02E0101 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C5 W1_H02E0601 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 E1_H02W0001 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0101 F4 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C91:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 W1_H02E0301 +arc: B1 H02E0301 +arc: B2 N1_V02S0101 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C1 W1_H02E0601 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 V02S0001 +arc: D1 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: B7 F3 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 V01N0101 +arc: C6 V02S0001 +arc: C7 F6 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: V00T0000 F0 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: B0 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: C0 H00L0100 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R27C94:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000010000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1011101100001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +arc: V00B0100 F7 +arc: V00T0000 F0 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R27C96:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 W1_H02E0701 +arc: A1 H01E0001 +arc: A2 V02S0501 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: V00T0000 F2 +word: SLICED.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R27C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D2 H02E0201 +arc: D4 F0 +arc: D5 N1_V02S0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F4 +arc: V00B0100 F7 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R27C98:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C2 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0601 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F1 +arc: N1_V01N0001 F3 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R27C99:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0301 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B2 W1_H02E0101 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: D0 V02S0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0100010001000100 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R28C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 V01S0000 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 E1_H02W0001 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0201 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A5 E1_H02W0701 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H00R0000 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 N1_V01S0100 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: D0 H02E0001 +arc: D2 V02S0001 +arc: D3 F2 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: V00T0100 F3 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R28C103:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R28C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F7 +arc: A2 H00L0100 +arc: A7 H00L0000 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0101 +arc: B7 H02W0101 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C7 S1_V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C105:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B3 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 N1_V01S0100 +arc: C3 H02W0401 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F0 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100001100000000 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R28C106:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C7 V00B0100 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C107:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 E1_H02W0301 +arc: B6 W1_H02E0101 +arc: B7 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1001100100000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C108:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 F1 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 V02S0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 F0 +arc: D4 N1_V02S0601 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0101 F3 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C109:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A1 F5 +arc: A2 N1_V02S0501 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B2 V01N0001 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C110:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02W0001 +arc: H00R0000 V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 V02N0501 +arc: A2 S1_V02N0501 +arc: A4 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B4 H00L0000 +arc: B6 F1 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C4 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 H02W0201 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V01S0100 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1101000000001101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010010100100001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C111:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A4 V02N0301 +arc: A6 N1_V01S0100 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B6 N1_V02S0701 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C112:PLC2 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 F7 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B3 N1_V02S0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C6 V02S0201 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 F0 +arc: D3 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1111000000110000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R28C113:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C114:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C115:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: B2 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R28C116:PLC2 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02S0501 +arc: B0 H02W0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: W1_H02W0301 V01N0101 + +.tile R28C118:PLC2 +arc: W1_H02W0401 V01N0001 + +.tile R28C13:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 S1_V02N0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: B0 H02W0301 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V01S0100 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: LSR1 V00B0100 +arc: M0 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C14:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C15:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A4 N1_V02S0101 +arc: A6 N1_V01S0100 +arc: A7 Q7 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010001110100000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C16:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S1_V02N0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 V06N0103 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B0 V02S0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: C0 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1000100010111000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C17:PLC2 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: A0 H00R0000 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100010111001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C18:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: B0 W1_H02E0101 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1000101110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C19:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: H00R0100 H02W0501 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H02E0301 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: V00T0000 Q0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1011100011001000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C20:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V01N0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 V02S0701 +arc: A2 V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C21:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 H02E0701 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V01N0001 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1110101001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1110101001100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B2 V02S0301 +arc: B4 V02N0501 +arc: B6 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: LSR0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110000001010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R28C23:PLC2 +arc: N1_V02N0201 H02E0201 +arc: V00T0100 H02E0301 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 Q5 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q1 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010111011000000 +word: SLICEA.K1.INIT 1111000011000000 +word: SLICEB.K0.INIT 1110101001001000 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K0.INIT 1110101001001000 +word: SLICEC.K1.INIT 1010101010001000 +word: SLICED.K0.INIT 1010111011000000 +word: SLICED.K1.INIT 1111000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C24:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: A4 V00T0100 +arc: B2 N1_V02S0301 +arc: C2 V02N0401 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 Q1 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C25:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: B0 V02N0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C26:PLC2 +arc: W1_H02W0501 V02N0501 + +.tile R28C27:PLC2 +arc: W1_H02W0201 V02N0201 + +.tile R28C29:PLC2 +arc: E1_H02E0001 V02S0001 +arc: V01S0100 S3_V06N0303 + +.tile R28C30:PLC2 +arc: H00L0000 E1_H02W0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: A3 F5 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B3 H01W0100 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C31:PLC2 +arc: E1_H02E0301 V02N0301 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V00B0000 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: D0 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000001000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C32:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: B2 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02S0601 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0201 F2 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C33:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0301 +arc: A7 N1_V01N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 F3 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F1 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICEB.K1.INIT 0001000101010000 +word: SLICEC.K1.INIT 0101000001010001 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C34:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H02E0701 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B1 H00R0100 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 F6 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEA.K0.INIT 0001010100000100 +word: SLICEA.K1.INIT 0000001000110010 +word: SLICED.K1.INIT 0101010100000001 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C35:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 F6 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 E1_H02W0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000000001110100 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0011001100000001 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C36:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 E1_H02W0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B4 H00L0000 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEA.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C37:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0000 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 F5 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0000000011110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C38:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A1 V02N0501 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: B1 H02W0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 F1 +arc: C1 W1_H02E0401 +arc: C3 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D1 W1_H02E0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F6 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R28C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06S0003 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 F6 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C40:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 V06S0003 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F0 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B0 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 0010001000100011 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V01N0101 +arc: A3 V01N0101 +arc: A4 F7 +arc: A5 H02W0701 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0100 F5 +word: SLICEB.K1.INIT 1110010000000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1110010000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICED.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C43:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 F5 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0000011100000100 +word: SLICED.K1.INIT 0000110000001101 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0100010001000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C44:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 S1_V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B3 H02E0101 +arc: B4 F1 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A1 V01N0101 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A5 N1_V02S0301 +arc: A6 E1_H01W0000 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 0010001000100011 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C46:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H00R0000 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010100000100000 +word: SLICED.K1.INIT 0001001100000010 +word: SLICEC.K0.INIT 0000010101000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C47:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B3 E1_H02W0301 +arc: C3 H00L0100 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R28C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C49:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 H01W0100 +arc: B4 H02E0101 +arc: B5 F1 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 F6 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 F0 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICED.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111001010100 +word: SLICEC.K0.INIT 1011101110001000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R28C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: B5 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C3 V02N0401 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D5 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICEA.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C52:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C53:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 N1_V02S0501 +arc: A3 F7 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 H02E0301 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1101100011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101000010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C54:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02E0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 H02E0501 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C1 N1_V01S0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M5 H02W0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 F7 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F6 +arc: V00B0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C55:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H00R0000 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A7 H02W0501 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C56:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B5 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C3 V02N0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R28C57:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02N0701 +arc: A5 V02S0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D5 H02E0201 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C58:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B3 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R28C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A6 H00L0000 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D6 V01N0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0010001011101110 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEA.K0.INIT 1011111110110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0501 +arc: A3 H00L0100 +arc: B3 V01N0001 +arc: C0 H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C61:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A6 S1_V02N0101 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 W1_H02E0301 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A7 H02W0701 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B7 H02W0301 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C7 H02W0601 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 0000111101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICED.K0.INIT 1000101010000000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C64:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F2 +arc: V00T0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C65:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A6 W1_H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 S1_V02N0401 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICED.K0.INIT 1110001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C66:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: V01S0100 Q5 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0301 +arc: A5 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: N1_V01N0001 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICEB.K1.INIT 0000000001110111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 S1_V02N0501 +arc: A5 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F5 +arc: V01S0000 F2 +arc: W3_H06W0203 Q4 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B5 E1_H02W0301 +arc: B7 V01S0000 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C5 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0010011100100010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R28C70:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A5 H02W0701 +arc: B0 H02W0101 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R28C71:PLC2 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 H01E0001 +arc: A6 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02N0301 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0201 Q0 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R28C72:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: B6 W1_H02E0101 +arc: C6 S1_V02N0201 +arc: D6 V01N0001 +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R28C73:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0203 S3_V06N0203 + +.tile R28C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E1_H01W0000 + +.tile R28C75:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V01N0001 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C76:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N3_V06S0103 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 V00B0000 +arc: A3 E1_H01E0001 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C4 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C77:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A4 V02S0301 +arc: B4 V02S0701 +arc: C4 V02S0001 +arc: D4 V00B0000 +arc: E1_H01E0001 F4 +arc: F4 F4_SLICE +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C78:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 H00L0000 +arc: B0 S1_V02N0301 +arc: B1 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C79:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 V01N0001 +arc: A0 H00L0000 +arc: A2 F7 +arc: A6 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0101 +arc: B2 H00R0000 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 H02W0401 +arc: C6 V02N0201 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D6 H00L0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C80:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0501 +arc: A2 H01E0001 +arc: A5 E1_H02W0501 +arc: A6 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 V01N0001 +arc: B5 F1 +arc: B6 S1_V02N0701 +arc: C1 E1_H02W0401 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0101 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: S1_V02S0701 F5 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C81:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02W0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: A6 W1_H02E0701 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 H02E0001 +arc: D4 V01N0001 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F7 +arc: V00T0000 F2 +arc: V00T0100 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 0011000000110000 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00R0000 +arc: A5 V02S0101 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D5 V00B0000 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C83:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A6 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0103 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 V02S0701 +arc: B5 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 H00L0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R28C85:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 0010001000100010 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: A0 H00R0000 +arc: A2 H02W0701 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 F5 +arc: B1 H02W0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 V00T0000 +arc: B0 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C6 V02N0201 +arc: D0 S1_V02N0201 +arc: D2 N1_V02S0201 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F6 +arc: N3_V06N0303 F6 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R28C88:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICEC.K0.INIT 0000000001001100 +word: SLICEC.K1.INIT 1111111101001100 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0101010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R28C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 V06N0303 +arc: A0 H00L0000 +arc: A5 V02S0301 +arc: B0 H00R0100 +arc: C0 N1_V01N0001 +arc: D0 V00T0100 +arc: D5 H00L0100 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R28C91:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0003 V06N0003 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0301 +arc: B3 H02W0301 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 V02S0201 +arc: D1 S1_V02N0001 +arc: D2 F0 +arc: D3 V02S0001 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R28C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: N1_V02N0601 F4 +arc: V01S0000 F3 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R28C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F7 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0000 +arc: B3 F1 +arc: B4 W1_H02E0301 +arc: B5 H01E0101 +arc: B6 E1_H02W0101 +arc: B7 H01E0101 +arc: C0 F4 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 E1_H02W0601 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R28C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V02S0701 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: B1 H02E0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 N1_V02S0701 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: N1_V01N0101 F3 +arc: N3_V06N0303 F5 +arc: V00T0000 F2 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C95:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F3 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R28C96:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 F5 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 H02W0101 +arc: B2 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: C7 V02S0001 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R28C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C2 E1_H02W0601 +arc: C4 N1_V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 F4 +arc: D0 V02S0001 +arc: D2 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0010001000100010 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R28C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 F1 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F4 +arc: V01S0000 F0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R28C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H00R0100 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R29C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B0 H00R0100 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 F0 +arc: D5 H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0101000001010000 +word: SLICEA.K1.INIT 0100010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A2 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B6 V02S0501 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1011000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H01E0101 +arc: C0 E1_H02W0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C5 V00T0100 +arc: C7 F6 +arc: D0 V00B0100 +arc: D1 F2 +arc: D2 V02N0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C103:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B1 W1_H02E0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C104:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A3 W1_H02E0701 +arc: A5 H02E0701 +arc: A7 W1_H02E0701 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B5 H02W0101 +arc: B7 N1_V02S0701 +arc: C1 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0100 +arc: C7 V00T0000 +arc: D1 N1_V02S0201 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C105:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 N1_V02S0501 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C106:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: S3_V06S0003 F3 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C107:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 W1_H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C109:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 0000000100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 + +.tile R29C110:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 N1_V02S0101 +arc: B2 F3 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H02W0401 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: S3_V06S0003 Q0 +arc: V01S0100 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C111:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A3 N1_V02S0701 +arc: A4 F5 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 F3 +arc: B7 H02E0301 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 Q0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0701 +arc: A6 N1_V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 F5 +arc: V01S0000 Q4 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1000010010100101 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C113:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02S0401 +arc: C3 V02S0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0001 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C114:PLC2 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000000110000 +word: SLICED.K0.INIT 1100100000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C115:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06S0103 +arc: B5 V02N0501 +arc: C5 V02N0001 +arc: D5 E1_H02W0201 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1100110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C116:PLC2 +arc: N1_V02N0201 H02E0201 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 + +.tile R29C117:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: B0 V00T0000 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C118:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 + +.tile R29C13:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0303 V06N0303 + +.tile R29C14:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: B0 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 H02E0101 +arc: C0 V02S0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C15:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 H01E0101 +arc: A2 V00T0000 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B6 V02S0501 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110001011010 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C16:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 F3 +arc: B3 E1_H01W0100 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEB.K1.INIT 1010101000111100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C17:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100000011001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C18:PLC2 +arc: H00L0000 H02W0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 W1_H02E0501 +arc: B0 H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100010111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C19:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 V01N0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C20:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V01N0101 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0001 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00T0100 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 Q7 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1110110001100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011111010 +word: SLICEB.K1.INIT 1100110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C21:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02E0401 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A2 V00T0000 +arc: A3 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 Q7 +arc: E3_H06E0203 Q7 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1100110011111010 +word: SLICEB.K1.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100111111001010 +word: SLICEC.K1.INIT 1100000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C22:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0103 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q6 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111111000110010 +word: SLICEA.K1.INIT 1100111000000010 +word: SLICEB.K0.INIT 1011101110111000 +word: SLICEB.K1.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C23:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 H02E0501 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0001 +arc: D3 H01E0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 F1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R29C24:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 H02E0401 +arc: W1_H02W0401 N1_V01S0000 +arc: A2 V01N0101 +arc: A5 Q5 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D7 H01W0000 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: V00T0100 Q3 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C25:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A5 V00T0100 +arc: B0 V02N0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 E1_H02W0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02W0001 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C26:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H01E0001 +arc: B0 H01W0100 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D3 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 0101001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C27:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00T0000 +arc: C0 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D6 V02N0601 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R29C28:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0003 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C29:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 H02W0101 +arc: A0 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C32:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A7 W1_H02E0701 +arc: B1 V02N0101 +arc: B4 H02W0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 F1 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C33:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: B0 S1_V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 W1_H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: N1_V01N0001 F7 +arc: S1_V02S0501 F5 +arc: V00T0000 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1010000010001000 +word: SLICEC.K0.INIT 0001001100000010 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 F7 +arc: A2 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A6 N1_V01S0100 +arc: A7 H02W0501 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 F3 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010000001110 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K1.INIT 0000110000001101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C35:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A6 H02W0501 +arc: B0 V02N0301 +arc: B2 E1_H02W0301 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 F5 +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1101100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C36:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 F6 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F3 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B2 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 F2 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C38:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 0001010100010000 +word: SLICEC.K1.INIT 0000001100100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C39:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 N1_V02S0701 +arc: A4 V00T0000 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: D0 H02E0201 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100010010000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C3:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R29C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A5 V00B0000 +arc: A6 N1_V01N0101 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000110000001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C41:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V06S0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A5 V02N0301 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 F1 +arc: B6 V00T0000 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 F4 +arc: C6 V00B0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000010101011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 F1 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C43:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A3 V00B0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B3 H02E0301 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 H02E0101 +arc: C0 F6 +arc: C3 V02S0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0001 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C44:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 F1 +arc: B5 F3 +arc: B6 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEC.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0000000011110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C45:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 E1_H01W0000 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 H02W0301 +arc: B3 E1_H01W0100 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 F0 +arc: D7 F0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 1010100000100000 +word: SLICEC.K1.INIT 0000000001110100 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICED.K0.INIT 0010001000100011 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C46:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02E0601 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEA.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A3 H02E0501 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D5 N1_V02S0401 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B3 H02E0301 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: E1_H02E0401 Q6 +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C49:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: B1 V02S0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N3_V06N0203 F4 +arc: S1_V02S0401 F6 +arc: V00T0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1110000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C50:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A1 H00L0100 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 H02W0101 +arc: C0 S1_V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000110000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C51:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V01S0100 +arc: B1 H02E0301 +arc: B3 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 F6 +arc: C3 V02N0601 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D3 S1_V02N0201 +arc: D7 V02S0601 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1011100010111000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C52:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B0 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C53:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A2 E1_H01E0001 +arc: A5 E1_H02W0501 +arc: A6 F7 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C54:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F7 +arc: A4 F7 +arc: A5 F7 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B7 V01S0000 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 F4 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0111011101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R29C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V01N0101 +arc: A1 H02E0501 +arc: A3 S1_V02N0701 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B3 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D3 V01S0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K1.INIT 1010110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C56:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A5 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B7 V02N0501 +arc: C0 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F0 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEA.K0.INIT 0101010100111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R29C57:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V02N0701 +arc: A6 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C1 V02S0401 +arc: C3 E1_H01W0000 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D6 H02W0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 F3 +arc: V00B0100 Q5 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R29C58:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0701 +arc: B2 V02S0301 +arc: C2 S1_V02N0401 +arc: D2 H02W0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEB.K0.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 S1_V02N0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 V02N0601 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111110001011100 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 1101111110001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C60:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B5 F1 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 H02E0501 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C61:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 S1_V02N0501 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C3 H00L0000 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M2 N1_V01N0001 +arc: W1_H02W0201 F2 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R29C62:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: B0 V02N0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R29C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V02N0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: H01W0100 Q7 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0401 F6 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C64:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 F7 +arc: A5 F7 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: C0 V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C65:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02E0501 +arc: A5 S1_V02N0101 +arc: B1 W1_H02E0301 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: E1_H01E0101 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C66:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A3 V02S0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 W1_H02E0201 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1101111111010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C67:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B2 E1_H02W0301 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F7 +arc: V01S0100 F0 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEA.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 0001010110111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C68:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A5 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C5 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 W1_H02E0201 +arc: D4 H01W0000 +arc: D5 V02N0601 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q6 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +arc: V01S0100 Q6 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1010001010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C69:PLC2 +arc: E1_H02E0601 V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V02N0501 +arc: C1 E1_H01W0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C70:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: B3 E1_H02W0101 +arc: C2 N1_V02S0401 +arc: C3 V02N0401 +arc: D3 N1_V01S0000 +arc: F2 F5B_SLICE +arc: M2 H02E0601 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R29C71:PLC2 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 E1_H02W0301 +arc: C3 N1_V02S0401 +arc: C5 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F0 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R29C72:PLC2 +arc: E1_H02E0501 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 V02N0501 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B7 V02N0701 +arc: C1 S1_V02N0401 +arc: C2 F4 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 F7 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F5 +arc: V01S0100 Q7 +arc: W1_H02W0501 F5 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R29C73:PLC2 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 + +.tile R29C74:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C75:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: C0 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F5 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C76:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V00B0100 +arc: C0 E1_H02W0401 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D5 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R29C77:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 S1_V02N0501 +arc: A1 V02N0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: A0 F7 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 E1_H02W0501 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: D0 S1_V02N0001 +arc: D1 N1_V02S0001 +arc: D2 H00R0000 +arc: D3 F0 +arc: D5 N1_V02S0601 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F3 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0100110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C79:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 W1_H02E0501 +arc: B0 V02N0301 +arc: C0 W1_H02E0401 +arc: D0 H02W0001 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C80:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00L0100 +arc: A1 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B5 F1 +arc: B6 H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C6 H02W0601 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A7 V00T0100 +arc: B7 W1_H02E0101 +arc: C7 V00T0000 +arc: D7 V02S0601 +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R29C82:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: A5 V02S0101 +arc: B0 V02S0301 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C83:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A3 V00T0000 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R29C84:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 1000001011000011 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 V06N0303 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0100 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C87:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 F5 +arc: A3 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 F6 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R29C88:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B0 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1111010100000000 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEB.K0.INIT 0011010111111111 +word: SLICEB.K1.INIT 0011010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: B0 H00R0100 +arc: B2 H02W0301 +arc: C0 S1_V02N0601 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R29C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B1 V00T0000 +arc: B3 H02W0301 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 W1_H02E0401 +arc: D0 E1_H02W0201 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0101001101010011 +word: SLICED.K0.INIT 0101010111111111 +word: SLICED.K1.INIT 0000111101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R29C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100110011 +word: SLICED.K0.INIT 1000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: B4 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0101010100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R29C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A2 H02W0501 +arc: B0 V00B0000 +arc: B2 H00R0100 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C6 H02E0401 +arc: D0 E1_H02W0001 +arc: D2 V02S0201 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 H01E0001 +arc: A1 H00R0000 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A7 H02W0701 +arc: B1 W1_H02E0301 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 F1 +arc: B7 V00B0100 +arc: C1 H02W0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C7 V02S0201 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0303 F5 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R29C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V00B0100 F5 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 H02E0401 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 H01E0101 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D5 E1_H01W0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C97:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B4 H02E0101 +arc: B6 N1_V02S0701 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C98:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B2 N1_V02S0301 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 F4 +arc: D0 V02S0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F7 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R29C99:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A2 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 W1_H02E0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 H02W0401 +arc: C2 H00L0000 +arc: C4 F6 +arc: C5 W1_H02E0401 +arc: C6 N1_V02S0201 +arc: C7 V01N0101 +arc: D0 W1_H02E0201 +arc: D2 H02E0201 +arc: D4 F0 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 F1 +arc: B1 V02N0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000100000100010 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C101:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H01E0001 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 V01N0001 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06N0303 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: B0 F1 +arc: B1 H00R0100 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 N1_V02S0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: D0 H02E0201 +arc: D1 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: W3_H06W0003 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A2 V02S0501 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C104:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A7 N1_V02S0301 +arc: B0 F3 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B5 N1_V02S0701 +arc: B7 F1 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C105:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 E1_H02W0401 +arc: C7 V02S0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 F2 +arc: D6 H02E0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S3_V06S0203 F4 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C106:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B6 F1 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000001000000 +word: SLICEC.K0.INIT 0010001100000011 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C107:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 H01E0001 +arc: N1_V01N0101 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 S1_V02N0701 +arc: A3 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A6 H02E0701 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 H00L0000 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02S0401 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0011001000010000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1010100000100000 +word: SLICED.K0.INIT 0000000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C109:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H02E0701 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0401 +arc: C7 H01E0001 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V00B0000 F6 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEA.K1.INIT 1010101100000000 +word: SLICEB.K1.INIT 1010000010001000 +word: SLICED.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C110:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02W0001 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C111:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06W0303 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 F5 +arc: A2 H00L0100 +arc: A5 V02S0301 +arc: A6 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 H00L0000 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 V00T0100 +arc: D5 H02W0001 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F0 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C112:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H01E0001 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 N1_V02S0501 +arc: C2 F4 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0101000001011111 +word: SLICED.K0.INIT 0000010100000011 +word: SLICED.K1.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C113:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F5 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEB.K0.INIT 1011100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C114:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C115:PLC2 +arc: H00L0000 H02W0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H01E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F7 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICED.K0.INIT 1111001100000000 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C116:PLC2 +arc: N1_V02N0601 W3_H06E0303 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06E0103 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R30C118:PLC2 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0303 E1_H01W0100 + +.tile R30C119:PLC2 +arc: H01W0100 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C120:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R30C13:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0203 S1_V02N0401 + +.tile R30C14:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: B0 V02S0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C15:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1100010111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010000000100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C16:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 H02W0301 +arc: B4 V02S0501 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000101110001000 +word: SLICEB.K0.INIT 1010111000000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C17:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00R0000 +arc: A2 E1_H01E0001 +arc: B0 H01W0100 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: C0 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C18:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 V01N0101 +arc: W3_H06W0103 E1_H01W0100 + +.tile R30C19:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: F0 F5A_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEA.K1.INIT 1010101011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C20:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0000 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100000011100010 +word: SLICEA.K1.INIT 1100110011111010 +word: SLICEB.K0.INIT 1010101011111100 +word: SLICEB.K1.INIT 1010000010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C21:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 S1_V02N0501 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C22:PLC2 +arc: E1_H02E0201 V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C23:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0501 V06S0303 +arc: A0 V02N0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B1 V02S0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C24:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0701 F5 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1011100010111000 +word: SLICEC.K1.INIT 0000000000110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C25:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 V00B0000 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C26:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06N0203 +arc: A0 V02N0701 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S3_V06S0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C27:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C28:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 W1_H02E0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C29:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06N0103 +arc: N1_V02N0101 H02E0101 +arc: V00T0100 S1_V02N0501 +arc: B0 H01W0100 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C30:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W3_H06E0303 +arc: A0 H02E0701 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C31:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0103 +arc: A3 H02E0701 +arc: B0 E1_H01W0100 +arc: B2 F3 +arc: B3 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0601 V02N0601 +arc: A4 S1_V02N0301 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +word: SLICEC.K1.INIT 0001001100000010 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0011000000110001 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C33:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 F7 +arc: A4 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 H02E0101 +arc: B2 H02W0101 +arc: B4 H02W0101 +arc: B5 F1 +arc: B6 V01S0000 +arc: B7 S1_V02N0501 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 F6 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02S0201 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1100010010000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 F7 +arc: A7 H00R0000 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 N1_V02S0201 +arc: C6 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C35:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 H02E0301 +arc: B5 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C36:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile R30C37:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C38:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 F4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICEB.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C39:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F5 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K0.INIT 0001001100010000 +word: SLICEA.K1.INIT 0001001100010000 +word: SLICEB.K0.INIT 0000011100000100 +word: SLICEC.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C40:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H01E0001 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C41:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 N1_V02S0101 +arc: B1 H02E0101 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 F4 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010001010000000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000010100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R30C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C4 H02W0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C43:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 W1_H02E0501 +arc: A4 V00B0000 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B1 V02N0101 +arc: B4 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C1 H02E0601 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D4 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C44:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B3 H00L0000 +arc: B5 F3 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 E1_H02W0001 +arc: D2 W1_H02E0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F6 +arc: V01S0000 F5 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100001100000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R30C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 E1_H02W0001 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C46:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: A7 H00R0000 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q6 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 E1_H01W0100 +arc: B4 F1 +arc: B5 H01E0101 +arc: B6 V00B0100 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEA.K0.INIT 0000001100001010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C48:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: B0 F3 +arc: B1 H00R0100 +arc: B3 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F1 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICEA.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R30C49:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 N1_V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 S1_V02N0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C1 H00L0100 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F0 +arc: V00B0000 Q6 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F5 +arc: A3 H01E0001 +arc: A4 F5 +arc: A5 V02S0301 +arc: B3 W1_H02E0101 +arc: B4 W1_H02E0101 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: M0 H02E0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: V00B0100 Q5 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 N1_V01S0100 +arc: B1 H02E0301 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: C1 H00L0000 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02S0401 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R30C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C53:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 F5 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0701 +arc: C1 H00R0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q5 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1110010011111111 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 N1_V01N0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0501 F5 +arc: V01S0000 F5 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 0010011101110111 +word: SLICEC.K1.INIT 0000000001011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R30C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V00T0000 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: C0 F6 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 F2 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C56:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A1 H02E0501 +arc: A3 V02N0701 +arc: A6 V02N0101 +arc: B0 F1 +arc: B1 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: M2 W1_H02E0601 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010001010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R30C57:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 E3_H06W0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 V00T0000 +arc: N1_V02N0001 F0 +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C58:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A4 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D3 H02W0201 +arc: D4 N1_V02S0401 +arc: D6 V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 F1 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1101100011110000 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C59:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A3 V02N0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B5 F1 +arc: B6 F1 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C60:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02W0701 +arc: A4 V02N0101 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B4 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D4 V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M1 H00L0000 +arc: M3 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q3 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C61:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 E1_H02W0701 +arc: A5 H02W0501 +arc: B1 H02W0101 +arc: B3 S1_V02N0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 N1_V01S0100 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 Q3 +arc: V01S0100 F0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R30C62:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B5 V02S0501 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 N1_V01N0001 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0100 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000001011111 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C63:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 H01E0001 +arc: A5 S1_V02N0101 +arc: B1 H02W0101 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 F4 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0101010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: B0 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C3 N1_V02S0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R30C65:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V01N0001 +arc: H00L0000 V02N0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: C1 S1_V02N0401 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R30C66:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A5 H02E0701 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 H00R0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C5 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 Q3 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 V02S0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0001101100001010 +word: SLICEB.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 1011111110001111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C68:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A3 H02W0501 +arc: A5 V02N0101 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: C1 V02N0401 +arc: C3 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 F0 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C69:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: B2 H02W0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V00T0100 +arc: D2 W1_H02E0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0001 F2 +arc: N1_V02N0201 F2 +arc: N3_V06N0003 F3 +word: SLICEB.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 + +.tile R30C71:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 H02W0501 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C3 S1_V02N0601 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C72:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B7 E1_H02W0101 +arc: C2 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C7 H02W0601 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000101000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C73:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: A2 F7 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B7 S1_V02N0701 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C7 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1001110010010011 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 + +.tile R30C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S1_V02N0201 + +.tile R30C76:PLC2 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 E1_H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C77:PLC2 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A2 V00B0000 +arc: B2 V01N0001 +arc: C0 V02N0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000100000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H02W0701 +arc: A4 V02S0301 +arc: B1 V02S0101 +arc: B4 H02W0101 +arc: C1 E1_H02W0401 +arc: C4 H02W0401 +arc: D1 V00B0100 +arc: D4 H02W0201 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C79:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 N1_V01S0100 +arc: A4 F7 +arc: A7 H02W0701 +arc: B4 N1_V01S0000 +arc: B7 V01S0000 +arc: C4 S1_V02N0201 +arc: C7 H02E0401 +arc: D4 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C80:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02N0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B4 H02W0301 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C4 V02N0201 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C82:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: B0 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0401 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q4 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C86:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0501 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 H02W0301 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0201 +arc: C5 W1_H02E0601 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010110010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C87:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0701 +arc: A3 S1_V02N0501 +arc: A6 H00L0000 +arc: B0 V02N0301 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D3 H02W0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEA.K0.INIT 1101100001010000 +word: SLICEB.K1.INIT 1010111100000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C88:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 H02E0701 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C89:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C3 N1_V02S0401 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0001 +arc: D5 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0701 F5 +arc: V01S0000 F3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C90:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V06N0203 +arc: A0 N1_V02S0501 +arc: A1 V02S0501 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0301 +arc: A7 H02W0501 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 N1_V02S0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 N1_V02S0601 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: S3_V06S0203 F7 +word: SLICEC.K1.INIT 1101000001010000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICED.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R30C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B5 H00L0000 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: M4 V00T0100 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 0001010100000000 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000000001010 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R30C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0701 +arc: A1 F7 +arc: A3 H02E0701 +arc: A4 S1_V02N0301 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1000000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 V06S0203 +arc: A0 S1_V02N0701 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 H01E0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A6 V00T0100 +arc: B2 W1_H02E0101 +arc: B6 H02W0301 +arc: C2 H00L0100 +arc: C6 V01N0101 +arc: D2 H02W0001 +arc: D6 E1_H01W0100 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R30C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C3 F6 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 F0 +arc: D5 V00B0000 +arc: D6 N1_V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R30C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 V00T0100 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C0 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 V00T0000 +arc: D0 H02W0001 +arc: D1 F0 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1001100100000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R30C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V01N0101 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 F0 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +arc: S1_V02S0501 F7 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R30C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00R0000 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 H01E0001 +arc: D0 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: M2 W1_H02E0601 +arc: M4 V00B0100 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEC.K0.INIT 1100001101000001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R30C99:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 N1_V02S0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 W1_H02E0701 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 H00R0100 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: N1_V01N0101 F7 +arc: N1_V02N0101 F3 +arc: S3_V06S0003 F0 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 0100010001000100 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C100:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 F3 +arc: B6 F1 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0201 +arc: D0 V02S0001 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 F0 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C101:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: W1_H02W0101 F1 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 V02S0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 F0 +arc: D6 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V02N0601 F4 +arc: V00T0100 F3 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C103:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02W0201 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H00L0000 +arc: A5 H02W0701 +arc: B1 V00T0000 +arc: B5 V00B0100 +arc: C1 N1_V02S0401 +arc: C5 V00T0100 +arc: D1 N1_V02S0201 +arc: D5 E1_H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: V01S0000 F1 +arc: V01S0100 F5 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0401 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: D0 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 N1_V02S0401 +arc: D5 H00L0100 +arc: D6 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C105:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: A2 E1_H02W0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 H02W0101 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C106:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 F5 +arc: A3 V00T0000 +arc: A5 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 H00L0000 +arc: B7 H02E0101 +arc: C0 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: C7 V00T0100 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 V02S0001 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C107:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 V02S0301 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F7 +arc: S1_V02S0301 F3 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0011001000000010 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 1010100000001000 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R31C108:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H02W0501 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q2 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C109:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 H02E0201 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: A1 H02E0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C4 V02N0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C110:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: C0 N1_V02S0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 F4 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100100000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C111:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H01E0001 +arc: A5 V02S0301 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D5 H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 F3 +arc: S3_V06S0103 F2 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100000011110000 +word: SLICEC.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICED.K1.INIT 0101010100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R31C112:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 H02W0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q6 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R31C113:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02N0701 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEA.K0.INIT 1010000010110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C114:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H02W0201 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C115:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 V06S0303 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V00B0000 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B7 H02E0301 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V02S0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V01S0100 F2 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICEB.K1.INIT 1010100000100000 +word: SLICEB.K0.INIT 1111000000010000 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICED.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R31C116:PLC2 +arc: N1_V02N0001 H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 + +.tile R31C117:PLC2 +arc: H01W0000 W3_H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C118:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R31C119:PLC2 +arc: W3_H06W0003 E1_H01W0000 + +.tile R31C120:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R31C13:PLC2 +arc: E3_H06E0103 V01N0101 + +.tile R31C14:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0201 +arc: A4 V00T0000 +arc: B2 V01N0001 +arc: B4 V02N0501 +arc: B7 V00B0000 +arc: C4 V02N0001 +arc: C7 V01N0101 +arc: D2 V02N0201 +arc: D4 F2 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +word: SLICEC.K0.INIT 0101111100010011 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEB.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R31C15:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 H02W0401 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0100 V02N0501 +arc: A1 H00R0000 +arc: A3 H01E0001 +arc: A5 H02E0501 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B5 H01E0101 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C5 V01N0101 +arc: D1 V00T0100 +arc: D5 V01N0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 0000111100001000 +word: SLICEB.K1.INIT 0001010100010101 +word: SLICEC.K1.INIT 0000000100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C16:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 N1_V01S0000 +arc: A2 V01N0101 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 F4 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEA.K0.INIT 0011000000000000 +word: SLICED.K0.INIT 1100000011000000 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 0111011100000111 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R31C17:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V02N0401 +arc: A0 H02E0701 +arc: A2 V00T0000 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 W1_H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F7 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0111000001110111 +word: SLICED.K0.INIT 0000000000000010 +word: SLICEA.K0.INIT 0101000111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C18:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 0011111100010101 +word: SLICEB.K0.INIT 0100110011000100 +word: SLICED.K1.INIT 0011111100010101 +word: SLICED.K0.INIT 0011000111110101 +word: SLICEC.K0.INIT 0011000111110101 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0000000000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C19:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0601 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R31C20:PLC2 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A5 V00T0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0101 +arc: B5 V01S0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D5 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C21:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0701 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: E1_H01E0001 F6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R31C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q3 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R31C23:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 V02N0501 +arc: A3 F7 +arc: A5 V02N0301 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B4 H02E0301 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000000100110001 +word: SLICEB.K1.INIT 1111000010100000 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R31C24:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F4 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C25:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C26:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: B2 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C27:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: B0 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C28:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: V00T0000 V02S0601 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C30:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 H02E0101 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C31:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B2 F3 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 W1_H02E0201 +arc: D3 V02S0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C32:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: S3_V06S0203 F7 +arc: V00T0100 F3 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C33:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A1 H00L0100 +arc: A3 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A7 W1_H02E0501 +arc: B0 E1_H01W0100 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000010101000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 H02W0501 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D2 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +word: SLICED.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEA.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C35:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 H01E0001 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: B1 H02E0301 +arc: B3 H02E0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 H00L0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 F3 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 V02S0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C37:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 N1_V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: B1 V00B0000 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: C1 H02E0601 +arc: C4 V02N0001 +arc: C5 F6 +arc: D1 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1000100010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C39:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A3 W1_H02E0501 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 H02E0501 +arc: B0 N1_V02S0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V01S0000 +arc: B6 F3 +arc: B7 H02E0101 +arc: C0 V02S0601 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 H01E0001 +arc: C7 S1_V02N0001 +arc: D0 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 V01S0100 +arc: D4 F0 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101000001011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C40:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B6 F1 +arc: B7 V02N0501 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D6 F2 +arc: D7 V02S0401 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S3_V06S0203 F4 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICED.K1.INIT 0000011100000100 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0101000001010001 +word: SLICEC.K0.INIT 0011000000110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 N1_V02S0501 +arc: A2 V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V02S0301 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: B0 F3 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: D3 N1_V02S0001 +arc: D4 F2 +arc: D6 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: V01S0100 F4 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010010000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1110010011100100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 + +.tile R31C42:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B6 F3 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C43:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C44:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 V02S0501 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00B0100 +arc: D0 S1_V02N0001 +arc: D1 H01E0101 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F7 +arc: V01S0000 F5 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C45:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0701 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B1 E1_H02W0101 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C1 N1_V01S0100 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H01W0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0101 F4 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C46:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F7 +arc: N3_V06N0103 F1 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1001000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C47:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 F1 +arc: B4 N1_V02S0501 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0001 F2 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C7 V00T0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 F0 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 F5 +arc: A1 H02E0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00B0000 F4 +arc: V00T0100 F1 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C50:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V00T0000 +arc: B0 V00T0000 +arc: C0 E1_H01W0000 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R31C52:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0100 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: B0 V01N0001 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: C0 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C53:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: B0 V02N0101 +arc: B4 H02W0101 +arc: C0 E1_H01W0000 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: V00B0100 Q5 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010100000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 V01N0001 +arc: A1 W1_H02E0501 +arc: A2 V01N0101 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 N1_V01N0101 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1001100100001001 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1101111111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A4 H02W0701 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C56:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 N1_V02S0501 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 Q5 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEA.K1.INIT 1100101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011100011111111 +word: SLICEA.K1.INIT 1101000010000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C58:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111011111010101 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R31C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 H01W0100 +arc: B2 H02E0101 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0001000010111010 +word: SLICEB.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C60:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: C0 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 1011111110110011 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R31C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B2 H02W0101 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D2 W1_H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 V01N0101 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N3_V06N0103 F2 +arc: V01S0100 Q7 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000111100100010 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B4 S1_V02N0501 +arc: B6 V02S0701 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C64:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: B0 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: D0 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1110000000100000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C65:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 N1_V01S0000 +arc: A5 S1_V02N0301 +arc: A7 H02W0501 +arc: B0 E1_H02W0301 +arc: B3 V02S0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D7 V01N0001 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 F2 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C66:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0501 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 W1_H02E0101 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: S1_V02S0201 F2 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R31C67:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 H02W0701 +arc: A5 W1_H02E0701 +arc: A6 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 W1_H02E0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001000101010101 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R31C68:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A3 V02S0501 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B5 H02W0301 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C69:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A5 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B3 V02N0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 N1_V02S0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C70:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 H02E0001 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F4 +arc: V00T0000 F0 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0101010100001100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R31C71:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06N0303 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: B0 H02W0301 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 0011000001010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101010000010000 +word: SLICEB.K0.INIT 0010001000001010 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R31C72:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V00B0100 F5 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000001000001 +word: SLICED.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0101000000110000 +word: SLICEA.K1.INIT 0000001000000001 +word: SLICED.K1.INIT 0101000001000100 +word: SLICEC.K1.INIT 0000101000100010 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R31C73:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A2 S1_V02N0701 +arc: A3 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D6 F0 +arc: D7 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010010111000011 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1101100000100111 +word: SLICEA.K1.INIT 1101100000100111 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C74:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H02W0301 + +.tile R31C75:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 + +.tile R31C76:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: A2 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: C0 H02W0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H00R0000 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C77:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B6 V00B0100 +arc: C0 H00R0100 +arc: C6 V02S0201 +arc: D0 N1_V02S0201 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0111000011110000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C78:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A6 V02N0301 +arc: B0 V02N0101 +arc: C0 F6 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02S0601 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C79:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 N1_V01S0100 +arc: A3 E1_H02W0501 +arc: B3 V02N0301 +arc: C3 H00L0000 +arc: D3 H02W0201 +arc: F3 F3_SLICE +arc: N1_V01N0001 F3 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R31C80:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A5 V00T0100 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 Q5 +arc: V01S0100 F6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +word: SLICEC.K0.INIT 1101100001010000 +word: SLICEC.K1.INIT 1110010001000100 +word: SLICED.K0.INIT 1111010100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010110010101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C82:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 V06N0303 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A6 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B5 V02S0501 +arc: C0 S1_V02N0401 +arc: C2 H02W0601 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICED.K0.INIT 1111000001010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +word: SLICEB.K0.INIT 1100110000001100 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C84:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 S1_V02N0101 +arc: A5 N1_V01S0100 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B2 H02W0301 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F5 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V02S0501 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C86:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 W1_H02E0301 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 E1_H02W0401 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0201 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1101110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C87:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 E1_H02W0101 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1110010011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C88:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A6 F7 +arc: A7 V02S0301 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B4 H02E0101 +arc: B6 F1 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C4 V02N0001 +arc: C6 F4 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D6 F2 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C89:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02E0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 V00B0000 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C3 H02W0401 +arc: C5 F6 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 F7 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 F3 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0601 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 W1_H02E0701 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B3 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111001111 +word: SLICED.K1.INIT 1000000011110000 +word: SLICED.K0.INIT 0000000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R31C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00L0000 +arc: A5 N1_V02S0301 +arc: B5 H00R0000 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C5 V00T0100 +arc: D0 H02E0201 +arc: D1 N1_V02S0201 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R31C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A3 W1_H02E0501 +arc: A6 H00R0000 +arc: B1 H02W0301 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C6 V00T0100 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: N1_V02N0601 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R31C94:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 V06N0203 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 F1 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 F4 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N3_V06N0203 F7 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1101000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 V02S0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 F3 +arc: B3 N1_V02S0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: D0 V00T0100 +arc: D1 N1_V02S0001 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R31C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 W1_H02E0501 +arc: A2 V02S0501 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A5 F7 +arc: A7 H02W0701 +arc: B0 H02E0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 N1_V01S0000 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H01W0000 +arc: E1_H02E0001 F0 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0401 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S1_V02S0601 F4 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1101110100001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R31C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A2 H02W0501 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 W1_H02E0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B2 W1_H02E0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 N1_V02S0501 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +arc: V00T0000 F2 +arc: V01S0000 F7 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: B0 F3 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C102:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 W1_H02E0201 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: A5 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 S1_V02N0501 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C5 N1_V02S0001 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D5 H00L0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0100 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1000100001000100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C104:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 S1_V02N0501 +arc: A1 F7 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B1 F3 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V02N0401 F4 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R32C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 H02E0701 +arc: A5 V02S0101 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 H00L0000 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 H02E0601 +arc: D0 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C106:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C4 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D4 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R32C107:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 H02W0301 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A2 W1_H02E0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 F6 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: D0 V00B0100 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V02N0201 F0 +arc: S1_V02S0001 F2 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C108:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 F7 +arc: A4 H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: H00L0100 H02E0101 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0203 F4 +arc: V01S0000 F6 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 1010101000000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C110:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V01N0101 +arc: A3 H02W0701 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 H00R0000 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V02S0701 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C111:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02E0201 +arc: D4 N1_V02S0401 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F7 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000111101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 E1_H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: A1 E1_H02W0501 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000111100110011 +word: SLICED.K1.INIT 0011001000010000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011000000111111 +word: SLICED.K0.INIT 0000000100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C113:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V06S0303 +arc: A1 N1_V02S0701 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 N1_V01S0100 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICED.K0.INIT 0000000000001010 +word: SLICEB.K1.INIT 1000100010001100 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 1010000010100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C114:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 F5 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0000000011100010 +word: SLICEB.K0.INIT 1111000100000000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 0000010100000011 +word: SLICEA.K0.INIT 0000001100000000 +word: SLICEA.K1.INIT 1100010011000000 +word: SLICEB.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C115:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01S0100 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 0000000000110000 +word: SLICEC.K1.INIT 1000110010001000 +word: SLICEB.K0.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C116:PLC2 +arc: N3_V06N0003 W3_H06E0003 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 V06N0203 + +.tile R32C117:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 + +.tile R32C118:PLC2 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 + +.tile R32C13:PLC2 +arc: S1_V02S0201 H06W0103 +arc: B5 H02W0301 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 0011001100000011 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R32C14:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 E1_H02W0201 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 F7 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 0000010100000000 +word: SLICEC.K1.INIT 0000010100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 0101011100100000 +word: SLICEA.K1.INIT 0000001111001100 +word: SLICEB.K0.INIT 0101011100100000 +word: SLICEB.K1.INIT 0100011001001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C15:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: M2 V00T0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F1 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 0000000011101100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 0000000000010000 +word: SLICEA.K0.INIT 0100010100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0000011100000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000100110011 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C16:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 W1_H02E0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 F3 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H01E0101 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010000011101100 +word: SLICEB.K1.INIT 0000000001110000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICEB.K0.INIT 1111111110100000 +word: SLICED.K0.INIT 1111100011111010 +word: SLICED.K1.INIT 0000100000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C17:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: A1 H02E0501 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H00R0100 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0601 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 F5 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F4 +arc: V00B0100 Q5 +arc: V01S0000 Q7 +arc: V01S0100 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111111111001100 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 0000110010101100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111110100000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R32C18:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 V06N0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0101 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +arc: S1_V02S0101 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0011101000001010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 0111010000110000 +word: SLICEC.K0.INIT 1111101011111010 +word: SLICEC.K1.INIT 0101110000001100 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 0000110010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A1 H02E0701 +arc: B1 V02N0101 +arc: C1 V02N0401 +arc: D1 V02N0001 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C20:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A3 V02S0701 +arc: B1 Q1 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D3 V02N0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0101101000001010 +word: SLICEA.K1.INIT 1010110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C21:PLC2 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C5 V00T0100 +arc: C6 H01E0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000000001000111 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000011101111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R32C22:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 N1_V02S0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: S3_V06S0003 Q3 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R32C23:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 V00B0000 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B7 F1 +arc: C0 F4 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000100110001 +word: SLICEB.K1.INIT 1111000011000000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K1.INIT 0000000000100111 +word: SLICED.K1.INIT 1111000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C24:PLC2 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: B1 H02E0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 W1_H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 F3 +arc: V01S0000 F5 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0100000001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C25:PLC2 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: A7 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1111110010101100 +word: SLICEB.K0.INIT 1011001110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C26:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 V01N0101 +arc: A2 F7 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C2 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0100011100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001000010110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C27:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 V02S0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C28:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D7 H02W0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000111000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C29:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R32C30:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: A5 Q5 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C31:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: B0 S1_V02N0301 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C32:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0301 V06N0003 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 F1 +arc: B7 F3 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 F0 +arc: D6 V02S0601 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0101000001010001 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEC.K0.INIT 0101000001010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C33:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B4 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D4 H02W0201 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000101011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 E1_H02W0701 +arc: A3 V02S0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0101110001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C35:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 H02E0501 +arc: A5 V02S0301 +arc: A7 F5 +arc: B0 V01N0001 +arc: B1 H02W0301 +arc: B2 N1_V02S0301 +arc: B3 H00L0000 +arc: B5 V00B0100 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V02S0201 +arc: D5 S1_V02N0401 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F2 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 F0 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 N1_V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICED.K1.INIT 0000000000101110 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C37:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H01E0001 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B0 V02N0101 +arc: B2 W1_H02E0301 +arc: B3 H01W0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 F3 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 V02S0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: V00B0100 F5 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010010100000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V02N0501 +arc: A2 W1_H02E0701 +arc: A5 S1_V02N0301 +arc: A6 N1_V01S0100 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 F1 +arc: B5 H00L0000 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C2 V02S0401 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02S0201 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0000010000001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C39:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A5 H02W0701 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 V02S0301 +arc: B5 V02N0701 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: D0 N1_V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D5 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F5 +arc: V00T0100 F3 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000001111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R32C40:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V01N0101 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0100 F2 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0000111100000001 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEC.K1.INIT 0000101000001011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C41:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 S1_V02N0501 +arc: A3 V02S0501 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 F4 +arc: C7 N1_V02S0001 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 H02E0201 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0101 F1 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICEA.K0.INIT 0001001100000010 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1011000010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C42:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000000001110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R32C43:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A3 H00L0100 +arc: A5 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B3 H02E0301 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 V02S0401 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: D0 V01S0100 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000011110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 F7 +arc: A2 V02S0501 +arc: A4 V00T0100 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 F1 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +arc: V00T0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 0001000101010000 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 F1 +arc: B5 H00R0000 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEB.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0011000011111100 +word: SLICEC.K0.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C47:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: B0 H02E0101 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M1 H00L0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010001010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C49:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02N0501 +arc: A5 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B5 V02N0501 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 H00R0000 +arc: D5 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C50:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B5 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02W0601 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C51:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F5 +arc: A5 H02E0701 +arc: B0 V02N0101 +arc: B1 N1_V02S0301 +arc: B5 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C52:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 V02N0501 +arc: A5 H02W0701 +arc: B1 V02N0101 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: C1 V02S0401 +arc: C3 H02E0401 +arc: C5 V00B0100 +arc: D1 H02W0201 +arc: D3 V02S0201 +arc: D5 V01N0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V02N0101 F1 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000011111110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C53:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: N1_V01N0101 F2 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C54:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 E1_H02W0501 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 F1 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C55:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q7 +arc: M0 H02E0601 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V02N0401 F4 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0011101000111010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1010000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C56:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02W0501 +arc: A4 N1_V01N0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B5 W1_H02E0301 +arc: B7 V02N0701 +arc: C3 H00L0100 +arc: C5 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0100 Q5 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C57:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 0100011101110111 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1011100011111111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0701 +arc: A5 E1_H02W0701 +arc: B2 V01N0001 +arc: B5 H02W0101 +arc: C2 H02E0601 +arc: C5 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D5 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C59:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B0 V01N0001 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0301 F1 +arc: S1_V02S0601 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1111011110110011 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C60:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06N0203 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0501 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 Q6 +arc: W1_H02W0601 F4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C61:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 N1_V01N0101 +arc: B0 V02N0301 +arc: B2 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F0 +arc: V00B0000 F6 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A3 F7 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B4 H00L0000 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: C0 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1010000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C63:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 H02W0301 +arc: C2 V02S0601 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C64:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C65:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: B0 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q4 +arc: W1_H02W0601 F6 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C66:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: A1 V02N0501 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 V00T0100 +arc: B0 V02S0301 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 Q5 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1110000000100000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C67:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B5 E1_H02W0101 +arc: B6 H01E0101 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R32C68:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A3 H02E0501 +arc: A5 S1_V02N0301 +arc: B3 H00R0100 +arc: B5 S1_V02N0501 +arc: C3 S1_V02N0401 +arc: C5 V02N0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H02E0701 +arc: A3 V00T0000 +arc: A7 N1_V01N0101 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: B5 H02E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C5 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICED.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C70:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: A0 H01E0001 +arc: A1 S1_V02N0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H00R0000 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 F4 +arc: M1 H00L0000 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 F7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000010100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R32C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 V02S0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V01S0100 Q6 +arc: W1_H02W0401 F4 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000000000100001 +word: SLICEC.K1.INIT 0011011011000110 +word: SLICED.K0.INIT 0100000000000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R32C72:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 V00B0100 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02W0601 +arc: N1_V01N0101 F0 +arc: V00T0100 F3 +arc: W1_H02W0501 F7 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000001000001 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 0011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R32C73:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 V02S0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D3 V02N0001 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 W1_H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0100 F3 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 1001110010010011 +word: SLICEA.K0.INIT 1010100101011001 +word: SLICED.K1.INIT 1011010010000111 +word: SLICEC.K1.INIT 1100101000110101 +word: SLICED.K0.INIT 1001101010010101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R32C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 H01E0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D4 H02W0001 +arc: D5 F2 +arc: D6 H02E0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1110001000011101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C75:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V01N0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A4 H02W0501 +arc: A7 H00R0000 +arc: B1 V02N0301 +arc: B2 H02W0301 +arc: B7 F1 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C7 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D4 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0100010000001100 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICED.K1.INIT 0011000100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R32C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 N1_V02S0701 +arc: A5 N1_V02S0101 +arc: B1 H02E0301 +arc: B5 S1_V02N0501 +arc: C1 N1_V01S0100 +arc: C5 V02S0201 +arc: D1 V00B0100 +arc: D5 H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C77:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H02W0501 +arc: A4 N1_V02S0101 +arc: B1 H02W0101 +arc: B4 N1_V02S0701 +arc: C1 H02E0401 +arc: C4 V02N0001 +arc: D1 V00B0100 +arc: D4 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C78:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: B1 H02W0301 +arc: C1 H02E0401 +arc: D1 S1_V02N0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R32C79:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C80:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 + +.tile R32C81:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V02S0501 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: B1 V02N0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0601 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R32C82:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02S0501 +arc: A1 N1_V02S0701 +arc: A3 W1_H02E0501 +arc: B1 H02E0101 +arc: B3 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02S0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C83:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R32C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V06S0203 +arc: A0 H00R0000 +arc: A5 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B5 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C5 F6 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C85:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 N1_V01S0000 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 N1_V01S0100 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V02N0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 W1_H02E0201 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C86:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B3 H00R0100 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V00T0000 F2 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 N1_V02S0201 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1111000000110000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F6 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0100 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R32C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 H00L0100 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B4 V00B0100 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 Q2 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R32C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 F1 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 N1_V02S0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V01S0100 +arc: D2 H02W0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R32C91:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06S0203 +arc: A0 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H01W0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 1101000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C92:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 H01E0101 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 V02S0601 +arc: C4 H02W0601 +arc: C5 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: N1_V01N0101 F2 +arc: V01S0000 F5 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R32C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B1 H01W0100 +arc: B5 H02E0101 +arc: C1 V02S0601 +arc: C5 S1_V02N0001 +arc: C7 V00B0100 +arc: D1 E1_H02W0201 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V00B0100 F5 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000001010000 +word: SLICEA.K1.INIT 1000101011001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C4 W1_H02E0401 +arc: C5 S1_V02N0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: S1_V02S0201 F0 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1000101000001010 +word: SLICEC.K0.INIT 1000000011110000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R32C95:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: C0 H02W0601 +arc: C2 W1_H02E0601 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 H02W0301 +arc: B2 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 W1_H02E0601 +arc: C1 H02W0401 +arc: C2 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0101 F0 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 F5 +word: SLICED.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0011001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R32C97:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 F7 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 N1_V02S0101 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0201 +arc: D0 V02N0001 +arc: D2 H02W0001 +arc: D3 V02S0201 +arc: D4 W1_H02E0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0701 F5 +arc: V01S0000 F2 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R32C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 H00R0000 +arc: A2 V01N0101 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 H01W0100 +arc: B2 F3 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000001000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 W1_H02E0701 +arc: A2 N1_V02S0501 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0601 F4 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 F1 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 F6 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F0 +arc: S1_V02S0501 F5 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A2 F7 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 F0 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F5 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C102:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 W1_H02E0101 +arc: C0 N1_V02S0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00L0000 +arc: A2 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 H02W0501 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C1 V02S0401 +arc: C2 F4 +arc: C4 V00T0000 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: S1_V02S0301 F1 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICEA.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C104:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 W1_H02E0501 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V01N0001 F6 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 E1_H02W0501 +arc: B0 F3 +arc: B1 H02E0301 +arc: B2 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 F7 +arc: S1_V02S0401 F6 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C106:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0301 +arc: B1 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 E1_H02W0101 +arc: B7 V00B0000 +arc: C1 H00L0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D1 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C107:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00R0000 +arc: A3 F5 +arc: A4 N1_V01S0100 +arc: A5 E1_H02W0501 +arc: A6 F7 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 V02S0401 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEB.K1.INIT 1111000100000000 +word: SLICEA.K1.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C108:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F5 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F4 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C109:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0101 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 V00B0100 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 W1_H02E0601 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C110:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02N0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0701 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0601 +arc: D1 W1_H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N3_V06N0203 F4 +arc: V00B0100 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1010001010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C111:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 F7 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000100000100010 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICED.K0.INIT 1010101000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C112:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0701 +arc: A1 W1_H02E0501 +arc: A2 V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000000101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C113:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K0.INIT 1100111111001010 +word: SLICEC.K1.INIT 1111111111101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R33C114:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 F7 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C115:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010111100000000 +word: SLICEC.K1.INIT 0000000000000101 +word: SLICEB.K0.INIT 1010101000000010 +word: SLICEC.K0.INIT 1000110010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C116:PLC2 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N1_V01S0000 +arc: A6 S1_V02N0301 +arc: B6 E1_H02W0101 +arc: D6 V02N0401 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: N1_V02N0601 F6 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1011101100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R33C117:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 S1_V02N0501 + +.tile R33C118:PLC2 +arc: W1_H02W0101 S1_V02N0101 + +.tile R33C13:PLC2 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0601 H02W0601 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C14:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 F7 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0001 +arc: D1 H01E0101 +arc: D3 E1_H02W0001 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 0000111100001101 +word: SLICEA.K1.INIT 0000101000001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111100100010 +word: SLICED.K1.INIT 0000000000000101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000011111110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C15:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C5 H02E0401 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111111111111100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000010001 +word: SLICEC.K1.INIT 0000000000010011 +word: SLICEA.K0.INIT 1111100011110000 +word: SLICED.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 1111010111111101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C16:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 S1_V02N0301 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B1 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02E0201 +arc: D7 N1_V02S0401 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0000000011010000 +word: SLICEB.K1.INIT 0111000001110000 +word: SLICEA.K1.INIT 1011111100000000 +word: SLICEC.K0.INIT 0001010100000000 +word: SLICEC.K1.INIT 0011111100000000 +word: SLICED.K0.INIT 0000000001010001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0011000100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C17:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 0000110000000100 +word: SLICEB.K1.INIT 0100010011001100 +word: SLICEC.K0.INIT 0011000100000000 +word: SLICEC.K1.INIT 0101111100000000 +word: SLICED.K1.INIT 0100110001011111 +word: SLICEA.K0.INIT 1100111011001100 +word: SLICED.K0.INIT 1000100010001000 +word: SLICEA.K1.INIT 1111001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R33C18:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 V06N0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0100010100000000 +word: SLICEA.K1.INIT 0011111100000000 +word: SLICEB.K0.INIT 1010000010100000 +word: SLICEB.K1.INIT 1110110011101110 +word: SLICEC.K0.INIT 0000100000001100 +word: SLICEC.K1.INIT 0100010011001100 +word: SLICED.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 0000000010110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C19:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0101 +arc: A1 F5 +arc: A5 V00T0100 +arc: B5 E1_H02W0301 +arc: C1 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 V02S0001 +arc: D5 E1_H02W0001 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: W1_H02W0101 F1 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C20:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 V02N0501 +arc: A6 E1_H01W0000 +arc: B0 F3 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1000111110001000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 0101110110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C21:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 H01E0001 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1111001000100010 +word: SLICEC.K1.INIT 1111001000100010 +word: SLICED.K0.INIT 1111010001000100 +word: SLICED.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C22:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00R0000 +arc: A2 H00L0100 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02W0301 +arc: M2 E1_H02W0601 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000111100001101 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000111100001011 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0101010101010001 +word: SLICED.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R33C23:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 V02N0501 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H02E0201 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R33C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: A2 H02E0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 W1_H02E0101 +arc: B3 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 F2 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 0000000101000101 +word: SLICEC.K1.INIT 1111000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R33C25:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 H02W0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A6 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C26:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 V06S0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A2 E1_H02W0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 F7 +arc: N3_V06N0203 Q4 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C27:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C28:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 E1_H01E0001 +arc: A4 V02S0301 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 W1_H02E0101 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F1 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0100011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C29:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C2:PLC2 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 S1_V02N0201 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R33C30:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q3 +arc: S3_V06S0103 Q2 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C32:PLC2 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 F3 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D6 E1_H02W0201 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0303 F6 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C33:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 F7 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C34:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 H01E0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F7 +arc: V00T0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEA.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 F5 +arc: A2 V01N0101 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 V02S0301 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01S0100 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 0000000011001101 +word: SLICEB.K0.INIT 0000010101000100 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEA.K1.INIT 0000110000001101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0001 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F7 +arc: V00B0000 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1000100011000000 +word: SLICED.K0.INIT 0001000101010101 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C37:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 V06N0203 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100010010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C38:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V01N0001 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +arc: W1_H02W0201 F2 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C2 F4 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C7 E1_H02W0601 +arc: D0 N1_V02S0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C3:PLC2 +arc: W1_H02W0701 S1_V02N0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C40:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0501 +arc: A4 V02N0301 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C41:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A3 V02S0701 +arc: A5 H02E0501 +arc: A6 F7 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V01S0000 +arc: D3 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000001000110010 +word: SLICED.K1.INIT 0001010100010000 +word: SLICED.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A7 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F4 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1010000010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 W1_H02E0401 +arc: C4 H02E0601 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V02N0301 F3 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C45:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B4 H02E0301 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0201 +arc: D0 E1_H02W0001 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M4 V00T0100 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1000001011000011 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A7 N1_V01N0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 W1_H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: M0 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0000 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1100000000110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C47:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A6 F7 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0100 F6 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C48:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 H02W0701 +arc: A6 H02E0501 +arc: B1 S1_V02N0101 +arc: B6 V02N0501 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0000 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q4 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A3 H02W0501 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0201 Q0 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C4:PLC2 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A3 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B1 H01W0100 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D5 F0 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F1 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A5 H02E0501 +arc: A6 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0701 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K1.INIT 1011100000000000 +word: SLICED.K0.INIT 1100100001000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C52:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A7 V02N0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 H02W0101 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B7 V02S0501 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: M2 N1_V01N0001 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V00T0000 Q2 +arc: V01S0000 F2 +arc: V01S0100 Q2 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 F3 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1110110001001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0000 +arc: A5 V02S0301 +arc: B3 V02S0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B3 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C4 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q4 +arc: V00B0000 F4 +arc: V01S0000 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C56:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A3 V02N0701 +arc: A5 V02S0101 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B6 F1 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02S0501 +arc: A3 E1_H02W0701 +arc: A4 V02S0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 0001110100111111 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C4 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D7 S1_V02N0401 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0701 F7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A6 H00R0000 +arc: B0 E1_H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R33C5:PLC2 +arc: B0 V00T0000 +arc: B1 Q1 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R33C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 H02W0701 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C61:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H01W0000 +arc: A7 S1_V02N0301 +arc: B0 H02W0301 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: C0 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: C5 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: D7 V00B0000 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R33C62:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B5 F1 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q3 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0401 F6 +arc: V00T0100 Q1 +arc: V01S0100 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 V02S0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 F2 +arc: N3_V06N0003 F3 +arc: V00T0100 F1 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1011000010000000 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 1111111110111000 +word: SLICEB.K0.INIT 1111000011101110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R33C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02S0701 +arc: A4 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0401 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A5 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B3 V02S0301 +arc: B5 H00L0000 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 Q6 +arc: S1_V02S0701 Q7 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0100 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100010010000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C66:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0701 +arc: A5 N1_V02S0101 +arc: A7 N1_V01N0101 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 W1_H02E0201 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B2 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C1 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: M0 H02E0601 +arc: M4 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C68:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: F0 F5A_SLICE +arc: M0 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R33C69:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02N0101 +arc: B0 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D5 W1_H02E0001 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C70:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 V02N0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06N0103 +arc: A1 H02W0501 +arc: A2 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 V02N0301 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C1 N1_V02S0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K0.INIT 0010001100100000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C71:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A3 F5 +arc: A4 H02W0701 +arc: A6 V02N0101 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 0000000000110001 +word: SLICEA.K1.INIT 0011000100000000 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001000000000001 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C72:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H02W0501 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V01S0000 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C73:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V01N0101 +arc: A0 H00R0000 +arc: A1 F7 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 H02W0501 +arc: B0 H00R0100 +arc: B1 H01W0100 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K0.INIT 0000001010100010 +word: SLICEA.K1.INIT 0000001000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0000000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R33C74:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B3 H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F6 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0011000000100010 +word: SLICEC.K1.INIT 0000000000100001 +word: SLICEA.K1.INIT 0000101000100010 +word: SLICEA.K0.INIT 0000010000000001 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R33C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A2 V02N0701 +arc: A4 F7 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B7 V00B0100 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 N1_V02S0001 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: H01W0100 Q7 +arc: M0 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0100 F3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000101000100010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R33C76:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02E0701 +arc: A1 E1_H02W0501 +arc: A3 V02S0501 +arc: A4 N1_V02S0301 +arc: A6 V02S0301 +arc: B2 H02E0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R33C77:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F7 +arc: A2 F5 +arc: A4 H02E0501 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 H00R0100 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H00L0100 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D2 H02E0201 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0100010001000100 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C78:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B1 H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0301 +arc: B7 V02N0501 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F0 +arc: S1_V02S0601 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1010010111000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C79:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V06S0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: A3 V00B0000 +arc: A5 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1001000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C80:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H02W0701 +arc: B1 E1_H02W0101 +arc: C1 H02W0401 +arc: D1 V00B0100 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0101 +arc: B1 F3 +arc: B2 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C82:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 N1_V02S0701 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F5 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R33C83:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C84:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02W0501 +arc: A2 V02S0701 +arc: A5 S1_V02N0301 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 Q4 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 F7 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEC.K1.INIT 1011101100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R33C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 V02S0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010010100000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 Q6 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0203 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V00B0000 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C88:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A5 H02E0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0303 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 S1_V02N0701 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 V00T0000 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0401 F4 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100001100000000 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000100000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A5 V02N0101 +arc: A6 N1_V02S0301 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B2 F3 +arc: B3 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C5 V02S0001 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: D0 V01S0100 +arc: D1 V02S0201 +arc: D2 F0 +arc: D3 N1_V01S0000 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 H02W0401 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: V01S0000 F5 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R33C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 W1_H02E0301 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0501 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: N1_V02N0601 F6 +arc: V01S0000 F7 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011001101010101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0001101100011011 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 1101111111001100 +word: SLICED.K1.INIT 0001000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 N1_V02S0501 +arc: A6 H00R0000 +arc: A7 N1_V01S0100 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: N1_V01N0101 F0 +arc: V01S0000 F2 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000001111110011 +word: SLICED.K0.INIT 0100110001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R33C94:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 V02N0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0401 +arc: D0 H02E0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F0 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011010100110101 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R33C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A4 S1_V02N0301 +arc: A5 N1_V02S0301 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 V02S0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 0111011101110111 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R33C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 S1_V02N0501 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 E1_H01E0001 +arc: A4 H02W0701 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 F6 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +arc: V00T0000 F0 +arc: V01S0000 F2 +arc: W1_H02W0301 F1 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R33C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H02W0701 +arc: A1 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 H02W0501 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0701 +arc: B6 V02S0501 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F7 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C98:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 S1_V02N0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 E1_H02W0301 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 F1 +arc: B7 W1_H02E0101 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010010000100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C99:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A1 H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F7 +arc: N1_V01N0001 F3 +arc: S1_V02S0301 F1 +arc: V00B0000 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C101:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D2 W1_H02E0001 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 F7 +arc: A3 N1_V02S0501 +arc: A4 N1_V01N0101 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 N1_V02S0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C1 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F4 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000100001000100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C103:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 F1 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: C7 V01N0101 +arc: D0 V02S0201 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: S3_V06S0203 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C104:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0701 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A5 N1_V01S0100 +arc: A7 F5 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B7 F3 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C7 E1_H01E0101 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D7 H01W0000 +arc: E1_H01E0101 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B3 W1_H02E0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 F6 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C106:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 V02S0201 +arc: H00R0000 H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 H02W0701 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B2 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C2 V02S0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: D0 H02E0001 +arc: D2 V00B0100 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: S1_V02S0401 F6 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C107:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H01W0000 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 1010001010000000 +word: SLICEB.K0.INIT 1100110100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C108:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: B7 N1_V02S0701 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICEC.K0.INIT 1100110100000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C109:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 V02S0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 F0 +arc: D3 N1_V02S0201 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F2 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 0000000000000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R35C110:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V02S0601 +arc: C1 H00R0100 +arc: C2 F4 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C111:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0501 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 V02S0301 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 W1_H02E0101 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 H02W0601 +arc: D0 N1_V02S0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F5 +word: SLICEA.K0.INIT 1110000000100000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B4 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q6 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C113:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H00L0100 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 F6 +arc: C3 W1_H02E0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0701 F5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C114:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C115:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A3 F5 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C5 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D5 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C116:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A0 H02W0501 +arc: B0 H02E0101 +arc: B2 H02E0101 +arc: C0 S1_V02N0601 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F2 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R35C117:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C118:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 + +.tile R35C14:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: A1 N1_V02S0501 +arc: B1 E1_H01W0100 +arc: C1 E1_H02W0601 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 1101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C15:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 F6 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 0000000000100010 +word: SLICEC.K1.INIT 1100110011001110 +word: SLICEB.K0.INIT 0000000000000111 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K1.INIT 0000001100010011 +word: SLICEA.K0.INIT 1010101110101010 +word: SLICED.K0.INIT 0000000000101010 +word: SLICEA.K1.INIT 1111100011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C16:PLC2 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 W1_H02E0201 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000011110011 +word: SLICEA.K1.INIT 0000000000111011 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICED.K1.INIT 0011000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R35C17:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06S0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 W1_H02E0301 +arc: C1 V02S0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: D0 W1_H02E0201 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +word: SLICEB.K0.INIT 0111011100000000 +word: SLICEB.K1.INIT 0000110100000000 +word: SLICEA.K0.INIT 0000000001010101 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1111111100111111 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R35C18:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 H00L0100 +arc: A5 S1_V02N0301 +arc: A6 N1_V02S0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02S0601 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 F4 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1100110011001010 +word: SLICEC.K1.INIT 0000101100000000 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICED.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEB.K1.INIT 0000000000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C19:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: A7 H00L0000 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0701 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 0000111100001000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C20:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 V01N0101 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1011101000110000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1011101000110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111001000100010 +word: SLICEB.K1.INIT 1011101000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C21:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A2 W1_H02E0501 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B2 H02W0101 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: C0 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: V01S0000 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 0000000011111011 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R35C22:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 E1_H01E0001 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A6 V02N0101 +arc: B2 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02N0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F1 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0401 F6 +arc: N3_V06N0103 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000111100001011 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R35C23:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 F5 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C24:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00R0000 +arc: A4 S1_V02N0101 +arc: B0 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 N1_V02S0401 +arc: C3 F4 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 N1_V02S0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 F3 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEC.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R35C25:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 N1_V02S0101 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F7 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1000111110001000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111001000100010 +word: SLICEC.K1.INIT 1011101000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C26:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B5 V02N0501 +arc: B6 H02E0301 +arc: B7 H01E0101 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 Q0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 F1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R35C27:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 F3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C28:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 H02E0701 +arc: A1 V02N0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C29:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 H00R0000 +arc: A3 V02N0501 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q6 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C2:PLC2 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R35C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A3 V02N0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 V02N0701 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 V02N0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C31:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 N3_V06S0003 +arc: A2 W1_H02E0701 +arc: A5 Q5 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C32:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A4 V00B0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B4 H02E0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q1 +arc: S3_V06S0203 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C33:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0401 W3_H06E0203 +arc: A2 S1_V02N0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 F5 +arc: B2 N1_V02S0101 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C2 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0401 +arc: C6 N1_V02S0001 +arc: C7 F6 +arc: D2 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F4 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0001000000110010 +word: SLICEB.K0.INIT 0000010101000100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C34:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 F1 +arc: B3 F1 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 V02S0601 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 N1_V02S0401 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C35:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B3 V01N0001 +arc: B4 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F7 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A7 F5 +arc: B1 H02W0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0001010100010101 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C37:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 N1_V02S0201 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F2 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 V02N0401 +arc: D5 W1_H02E0201 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: A7 W1_H02E0701 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 W1_H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C3:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R35C40:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0501 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 N1_V02S0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F0 +arc: V00T0100 F1 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000100001000100 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C41:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 F3 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 F0 +arc: D7 H02W0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S3_V06S0103 F2 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C42:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 H02E0701 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0101 +arc: A7 H02W0701 +arc: B0 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 V02S0701 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: C6 F4 +arc: C7 S1_V02N0201 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 W1_H02E0201 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: V01S0100 F0 +arc: W1_H02W0501 F7 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0701 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B7 V02N0501 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C7 V02S0001 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: V01S0100 F5 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F0 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F4 +arc: V00B0100 F5 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C46:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V00T0100 F1 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A1 H02W0501 +arc: A3 N1_V02S0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 V02N0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 F4 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 Q3 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C48:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02N0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B3 V02S0301 +arc: B5 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 W1_H02E0201 +arc: D3 V00T0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F5 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEA.K0.INIT 1111101000111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C49:PLC2 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02N0701 +arc: A5 V00B0000 +arc: A7 S1_V02N0101 +arc: B4 V01S0000 +arc: B6 V01S0000 +arc: B7 S1_V02N0701 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C50:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A3 H00L0100 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B3 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C3 V02S0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +word: SLICED.K1.INIT 0100011101110111 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 0011001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 V02N0501 +arc: B0 N1_V02S0301 +arc: B5 H02W0301 +arc: B7 V02S0501 +arc: C0 V02S0601 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D4 H01W0000 +arc: D5 H02W0201 +arc: D7 F0 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V02N0501 Q7 +arc: V00T0000 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C52:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 S1_V02N0301 +arc: A6 V02S0101 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B6 V02N0701 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F4 +arc: V00T0100 Q3 +arc: V01S0100 F2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C53:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011111110110011 +word: SLICEA.K0.INIT 1011100011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C54:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 H02W0001 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0601 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 H02E0601 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0303 Q6 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q3 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C56:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00L0100 +arc: A5 V02S0301 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1101111110000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R35C57:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02N0701 +arc: A3 F7 +arc: A4 F7 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C58:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A3 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B5 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 Q1 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C59:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 V02S0301 +arc: B0 V02N0301 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C60:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A5 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B7 H02W0101 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q5 +arc: V00B0000 F4 +arc: V00B0100 Q5 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 0000111101110111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C61:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A3 H02W0701 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H00R0100 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 H02W0101 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V01S0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010100000100000 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R35C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 F3 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 0100011101000100 +word: SLICED.K1.INIT 0011000011111100 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEB.K0.INIT 0000000001011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C63:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 W1_H02E0301 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1011100011111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1000100011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A2 H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B5 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H00L0000 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110001011100010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0501 +arc: A7 E1_H02W0701 +arc: B1 E1_H02W0301 +arc: B3 H02W0101 +arc: B5 W1_H02E0301 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q3 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 F6 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00L0100 +arc: A6 H02E0501 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: C0 V02S0601 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 F0 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 Q5 +arc: V00T0000 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C67:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H00L0000 +arc: A3 V02N0501 +arc: B0 H02E0101 +arc: B5 H00R0000 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D5 H02W0201 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C68:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 W1_H02E0501 +arc: A6 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: D0 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: N1_V01N0001 F0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEC.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C69:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B4 W1_H02E0101 +arc: B6 V02N0701 +arc: C1 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 Q5 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEC.K0.INIT 1010010100100001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001100100001001 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C70:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 H00R0000 +arc: A4 F7 +arc: A7 S1_V02N0301 +arc: B1 V02S0101 +arc: B3 N1_V02S0301 +arc: B5 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C1 V02S0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 N1_V02S0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: E1_H02E0501 F5 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: V00B0100 F5 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0100010101000000 +word: SLICEC.K0.INIT 0000000000001010 +word: SLICED.K1.INIT 1101001010000111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C71:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M6 H02W0401 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F6 +arc: N3_V06N0303 Q6 +arc: S1_V02S0701 F5 +arc: V01S0100 F7 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V01N0101 +arc: A3 V02S0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 V00B0100 +arc: B7 H02E0301 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C7 N1_V02S0201 +arc: D2 V02N0001 +arc: D4 F2 +arc: D5 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F2 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101100011011000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 + +.tile R35C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: A1 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B3 E1_H02W0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C5 V01N0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 F0 +arc: V00T0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C74:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A1 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B6 V02N0701 +arc: C1 W1_H02E0401 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F0 +arc: S1_V02S0701 F7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C75:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 W1_H02E0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B7 H02W0301 +arc: C1 N1_V02S0601 +arc: C2 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C7 V02N0001 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: N1_V01N0101 F7 +arc: N1_V02N0701 F5 +arc: S1_V02S0201 F2 +arc: V01S0100 F7 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000100001 +word: SLICEC.K1.INIT 0011001000000010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000010011000100 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R35C76:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02N0701 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B1 V02S0301 +arc: B2 S1_V02N0101 +arc: B5 V02S0701 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 V02S0601 +arc: C7 N1_V02S0001 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 N1_V02S0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0301 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R35C77:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: A2 W1_H02E0701 +arc: A4 H02W0501 +arc: A5 N1_V02S0301 +arc: B0 V00T0000 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 V02N0501 +arc: C0 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: D0 F2 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1100001110011001 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R35C78:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H01E0001 +arc: A3 S1_V02N0701 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D1 H01E0101 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000000000011 +word: SLICEB.K1.INIT 0000100000000010 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C79:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A7 F5 +arc: B0 F3 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B4 F1 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C80:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 E1_H02W0301 + +.tile R35C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 N1_V02S0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C82:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 N1_V02S0501 +arc: A2 H00L0100 +arc: A5 V00T0100 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0601 F4 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C84:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B6 V02N0501 +arc: B7 H01E0101 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 N1_V02S0201 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010000000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R35C85:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02S0501 +arc: A2 F7 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0501 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C87:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F5 +arc: A3 H01E0001 +arc: A4 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 W1_H02E0501 +arc: A7 V02N0301 +arc: B1 W1_H02E0301 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0501 +arc: A2 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 N1_V02S0301 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B5 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0501 F5 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 W1_H02E0501 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 H01E0001 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06W0103 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A4 S1_V02N0101 +arc: A5 N1_V01N0101 +arc: A6 F7 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: B7 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 W1_H02E0601 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: A2 V00T0000 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 N1_V02S0401 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R35C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B3 N1_V02S0101 +arc: B4 V02S0501 +arc: B7 F3 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICEA.K0.INIT 1000101000001010 +word: SLICEB.K1.INIT 1010001000100010 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R35C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 F6 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0001001100000000 +word: SLICEB.K1.INIT 1011111110101010 +word: SLICEC.K1.INIT 0011011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 H02E0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 F6 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 H02W0001 +arc: D1 N1_V02S0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H02W0201 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F4 +arc: N1_V02N0201 F0 +arc: V01S0000 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C95:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 H02W0501 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F0 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C96:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 V01N0101 +arc: A2 H02W0701 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 V02N0101 +arc: B4 N1_V02S0701 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: D0 W1_H02E0001 +arc: D1 F0 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06S0303 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 N1_V02S0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F0 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R35C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 S1_V02N0501 +arc: A4 F7 +arc: A5 N1_V02S0301 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: V01S0100 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R35C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 F5 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0401 F4 +arc: V00T0100 F1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0501 +arc: B5 V02S0501 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 N1_V02S0601 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 W1_H02E0001 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V01S0000 F6 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0000101000001010 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C102:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B4 V02S0501 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V02N0001 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 F3 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C103:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02W0001 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 F5 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 H02W0301 +arc: B7 V02S0501 +arc: C1 H00R0100 +arc: C2 F6 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0401 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C104:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 S1_V02N0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A3 F7 +arc: A4 H02W0501 +arc: A7 H00L0000 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B7 H02E0101 +arc: C3 F4 +arc: C4 V00B0100 +arc: C7 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C105:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 V02S0501 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 H02E0701 +arc: B0 F1 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 F0 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C106:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 V02S0501 +arc: A5 E1_H02W0701 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B5 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 V01N0101 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R36C107:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 N1_V01S0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 F4 +arc: C2 N1_V01N0001 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C108:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B2 E1_H02W0101 +arc: B3 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1100100001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C109:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 S1_V02N0501 +arc: A3 H02E0701 +arc: A4 V02S0301 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0301 +arc: B1 H02E0101 +arc: B2 N1_V02S0101 +arc: B3 E1_H01W0100 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 V01N0101 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H01E0001 +arc: D0 H01E0101 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N3_V06N0003 F3 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1100110000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C110:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0201 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICEB.K1.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R36C111:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 F3 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 0010001000110010 +word: SLICED.K1.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C112:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A2 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0303 F5 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F6 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0011001101010101 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0000101001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R36C113:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V02S0501 +arc: A4 N1_V02S0101 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 1110000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C114:PLC2 +arc: E1_H02E0101 H01E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 E1_H02W0501 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: B7 E1_H02W0301 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010100000000 +word: SLICED.K1.INIT 1111000000100000 +word: SLICED.K0.INIT 0000111000000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C115:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A5 V02S0301 +arc: B5 N1_V02S0501 +arc: C5 W1_H02E0601 +arc: D5 S1_V02N0401 +arc: F5 F5_SLICE +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C116:PLC2 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: A0 H02W0501 +arc: B0 V02S0301 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R36C117:PLC2 +arc: N1_V02N0501 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 + +.tile R36C118:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R36C14:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0101 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R36C15:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 + +.tile R36C16:PLC2 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: A0 V02N0501 +arc: B0 E1_H01W0100 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0011101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C17:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 F5 +arc: A6 H02W0501 +arc: A7 F5 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 1111010100000000 +word: SLICED.K0.INIT 0001000101010001 +word: SLICEA.K0.INIT 0000000011000000 +word: SLICEA.K1.INIT 1010101011101010 +word: SLICEC.K0.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R36C18:PLC2 +arc: E1_H02E0401 V02N0401 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 H01E0001 +arc: A0 H02E0701 +arc: A1 F5 +arc: A3 V02S0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 F6 +arc: C1 F4 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 N1_V02S0401 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0010000000100000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K0.INIT 0000000000001011 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEB.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 1101010101010101 +word: SLICEC.K0.INIT 0000000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R36C19:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: S3_V06S0303 H01E0101 +arc: A6 V02N0101 +arc: B3 V02N0101 +arc: C1 E1_H02W0601 +arc: C6 V02N0001 +arc: D1 V01S0100 +arc: D3 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 0000000000110011 +word: SLICED.K0.INIT 0101000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R36C20:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0501 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A7 F5 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 H00L0000 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICEC.K0.INIT 1011101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R36C21:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 0000000010101000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1000111110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C22:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B6 H01E0101 +arc: C1 V02S0601 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F4 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C23:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: H00L0000 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0701 +arc: A2 V00T0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 V02S0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0101010100000000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R36C24:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010111000001100 +word: SLICED.K0.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C25:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H00R0000 +arc: A2 V02N0501 +arc: A5 N1_V01S0100 +arc: A7 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R36C26:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111010001000100 +word: SLICEC.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1101010111000000 +word: SLICED.K0.INIT 1101110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C27:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 V06S0303 +arc: A1 S1_V02N0701 +arc: A3 V01N0101 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0100 F5 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C28:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: A0 H02E0501 +arc: A3 F5 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R36C29:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02S0001 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: C0 S1_V02N0401 +arc: C1 F6 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0301 Q3 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 1100111000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C30:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: A0 H02W0701 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C31:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 V02N0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C32:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 W3_H06E0303 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0203 F7 +arc: V00T0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C33:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 F4 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02S0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F6 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEB.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 0000111100000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 S1_V02N0701 +arc: A4 F7 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B5 F3 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F2 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0001000100110011 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C35:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0501 +arc: A1 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C7 V02S0201 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D4 F0 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0100 F7 +arc: N1_V01N0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R36C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A0 V02S0701 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C37:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0601 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D7 H02E0201 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: N1_V01N0001 F2 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 F7 +arc: A3 S1_V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0000101000001011 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEC.K0.INIT 0000111100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 E1_H02W0601 +arc: C6 V01N0101 +arc: C7 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICEB.K0.INIT 0000000000111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B3 N1_V02S0301 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: B7 V01S0000 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V01N0101 +arc: C6 H02W0401 +arc: C7 F6 +arc: D1 V02S0201 +arc: D2 W1_H02E0001 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0001 F2 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C42:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 H02W0601 +arc: C1 N1_V01S0100 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: N1_V01N0001 F7 +arc: S1_V02S0601 F4 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C44:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V02N0301 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B7 V02S0501 +arc: C0 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0001 +arc: D5 E1_H02W0201 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0000 F3 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 0000001000110010 +word: SLICEB.K1.INIT 0000001000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 H00L0100 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C46:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 F3 +arc: C0 H00R0100 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: D0 V02N0001 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F0 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C47:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 E1_H02W0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B2 V02N0101 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 0000010101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R36C48:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 H02E0501 +arc: B3 V01N0001 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0001 +arc: F3 F3_SLICE +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 0011001101011111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C49:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B5 H02W0101 +arc: C1 S1_V02N0601 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 N1_V01N0001 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111110000110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C50:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A7 H00R0000 +arc: B2 V01N0001 +arc: B5 H02W0301 +arc: C1 H02E0401 +arc: C2 V02S0401 +arc: C5 V00T0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 Q7 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0201 Q2 +arc: N3_V06N0203 Q7 +arc: V00T0000 F0 +arc: V01S0000 F6 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C51:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A5 H02E0701 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B5 V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEC.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010100000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B1 H02W0101 +arc: B2 H02W0301 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R36C53:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 E1_H02W0501 +arc: A6 S1_V02N0101 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B3 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C3 H02E0401 +arc: C6 N1_V02S0001 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0101010100001100 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R36C54:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 S1_V02N0501 +arc: A4 V02N0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 W1_H02E0201 +arc: D4 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 F3 +arc: V00B0100 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R36C55:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0701 +arc: A5 N1_V02S0301 +arc: A6 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B6 H01E0101 +arc: C3 H02W0601 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 F0 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N3_V06N0303 F6 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1110010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C56:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: B2 V01N0001 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C57:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 F1 +arc: B5 V01S0000 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 F4 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0011001000000010 +word: SLICEB.K1.INIT 1111111011001110 +word: SLICEC.K1.INIT 1100111111001010 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 1111000011101110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C58:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: E1_H02E0401 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V02N0301 F3 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1010000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C59:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0701 +arc: A2 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 V02S0101 +arc: C0 H02E0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C60:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0401 F6 +arc: V01S0100 F6 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C61:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q7 +arc: M0 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 H02E0701 +arc: A4 N1_V02S0101 +arc: A5 E1_H02W0501 +arc: A6 V02S0101 +arc: B0 V02S0301 +arc: B1 V01N0001 +arc: B3 H02W0301 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 S1_V02N0501 +arc: C0 F6 +arc: C1 V02N0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K1.INIT 1101111111010000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R36C63:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V01N0101 +arc: A1 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR0 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C64:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 W1_H02E0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V02S0501 +arc: C1 H02E0401 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V02S0401 +arc: E1_H01E0101 Q7 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 W1_H02E0401 +arc: M5 H02E0001 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F6 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1111000011101110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C65:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile R36C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 H06W0103 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 H02W0701 +arc: B1 H02E0301 +arc: B3 V02N0101 +arc: C1 W1_H02E0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0201 +arc: D3 S1_V02N0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0100010001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C67:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: A7 V02N0301 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 H00R0100 +arc: C4 N1_V02S0001 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 F2 +arc: V00B0000 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 0000001010100010 +word: SLICEB.K0.INIT 0000000001000001 +word: SLICED.K1.INIT 0101010000000100 +word: SLICEC.K1.INIT 0000101000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 F5 +arc: A7 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B4 V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C4 S1_V02N0001 +arc: C5 V02S0001 +arc: C6 H01E0001 +arc: C7 V01N0101 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: N1_V01N0101 F1 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K0.INIT 0000000000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0010000000101010 +word: SLICEC.K1.INIT 0000000001000001 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0100000001110000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R36C69:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02W0701 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: B3 H00R0100 +arc: B5 H02E0101 +arc: C1 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0701 F5 +arc: N3_V06N0003 F3 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C70:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 H00R0100 +arc: B3 H01W0100 +arc: B5 N1_V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0501 +arc: C0 V02S0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V02N0001 F0 +arc: N3_V06N0303 F5 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000000011100010 +word: SLICEA.K1.INIT 0100000001001100 +word: SLICEB.K0.INIT 1100101000110101 +word: SLICED.K0.INIT 0100011100000000 +word: SLICED.K1.INIT 0011010100000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C71:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: A4 N1_V01S0100 +arc: A5 W1_H02E0501 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V02N0501 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 F4 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C72:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A2 F7 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: C0 H00R0100 +arc: C2 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0501 F7 +arc: V01S0000 F5 +arc: V01S0100 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0011000001010000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C73:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0000000000100011 +word: SLICEB.K1.INIT 0000000010001100 +word: SLICEC.K1.INIT 0101000001000100 +word: SLICEC.K0.INIT 0011000000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C74:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 H00L0100 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICEB.K1.INIT 0000110001000100 +word: SLICED.K1.INIT 0001000000000001 +word: SLICEA.K0.INIT 0010000001110000 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000110000001111 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R36C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: A0 F5 +arc: A1 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICEB.K1.INIT 0010001000110000 +word: SLICEC.K1.INIT 0101010100010001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0011000000100010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C76:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 V02S0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0701 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 H02W0301 +arc: B4 N1_V02S0501 +arc: B5 H02W0101 +arc: B7 V02S0501 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D2 H01E0101 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F5 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0011000000100010 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R36C77:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 N1_V02S0701 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0401 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 H02W0001 +arc: D3 F2 +arc: D5 H02W0201 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V00T0100 F1 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEB.K0.INIT 0011001000010000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEB.K1.INIT 0000000001000001 +word: SLICED.K0.INIT 0001000000000001 +word: SLICEA.K1.INIT 0010011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A4 H02W0701 +arc: A5 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 H02E0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0101000000110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C79:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: B5 H02E0101 +arc: C5 H02W0401 +arc: D5 V02N0401 +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R36C80:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 + +.tile R36C81:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: V01S0000 N3_V06S0103 + +.tile R36C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A3 H02W0701 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 F5 +arc: A7 H02E0501 +arc: B3 N1_V02S0301 +arc: B4 H00L0000 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V02S0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 E1_H02W0001 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 V06N0003 +arc: A2 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C84:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0501 +arc: A2 V00B0000 +arc: A3 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R36C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V01N0001 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 F3 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C86:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: A1 E1_H02W0501 +arc: A4 V00T0100 +arc: A6 V02S0301 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B6 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 Q3 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C87:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: A1 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 N1_V02S0301 +arc: B4 V00B0100 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 H01E0101 +arc: C0 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 H02W0601 +arc: C5 F4 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C88:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 N1_V02S0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C89:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0701 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 W1_H02E0601 +arc: C5 V02S0001 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0103 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R36C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 V02N0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D0 H02E0001 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F6 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 V01N0101 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 V00B0100 +arc: B5 H01E0101 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 F4 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 N1_V02S0401 +arc: D6 V02N0401 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: M0 H02W0601 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F0 +arc: V00T0000 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000101010 +word: SLICEA.K1.INIT 1011111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 E1_H02W0501 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: D0 E1_H02W0201 +arc: D1 V02S0001 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: D4 N1_V02S0601 +arc: D5 W1_H02E0001 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R36C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: A1 N1_V02S0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V02N0201 F2 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000111100000000 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R36C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 S1_V02N0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010001000100 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R36C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 V01N0101 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 W1_H02E0401 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 N1_V02S0601 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 F0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C96:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 H01E0101 +arc: A0 V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R36C97:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 V06N0203 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H02W0301 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C2 F4 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 H01E0001 +arc: C6 V01N0101 +arc: C7 S1_V02N0201 +arc: D0 V00B0100 +arc: D2 F0 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0101 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0401 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 F0 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R36C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V00T0000 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C100:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V01N0101 +arc: A0 N1_V02S0501 +arc: A1 V02S0701 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C101:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 E1_H02W0501 +arc: A2 V02N0501 +arc: A3 V01N0101 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C102:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 V02S0301 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 F1 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C103:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0501 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 S1_V02N0101 +arc: A5 H02E0701 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: B7 H02W0301 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C7 V00T0000 +arc: D1 F2 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 H02E0601 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C104:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 F5 +arc: A5 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B5 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C5 V00T0100 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C105:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0701 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C106:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H00L0000 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0601 +arc: C6 N1_V02S0001 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C107:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B4 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D4 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C108:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 F2 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C110:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEC.K1.INIT 0000010100010001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 0000101100001010 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C111:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A2 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 H00R0000 +arc: B1 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 V02S0701 +arc: B7 H01E0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F5 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEC.K1.INIT 0000000011110100 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICED.K1.INIT 1010101100000000 +word: SLICEA.K0.INIT 0000101001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R37C112:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 N1_V02S0101 +arc: B1 V01N0001 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0101010100110011 +word: SLICEC.K0.INIT 0000010100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C113:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 V01N0001 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C114:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 V00B0000 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 H02E0101 +arc: B7 F1 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICEC.K0.INIT 1100000011001000 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICED.K1.INIT 1010101000000010 +word: SLICEB.K0.INIT 1011101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C115:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0501 +arc: B0 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: C0 H00L0100 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R37C116:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0501 F7 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R37C117:PLC2 +arc: N1_V02N0601 H01E0001 + +.tile R37C119:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R37C120:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R37C14:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: V00T0100 N1_V02S0701 +arc: A0 H02W0701 +arc: B0 V02S0301 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0111010100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C15:PLC2 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 V02S0701 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R37C16:PLC2 +arc: N1_V02N0501 H02E0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02W0301 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 0100010001100110 +word: SLICEB.K1.INIT 0111001001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R37C17:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 V02S0701 + +.tile R37C18:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0201 N3_V06S0103 +arc: V00T0100 V02S0701 +arc: A0 H02W0701 +arc: B0 H02E0301 +arc: C0 E1_H01W0000 +arc: D0 V02N0201 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111111111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C19:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: S1_V02S0101 H06E0103 +arc: W1_H02W0701 N1_V02S0701 +arc: B2 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C5 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: LSR1 E1_H02W0301 +arc: M5 H02E0001 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C20:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 V02N0301 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C21:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 F5 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111010001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 W1_H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 V02S0501 +arc: A3 H01E0001 +arc: A5 V02N0101 +arc: A6 V02S0101 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 H02E0301 +arc: B4 H02E0301 +arc: B5 W1_H02E0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0100 F2 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R37C23:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B0 H02W0101 +arc: B3 V01N0001 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 F3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1010000010100000 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C24:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: A3 S1_V02N0701 +arc: A5 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 W1_H02E0301 +arc: B6 H02W0301 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R37C25:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: A0 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 V02S0301 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R37C26:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0401 N1_V01S0000 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02S0501 +arc: A4 H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0701 Q5 +arc: V00T0000 Q2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R37C27:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C4 V00B0100 +arc: C5 H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F6 +arc: V01S0100 F4 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R37C28:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F5 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F5 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R37C29:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H02E0701 +arc: B0 F3 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C30:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H02E0501 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: E1_H02E0101 Q3 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C31:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C32:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C33:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 E1_H02W0101 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 V01S0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02S0401 +arc: C4 V00T0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D4 H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEC.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C34:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 H01E0101 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 0001010100010000 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICEB.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000000011110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C36:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 S1_V02N0301 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000001001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C37:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 H02E0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H00R0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V02S0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0001 +arc: D3 W1_H02E0201 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0201 F2 +arc: V01S0100 Q0 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C38:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 F6 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0701 F5 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A5 H02E0701 +arc: A7 H02E0701 +arc: B1 H02E0101 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C1 V02S0601 +arc: C2 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V00B0100 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F0 +arc: V01S0100 F5 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A4 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B4 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C4 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F0 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C41:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0501 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02W0401 +arc: C6 F4 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101110100001101 +word: SLICED.K0.INIT 1001000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C42:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V01N0101 +arc: A1 H00R0000 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 N1_V02S0101 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C1 E1_H02W0601 +arc: C2 F6 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02S0001 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: V00B0100 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C43:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A4 V02S0101 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B0 N1_V02S0101 +arc: B1 H01W0100 +arc: B2 W1_H02E0301 +arc: B3 H01W0100 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: B7 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: C7 V02N0001 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0701 F7 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001010000010 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C44:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 H02E0301 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 N1_V02S0101 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: S3_V06S0303 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEA.K0.INIT 0101000001010001 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 F5 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEB.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C46:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V01N0101 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0001 F3 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C47:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B6 F1 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q0 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H02W0501 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0701 Q7 +arc: V00T0100 Q3 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0701 +arc: B2 E1_H02W0101 +arc: C2 H02W0601 +arc: D2 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +word: SLICEB.K0.INIT 1000110010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C50:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02S0101 +arc: B1 H02E0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B7 S1_V02N0701 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R37C51:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 S1_V02N0301 +arc: B1 H02W0301 +arc: B4 V02N0501 +arc: C1 H00L0100 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100000010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C52:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02N0501 +arc: A3 H02W0501 +arc: B0 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 H02W0301 +arc: B7 V00B0100 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 V02S0201 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q1 +arc: V00B0100 Q5 +arc: V00T0000 F0 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W1_H02W0401 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 E1_H02W0701 +arc: B0 H02E0101 +arc: B3 E1_H02W0301 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C3 H02E0601 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 F0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001000011011100 +word: SLICED.K1.INIT 0011000011111100 +word: SLICEA.K0.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R37C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 S1_V02N0501 +arc: A6 V02S0301 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C1 H02W0601 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0010101000101010 +word: SLICEB.K0.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R37C55:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E1_H01W0100 +arc: H00L0100 H02W0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02S0701 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 V02N0101 +arc: B5 E1_H02W0301 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C5 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D2 H02E0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00L0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 E1_H02W0701 +arc: A7 V02S0301 +arc: B7 H02E0301 +arc: C4 H01E0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D7 H02W0201 +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M1 H00L0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F7 +arc: V01S0000 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q6 +word: SLICED.K1.INIT 0000111101110111 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A2 V00B0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: B0 W1_H02E0101 +arc: B1 V01N0001 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V00T0100 F1 +arc: V01S0000 Q7 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0000000010101100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C59:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: B0 V02S0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F0 +arc: V01S0100 F4 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICEA.K0.INIT 0000111101110111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C60:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B6 S1_V02N0701 +arc: B7 F1 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F7 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C62:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A6 H00R0000 +arc: B1 H02E0101 +arc: B6 V02S0501 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D6 F2 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 Q4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q6 +arc: V00B0000 Q6 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1110000001000000 +word: SLICED.K0.INIT 0000011111110111 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 V00B0000 +arc: A5 E1_H02W0701 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B4 H02W0301 +arc: B7 F1 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0601 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C64:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 V00B0100 +arc: D5 V02S0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 W1_H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0203 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C65:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 V01N0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0301 +arc: B3 V02N0301 +arc: B5 H02W0301 +arc: C1 V02S0601 +arc: C3 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q3 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C66:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B7 S1_V02N0501 +arc: C2 V02N0401 +arc: C3 N1_V01N0001 +arc: C7 W1_H02E0601 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +word: SLICEB.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R37C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: A3 V02N0701 +arc: A4 F5 +arc: A5 H02E0701 +arc: A6 N1_V01N0101 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 N1_V02S0701 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D0 V00T0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F4 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEC.K0.INIT 0001000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H00L0000 +arc: A2 H02E0701 +arc: A3 E1_H01E0001 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: A7 F5 +arc: B2 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 W1_H02E0601 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 0000001000000001 +word: SLICED.K0.INIT 0000000011100100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0010011100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C69:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 V01N0101 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A0 N1_V02S0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B3 H00L0000 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 V02S0201 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0100000001001100 +word: SLICEB.K1.INIT 0000000001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C70:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A5 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: C1 V02S0601 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H00L0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R37C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0701 +arc: A2 H02W0701 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 F5 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0101011010100110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0100010001010000 +word: SLICED.K1.INIT 0010000100000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 0101000000110000 +word: SLICEB.K1.INIT 0100011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C72:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F6 +arc: V00T0000 F0 +word: SLICED.K1.INIT 0000001000000001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0101000001000100 +word: SLICEA.K1.INIT 0000001010100010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101010000000100 +word: SLICEC.K0.INIT 0011010100000000 +word: SLICED.K0.INIT 0000010000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A3 H02W0701 +arc: A5 H02E0701 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F5 +arc: V01S0100 F4 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000010011000100 +word: SLICEA.K0.INIT 0011000000000011 +word: SLICEA.K1.INIT 0100000100000000 +word: SLICEC.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R37C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A2 N1_V02S0701 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: B0 H02E0301 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B6 H01E0101 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 0011000000100010 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R37C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 N1_V02S0501 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 0000111000000100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000110001000100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C76:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A3 V02S0701 +arc: A4 N1_V02S0101 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B4 V00B0100 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 S1_V02N0401 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D0 F2 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0001110100000000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C77:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A2 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 V02S0301 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C1 V02S0401 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1001100100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1010000001010000 +word: SLICED.K0.INIT 0000000001000001 +word: SLICEB.K0.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C78:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A2 F7 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 F6 +arc: C2 F6 +arc: C3 F6 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000100001001100 +word: SLICEB.K0.INIT 0101000000000101 +word: SLICEB.K1.INIT 0100000100000000 +word: SLICEC.K1.INIT 0000100000101010 +word: SLICEC.K0.INIT 0011000100100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C79:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02E0701 +arc: A4 N1_V02S0101 +arc: A6 V02S0101 +arc: B2 H02W0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V01S0000 +arc: C2 V02N0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D2 E1_H02W0201 +arc: D4 F2 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: S1_V02S0501 F7 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111000000100 +word: SLICED.K0.INIT 0000101000100010 +word: SLICEC.K0.INIT 0000000000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C80:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 H00L0000 +arc: A1 F5 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B1 H00R0100 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 F6 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 F0 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C81:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 V02S0101 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H01E0001 +arc: A6 H00L0000 +arc: B0 V02S0301 +arc: B3 E1_H02W0301 +arc: B6 V02S0501 +arc: C0 H02E0601 +arc: C3 N1_V01S0100 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00T0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A4 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 N1_V02S0101 +arc: B1 V01N0001 +arc: B2 N1_V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0201 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D6 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C84:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V01N0001 +arc: A0 H02W0701 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C85:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0001 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 V01S0000 +arc: B5 F3 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICED.K1.INIT 1000100000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C87:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R37C88:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 F7 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010110010101100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R37C89:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02S0701 +arc: B6 V00B0100 +arc: B7 F3 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C90:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 V06N0303 +arc: A2 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0401 +arc: C1 H02W0401 +arc: C2 F4 +arc: C3 E1_H02W0401 +arc: C4 F6 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0701 F7 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R37C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A2 H02W0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: D1 E1_H02W0001 +arc: D2 V00T0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0000001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R37C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: B1 W1_H02E0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 F3 +arc: C0 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 N1_V02S0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0101 F5 +arc: S1_V02S0001 F0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0001000110111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R37C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H02E0501 +arc: A4 V00T0100 +arc: A6 N1_V02S0301 +arc: B1 S1_V02N0101 +arc: B4 H00R0000 +arc: B6 V00T0000 +arc: C1 V02N0401 +arc: C4 V01N0101 +arc: C6 H02E0601 +arc: D1 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: V00T0100 F1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 V02N0501 +arc: B4 H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C4 V00T0100 +arc: D1 E1_H02W0201 +arc: D4 V02S0601 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0000 +arc: S1_V02S0201 F0 +arc: S3_V06S0203 F4 +word: SLICEC.K0.INIT 0000000011110011 +word: SLICEA.K1.INIT 0000101001011111 +word: SLICEA.K0.INIT 0101111101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R37C95:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0003 V06N0003 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 V02S0101 +arc: B4 F3 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 V02N0201 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00T0000 F0 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R37C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02S0201 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 F5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: A7 H02W0701 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02W0401 +arc: C5 V00B0100 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 F0 +arc: V00T0100 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R37C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0501 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V00B0100 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 F6 +arc: C3 W1_H02E0401 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: D0 H02W0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R37C99:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 F4 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 E1_H02W0201 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F2 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 V02N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D0 V02N0201 +arc: D2 N1_V02S0201 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 F0 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H02E0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 H02E0401 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C103:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A0 N1_V02S0701 +arc: A1 H01E0001 +arc: A2 F5 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 F3 +arc: B2 F1 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 H00L0100 +arc: C2 F6 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1101110100001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C104:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R38C105:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A7 H00L0000 +arc: B1 V02S0301 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C7 S1_V02N0201 +arc: D1 V00T0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C106:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 F7 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 H02E0101 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0101 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: N1_V01N0101 F6 +arc: V00T0000 F2 +arc: V01S0000 F3 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C107:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 V02S0701 +arc: A6 H00L0000 +arc: B0 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B6 F3 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C6 V00T0000 +arc: D0 V00T0100 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D6 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C108:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 F7 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H00R0100 +arc: B2 H02E0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 W1_H02E0101 +arc: C0 V02S0601 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 F6 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R38C109:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 F0 +arc: S1_V02S0701 F5 +word: SLICEB.K0.INIT 0000010111110101 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C110:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A6 H02W0501 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000101001000101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000011111101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C111:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 H02E0501 +arc: A4 F5 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0501 +arc: B0 V02S0101 +arc: B1 N1_V02S0101 +arc: B2 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: S3_V06S0003 F0 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 0000111000001111 +word: SLICED.K1.INIT 0000111000001111 +word: SLICEB.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICEC.K0.INIT 0011000000110010 +word: SLICEA.K0.INIT 0000111000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R38C112:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A1 V02S0501 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V00B0000 F6 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000000010101100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1100000011000100 +word: SLICEA.K1.INIT 0001000000010000 +word: SLICED.K1.INIT 1010101000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C113:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C114:PLC2 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 N1_V01S0000 + +.tile R38C115:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 V02S0501 +arc: A4 V00B0000 +arc: B0 V02N0301 +arc: C0 V02N0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D4 S1_V02N0401 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K0.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R38C116:PLC2 +arc: N3_V06N0303 S1_V02N0601 +arc: A0 H00L0000 +arc: B0 H02E0301 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C117:PLC2 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0601 V06N0303 + +.tile R38C118:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R38C14:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 V06N0203 + +.tile R38C15:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R38C16:PLC2 +arc: H00R0100 H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 N1_V01S0100 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B6 H02W0301 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +word: SLICED.K0.INIT 0011000010101010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C17:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: C3 H00L0000 +arc: C6 H01E0001 +arc: D3 H01E0101 +arc: D6 H02E0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V01S0100 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R38C18:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0401 V01N0001 + +.tile R38C19:PLC2 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R38C20:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: A0 H00R0000 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100000011000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C21:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111010001000100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C22:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 H01E0101 +arc: A0 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 V02S0501 +arc: A7 V02N0301 +arc: B1 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0203 F7 +arc: S3_V06S0203 F4 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R38C23:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: A1 W1_H02E0701 +arc: B0 V00T0000 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: B6 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0101000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R38C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 F5 +arc: A5 V02S0101 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: C0 N1_V01N0001 +arc: C3 F4 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICED.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEC.K1.INIT 0000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C25:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 H00L0000 +arc: A6 V02N0301 +arc: B1 E1_H01W0100 +arc: B4 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R38C26:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A2 V00B0000 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 W1_H02E0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000001010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C27:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A5 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B5 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F4 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R38C28:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A6 H02W0701 +arc: A7 E1_H02W0501 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R38C29:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02S0601 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010000011101100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1100111000001010 +word: SLICEC.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C30:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V01N0101 +arc: B0 H02E0101 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C31:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 S1_V02N0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C32:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 V06N0003 + +.tile R38C33:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: A0 F5 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 W1_H02E0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D5 H02W0201 +arc: D6 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C34:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B5 H02W0301 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D5 F0 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: B1 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 F1 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00L0000 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 F3 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100001010 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEB.K1.INIT 0000000011001101 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0100010001000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B4 F1 +arc: B5 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICEC.K0.INIT 0001000100110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B1 V00T0000 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C3 V02S0401 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F0 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1101110100001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C39:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 H01E0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A5 V02N0101 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: D0 N1_V02S0201 +arc: D5 N1_V02S0601 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0601 F6 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C40:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B4 V01S0000 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 0000000001110010 +word: SLICED.K0.INIT 0000000011001101 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 0000010000001110 +word: SLICEC.K1.INIT 0000000011001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C41:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A2 H01E0001 +arc: A3 V02N0701 +arc: A6 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 F2 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F3 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1100000000110000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R38C42:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A4 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B1 H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 F1 +arc: C1 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C6 V00T0000 +arc: C7 N1_V02S0201 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F7 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010001010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: D0 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C44:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N3_V06N0203 F4 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 F7 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 V01N0101 +arc: D1 F2 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C46:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: A3 H02E0701 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0203 F7 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICED.K1.INIT 1110001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C47:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 E1_H02W0701 +arc: B3 E1_H02W0101 +arc: C3 N1_V01N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: E1_H01E0001 F7 +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICED.K1.INIT 0101000001010000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C48:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A2 V01N0101 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 F2 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R38C49:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: B0 V00B0000 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1011111110110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 E1_H02W0501 +arc: A2 E1_H01E0001 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B5 F3 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: M0 V00T0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R38C51:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 H00R0100 +arc: B3 F1 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 F0 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 F0 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C52:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0701 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B5 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 H00R0100 +arc: C3 S1_V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEA.K1.INIT 1110010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C53:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A3 F7 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B5 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0000010100001111 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010001010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C54:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H02W0701 +arc: A4 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 F4 +arc: C1 V02N0401 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C6 V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B4 V02N0701 +arc: B6 H01E0101 +arc: C0 H00R0100 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 Q7 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0001101100001010 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 0100110001001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R38C56:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 V02S0501 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101110111110000 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: B3 H02W0101 +arc: C0 H02E0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 H02E0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C58:PLC2 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 V01N0101 +arc: A5 V02S0101 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C3 H00L0100 +arc: C5 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0203 F7 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1100101011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C60:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C2 E1_H01W0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 1111011111010101 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICED.K1.INIT 1111111111001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C61:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V00B0000 +arc: B5 V01S0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F5 +arc: F5 F5_SLICE +arc: H01W0000 Q3 +arc: M3 H02E0201 +arc: M5 H02W0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1010000011000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C62:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: B0 H02E0301 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C63:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: C2 W1_H02E0601 +arc: C4 V01N0101 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00T0000 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C64:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06S0203 +arc: B1 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: C1 V02N0401 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C65:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 V06N0103 +arc: A0 F7 +arc: A7 V02N0301 +arc: B1 H02W0101 +arc: B4 H02W0101 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0601 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M3 H00R0000 +arc: MUXCLK1 CLK0 +arc: V00B0000 F4 +arc: V01S0000 Q3 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C66:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 S3_V06N0003 +arc: B3 V02N0301 +arc: C3 S1_V02N0601 +arc: D3 V00T0100 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R38C67:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0501 +arc: A2 F5 +arc: A4 W1_H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 W1_H02E0401 +arc: C7 H02W0401 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000101000100010 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICED.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R38C68:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEA.K1.INIT 0010000001110000 +word: SLICED.K1.INIT 0001000000000001 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R38C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A3 F5 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B5 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 E1_H01E0101 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F1 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0100000001001100 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000100000101010 +word: SLICED.K0.INIT 0101000101000000 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C70:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 F5 +arc: A6 H00L0000 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 F4 +arc: C4 V01N0101 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 F1 +arc: V00B0000 F6 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 0010001000110000 +word: SLICEC.K0.INIT 0000001000000001 +word: SLICEB.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0010011100000000 +word: SLICEB.K0.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C71:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A3 V02S0501 +arc: A5 S1_V02N0101 +arc: A6 F7 +arc: A7 W1_H02E0501 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 V02S0201 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F0 +arc: S1_V02S0401 F6 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000010100101 +word: SLICEA.K1.INIT 0000000010000100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A4 N1_V02S0101 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B5 N1_V02S0501 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 F4 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICED.K0.INIT 0000000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C73:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0501 +arc: A2 V02N0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D0 V02S0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0010001000110000 +word: SLICEA.K0.INIT 0001110100000000 +word: SLICEC.K1.INIT 0000000001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C74:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 F0 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010110001010011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110010000011011 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B2 E1_H01W0100 +arc: B5 N1_V01S0000 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 W1_H02E0401 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R38C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V01N0101 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: N1_V01N0001 F4 +arc: V00T0000 F0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C77:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0501 +arc: A1 F5 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A6 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: C0 F6 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D3 H02W0201 +arc: D4 F0 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: V00T0100 F1 +arc: V01S0000 F3 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C78:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00R0000 +arc: A4 E1_H02W0701 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: B0 H02E0301 +arc: B2 N1_V02S0101 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: D0 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F2 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 0000110001000100 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C79:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A7 E1_H02W0701 +arc: B3 S1_V02N0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C3 V02N0601 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: D3 H02E0201 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F6 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C80:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V01N0101 +arc: A2 H02W0501 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H02E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: S1_V02S0201 F2 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 1100000011110000 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 H00R0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 N1_V01N0001 +arc: C3 H02E0401 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 S1_V02N0501 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C83:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 H00L0100 +arc: A4 V00B0000 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 H02W0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C84:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02E0701 +arc: A4 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C4 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1000000001000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C85:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A3 E1_H01E0001 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B1 H02E0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 E1_H01W0000 +arc: C4 N1_V02S0001 +arc: C5 F4 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R38C87:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 N1_V02S0301 +arc: B2 H02W0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0301 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0601 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0501 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A4 H02W0501 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C2 S1_V02N0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C89:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 V06S0103 +arc: A0 V02N0501 +arc: A5 Q5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C90:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 V01N0101 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A6 H00R0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B6 F1 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D6 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R38C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A0 W1_H02E0501 +arc: A1 H02W0701 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 F6 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C92:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 F7 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B6 H02W0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S3_V06S0103 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R38C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00L0100 +arc: A4 W1_H02E0701 +arc: B1 E1_H02W0101 +arc: B4 V00B0100 +arc: C1 N1_V01N0001 +arc: C4 V00T0100 +arc: D1 H00R0000 +arc: D4 S1_V02N0601 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F4 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 + +.tile R38C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A1 F5 +arc: A3 S1_V02N0501 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 F3 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0401 F4 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C96:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 N1_V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F1 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R38C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A1 F5 +arc: A2 V02N0501 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B7 V00B0000 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 S1_V02N0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V02N0201 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R38C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H00R0100 +arc: B2 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02S0001 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 F0 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R38C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 H01E0001 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 F7 +arc: A7 V02S0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C101:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 H02W0301 +arc: B4 F1 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 F2 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 F1 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V02S0001 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R39C103:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A5 W1_H02E0701 +arc: A6 E1_H01W0000 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B5 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C104:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 F5 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 N1_V02S0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 V02N0501 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 N1_V02S0701 +arc: C0 H02E0401 +arc: C2 V02N0401 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: D0 V02S0001 +arc: D2 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 F0 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C106:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F5 +arc: A1 V01N0101 +arc: A2 N1_V02S0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F2 +arc: V00T0100 F1 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C107:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0000 H02W0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A1 V02S0501 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 F3 +arc: B3 H02E0101 +arc: B4 V02N0501 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C1 N1_V02S0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V01S0000 F4 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C108:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H01E0001 +arc: A3 V00T0000 +arc: A4 F7 +arc: A7 H00L0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B7 S1_V02N0501 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C7 H02W0401 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 0000010100000000 +word: SLICEB.K1.INIT 0010001000110010 +word: SLICEB.K0.INIT 0000111000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C109:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 F3 +arc: B5 E1_H02W0301 +arc: B6 W1_H02E0301 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 F6 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICED.K1.INIT 0000101001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R39C110:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A4 H02E0701 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 N1_V02S0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICED.K0.INIT 0000010000000111 +word: SLICED.K1.INIT 0101000001010100 +word: SLICEC.K0.INIT 0000111000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C111:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0701 +arc: A2 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: D0 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 F0 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +word: SLICEA.K0.INIT 0100010001110111 +word: SLICEC.K1.INIT 0000000100001011 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R39C112:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: A1 H02W0701 +arc: A3 N1_V02S0701 +arc: B1 V02S0301 +arc: B3 H02W0301 +arc: B5 F3 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C5 E1_H01E0101 +arc: D1 E1_H02W0201 +arc: D3 V02S0201 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEC.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R39C113:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C0 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +arc: V01S0100 F2 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R39C114:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C115:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: B0 S1_V02N0301 +arc: B1 V01N0001 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C116:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 + +.tile R39C117:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile R39C15:PLC2 +arc: N1_V02N0101 S1_V02N0101 + +.tile R39C16:PLC2 +arc: E1_H02E0401 N1_V01S0000 + +.tile R39C17:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 + +.tile R39C18:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F0 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0100010111001100 +word: SLICEA.K1.INIT 0100000011001100 +word: SLICEB.K0.INIT 0100010111001100 +word: SLICEB.K1.INIT 0100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C19:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: V01S0000 N3_V06S0103 +arc: A2 F5 +arc: A3 W1_H02E0501 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C3 V02S0401 +arc: C5 W1_H02E0401 +arc: D1 W1_H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K1.INIT 0000101000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R39C20:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 H01E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: B1 V02N0101 +arc: C0 H02E0401 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: S3_V06S0003 F0 +arc: V00B0000 F4 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R39C21:PLC2 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: A2 V00B0000 +arc: A3 F7 +arc: A6 E1_H01W0000 +arc: A7 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 H00L0000 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 0011001000010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C22:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0301 H02W0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 H01E0001 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010000011101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C23:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 0000010100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R39C24:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: A1 V02N0501 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100111000001010 +word: SLICED.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1010111000001100 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100111000001010 +word: SLICEC.K0.INIT 1000100011111000 +word: SLICEC.K1.INIT 1010111000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C25:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 V01N0101 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 H01E0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H01W0100 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R39C26:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 V02S0601 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 V02S0301 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q6 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1011001110100000 +word: SLICEB.K0.INIT 1011001110100000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICEC.K0.INIT 1011001110100000 +word: SLICEC.K1.INIT 1111001000100010 +word: SLICED.K0.INIT 1111001000100010 +word: SLICED.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C27:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 W3_H06E0103 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B1 Q1 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R39C28:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0501 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 1011101111110011 +word: SLICED.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1011100010111000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R39C29:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02N0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 W1_H02E0701 +arc: A4 F7 +arc: A5 Q5 +arc: A6 H02W0701 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V02N0501 +arc: B6 H01E0101 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010111000001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111000001100 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1101110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C30:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C31:PLC2 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C32:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: A6 N1_V02S0301 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C33:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0701 +arc: A1 N1_V02S0501 +arc: A4 E1_H01W0000 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 F1 +arc: B1 H01W0100 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C1 F4 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEC.K0.INIT 0001000100110000 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C34:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06N0303 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 H01E0001 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 V00T0100 +arc: B1 W1_H02E0101 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 H02W0401 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001010100010000 +word: SLICEC.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000000010101011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F5 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F7 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C36:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A4 V00T0100 +arc: A6 H02E0501 +arc: B0 N1_V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C6 V00T0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: W1_H02W0001 F0 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEC.K0.INIT 0000000001001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C37:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H00L0000 +arc: A1 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 V02N0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: B0 V01N0001 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 V02S0701 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 F4 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: S3_V06S0103 F2 +arc: V00B0000 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0001010100010000 +word: SLICEB.K0.INIT 0000000010101011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C38:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A4 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0100010001000101 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 1011100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C39:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 V02S0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H02E0301 +arc: B6 F3 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: S1_V02S0501 F7 +arc: V00B0000 F4 +arc: V01S0000 F0 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0001000100110011 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 E3_H06W0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A5 V00B0000 +arc: B1 V01N0001 +arc: B4 H02E0301 +arc: B5 V02N0701 +arc: C1 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: D1 H02W0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N3_V06N0103 F1 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H02W0501 +arc: B0 F3 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: S1_V02S0601 F6 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: A0 V02N0501 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A3 W1_H02E0501 +arc: A4 H02E0501 +arc: A6 V02S0101 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 N1_V02S0701 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C43:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: D0 V00T0100 +arc: D1 N1_V02S0001 +arc: D3 H02W0201 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1010100000100000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 N1_V02S0701 +arc: A1 H00L0000 +arc: A2 V01N0101 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0301 +arc: B6 F1 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 F4 +arc: D0 F2 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: V00B0100 F5 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000000001110111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 0000010000001110 +word: SLICEA.K1.INIT 0000010000001110 +word: SLICED.K0.INIT 0101000001010001 +word: SLICED.K1.INIT 0000110000001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C45:PLC2 +arc: E1_H02E0101 V06S0103 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06N0303 +arc: A0 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 E1_H02W0701 +arc: A6 H02W0501 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B4 V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: C0 H00L0100 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 0000101000001010 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C46:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 E1_H01E0001 +arc: A7 N1_V01N0101 +arc: B3 N1_V02S0301 +arc: B5 F3 +arc: B7 H02E0101 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 V00T0100 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M4 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0101001101011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 N3_V06S0303 +arc: A6 H02W0501 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B6 H02W0301 +arc: C1 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0601 F6 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C48:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 E1_H01E0001 +arc: A6 V00T0100 +arc: B1 V02S0301 +arc: C1 V02S0601 +arc: C3 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 Q4 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R39C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 V02N0301 +arc: B6 V00B0100 +arc: C6 H02W0401 +arc: D6 H00R0100 +arc: F6 F6_SLICE +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 1100000010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C50:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0701 +arc: A3 H02W0501 +arc: B4 N1_V02S0701 +arc: B5 V02N0501 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R39C51:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1101111110001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C52:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0501 +arc: A5 E1_H01W0000 +arc: B1 V01N0001 +arc: B3 S1_V02N0301 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R39C53:PLC2 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: A6 V02N0101 +arc: B0 V00B0000 +arc: C0 H02W0401 +arc: C6 V00T0100 +arc: D0 V00B0100 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C54:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 N1_V01N0101 +arc: B6 W1_H02E0101 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q1 +arc: F6 F6_SLICE +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 1010000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C55:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 H02W0301 +arc: B7 H02W0101 +arc: C0 F4 +arc: C1 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0001101101011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R39C56:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C57:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A4 F7 +arc: A7 V02S0301 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D5 H00L0100 +arc: D7 H00R0100 +arc: E1_H02E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: V00T0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0010101000101010 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C58:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A6 V00T0100 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 H01E0001 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0201 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0303 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0101010100110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R39C59:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R39C60:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: C1 H02W0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 F2 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 1111101100111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: A3 V02N0701 +arc: B3 H00L0000 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 S1_V02N0001 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 F3 +arc: F3 F3_SLICE +arc: M2 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q6 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEB.K1.INIT 1101000010000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C62:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A5 W1_H02E0701 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 H01E0101 +arc: C0 S1_V02N0601 +arc: C3 H02E0601 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0000011111110111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C63:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C3 H00L0100 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0301 Q3 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1010110011111111 +word: SLICEB.K0.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R39C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 V06N0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02W0701 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 Q3 +arc: F2 F5B_SLICE +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C65:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D5 H02E0001 +arc: D6 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1011100010111000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R39C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 W1_H02E0701 +arc: B2 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: V00B0100 F7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0010001000110000 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICED.K0.INIT 0000101000100010 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICED.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R39C67:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 V02S0501 +arc: A2 V01N0101 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H01E0001 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F2 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001001 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C68:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 F1 +arc: B6 N1_V02S0701 +arc: B7 H02E0301 +arc: C1 S1_V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 0100010000001100 +word: SLICEA.K1.INIT 0101000001000100 +word: SLICEC.K1.INIT 0000000000100000 +word: SLICED.K1.INIT 1110010000011011 +word: SLICEB.K1.INIT 1100000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R39C69:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B2 S1_V02N0301 +arc: B3 F1 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: D0 V02S0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 F0 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K1.INIT 0000010011000100 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 0101000101000000 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICED.K0.INIT 0000000001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C70:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 F5 +arc: A3 N1_V02S0701 +arc: A7 V00T0100 +arc: B0 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 S1_V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000011100010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEA.K1.INIT 0000101000000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R39C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 H01E0101 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0101 +arc: C0 H02W0401 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0100010101000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C72:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: A0 N1_V02S0501 +arc: A1 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02N0501 +arc: A4 F7 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V01S0000 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F2 +arc: S1_V02S0001 F0 +arc: V00B0000 F4 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 0000000000001001 +word: SLICED.K1.INIT 0010011111011000 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C73:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 H02W0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0001 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0501 F7 +arc: V00T0100 F3 +arc: V01S0000 F1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100101000110101 +word: SLICED.K0.INIT 1101100000100111 +word: SLICEB.K1.INIT 1001101010010101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1001101010010101 +word: SLICEA.K1.INIT 0000000011001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 N1_V02S0501 +arc: A2 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 F7 +arc: A5 V02S0301 +arc: A7 V02N0101 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 N1_V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0001 F2 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 0101000001000100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000001000000001 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 V02S0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 E1_H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F2 +arc: S3_V06S0003 F3 +arc: V01S0000 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C76:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A6 V02S0301 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F1 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 0100110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C77:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B4 V00B0100 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C3 V02S0601 +arc: C4 H02W0601 +arc: C7 V00T0100 +arc: D0 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 F4 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0011000100100000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C78:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0001 +arc: C6 H02W0601 +arc: D0 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D6 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: S1_V02S0201 F0 +arc: S1_V02S0601 F4 +arc: V01S0000 F6 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0101000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: B0 V02S0301 +arc: C0 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00T0000 +arc: V00T0000 F2 +arc: V01S0000 F0 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R39C80:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A6 H02E0701 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B6 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 E1_H02W0401 +arc: C3 H00R0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D6 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1110010001000100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C81:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B0 V01N0001 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K0.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R39C82:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C83:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 S3_V06N0103 + +.tile R39C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0203 V06N0203 +arc: A1 V02N0701 +arc: B1 E1_H01W0100 +arc: C1 H02W0401 +arc: D1 H02W0001 +arc: F0 F5A_SLICE +arc: M0 V00B0100 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A4 H02E0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B7 V02S0701 +arc: C2 H00L0000 +arc: C4 V00T0000 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D4 V00B0000 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 W1_H02E0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F4 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1000100011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000000011001100 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C87:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V01N0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 1000111110000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R39C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 F1 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 F4 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0601 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C90:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A4 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0401 F4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1011001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R39C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: C0 H02W0601 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00T0000 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1101010100000000 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICEB.K1.INIT 0000110001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A3 S1_V02N0701 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 + +.tile R39C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: W1_H02W0001 F0 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEA.K0.INIT 0001010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 F5 +arc: A1 S1_V02N0501 +arc: A2 V00B0000 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C7 W1_H02E0401 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0001 F2 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R39C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B2 H00L0000 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 W1_H02E0601 +arc: C2 W1_H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 F5 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R39C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 F5 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 S1_V02N0301 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: V01S0000 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R39C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R39C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 H02E0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 F5 +arc: A2 H01E0001 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 W1_H02E0101 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 H01E0101 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: N1_V01N0001 F2 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R3C43:PLC2 +arc: V00B0000 E1_H02W0401 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F5A_SLICE +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C44:PLC2 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0301 S1_V02N0301 + +.tile R3C45:PLC2 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 + +.tile R3C46:PLC2 +arc: H00L0000 V02N0201 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: A0 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C47:PLC2 +arc: S1_V02S0001 H02W0001 +arc: W1_H02W0401 S1_V02N0401 + +.tile R3C48:PLC2 +arc: W1_H02W0001 V06N0003 + +.tile R40C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0501 +arc: A1 H02E0501 +arc: A4 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B4 H02E0301 +arc: C0 N1_V02S0401 +arc: C1 F4 +arc: C4 S1_V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C101:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A2 V00B0000 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A7 F5 +arc: B0 V01N0001 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B7 H02E0301 +arc: C0 F4 +arc: C2 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: D0 F2 +arc: D2 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F0 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000100000100010 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A3 N1_V02S0701 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 W1_H02E0601 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 W1_H02E0201 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R40C103:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 F1 +arc: B4 H01E0101 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C104:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0100 +arc: A2 V02S0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 N1_V02S0601 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: S1_V02S0301 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C105:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02E0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H01E0001 +arc: A3 S1_V02N0501 +arc: A6 V00T0100 +arc: B2 F3 +arc: B3 H02W0101 +arc: B6 V02S0501 +arc: C2 F6 +arc: C3 V02N0401 +arc: C6 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D6 H00L0100 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C106:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 E1_H02W0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 N1_V02S0701 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 N1_V02S0601 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0701 F7 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010000001010000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R40C107:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C6 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 F0 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F2 +arc: W3_H06W0103 F1 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0001000111011101 +word: SLICEA.K0.INIT 0011000000111111 +word: SLICEB.K1.INIT 0000000100100011 +word: SLICED.K0.INIT 0101010100000100 +word: SLICEA.K1.INIT 1110111011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C108:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00R0000 +arc: A2 E1_H02W0501 +arc: A4 F7 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B4 F1 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 F6 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02N0001 +arc: D2 V02S0001 +arc: D4 F2 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C109:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A7 N1_V02S0301 +arc: B0 W1_H02E0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C4 Q4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0000010110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R40C110:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 H02E0701 +arc: A5 S1_V02N0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C4 V00B0100 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: V00B0100 F5 +arc: V00T0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEC.K1.INIT 0011001101010101 +word: SLICEC.K0.INIT 0000001100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C111:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0501 +arc: A5 F7 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0101 +arc: B5 H01E0101 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F5 +arc: N3_V06N0203 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0011010100110101 +word: SLICEC.K1.INIT 0000010100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C112:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D7 V00B0000 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R40C113:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 F5 +arc: V01S0100 F3 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C114:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02W0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: B0 V01N0001 +arc: B4 H02W0101 +arc: C0 H00L0000 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D4 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEC.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R40C115:PLC2 +arc: N1_V02N0401 S1_V02N0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q2 +arc: V00T0000 Q2 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C116:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 + +.tile R40C17:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 E1_H01W0100 + +.tile R40C18:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: V01S0000 F2 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0000101110101010 +word: SLICEA.K1.INIT 0000100010101010 +word: SLICEB.K0.INIT 0101000111110000 +word: SLICEB.K1.INIT 0100000011110000 +word: SLICEC.K0.INIT 0000101010111010 +word: SLICEC.K1.INIT 0000101010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C19:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D5 N1_V02S0401 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q7 +arc: N3_V06N0003 F3 +arc: V01S0000 F0 +arc: V01S0100 Q7 +word: SLICED.K0.INIT 0010001110101010 +word: SLICED.K1.INIT 0010001010100010 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R40C20:PLC2 +arc: E1_H02E0001 V01N0001 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: A0 V02S0701 +arc: A1 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 H02E0701 +arc: A6 W1_H02E0501 +arc: B0 F3 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0201 +arc: D3 V01S0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 F1 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0011110010101010 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C21:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A3 F5 +arc: A6 F7 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 F3 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R40C22:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: A3 V02N0701 +arc: A5 N1_V02S0301 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 N1_V02S0201 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: S1_V02S0201 F2 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000001010011 +word: SLICED.K1.INIT 0011001100100010 +word: SLICED.K0.INIT 0001000000010101 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R40C23:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02E0501 +arc: A2 F7 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 H01W0100 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0001 +arc: D3 H01E0101 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 F5 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C24:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: A1 V02N0501 +arc: A2 H01E0001 +arc: A3 N1_V02S0501 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 V02S0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0100000000000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001000100010 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C25:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 N1_V01S0100 +arc: A7 Q7 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02S0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1010000011101100 +word: SLICEC.K0.INIT 1011101000110000 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1000100011111000 +word: SLICED.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C26:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A4 V02S0101 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C27:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 H02W0701 +arc: A5 V02S0101 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B7 F3 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 V01N0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R40C28:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: B1 Q1 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 W1_H02E0601 +arc: C4 V02S0001 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R40C29:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A6 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B6 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: V01S0000 F1 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C30:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 H06E0303 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0501 H06E0303 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C32:PLC2 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: A0 W1_H02E0701 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C33:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: A0 H02W0701 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 F7 +arc: A2 F7 +arc: A3 H01E0001 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B5 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F1 +arc: S3_V06S0303 F5 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000000011001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C35:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0701 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B7 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C36:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B5 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C5 E1_H01E0101 +arc: D0 H00R0000 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 0000000001001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C37:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E1_H01W0000 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V02S0501 +arc: A5 V02N0101 +arc: B5 F3 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: D3 V00T0100 +arc: D5 V02S0601 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010000010001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C38:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 N1_V01S0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 F6 +arc: C3 H02W0601 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: C6 S1_V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0001 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S3_V06S0103 F2 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICED.K0.INIT 0000000000111010 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 0000000010101011 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0010001000100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C39:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B1 H02E0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 F2 +arc: D7 H02W0201 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 0001000101010101 +word: SLICEA.K1.INIT 0000001000001110 +word: SLICED.K0.INIT 0000001000110010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEB.K1.INIT 0000000011110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C40:PLC2 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A2 F5 +arc: A3 F7 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 N1_V02S0101 +arc: B2 F1 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C2 F4 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 F0 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 H02W0701 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 F0 +arc: D2 H01E0101 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: V01S0000 F3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C42:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H02W0501 +arc: A7 N1_V02S0301 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: D0 V02S0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V02N0301 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1000100010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C43:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 F7 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B1 H02E0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D0 H02W0201 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D6 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 1100010011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A5 H02E0701 +arc: A7 V00T0100 +arc: B5 H02E0301 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V00T0100 F1 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C45:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 V02N0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02E0501 +arc: A4 H02E0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C1 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: H01W0100 Q6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0501 Q5 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: V00T0000 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C46:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A6 H02E0701 +arc: B1 E1_H02W0101 +arc: B6 H01E0101 +arc: C1 S1_V02N0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S1_V02S0601 F6 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C47:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: C1 H02W0601 +arc: C3 H00R0100 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02N0701 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B6 H01E0101 +arc: C1 N1_V02S0601 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D3 S1_V02N0001 +arc: D6 H02W0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: N1_V02N0401 F6 +arc: V00T0000 F2 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C49:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B5 F1 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 H00L0100 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 W1_H02E0001 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0401 F6 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B1 W1_H02E0301 +arc: B4 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C3 H00R0100 +arc: C4 H02E0401 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0101001101011111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R40C51:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B3 V01N0001 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C52:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0501 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: C1 N1_V02S0401 +arc: C3 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 F6 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000101001001110 +word: SLICED.K1.INIT 0100010011101110 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R40C53:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A4 V00B0000 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 Q3 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R40C54:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V02S0101 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F5 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R40C55:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A6 V02N0301 +arc: B1 S1_V02N0301 +arc: B6 H01E0101 +arc: C1 H02W0601 +arc: C2 F6 +arc: C3 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D6 H00R0100 +arc: E1_H02E0401 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F0 +arc: W1_H02W0201 F2 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C56:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02E0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0701 +arc: A3 V02S0501 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: S3_V06S0003 Q3 +arc: V00T0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100100001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C57:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02N0501 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C58:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: B0 F1 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B6 V02N0701 +arc: C0 H00L0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F3 +arc: V01S0000 Q0 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C59:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: C0 S1_V02N0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02W0201 +arc: D5 V01N0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 F2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 0001001111011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C60:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C61:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B3 S1_V02N0301 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C62:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 E1_H02W0701 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 H02E0101 +arc: B3 H00R0000 +arc: B6 H02E0101 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0100 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C63:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 F2 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E3_H06W0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 H02E0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C65:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 E1_H01E0001 +arc: A4 H02E0701 +arc: A6 E1_H02W0501 +arc: B4 S1_V02N0501 +arc: C1 H02E0401 +arc: C4 V02S0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D4 V00B0000 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C66:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 S1_V02N0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A7 H00R0000 +arc: B1 H02W0101 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C4 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D4 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 0101000001000100 +word: SLICEA.K1.INIT 0000110001000100 +word: SLICED.K1.INIT 0000000000100001 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R40C67:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0101 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A1 F7 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 V01N0001 +arc: B5 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H02E0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 F2 +arc: D2 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 0000000011001010 +word: SLICED.K1.INIT 0101001100000000 +word: SLICEA.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R40C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A7 V00T0100 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C69:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V01N0101 +arc: A6 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R40C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 W1_H02E0501 +arc: A3 F7 +arc: A4 H02W0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B3 F1 +arc: B4 H00L0000 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C3 F6 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000011100100 +word: SLICED.K1.INIT 0001000010110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010000000001 +word: SLICEC.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R40C72:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 V00T0000 +arc: B2 F3 +arc: B5 F3 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 W1_H02E0601 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V02N0101 F1 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 0010001000110000 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEA.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C73:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 F5 +arc: A5 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 V02S0101 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 F1 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 W1_H02E0601 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F4 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0000101000100010 +word: SLICEA.K1.INIT 0000000001000001 +word: SLICEB.K0.INIT 0011000001010000 +word: SLICEC.K1.INIT 0001000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C74:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 F1 +arc: B3 H02E0301 +arc: B4 H01E0101 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01N0001 +arc: C4 F6 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: D0 F2 +arc: D1 W1_H02E0001 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0100 F7 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K0.INIT 0000000000001001 +word: SLICED.K0.INIT 0100010001010000 +word: SLICEB.K1.INIT 0011000001010000 +word: SLICED.K1.INIT 0011000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R40C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0501 +arc: A1 V02N0501 +arc: A4 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B4 V01S0000 +arc: B6 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: S1_V02S0101 F1 +word: SLICEC.K0.INIT 0101000101000000 +word: SLICED.K0.INIT 0000100000101010 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C76:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 F7 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: D0 V00T0100 +arc: D2 H02W0201 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1001000010011001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1110010000011011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0010001000110000 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C77:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 F5 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B2 V01N0001 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C2 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D2 N1_V02S0001 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000101000001100 +word: SLICEC.K1.INIT 0000000000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C78:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B0 V02N0301 +arc: B2 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V02S0601 +arc: C2 N1_V01S0100 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: V00T0000 F0 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICED.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0000000000001001 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C79:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile R40C80:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H02W0501 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 F0 +arc: D3 V02N0201 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: N1_V01N0001 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C81:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: C0 V02S0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F7 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R40C82:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H01E0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0701 +arc: A5 Q5 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06N0303 + +.tile R40C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02E0401 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: B0 H02E0101 +arc: C0 H00L0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1101110100001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R40C85:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 H00L0100 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C86:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 V02S0401 +arc: A1 N1_V02S0501 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 F7 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H00R0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 F6 +arc: C5 V02S0201 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02E0701 +arc: A2 E1_H02W0501 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D5 E1_H02W0001 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C88:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02W0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V02N0701 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 F1 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C89:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 W1_H02E0701 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 F3 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W1_H02W0001 Q2 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111000000110000 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C90:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A5 V02S0101 +arc: B0 E1_H02W0101 +arc: B2 H00L0000 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0201 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101011100000000 +word: SLICEB.K0.INIT 1010101010100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C91:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 H02W0701 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 F3 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001000001010000 +word: SLICEC.K1.INIT 1011101011111010 +word: SLICEB.K1.INIT 0001000100010011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C92:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A2 H02W0501 +arc: B2 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 H00R0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 0101000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R40C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 W1_H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00R0000 +arc: A3 H02W0701 +arc: B0 V00B0000 +arc: B3 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C3 S1_V02N0401 +arc: C7 V01N0101 +arc: D0 S1_V02N0201 +arc: D3 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1000000010101010 +word: SLICEB.K1.INIT 0101001100000000 +word: SLICED.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R40C94:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 V06S0203 +arc: B3 N1_V02S0101 +arc: C3 W1_H02E0601 +arc: D3 V00B0100 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0011000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R40C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 F3 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 F0 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R40C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: A0 S1_V02N0501 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 H00R0100 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C97:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 F5 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 H01E0001 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D2 V02N0201 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V01S0100 F1 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C98:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A6 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B6 F3 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C6 F4 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R40C99:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 E1_H01W0000 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 H01E0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 N1_V02S0001 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: N3_V06N0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R41C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 H02E0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: V00T0100 F3 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C101:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 F6 +arc: C6 V00B0100 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 H01E0101 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0501 +arc: A1 F7 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 E1_H01W0000 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D5 V02S0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C103:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0501 +arc: A2 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 F1 +arc: B4 H02E0101 +arc: B5 H01E0101 +arc: B6 E1_H02W0301 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V00B0100 +arc: C6 E1_H02W0601 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00L0100 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C104:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02W0201 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A2 V02N0701 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: V00B0000 F6 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C105:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: B0 S1_V02N0301 +arc: C0 H02W0401 +arc: D0 N1_V01S0000 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C106:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02W0501 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A5 W1_H02E0501 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 F3 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000001000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C107:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 F5 +arc: A1 H00L0000 +arc: A4 W1_H02E0501 +arc: A5 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 V02N0701 +arc: B7 V02N0501 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F4 +arc: N1_V02N0201 F0 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C108:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0401 +arc: A5 V00T0100 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C3 H00L0100 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: D3 E1_H02W0201 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +word: SLICED.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000001111110011 +word: SLICEC.K1.INIT 0000010100000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C109:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0501 +arc: A5 Q5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C110:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 S1_V02N0101 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C111:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 Q5 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 N1_V02S0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C112:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A2 V02N0701 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C113:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V06S0103 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C114:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: B0 S1_V02N0301 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C115:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile R41C116:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R41C117:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R41C118:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 + +.tile R41C14:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R41C15:PLC2 +arc: N1_V02N0101 S3_V06N0103 + +.tile R41C16:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E3_H06E0103 V06S0103 + +.tile R41C17:PLC2 +arc: N1_V02N0101 H02E0101 + +.tile R41C18:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N3_V06S0303 + +.tile R41C19:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0201 H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A5 H02E0701 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0601 Q6 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 Q6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1000101011001110 +word: SLICEA.K1.INIT 1000000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0100010100000001 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R41C20:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 H02E0101 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H02E0401 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 0011110010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R41C21:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0101110010101100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEB.K1.INIT 1111001110111011 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R41C22:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0501 +arc: A1 W1_H02E0501 +arc: B1 H02E0101 +arc: B2 V01N0001 +arc: B4 H02W0101 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0601 F4 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R41C23:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: B0 V01N0001 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 N1_V02S0001 +arc: D3 F2 +arc: D4 F2 +arc: D5 W1_H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R41C24:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 F7 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 W1_H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K0.INIT 1110111000100010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010000011101100 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R41C25:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0501 F7 +arc: S1_V02S0601 F6 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R41C26:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B4 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000101000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C27:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 W1_H02E0301 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C6 N1_V02S0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0401 Q6 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C28:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N1_V01S0100 +arc: V00B0000 H02E0601 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 N1_V02S0501 +arc: A7 V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 N1_V01S0000 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C29:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0701 +arc: B1 V02N0101 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C30:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C31:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: A2 V00B0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V02S0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C32:PLC2 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C33:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: A2 N1_V02S0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A6 V02S0301 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 F4 +arc: C4 V01N0101 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICED.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0010001000100011 +word: SLICEB.K1.INIT 0100010001000101 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C34:PLC2 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02N0701 +arc: A0 F7 +arc: A1 V02S0501 +arc: A2 F5 +arc: A5 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H02W0201 +arc: D5 H02W0001 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICEC.K1.INIT 0000000001110100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C35:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: A1 F5 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: B2 H02W0101 +arc: B4 V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 F2 +arc: D7 V02N0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00B0000 F4 +arc: W1_H02W0301 F1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1110010000000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C36:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A7 H00R0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C2 N1_V02S0601 +arc: C3 V02N0401 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D6 W1_H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C37:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0601 E3_H06W0303 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 H02E0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B5 E1_H02W0301 +arc: B6 H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: S3_V06S0103 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEB.K1.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000001100001010 +word: SLICEA.K1.INIT 0000001100001010 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C38:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D4 H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: V01S0100 F1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0000110000001101 +word: SLICEA.K1.INIT 0001010100000100 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000011001101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C39:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A7 F5 +arc: B0 H02W0301 +arc: B1 V00B0000 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: D0 H02E0201 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 S1_V02N0601 +arc: D6 V02S0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1010001010000000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000110010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R41C40:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F5 +arc: A1 H02W0501 +arc: A2 H02E0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICED.K1.INIT 1010100000100000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICED.K0.INIT 0001000101010000 +word: SLICEC.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C41:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 F1 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 E1_H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 V02S0501 +arc: A3 H02W0501 +arc: A6 E1_H02W0701 +arc: B1 V02N0101 +arc: B3 F1 +arc: C1 H00L0000 +arc: C6 V01N0101 +arc: D1 N1_V01S0000 +arc: D3 E1_H02W0201 +arc: D6 V01N0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +arc: W1_H02W0101 F3 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R41C43:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A2 H02E0501 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 H01W0100 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K1.INIT 0000000001110010 +word: SLICEB.K1.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0011000000110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B7 F3 +arc: C0 H02E0601 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 F0 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +word: SLICED.K1.INIT 0000101000001011 +word: SLICEB.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0000011100000100 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C45:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02W0701 +arc: A5 F7 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1010000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C46:PLC2 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: A3 H02E0501 +arc: A7 H00R0000 +arc: B3 H00R0100 +arc: B7 H02E0101 +arc: C3 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D3 H01E0101 +arc: D7 H02W0001 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C47:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A5 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q5 +arc: H01W0100 F1 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1011111110001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C49:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A4 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 H01E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F4 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 F7 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C51:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: B1 V01N0001 +arc: C1 V02S0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 1101100000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C52:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 H02W0101 +arc: B5 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 F7 +arc: S3_V06S0303 Q5 +arc: V00T0000 F0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R41C53:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 N1_V02S0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 F5 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: W1_H02W0001 F2 +arc: W3_H06W0303 Q5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1011100000000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E1_H02W0601 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 V02S0301 +arc: B3 V02N0101 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0601 F4 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R41C55:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02W0501 +arc: A2 V02S0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H02W0501 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B4 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: M2 N1_V01N0001 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000010011110100 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H01E0001 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 1111001110111011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02E0401 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B0 V02N0101 +arc: B1 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +word: SLICEA.K1.INIT 1110000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C58:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A3 V02N0701 +arc: B3 N1_V02S0101 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK3 CLK0 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R41C59:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A6 H02E0701 +arc: B0 H02E0301 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: C0 H00L0000 +arc: C5 F6 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0201 F2 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 F7 +arc: A3 H02W0501 +arc: A4 H02E0501 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K0.INIT 1101111111010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C61:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02E0101 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 S1_V02N0501 +arc: A3 H02E0501 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 S1_V02N0301 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q2 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V02N0001 Q2 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEB.K0.INIT 1010000011000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C62:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0000 +arc: A3 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 E1_H01W0100 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: B7 V02N0701 +arc: C1 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: V00B0000 F4 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1111111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R41C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: B1 V02S0101 +arc: B3 V02N0101 +arc: B7 H01E0101 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F0 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R41C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 F6 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R41C65:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 E1_H02W0601 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 H02W0501 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R41C68:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 V02S0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 V02S0101 +arc: B0 W1_H02E0101 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 V01N0101 +arc: C6 H02E0401 +arc: C7 V00B0100 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 0000110000001010 +word: SLICEA.K1.INIT 0000101000100010 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C69:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A6 F5 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C5 V02S0001 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C70:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 N1_V02S0501 +arc: A3 W1_H02E0701 +arc: A6 N1_V01S0100 +arc: B0 S1_V02N0301 +arc: B2 V02S0101 +arc: B3 E1_H02W0101 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 W1_H02E0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D6 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H01E0001 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B3 N1_V02S0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: C7 H02E0401 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F6 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 0000101000001100 +word: SLICED.K1.INIT 0101000000110000 +word: SLICED.K0.INIT 0000000000001001 +word: SLICEB.K1.INIT 0011111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R41C72:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 V00B0000 +arc: B1 V00T0000 +arc: B5 H02W0301 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0601 +arc: C5 H02E0601 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D5 E1_H01W0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: N1_V01N0001 F1 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 0100011110111000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R41C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 E1_H02W0701 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R41C74:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 F5 +arc: A3 V02N0501 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 W1_H02E0401 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICEC.K1.INIT 0000110000001010 +word: SLICEC.K0.INIT 0011110001011010 +word: SLICEB.K0.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R41C75:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A4 V02S0301 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 F2 +arc: D2 N1_V02S0201 +arc: D4 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 0000001010001010 +word: SLICEA.K0.INIT 0000000011000011 +word: SLICEA.K1.INIT 0000000010000010 +word: SLICED.K1.INIT 0000101000001100 +word: SLICEC.K0.INIT 0001000010110000 +word: SLICED.K0.INIT 0001000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H01E0001 +arc: A4 N1_V02S0101 +arc: B4 H00L0000 +arc: C0 N1_V02S0401 +arc: C4 H02E0601 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 H02E0601 +arc: N1_V02N0001 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0010000000101010 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0101010110101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R41C77:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00R0000 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 F2 +arc: D6 V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: V01S0000 F6 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 0000101000100010 +word: SLICED.K1.INIT 0000110000001010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000101100001000 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000000000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A2 H01E0001 +arc: A5 S1_V02N0301 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B5 H00R0000 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C79:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V01N0101 +arc: A2 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0100 F7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C80:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 V01N0101 +arc: B0 N1_V02S0101 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C81:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1010000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R41C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0401 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B5 H00R0000 +arc: B7 H02W0301 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 Q1 +arc: V00T0100 F3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C83:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0701 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 V02N0701 +arc: B7 H02E0301 +arc: C2 H02W0601 +arc: C3 F4 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: W1_H02W0301 F3 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C84:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 F1 +arc: B1 V02S0301 +arc: B2 N1_V02S0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 V00B0000 +arc: B3 H02E0101 +arc: C3 H02E0401 +arc: D3 H02E0001 +arc: F3 F3_SLICE +arc: H01W0000 F3 +word: SLICEB.K1.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C86:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 + +.tile R41C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V00T0000 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A7 F5 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 F2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C88:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 V01N0001 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B6 H02W0301 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R41C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 E1_H02W0301 +arc: B2 H02W0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D6 H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: V00B0000 F4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110100000000 +word: SLICEC.K0.INIT 0000000000000011 +word: SLICEB.K1.INIT 0101011100000000 +word: SLICEB.K0.INIT 0000110001001100 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V01S0000 + +.tile R41C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A5 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B2 E1_H01W0100 +arc: B5 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C5 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F7 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1010100010101010 +word: SLICEA.K1.INIT 0100010001001100 +word: SLICEC.K1.INIT 0101000001110000 +word: SLICEB.K0.INIT 0000000000010001 +word: SLICED.K1.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R41C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0601 +arc: D1 S1_V02N0201 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F6 +word: SLICED.K1.INIT 1000000010101010 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000010110101111 +word: SLICED.K0.INIT 1011001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R41C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0100 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 F5 +arc: B0 V02N0301 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 F3 +arc: C0 H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H00L0000 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0000 F0 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 V00B0000 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B2 N1_V02S0101 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 F4 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R41C96:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V01N0101 +arc: A0 H00L0100 +arc: A2 S1_V02N0501 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R41C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 N1_V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 N1_V01S0100 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R41C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 F4 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: D0 W1_H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C99:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 W1_H02E0301 +arc: B2 F1 +arc: B3 W1_H02E0101 +arc: B4 N1_V02S0701 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 V02S0001 +arc: C7 W1_H02E0401 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 V02N0301 +arc: B1 V02S0301 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V01S0000 +arc: C1 N1_V02S0601 +arc: C2 V02S0601 +arc: C3 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 V02N0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F1 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C101:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A2 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 V02N0301 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 F3 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: D6 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: V01S0000 F1 +arc: V01S0100 F5 +arc: W1_H02W0201 F2 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1101000001010000 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1100000000110000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C102:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 N1_V02S0301 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: B7 S1_V02N0701 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D1 H02W0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C103:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: B1 H02W0101 +arc: B2 F3 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C104:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 V02N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: C0 V02S0601 +arc: C2 F6 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: M0 H01E0001 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C105:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C4 F6 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: V00B0100 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C106:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02W0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: B0 H01W0100 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: C0 V02S0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: D0 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: N1_V01N0101 F5 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C107:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A3 F5 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D3 V01S0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0101 F0 +arc: N3_V06N0003 F3 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1011000000001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C108:PLC2 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B1 H02E0101 +arc: B4 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C4 V02S0001 +arc: C6 W1_H02E0401 +arc: C7 V02S0001 +arc: D1 V00B0100 +arc: D4 H02E0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F4 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C109:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V06N0303 +arc: A0 E1_H02W0501 +arc: B0 H01W0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C110:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N3_V06N0003 Q0 +arc: W1_H02W0001 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C111:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N1_V01S0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C112:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile R42C113:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 N1_V02S0701 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C114:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: W3_H06W0303 N3_V06S0303 + +.tile R42C115:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R42C18:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R42C19:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 + +.tile R42C20:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: A0 F7 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1010000011101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C21:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 E1_H02W0701 +arc: A1 V01N0101 +arc: A5 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C6 F4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R42C22:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B4 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F6 +arc: V01S0000 Q2 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R42C23:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H01W0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C3 W1_H02E0401 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F4 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICED.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C24:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 E1_H01E0001 +arc: A2 F7 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F4 +arc: N3_V06N0303 F5 +arc: V00T0000 Q2 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100010010000000 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1011001110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C25:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00L0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C26:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 V02S0501 +arc: A3 H02W0501 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H01W0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100101011001010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R42C27:PLC2 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0401 Q6 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1101010111000000 +word: SLICEC.K0.INIT 1010000011101100 +word: SLICEC.K1.INIT 1100000011101010 +word: SLICED.K0.INIT 1111001000100010 +word: SLICED.K1.INIT 1111001000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C28:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02S0601 +arc: A2 H02E0501 +arc: A4 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 V02S0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C29:PLC2 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 F7 +arc: A5 Q5 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C30:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: B0 V02N0101 +arc: C0 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0401 V02S0401 +arc: A1 N1_V02S0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C32:PLC2 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H02E0001 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: B0 V02S0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C33:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: B0 S1_V02N0101 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C34:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: A0 H00L0000 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H02W0401 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C35:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0601 E1_H02W0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEC.K1.INIT 0000000001011100 +word: SLICEB.K1.INIT 0001001100010000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 N1_V02S0501 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 F1 +arc: B5 N1_V02S0501 +arc: B6 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A6 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 V00B0000 +arc: B4 V02N0701 +arc: B6 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C4 V02N0201 +arc: C6 F4 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D4 F0 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICED.K0.INIT 0000000000101110 +word: SLICEA.K1.INIT 0000011100000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A5 N1_V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 V00B0000 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C5 V00B0100 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1000110010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R42C40:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A7 H02W0501 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C7 V01N0101 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 F0 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010100000001000 +word: SLICED.K1.INIT 0001000101010000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICEB.K0.INIT 0011000000110001 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C41:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 N1_V02S0501 +arc: A1 V01N0101 +arc: A2 H02E0701 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 H02E0701 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V02N0201 +arc: D1 F0 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F1 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICED.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1100101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A6 H02W0701 +arc: B0 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 H00L0100 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C43:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0601 V06S0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V06S0103 +arc: A1 H02W0501 +arc: A2 H02E0501 +arc: A4 V00T0100 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D4 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V02N0101 F1 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F7 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1011101100001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A3 E1_H01E0001 +arc: B3 V02S0101 +arc: C3 H02E0601 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: S1_V02S0301 F3 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C45:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 F7 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 H02W0501 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 F3 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V02N0701 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: N3_V06N0203 F4 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C46:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02E0701 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: E1_H01E0101 Q0 +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R42C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A5 H02W0501 +arc: B5 S1_V02N0701 +arc: C5 V00B0100 +arc: D5 H00R0100 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +word: SLICEC.K1.INIT 1110010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 N3_V06S0203 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: B1 V00B0000 +arc: B5 V02S0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R42C49:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A6 W1_H02E0501 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: C0 N1_V01N0001 +arc: C2 H00R0100 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0000010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R42C50:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A6 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B3 V02N0301 +arc: B6 V02S0501 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C3 H00L0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02W0001 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C51:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 E1_H02W0501 +arc: A4 V02S0101 +arc: B4 H02E0101 +arc: C1 H02W0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D4 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q6 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00T0000 F0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C52:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K0.INIT 1000110010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C53:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V02S0301 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B3 H01W0100 +arc: B5 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F4 +arc: N3_V06N0103 F2 +arc: V00B0100 F7 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R42C54:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0001000101010101 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C55:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H00R0100 +arc: B2 H01W0100 +arc: B5 F1 +arc: C0 H02W0601 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C5 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C56:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: B0 H00R0100 +arc: B1 H02E0301 +arc: B2 F1 +arc: B4 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D4 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0010011101110111 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 + +.tile R42C57:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 S1_V02N0501 +arc: A4 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +word: SLICEA.K0.INIT 0000111101000100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C58:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A6 N1_V01S0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B6 V02N0701 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 S1_V02N0601 +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F2 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEB.K1.INIT 1111011111010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C59:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A6 E1_H01W0000 +arc: B0 H00R0100 +arc: B6 V02S0501 +arc: C0 F6 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C60:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C5 V01N0101 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 1110001011111111 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R42C61:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H00L0100 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C2 V02N0401 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 H02E0201 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100100000001000 +word: SLICED.K1.INIT 1111101100111011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C62:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 E1_H02W0501 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D7 F0 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q5 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 F4 +arc: S3_V06S0203 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0010011100100010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R42C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B7 H01E0101 +arc: C0 F4 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0011001101011111 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B3 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V01S0100 +arc: D3 F0 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R42C65:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A3 H02E0701 +arc: A6 V02N0301 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B3 W1_H02E0101 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C66:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 H02E0701 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 V00B0000 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02W0601 +arc: C4 V01N0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 F0 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0000111100100010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0010001010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R42C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H01E0101 +arc: D3 S1_V02N0201 +arc: D6 S1_V02N0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R42C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 F5 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1011100001000111 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000001011110010 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 0000001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R42C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B3 S1_V02N0301 +arc: B6 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0201 +arc: D3 H00R0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 H02W0601 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEA.K0.INIT 0101111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R42C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: B0 H01W0100 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B5 H02E0301 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: D0 N1_V02S0001 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 F0 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +word: SLICEC.K1.INIT 0010001000001010 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEC.K0.INIT 0100011100000000 +word: SLICEA.K1.INIT 0100010001010000 +word: SLICEA.K0.INIT 0000001010001010 +word: SLICED.K0.INIT 0000000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 H01E0101 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 F0 +arc: D4 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1100000000000000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000010000000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0110011000111100 +word: SLICEC.K1.INIT 0000000011011000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C73:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 H02W0501 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: V01S0000 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001000000000001 +word: SLICEC.K1.INIT 0001000000000001 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C74:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A7 H00R0000 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 F3 +arc: B7 H02W0301 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 H01E0001 +arc: C7 H02E0401 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V01N0001 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F0 +arc: N1_V02N0701 F5 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +word: SLICEB.K1.INIT 0110011000111100 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C75:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A7 H02E0701 +arc: B0 V02N0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 H00R0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1100111110101111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0010011111011000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C76:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R42C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A6 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C6 V02N0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D6 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0000 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000010101100 +word: SLICEA.K0.INIT 0000000000100011 +word: SLICEA.K1.INIT 0010001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C78:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C79:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C80:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 H02E0301 +arc: B5 W1_H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 F6 +arc: C3 F6 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C81:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V02S0701 +arc: B6 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q5 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C82:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A4 W1_H02E0701 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 V02N0301 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C1 H00R0100 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K0.INIT 0010101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C83:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q4 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 F7 +arc: A6 V02S0301 +arc: A7 E1_H02W0501 +arc: B0 V01N0001 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C6 V02S0201 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0201 F0 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R42C85:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 H00R0000 +arc: B1 H02E0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 + +.tile R42C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B6 V00B0100 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 0100011100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W3_H06W0303 V01N0101 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0100 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 V02S0601 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0011010111111111 +word: SLICEA.K1.INIT 0011010100000000 +word: SLICED.K0.INIT 0011000001110000 +word: SLICEB.K0.INIT 0011000001110000 +word: SLICED.K1.INIT 1010101010001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C90:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A7 H00L0000 +arc: B7 H02W0301 +arc: C7 H02E0401 +arc: D7 V01N0001 +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICED.K1.INIT 1000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: A1 V02N0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B6 F1 +arc: B7 V02N0501 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 1101000001010000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICED.K0.INIT 1100100011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R42C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A4 V02S0101 +arc: A6 H00R0000 +arc: B4 V02N0501 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C4 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: D0 N1_V01S0000 +arc: D1 W1_H02E0001 +arc: D4 V01N0001 +arc: D6 F0 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000101001011111 +word: SLICED.K0.INIT 1000000010101010 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R42C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A4 E1_H02W0501 +arc: B1 H02E0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: D0 W1_H02E0001 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0001 +arc: D4 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0001000110111011 +word: SLICEB.K0.INIT 0101010111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R42C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 N1_V02S0701 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 N1_V02S0501 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 W1_H02E0201 +arc: D1 N1_V02S0201 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 V02N0601 +arc: C6 V00T0100 +arc: C7 V01N0101 +arc: D0 H02W0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0201 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: W1_H02W0101 F1 +word: SLICED.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K1.INIT 0011000001110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 V01N0101 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0001 +arc: D7 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R42C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 V02S0101 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 F3 +arc: B1 V02S0101 +arc: B2 F1 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 N1_V01N0001 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000001000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R42C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A3 V02N0701 +arc: A4 F7 +arc: A5 V00B0000 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 V02S0001 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 F0 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R42C99:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: N1_V01N0101 F0 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B6 V00B0100 +arc: B7 N1_V02S0501 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: V00T0100 F3 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICEA.K0.INIT 0111011101110111 +word: SLICEA.K1.INIT 0000101001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C101:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 H02E0701 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 F3 +arc: B5 W1_H02E0101 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: D0 E1_H02W0001 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +arc: V00T0000 F0 +arc: V01S0100 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C102:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0701 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000010111110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C103:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A2 V00B0000 +arc: A4 F5 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B2 H02E0301 +arc: B4 V01S0000 +arc: B5 W1_H02E0301 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C2 V02S0601 +arc: C4 V01N0101 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V00T0100 +arc: D4 F0 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C104:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 H02E0601 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 F0 +arc: D6 H01W0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C105:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B0 H02W0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 N1_V02S0201 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0001 F0 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C106:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: B0 H00R0100 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 F1 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C107:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A6 H00R0000 +arc: B0 V01N0001 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B6 F3 +arc: C0 H02E0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C6 H01E0001 +arc: D0 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C108:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 H06W0003 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H01W0100 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C109:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H06W0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H02W0701 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C110:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 V01N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C111:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E1_H01W0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 N3_V06S0303 + +.tile R43C112:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: A7 N1_V02S0101 +arc: C7 S1_V02N0001 +arc: D7 V00B0000 +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0000 F7 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1010111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C113:PLC2 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0103 +arc: A0 H02W0501 +arc: A1 V01N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1000100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C114:PLC2 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 + +.tile R43C115:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 + +.tile R43C20:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: V00B0100 V02S0101 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: C0 V02N0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V02N0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C21:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: A1 E1_H01E0001 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 H02E0401 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 Q4 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: LSR0 V00T0100 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: V00B0100 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1100000011101010 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICEB.K1.INIT 1100000011101010 +word: SLICEC.K0.INIT 1101110001010000 +word: SLICEC.K1.INIT 1100111000001010 +word: SLICED.K0.INIT 1100000011101010 +word: SLICED.K1.INIT 1010111000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C22:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: A2 H02W0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B3 E1_H01W0100 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 Q6 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C23:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 V01N0101 +arc: A0 V02S0501 +arc: A4 W1_H02E0501 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F6 +arc: W1_H02W0101 Q3 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000001000111 +word: SLICEC.K1.INIT 0000000011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C24:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: C0 H02E0601 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 F2 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C25:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: W1_H02W0601 V06N0303 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C26:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: B0 H02W0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 F6 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1000100011111000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101010111000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100000011101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C27:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: S1_V02S0001 H02E0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: A0 H02W0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C3 H00L0100 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 Q1 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: V01S0000 Q0 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C28:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: A5 V02N0101 +arc: B0 V00T0000 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00T0100 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C29:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0001 V02N0001 +arc: A1 N1_V02S0701 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C30:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: B0 H02E0101 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C31:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 V02N0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C32:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N3_V06S0303 +arc: A4 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C4 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D4 V02N0401 +arc: D7 V00B0000 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C33:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 V02S0701 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: B6 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C34:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: A7 H02E0701 +arc: B1 H00R0100 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000011100000010 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C35:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A3 V00T0000 +arc: A6 S1_V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C6 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 F0 +arc: D3 W1_H02E0201 +arc: D6 H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1010001010000000 +word: SLICEA.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 0001000000110010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C36:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 V00B0000 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C4 V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D4 H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0001 Q0 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEA.K0.INIT 0101000011111010 +word: SLICEA.K1.INIT 0100010011101110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C37:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S3_V06S0103 F1 +arc: V00T0000 Q0 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B4 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 F4 +arc: C2 V02N0601 +arc: C4 W1_H02E0601 +arc: C7 V02N0001 +arc: D0 F2 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D4 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F0 +arc: V00T0100 F1 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100001100000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000001011100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C39:PLC2 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0701 +arc: A2 N1_V02S0701 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A5 N1_V01S0100 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 F4 +arc: C7 V02S0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: V01S0000 F7 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEC.K0.INIT 0001001100010011 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000000101110 +word: SLICEC.K1.INIT 0100010001000101 +word: SLICED.K1.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C40:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 F4 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000001000110010 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000000011001101 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H01E0001 +arc: A2 V00B0000 +arc: A3 V02N0701 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B4 V02N0501 +arc: B6 V00B0100 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: D0 V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02E0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: V00T0000 F0 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R43C42:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H02W0501 +arc: B0 V00B0000 +arc: B1 F3 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F1 +arc: V00B0000 F6 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: A1 S1_V02N0701 +arc: A3 N1_V02S0701 +arc: A6 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0100 +arc: B6 V02N0501 +arc: C1 F6 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C6 H02E0401 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D6 H00L0100 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F3 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C44:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: C1 F6 +arc: C2 N1_V02S0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: D1 F2 +arc: D2 H02E0001 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N3_V06N0103 F1 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C45:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0701 +arc: A5 E1_H01W0000 +arc: A6 N1_V02S0101 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V02N0701 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F2 +arc: N3_V06N0003 F3 +arc: S3_V06S0303 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1100010010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 S1_V02N0501 +arc: A3 S1_V02N0701 +arc: B1 V02S0101 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0501 Q7 +arc: S3_V06S0203 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C47:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 S1_V02N0701 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D5 H02W0201 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: S3_V06S0303 Q5 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 F1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R43C49:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 H02W0501 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 V02N0501 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R43C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02W0701 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: C1 V02N0601 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: M0 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C51:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V01N0001 + +.tile R43C52:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 S1_V02N0101 +arc: B3 N1_V02S0301 +arc: B5 F1 +arc: C0 V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 1011101110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R43C53:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 S1_V02N0501 +arc: A7 V00T0100 +arc: B0 F3 +arc: B3 H02W0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C3 H00R0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1010000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 H02W0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0501 +arc: A4 E1_H01W0000 +arc: A6 W1_H02E0501 +arc: B1 V02S0101 +arc: B4 V02S0501 +arc: B6 V00T0000 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C4 V00T0100 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D4 E1_H01W0100 +arc: D6 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0000000100010001 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C55:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F1 +arc: V01S0100 F6 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 1101000001010000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C56:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 E1_H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A0 H02E0501 +arc: A2 H02W0501 +arc: A3 V00B0000 +arc: A5 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 H02W0101 +arc: B6 V01S0000 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 W1_H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: M4 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F6 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R43C58:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B3 H00R0000 +arc: B7 N1_V02S0501 +arc: C0 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C59:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A6 V00T0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B3 V02S0101 +arc: B6 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 W1_H02E0601 +arc: C3 H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D6 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEA.K1.INIT 1110001010101010 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 0101001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 Q1 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0100011101000100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C61:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: B4 S1_V02N0501 +arc: C1 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: M0 V00B0100 +arc: M3 H02W0201 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C62:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 F7 +arc: A3 H02E0701 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICED.K1.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C63:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B5 E1_H02W0301 +arc: C5 H02E0401 +arc: D5 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C64:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F7 +arc: A2 V02S0501 +arc: A4 H02E0501 +arc: A6 W1_H02E0701 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B6 V02S0701 +arc: B7 V01S0000 +arc: C1 E1_H02W0601 +arc: C2 F4 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C65:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V01N0101 +arc: A5 H02W0701 +arc: B0 H02W0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C5 V02N0001 +arc: D0 H00R0000 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F0 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0011001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A1 H02W0701 +arc: A2 F7 +arc: A3 F7 +arc: A7 H02W0501 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000001011111 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A4 H02W0501 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M2 V00B0100 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C68:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A4 H02W0701 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 F1 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 F1 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0601 F4 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0001000010111010 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B6 V02S0501 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02S0201 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0201 F2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R43C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 H06E0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: B0 V02S0301 +arc: B1 V02N0101 +arc: B3 F1 +arc: B4 H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: D0 N1_V02S0201 +arc: D1 V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F3 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000011001010 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICEB.K1.INIT 0001000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0501 +arc: A1 W1_H02E0501 +arc: A3 E1_H02W0501 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 H02E0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C3 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 F0 +arc: D3 V02N0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F7 +word: SLICEA.K1.INIT 0000000000000010 +word: SLICEB.K1.INIT 0011000001010000 +word: SLICEA.K0.INIT 0000000010101100 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R43C73:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C4 E1_H02W0601 +arc: C6 H02W0401 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D4 S1_V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0100010000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0501 +arc: A7 W1_H02E0701 +arc: B0 H02W0301 +arc: C0 E1_H01W0000 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111001111110101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C75:PLC2 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B5 S1_V02N0701 +arc: C2 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: S1_V02S0001 F2 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R43C76:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R43C77:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 + +.tile R43C78:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 + +.tile R43C79:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0101 +arc: C0 H02E0401 +arc: C2 H00R0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C80:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R43C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A5 V00B0000 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02S0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEC.K1.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R43C82:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02S0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V01N0101 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B1 H01W0100 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 H02E0101 +arc: C1 W1_H02E0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D1 W1_H02E0001 +arc: D2 V02S0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0201 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C83:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 F3 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B1 E1_H01W0100 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 F3 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 F4 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C85:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C86:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02W0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R43C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A6 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R43C88:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H01E0001 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B3 H00R0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 E1_H02W0001 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 0100010001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R43C89:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: B2 V02N0101 +arc: C2 S1_V02N0601 +arc: D2 V00B0100 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEB.K0.INIT 0000110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R43C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A6 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 H00R0000 +arc: B6 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: C6 V02N0001 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D6 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +word: SLICED.K0.INIT 0001000100010011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R43C91:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 V02S0501 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0301 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 F2 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +word: SLICEC.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1000000011110000 +word: SLICED.K1.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R43C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R43C93:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000011100000000 +word: SLICEA.K1.INIT 1011111110101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A1 F5 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D0 H02E0001 +arc: D1 W1_H02E0001 +arc: D2 H02E0201 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F1 +arc: S1_V02S0101 F3 +arc: V00T0000 F2 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 F5 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H00L0100 +arc: C2 F6 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: M0 V00T0100 +arc: V00B0100 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0011000000111111 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R43C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: A1 V01N0101 +arc: A2 W1_H02E0701 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H02W0701 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1011000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R43C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 H01E0101 +arc: A1 H02E0501 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B1 V02N0101 +arc: B3 F1 +arc: B4 V01S0000 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C1 H02E0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C98:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02E0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H02E0101 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: D0 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R43C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 H02E0701 +arc: A3 F7 +arc: A4 F5 +arc: A5 H02W0501 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: S1_V02S0301 F3 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R44C100:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 E1_H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A4 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: D0 V02N0201 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02W0601 +arc: M2 V00T0100 +arc: N1_V02N0001 F0 +arc: W1_H02W0001 F2 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R44C101:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0100 +arc: A7 V02N0301 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 F4 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C7 V02S0001 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: N1_V01N0101 F7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101000001011111 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C102:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A1 H00R0000 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 N1_V02S0701 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 F4 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 F0 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: S1_V02S0101 F1 +arc: V01S0100 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C103:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 F1 +arc: B7 V00B0100 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V02S0201 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0001 +arc: D6 H02E0001 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0101 F6 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 N1_V02S0701 +arc: A3 V00T0000 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F1 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C105:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V01N0101 +arc: A3 E1_H02W0701 +arc: B3 H00R0100 +arc: C3 S1_V02N0401 +arc: D3 E1_H02W0201 +arc: F3 F3_SLICE +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C106:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F7 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C107:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C6 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C108:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 H02E0101 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0201 +arc: D4 F0 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C109:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00T0000 +arc: A5 Q5 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C110:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0103 V06N0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 V01N0101 +arc: S1_V02S0301 H02W0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q6 +arc: N1_V02N0701 Q7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C111:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 N3_V06S0003 +arc: B4 E1_H02W0101 +arc: C4 H02W0401 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: F4 F4_SLICE +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1100000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R44C112:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A6 E1_H01W0000 +arc: C6 V02N0001 +arc: D6 S1_V02N0401 +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R44C113:PLC2 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: W1_H02W0101 N1_V01S0100 +arc: A0 H00L0000 +arc: B0 H02E0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 V06N0003 + +.tile R44C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R44C17:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R44C19:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 + +.tile R44C20:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: A0 F5 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 V00B0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C21:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: A6 W1_H02E0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R44C22:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V06S0303 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A4 F7 +arc: A7 N1_V02S0101 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B6 E1_H02W0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 H02E0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 0000000100110001 +word: SLICED.K0.INIT 0000111100001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0001000100000011 +word: SLICEC.K0.INIT 0000111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R44C23:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A4 N1_V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q3 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C24:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 F7 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: C0 H02E0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D7 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 Q3 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000100011111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C25:PLC2 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 E1_H02W0401 +arc: A6 S1_V02N0101 +arc: B0 V00B0000 +arc: B6 V02N0701 +arc: C0 E1_H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0101001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C26:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0203 V01N0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R44C27:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02E0601 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A6 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B6 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0010000000101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C28:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: A2 N1_V02S0701 +arc: A4 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D4 V01N0001 +arc: D5 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0100000001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: B0 S1_V02N0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C30:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 W1_H02E0701 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02N0401 +arc: B0 S1_V02N0301 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C32:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 V06N0303 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 H01E0001 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 H02W0301 +arc: B2 F1 +arc: B3 H00L0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 N1_V01S0100 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICED.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C33:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A1 F7 +arc: A5 N1_V02S0301 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02S0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A3 F7 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 S1_V02N0101 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0601 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0001001100010000 +word: SLICEA.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 0101000001010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 V02S0501 +arc: C0 N1_V02S0601 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: D0 V02N0201 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +word: SLICEC.K1.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C36:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02S0501 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: A5 V02S0301 +arc: A6 W1_H02E0501 +arc: B0 W1_H02E0101 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 F0 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000000001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C37:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A2 H02E0501 +arc: B0 S1_V02N0101 +arc: B2 V02N0101 +arc: B5 E1_H02W0301 +arc: C0 V02N0401 +arc: C2 S1_V02N0401 +arc: C5 H02E0601 +arc: D0 V02N0201 +arc: D2 V02N0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: S1_V02S0201 F2 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEB.K0.INIT 1010110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C38:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00T0100 H02W0101 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 E1_H02W0701 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 N1_V02S0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICED.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K1.INIT 0100010001000101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C39:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B2 W1_H02E0301 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D2 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0601 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K1.INIT 0000000000111010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICED.K0.INIT 1010001010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C40:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: D2 V02S0201 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V00T0000 F0 +arc: V01S0000 F1 +word: SLICEC.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1101000010000000 +word: SLICEB.K0.INIT 0001010100010000 +word: SLICED.K1.INIT 0000010101000100 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0010001000100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C41:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C2 E1_H02W0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: D0 V02S0001 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F3 +arc: S3_V06S0203 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1010110010101100 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICEA.K0.INIT 0000000000111010 +word: SLICEC.K0.INIT 0011001100000001 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C42:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 V02S0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 N1_V02S0101 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 F3 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1110010000000000 +word: SLICEC.K0.INIT 0101000001010001 +word: SLICEA.K1.INIT 1000100011000000 +word: SLICEC.K1.INIT 0000000001011111 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0010001000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 F5 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: N1_V01N0001 F5 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000010101000100 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0203 V06S0203 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 F5 +arc: A4 E1_H01W0000 +arc: A5 E1_H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: M0 V00B0000 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V01N0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A7 Q7 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: C1 H02W0601 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 V02N0301 +arc: B5 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0100 +arc: C6 H01E0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0100 F0 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100010010000000 +word: SLICED.K0.INIT 0000111101110111 +word: SLICED.K1.INIT 1010001010000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 W1_H02E0501 +arc: A7 H00R0000 +arc: B1 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R44C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 V06N0203 +arc: A2 H02E0501 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B5 V02N0701 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C6 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 N1_V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0100 F7 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0011001101010000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R44C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02S0301 +arc: A5 H02E0501 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0100 F0 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C50:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0501 +arc: A5 H02E0701 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02E0101 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 F6 +arc: C3 N1_V02S0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C51:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H02E0501 +arc: A2 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H01E0101 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q3 +arc: M3 H00R0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 Q7 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0001001111011111 +word: SLICEA.K1.INIT 1110000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C52:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 H02W0101 +arc: C1 H02W0401 +arc: C3 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V02S0401 +arc: D7 H00L0100 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q6 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 N1_V01N0101 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 Q1 +arc: S3_V06S0303 Q6 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0001101101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0001 +arc: D3 V01S0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1110010011101110 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100100001000000 +word: SLICED.K1.INIT 1111101101110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: B0 H00R0100 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0101 +arc: C0 F6 +arc: C1 F6 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 0001000011011100 +word: SLICEA.K1.INIT 0101000011111010 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C55:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 F5 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: B4 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 V00B0100 +arc: C0 F6 +arc: C1 H02E0401 +arc: C4 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: B0 V00T0000 +arc: B4 E1_H02W0301 +arc: C0 H02W0401 +arc: C2 H00R0100 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 V02N0201 +arc: D4 H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1100101010101010 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R44C57:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 E1_H02W0701 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A6 H00L0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C1 V02S0401 +arc: C2 V02S0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D4 F2 +arc: D5 V02S0601 +arc: D6 H02E0001 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: V01S0000 F0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R44C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0100 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A6 V02N0101 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A6 N1_V02S0301 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C1 H02E0401 +arc: C3 S1_V02N0601 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D6 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 F7 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0001 F2 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1011000010000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R44C60:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00R0000 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: B0 V01N0001 +arc: B2 S1_V02N0101 +arc: B4 H01E0101 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F4 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEC.K0.INIT 0001001100010011 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0000 +arc: A3 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: B0 F3 +arc: B1 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B6 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 H00R0100 +arc: C5 H02W0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 V02N0201 +arc: D5 N1_V02S0401 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 1100100001000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R44C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: B1 V02S0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0203 F4 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 0101010100110000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110111000100010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C63:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V02N0701 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1101100000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00T0100 V02N0701 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 V06N0203 +arc: A0 E1_H02W0701 +arc: A1 H02E0701 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 F1 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V00T0000 F2 +arc: W3_H06W0303 Q6 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1011100011110000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R44C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A6 N1_V02S0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B6 H02W0101 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C6 H02E0401 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D6 H00R0100 +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 V00B0100 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICEB.K1.INIT 1011111110001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0100 +arc: B3 E1_H02W0101 +arc: B5 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 N1_V01N0001 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V01S0000 F4 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C67:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A5 V02S0101 +arc: A7 H02E0501 +arc: B5 H00R0000 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C5 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 N1_V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K1.INIT 1000100011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 V00B0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D5 H00R0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: V01S0000 F1 +word: SLICEC.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R44C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100100000001000 +word: SLICEC.K1.INIT 1111101100111011 +word: SLICED.K0.INIT 1000110010000000 +word: SLICED.K1.INIT 1011111110110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R44C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 V00T0000 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 N1_V02S0001 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: V01S0100 F3 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000101001011111 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 1111101101110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C71:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 N1_V02S0501 +arc: B5 V00B0100 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101111111010101 +word: SLICEC.K1.INIT 0000000000001001 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 0101010000010000 +word: SLICEB.K0.INIT 0101010000010000 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEC.K0.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 V06N0303 +arc: A0 F5 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 H01W0100 +arc: B2 N1_V02S0301 +arc: B4 W1_H02E0101 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C2 H02W0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000001000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R44C73:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 S1_V02N0701 +arc: A3 F5 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0101 +arc: B3 F1 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F6 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1100001110011001 +word: SLICEA.K0.INIT 0110011000111100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C74:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V01N0101 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 N1_V02S0501 +arc: A5 S1_V02N0101 +arc: A6 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B4 H00R0000 +arc: B5 H01E0101 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C4 H01E0001 +arc: C5 F4 +arc: C6 V02N0201 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02W0001 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R44C75:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 F5 +arc: A3 F5 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: B0 V00T0000 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: D0 V02S0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 F0 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101000000110000 +word: SLICEB.K0.INIT 0000000010100101 +word: SLICEB.K1.INIT 0000100000000100 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C76:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R44C77:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 S3_V06N0303 + +.tile R44C78:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 E1_H02W0501 + +.tile R44C79:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C80:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 H02W0501 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0100 F7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C81:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 E1_H02W0501 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V01N0001 +arc: B2 V02N0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C82:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00B0100 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: S1_V02S0401 Q6 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C83:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 F5 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: C0 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 H02E0601 +arc: N1_V01N0001 F3 +arc: V01S0000 F7 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1010000001010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R44C84:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02E0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: A0 H02W0701 +arc: A4 V00T0100 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B4 H02W0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C4 H02W0401 +arc: C7 H02W0601 +arc: D0 E1_H02W0201 +arc: D4 H00L0100 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: S1_V02S0001 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R44C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V01N0001 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 W1_H02E0101 +arc: B2 F1 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 F4 +arc: D0 V02S0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0100 +arc: A7 V02S0101 +arc: B0 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D6 F0 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F7 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1100001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R44C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R44C88:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: B2 V02S0301 +arc: B4 V02N0701 +arc: C2 E1_H02W0601 +arc: C4 H02W0401 +arc: D2 V02N0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000110001001100 +word: SLICEB.K0.INIT 1010100010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R44C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0401 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C4 V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEA.K0.INIT 0000000001001100 +word: SLICEA.K1.INIT 1111111101001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: N1_V01N0101 F0 +arc: V01S0000 F6 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 0001010100000000 +word: SLICEA.K1.INIT 1011111110101010 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0001000110111011 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0000010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R44C91:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 H02W0701 +arc: A3 H02E0501 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V00T0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: V00T0000 F2 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0011001101010101 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEC.K0.INIT 0001001100000000 +word: SLICEC.K1.INIT 1101111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R44C92:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0701 +arc: A1 W1_H02E0701 +arc: A4 F5 +arc: A5 F7 +arc: A7 H02W0501 +arc: B2 V02N0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B7 H02W0101 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V01N0101 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1100010001000100 +word: SLICEC.K1.INIT 0000000000010001 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEC.K0.INIT 0101000001110000 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R44C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A4 V00T0100 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 V00T0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICED.K1.INIT 0111011100000000 +word: SLICEA.K0.INIT 0011001111111111 +word: SLICEA.K1.INIT 0000010110101111 +word: SLICED.K0.INIT 1000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R44C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 H02W0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R44C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0501 +arc: A2 V02N0501 +arc: A3 F5 +arc: A5 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 N1_V01N0001 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D1 H01E0101 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0101000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R44C96:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0000 +arc: D0 S1_V02N0001 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D3 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: V00B0100 F5 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000110000111111 +word: SLICEC.K1.INIT 0011000011110000 +word: SLICEB.K0.INIT 0000010001000100 +word: SLICEB.K1.INIT 1010111011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R44C97:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 F2 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000010000001100 +word: SLICEA.K1.INIT 1111010011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R44C98:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A4 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B1 W1_H02E0101 +arc: B2 H00R0000 +arc: B4 N1_V02S0501 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C2 V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C7 H02E0601 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 V02N0601 +arc: D5 V01N0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F7 +arc: S3_V06S0203 F4 +arc: W3_H06W0003 F0 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0011111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R44C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 V01N0101 +arc: A3 W1_H02E0701 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 F4 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D3 N1_V02S0201 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: S3_V06S0103 F2 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100111111 +word: SLICEA.K1.INIT 0000110000111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 H02W0501 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B1 H02W0101 +arc: B2 H00R0100 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V02N0001 F0 +arc: S1_V02S0601 F6 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000111100110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 H02E0501 +arc: A4 N1_V02S0101 +arc: A6 F5 +arc: A7 H02W0501 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 F1 +arc: B7 V02S0701 +arc: C0 W1_H02E0401 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100000000110000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C102:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A1 S1_V02N0701 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 H01W0100 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0100 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C103:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C5 V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D5 E1_H01W0100 +arc: D6 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C104:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: A3 V00B0000 +arc: A6 S1_V02N0301 +arc: B3 H02E0101 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C3 W1_H02E0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 V00T0100 +arc: D6 H00R0100 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C105:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 W1_H02E0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C106:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 V00B0000 +arc: A5 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C107:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H01E0101 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C108:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V00T0000 +arc: A5 Q5 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 V02S0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C109:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C110:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A5 Q5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C2 H00L0000 +arc: C4 H02W0601 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: V00B0000 Q6 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C111:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 + +.tile R45C112:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 + +.tile R45C113:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 N3_V06S0003 + +.tile R45C114:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 + +.tile R45C20:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 + +.tile R45C21:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 + +.tile R45C22:PLC2 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02W0401 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 H02W0101 +arc: A4 N1_V01N0101 +arc: A5 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 E1_H01W0100 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 F7 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C23:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N3_V06S0203 +arc: A6 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 N1_V02S0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R45C24:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 V02N0501 +arc: B0 V00B0000 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C25:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H01E0001 +arc: A0 V02S0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C26:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: C2 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C27:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0601 V02S0601 +arc: B0 V00B0000 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C28:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 V06N0303 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D5 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R45C29:PLC2 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: B0 V02N0101 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C30:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 V02N0301 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C31:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: V00B0000 H02W0401 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 F7 +arc: A4 V02N0101 +arc: A6 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0100 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C6 F4 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 V02N0601 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K0.INIT 0001000101010000 +word: SLICED.K0.INIT 0100010001000101 +word: SLICEA.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C33:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 F7 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0000111100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C34:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: A1 H01E0001 +arc: A4 S1_V02N0301 +arc: A5 V02S0101 +arc: A6 V02N0301 +arc: B0 H02E0301 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C2 F4 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C35:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A2 H01E0001 +arc: A4 V02S0101 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V02S0501 +arc: B6 V02S0501 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C36:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 N1_V01S0100 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: S1_V02S0001 F2 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C37:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: A0 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 W1_H02E0701 +arc: A5 F7 +arc: A7 H02W0501 +arc: B1 H02W0301 +arc: B2 F1 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C2 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D5 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 0001001100000010 +word: SLICED.K1.INIT 0000001100100010 +word: SLICEC.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C38:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: A0 N1_V02S0501 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: A7 V02N0301 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 N1_V01S0000 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C7 E1_H01E0101 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F4 +arc: S1_V02S0001 F2 +arc: V00T0000 F0 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0001001100000010 +word: SLICEA.K0.INIT 0000001100001010 +word: SLICEC.K0.INIT 0011000000110001 +word: SLICEB.K0.INIT 0000000011001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C39:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A1 S1_V02N0501 +arc: A4 F5 +arc: A6 N1_V02S0301 +arc: B0 H02W0301 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C4 H02W0401 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0001 +arc: D4 V02N0401 +arc: D5 V02S0601 +arc: D6 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V01S0100 F1 +arc: W3_H06W0203 F4 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEA.K1.INIT 1100000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R45C40:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 V02S0501 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 F4 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0100 F3 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000000101110 +word: SLICEB.K1.INIT 0000010101000100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 0011000000110001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C41:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A5 F7 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000001011100 +word: SLICEC.K1.INIT 0000000011110001 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C42:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A1 F5 +arc: A2 V00B0000 +arc: A4 H02W0501 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A4 V02N0301 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 S1_V02N0601 +arc: C4 H01E0001 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 F2 +arc: D5 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1000101011001111 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C44:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0101 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H00L0000 +arc: A3 V02N0501 +arc: A5 N1_V02S0301 +arc: A7 S1_V02N0101 +arc: B1 H02E0301 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 W1_H02E0301 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: D1 V00T0100 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 F3 +arc: V01S0000 F1 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C45:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A5 S1_V02N0101 +arc: A7 N1_V02S0101 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C5 E1_H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D5 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 F7 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M1 H02W0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1000100010100000 +word: SLICED.K1.INIT 1110010000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C46:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0501 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F7 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICED.K1.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 E1_H02W0501 +arc: A4 F7 +arc: A5 F7 +arc: A6 H02W0701 +arc: B0 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B7 E1_H02W0101 +arc: C1 V02S0601 +arc: C3 N1_V01S0100 +arc: C4 F6 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q5 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S3_V06S0203 F4 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000111100100010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R45C48:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C3 H02E0401 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 Q3 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C49:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0401 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0101010100111111 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C50:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C5 N1_V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 S1_V02N0201 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F6 +arc: V01S0100 Q7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C51:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A4 V02S0101 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C5 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1110001011101110 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C52:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0601 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: V00B0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0101001101010000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 1110001011101110 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C53:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B3 F1 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 F4 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R45C54:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A5 H02W0501 +arc: A7 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 F1 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C55:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 W1_H02E0101 +arc: B3 H02E0301 +arc: B7 V01S0000 +arc: C0 W1_H02E0401 +arc: C1 H00L0100 +arc: C3 H02E0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0201 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110001010101010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000000000111111 +word: SLICED.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C56:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F7 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B1 E1_H02W0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: V01S0000 Q6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 1101100011011000 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEC.K1.INIT 1110001011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C57:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0100 +arc: B2 H00R0100 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: C2 V02N0601 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: M2 H02W0601 +arc: N1_V01N0001 F4 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1010000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 0100010011001100 +word: SLICEC.K1.INIT 0001000101010101 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 E1_H02W0501 +arc: A5 V02N0301 +arc: B0 V02S0301 +arc: B7 V02S0501 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C60:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 N1_V02S0301 +arc: A7 E1_H02W0701 +arc: B1 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B7 H02W0301 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 F0 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1110111101001111 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0011001101011111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C61:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A3 V00B0000 +arc: A6 V00T0100 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: C1 H02W0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A2 W1_H02E0701 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B5 H02E0101 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 F6 +arc: C2 V02N0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0011111100001100 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R45C63:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: C3 W1_H02E0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K1.INIT 0000000000111111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: A6 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 E1_H01W0100 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0303 F6 +arc: V01S0100 Q7 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0011001101010000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 0011001101010000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000001100001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C65:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: B0 H01W0100 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1110001000000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICED.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R45C66:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A6 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 V02S0101 +arc: C0 F6 +arc: C3 H00L0100 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 1010000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R45C67:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: B0 H02E0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C68:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02S0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: B0 W1_H02E0101 +arc: B2 H02E0301 +arc: C0 E1_H02W0601 +arc: C2 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: D0 V02N0001 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F3 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000101001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 S1_V02N0701 +arc: A3 H01E0001 +arc: A4 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B3 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N1_V01N0001 F0 +arc: V00B0100 F7 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0000111101010101 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0010001000110000 +word: SLICEB.K1.INIT 0000001000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C71:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 W1_H02E0601 +arc: M2 V00T0000 +arc: N1_V01N0001 F0 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 0000000000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C72:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 F5 +arc: A4 H02E0701 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B4 F3 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C4 H01E0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: S1_V02S0201 F0 +arc: W1_H02W0001 F2 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010010110011001 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R45C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0401 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: D0 F2 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: S1_V02S0701 F5 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 0110011000111100 +word: SLICEA.K0.INIT 0000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 F5 +arc: B0 V02S0301 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B5 E1_H02W0301 +arc: B7 V02N0701 +arc: C0 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 F6 +arc: C6 V02S0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: M0 V00B0000 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C75:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H00L0100 +arc: A6 E1_H01W0000 +arc: B1 H02E0101 +arc: B3 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: C1 W1_H02E0401 +arc: C3 H02W0601 +arc: C6 S1_V02N0201 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D6 H02W0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A5 H02W0501 +arc: A6 E1_H01W0000 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 V00B0100 +arc: D1 V00T0100 +arc: D2 F0 +arc: D5 W1_H02E0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000100000000000 +word: SLICEB.K0.INIT 0111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R45C77:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 V02N0701 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: S1_V02S0001 F0 +arc: V00T0100 F3 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C78:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: B2 H00R0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C79:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 N1_V02S0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C80:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: C0 H02W0601 +arc: C1 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1110010001000100 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEC.K0.INIT 1011101100000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R45C81:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R45C82:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 V00B0000 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 F3 +arc: B2 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F4 +arc: N1_V02N0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1010000011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R45C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H01W0100 +arc: B3 F1 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 H00L0100 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 S1_V02N0001 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00T0000 F2 +arc: W1_H02W0301 F3 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 V02N0501 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R45C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02W0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 + +.tile R45C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: A0 H02W0501 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C3 F4 +arc: C4 H02E0601 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D3 F0 +arc: D4 H00L0100 +arc: D6 V02S0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R45C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06N0303 +arc: A0 H01E0001 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F0 +arc: V01S0100 F0 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R45C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 + +.tile R45C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 W1_H02E0301 +arc: A1 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C4 V02N0001 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: V01S0100 F4 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 0000101010101010 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C92:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 N1_V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 W1_H02E0601 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 0101111100000000 +word: SLICEA.K0.INIT 0101111101011111 +word: SLICEA.K1.INIT 0000001111110011 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEB.K0.INIT 0000001000001010 +word: SLICEB.K1.INIT 1111001011111010 +word: SLICEC.K0.INIT 0101010111111111 +word: SLICEC.K1.INIT 0011001101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R45C93:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 H01E0001 +arc: A2 S1_V02N0701 +arc: A3 H02W0701 +arc: A5 N1_V01S0100 +arc: A6 W1_H02E0701 +arc: B1 E1_H02W0101 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B5 F3 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 F6 +arc: C6 V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 F2 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0011001100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R45C94:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 F4 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R45C95:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 S3_V06N0303 +arc: A5 V00B0000 +arc: B0 E1_H01W0100 +arc: B3 H00R0000 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R45C96:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 F1 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 V02N0701 +arc: B5 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 H00L0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 F6 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C97:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 F3 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 F2 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V02N0601 F4 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R45C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A2 F5 +arc: A5 E1_H02W0701 +arc: A7 V02N0101 +arc: B2 V02S0101 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C5 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: S1_V02S0001 F2 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0000111101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R45C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 H02W0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 H00L0000 +arc: B4 F3 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 N1_V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C100:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 F7 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 W1_H02E0601 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 H02E0201 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100000000110000 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C101:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 H02E0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 F3 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S3_V06S0203 F4 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C102:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R47C103:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02W0301 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 F3 +arc: B3 H02W0101 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: C1 H02E0601 +arc: C2 F6 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00T0000 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C104:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F7 +arc: S3_V06S0103 Q1 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1110010011100100 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000001110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R47C105:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02E0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A4 E1_H02W0501 +arc: A5 Q5 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F6 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C106:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B4 F1 +arc: B6 V02S0501 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 F2 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F7 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C107:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V01S0000 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q4 +arc: V01S0000 F7 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000010010000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R47C108:PLC2 +arc: E1_H02E0001 V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B6 H02W0301 +arc: C0 F6 +arc: C1 V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R47C109:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 V01N0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C110:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: B0 N1_V02S0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B5 H02E0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: S3_V06S0003 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R47C111:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0401 S3_V06N0203 + +.tile R47C112:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R47C113:PLC2 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R47C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R47C116:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C117:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C118:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R47C14:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R47C15:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C20:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R47C21:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 + +.tile R47C23:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C24:PLC2 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 V02N0401 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C25:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C26:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C27:PLC2 +arc: E1_H02E0401 V06S0203 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: A3 H01E0001 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 H00L0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F3 +arc: V00T0100 Q1 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R47C28:PLC2 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: B0 V02N0301 +arc: B1 V02S0101 +arc: B2 V02N0301 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C29:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: W1_H02W0401 E1_H01W0000 + +.tile R47C30:PLC2 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 N1_V02S0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02E0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: B0 V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C31:PLC2 +arc: E1_H02E0401 V06N0203 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 + +.tile R47C32:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 E1_H01W0100 +arc: A0 V02N0701 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C33:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H02W0501 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEC.K1.INIT 0000010101000100 +word: SLICEB.K1.INIT 0000010000001110 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEB.K0.INIT 0000111100000001 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 F5 +arc: B1 H01W0100 +arc: B2 H00R0000 +arc: B3 F1 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 V02S0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 F2 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V00T0100 F3 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000000001001110 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICED.K0.INIT 0000101000001011 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C35:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A2 V02S0501 +arc: A3 F7 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 F6 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C36:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: A0 H02W0701 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B2 F1 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V02S0701 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C37:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 V02S0401 +arc: A0 H01E0001 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 N1_V02S0001 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 F0 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 0000110000001101 +word: SLICED.K0.INIT 0000000011001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C38:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H02E0701 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: V01S0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100010010000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 0000010100001111 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 0001010100010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C39:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 N3_V06S0203 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 0000001100001010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R47C40:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 V06S0103 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A6 F7 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: D4 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V01S0100 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000001100001111 +word: SLICED.K1.INIT 0000001000001110 +word: SLICEB.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 0010001000100011 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K0.INIT 0000110000001101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 V06S0103 +arc: A1 S1_V02N0501 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B7 F1 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D6 H02W0201 +arc: D7 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000101000001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C42:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A3 N1_V02S0501 +arc: A6 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F4 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0101110001011100 +word: SLICEB.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C43:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A3 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 F1 +arc: B1 H00R0100 +arc: B3 V02N0101 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 F6 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V02N0501 Q5 +arc: S1_V02S0601 Q6 +arc: V00T0000 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1010000010001000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K1.INIT 0000000001001110 +word: SLICEA.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A6 E1_H01W0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 V00B0000 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F5 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0100011101110111 +word: SLICEA.K1.INIT 1010111111001100 +word: SLICEC.K0.INIT 1010110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C45:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02E0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 Q1 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICED.K1.INIT 1110010000000000 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C46:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: A3 V00B0000 +arc: A5 E1_H02W0501 +arc: A7 E1_H01W0000 +arc: B1 V02N0101 +arc: C1 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C47:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 H02W0301 +arc: B3 V02S0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R47C48:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H01E0001 +arc: A4 H02E0501 +arc: A6 S1_V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 V01N0001 +arc: B5 H01E0101 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C3 V02N0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0001000010111010 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F5 +arc: A5 V00T0100 +arc: A7 W1_H02E0701 +arc: B1 S1_V02N0101 +arc: B4 W1_H02E0301 +arc: B7 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0701 F5 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R47C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0701 +arc: A3 S1_V02N0501 +arc: A5 E1_H02W0701 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V00B0000 F4 +arc: V01S0100 Q2 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1011100010111000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A3 N1_V02S0501 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 S1_V02N0401 +arc: C3 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEC.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C52:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 V01N0101 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 F1 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 V02S0401 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1110101000101010 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111010111011101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C53:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A3 V02N0701 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B5 N1_V02S0501 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A5 W1_H02E0701 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 H02E0601 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEA.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 1011000010000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 0000111101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 V01N0001 +arc: H00L0000 V02S0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 V01N0101 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 H00R0100 +arc: B1 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C1 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 Q4 +arc: V01S0100 F4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1011101111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B3 H02E0301 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C3 N1_V01N0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K1.INIT 1101100000000000 +word: SLICED.K0.INIT 0011001101011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R47C58:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: B0 E1_H02W0301 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C4 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 V02S0401 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R47C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V00B0000 +arc: A5 W1_H02E0501 +arc: A7 Q7 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: M2 E1_H02W0601 +arc: M4 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEB.K1.INIT 1111011111010101 +word: SLICEC.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICED.K1.INIT 1110001011100010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C60:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N3_V06N0003 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1110110001001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1011111110110011 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R47C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02W0101 +arc: B4 W1_H02E0301 +arc: B6 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C6 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D6 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1110001011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00T0000 +arc: A5 H02W0701 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 W1_H02E0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: V00T0000 F0 +arc: V01S0000 Q7 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C63:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0101 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 H02W0001 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R47C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A3 W1_H02E0501 +arc: A5 F7 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C5 V02S0201 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +arc: V01S0100 Q1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R47C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 H00L0100 +arc: A6 H02W0501 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C2 H02W0601 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D6 H00L0100 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C66:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F1 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00R0000 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 N1_V02S0401 +arc: C2 H02E0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 H01E0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 F5 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B4 V02S0501 +arc: B5 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F4 +arc: C4 V02S0001 +arc: C5 W1_H02E0601 +arc: C6 N1_V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C69:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: N1_V02N0201 F2 +arc: V00B0000 F6 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 1110111100101111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C70:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B7 H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 F0 +arc: D5 F2 +arc: D6 H02W0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: N1_V01N0001 F7 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEC.K0.INIT 0101000001011111 +word: SLICED.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 0101000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R47C71:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B1 V02S0301 +arc: B2 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 E1_H01W0000 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 F0 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F3 +arc: V00B0000 F4 +arc: V01S0000 F5 +arc: V01S0100 F7 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0011000001010000 +word: SLICEA.K0.INIT 0001000010110000 +word: SLICEC.K1.INIT 0000000001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 S1_V02N0301 +arc: B5 H00L0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D5 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R47C73:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C7 H01E0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: N1_V02N0601 F4 +word: SLICEA.K0.INIT 0001000000010011 +word: SLICEA.K1.INIT 1111010011110111 +word: SLICEB.K0.INIT 0000010000000111 +word: SLICEB.K1.INIT 1101110011011111 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R47C74:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: N3_V06N0103 F2 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000001100000101 +word: SLICEA.K1.INIT 1111001111110101 +word: SLICEB.K0.INIT 0000010100000011 +word: SLICEB.K1.INIT 1111010111110011 +word: SLICEC.K0.INIT 0000001000000111 +word: SLICEC.K1.INIT 1111001011110111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C75:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C7 V02S0001 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 0010001000010001 +word: SLICED.K1.INIT 0010000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R47C76:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R47C77:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 E1_H02W0501 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: C2 N1_V02S0401 +arc: C3 H02E0401 +arc: D2 N1_V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0101000000110000 +word: SLICEB.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R47C78:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R47C79:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: F0 F0_SLICE +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R47C80:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 Q5 +arc: A7 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 H02W0601 +arc: C5 V00T0100 +arc: C6 Q6 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: B5 F3 +arc: B6 V02N0701 +arc: C0 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R47C82:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 V02N0301 +arc: B4 N1_V02S0701 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H02W0401 +arc: C2 W1_H02E0401 +arc: C4 V00B0100 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D6 E1_H01W0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q1 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 N1_V02S0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C84:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F7 +arc: A1 N1_V02S0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B7 N1_V02S0701 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 F7 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C86:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R47C87:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A3 H02E0701 +arc: A4 F7 +arc: A6 W1_H02E0701 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 F3 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C3 H00L0000 +arc: C4 F6 +arc: C6 N1_V02S0001 +arc: C7 W1_H02E0401 +arc: D0 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 F0 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R47C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 H00R0100 +arc: B4 W1_H02E0101 +arc: B6 V00T0000 +arc: B7 F3 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D6 V02S0401 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C89:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 V01N0001 +arc: A2 V02S0701 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B2 H00R0100 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C2 H02E0601 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: D2 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R47C90:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A3 F5 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: B0 V02S0101 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: C0 H00L0100 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V02S0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1000101001000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 H01E0001 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 0000100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R47C92:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02E0701 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C7 W1_H02E0401 +arc: D1 V02N0001 +arc: D7 E1_H01W0100 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 0111011100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R47C93:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 N1_V02S0001 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: V00T0000 Q2 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C94:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A2 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 N1_V02S0301 +arc: A5 Q5 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B7 E1_H02W0301 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C5 N1_V02S0001 +arc: C6 Q6 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F7 +arc: V01S0100 Q1 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R47C95:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: A4 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V00B0000 F6 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R47C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0501 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A4 S1_V02N0301 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: A7 F5 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D6 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0000 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R47C97:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02S0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 S1_V02N0501 +arc: A3 F7 +arc: A4 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B4 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 V02S0401 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D6 H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C98:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A5 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B3 H00R0000 +arc: B5 H02E0301 +arc: B7 N1_V02S0701 +arc: C0 V02S0401 +arc: C1 V02N0601 +arc: C3 N1_V01S0100 +arc: C5 V02S0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F5 +arc: W1_H02W0001 Q0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R47C99:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 E1_H02W0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 H01E0101 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q5 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C100:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 V02S0301 +arc: A7 F5 +arc: B0 H02W0301 +arc: B2 V02S0301 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C2 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 H01E0001 +arc: D0 V02N0001 +arc: D2 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: N3_V06N0203 F7 +arc: V00B0000 F4 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1101000000001101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C101:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 H02W0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A3 V00B0000 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: B1 E1_H02W0101 +arc: B3 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C1 F4 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: D1 W1_H02E0001 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: V00T0100 F3 +arc: W3_H06W0003 F0 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C102:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: V00B0000 V02S0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 W1_H02E0101 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 V02S0001 +arc: C6 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 H02W0201 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F4 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C103:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H02W0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E1_H02W0401 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C104:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H02W0501 +arc: A2 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C105:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A5 H02W0701 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C106:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C107:PLC2 +arc: E1_H02E0301 V06N0003 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02W0101 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C108:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0501 +arc: A6 V02S0301 +arc: B0 E1_H01W0100 +arc: C0 N1_V01S0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICED.K0.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R48C109:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 V00T0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C5 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D5 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICED.K1.INIT 1100110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R48C110:PLC2 +arc: N1_V02N0301 H01E0101 + +.tile R48C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R48C112:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 + +.tile R48C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R48C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R48C24:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 + +.tile R48C25:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R48C26:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 + +.tile R48C27:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0601 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 + +.tile R48C28:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 + +.tile R48C30:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 + +.tile R48C31:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: V01S0100 S3_V06N0303 +arc: A1 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C32:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0501 V06S0303 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: B1 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C33:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 N1_V01S0100 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 N1_V02S0601 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0011000000110001 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0010001000100011 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C34:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A1 W1_H02E0501 +arc: A5 H02E0501 +arc: A7 F5 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: B2 F1 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0001000101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R48C35:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 E1_H01E0001 +arc: A3 F5 +arc: A5 V00B0000 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B5 V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 F2 +arc: D5 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0011111100110000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C36:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C37:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02S0301 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 Q0 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEB.K1.INIT 0000000000101110 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICED.K0.INIT 0000111100000001 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C38:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H02E0701 +arc: A4 V02N0301 +arc: A5 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: A7 F5 +arc: B1 H02E0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S3_V06S0303 F6 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C39:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H00L0000 +arc: A2 F7 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000011110001 +word: SLICEC.K0.INIT 0010001000100011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C40:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: C0 W1_H02E0401 +arc: C1 F4 +arc: C2 E1_H02W0401 +arc: C3 W1_H02E0401 +arc: C4 V02N0001 +arc: C6 E1_H01E0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V00B0000 F4 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000000001001110 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000000001011100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R48C41:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: A7 V00T0100 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEB.K0.INIT 0000010001010100 +word: SLICED.K1.INIT 0000001000110010 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 0101010100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A1 F7 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C3 H00R0100 +arc: C4 F6 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICED.K1.INIT 0001000100110000 +word: SLICEA.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C43:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C4 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D4 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 0011010100111111 +word: SLICEA.K0.INIT 1110001011101110 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 0000001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R48C44:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B6 H02W0301 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 N1_V01S0100 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D6 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1111111000001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: A3 H02W0501 +arc: B0 S1_V02N0301 +arc: B4 H00L0000 +arc: C0 H02E0601 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M5 H02W0001 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: V00T0000 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1100010010000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C46:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 F7 +arc: A4 F7 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B4 F1 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V01S0100 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 0101000001011100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICEA.K1.INIT 0000010101010101 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R48C47:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0501 +arc: A3 S1_V02N0501 +arc: A6 V02S0301 +arc: C0 H02W0601 +arc: C3 V02N0601 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0201 +arc: D3 V01S0100 +arc: D6 V02S0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C48:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 F5 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 H01E0101 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1011100000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C5 V02S0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C50:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: A2 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 F1 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 H01E0001 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 0101000001011100 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0000000011100010 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICEC.K0.INIT 0000000011100010 +word: SLICED.K0.INIT 1110001000000000 +word: SLICEA.K0.INIT 1111111000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R48C51:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: A0 V02N0701 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000111000000010 +word: SLICEC.K1.INIT 1111111011110010 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R48C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0501 +arc: A2 H02W0701 +arc: A3 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H01W0000 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 Q2 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C53:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F7 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 H01W0100 +arc: B4 W1_H02E0101 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C54:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A5 V02S0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B3 H00L0000 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICED.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100101011111111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A3 F7 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: C0 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 H02E0601 +arc: M2 E1_H02W0601 +arc: M4 V00T0000 +arc: N1_V01N0101 F0 +arc: V00B0100 F7 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C56:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F5 +arc: A1 S1_V02N0501 +arc: A3 F7 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: B2 H02E0101 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C3 V02S0601 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M1 H00L0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C57:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 H02W0101 +arc: C0 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111110101011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C58:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V02S0301 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H00R0000 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M2 N1_V01N0001 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R48C60:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 H02E0701 +arc: B1 W1_H02E0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F2 +arc: N3_V06N0203 Q7 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 Q7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEB.K1.INIT 1100111110101111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C62:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A4 F5 +arc: A5 H02W0701 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A4 H02E0501 +arc: A5 S1_V02N0101 +arc: B0 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: C0 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 V06N0303 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V01S0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1101000011010000 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0501 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B6 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A7 S1_V02N0101 +arc: B2 V02N0301 +arc: C0 V02N0601 +arc: C2 H00L0000 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R48C68:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A4 N1_V01S0100 +arc: A5 V02S0101 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 F5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0101000000000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R48C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N3_V06N0103 Q2 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A5 H02E0701 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0100 +arc: C5 V02S0001 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V02S0001 +arc: D5 E1_H01W0100 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F6 +arc: S1_V02S0501 F7 +arc: V00T0100 F3 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C71:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02W0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 V00B0000 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +word: SLICEA.K0.INIT 1011000010000000 +word: SLICEA.K1.INIT 1011111110001111 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICEB.K1.INIT 1110111101001111 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1110111100101111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 V02N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 E1_H02W0501 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B7 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C7 H01E0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0010001000001010 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1100111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C73:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: N1_V02N0001 F0 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100111110101111 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 H02W0101 +arc: B4 N1_V01S0000 +arc: B7 V02S0501 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 W1_H02E0401 +arc: C7 H02W0601 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 0010000000100010 +word: SLICED.K1.INIT 0000000000000010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: N1_V01N0101 F0 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1110111100101111 +word: SLICEC.K0.INIT 0011111100000000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C76:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: B1 H02E0101 +arc: B4 V02S0701 +arc: C1 H02E0601 +arc: C2 E1_H02W0401 +arc: C4 V02S0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D4 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: M0 V00T0000 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R48C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A5 H02W0701 +arc: C5 S1_V02N0201 +arc: D5 E1_H02W0001 +arc: F5 F5_SLICE +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R48C78:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 H02E0101 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 H02W0101 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R48C79:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 V06S0303 +arc: F0 F0_SLICE +arc: H01W0100 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 H02W0501 +arc: B0 H02W0101 +arc: B4 H02E0301 +arc: C0 V02S0601 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H00R0000 +arc: B6 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R48C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0100 H02E0301 +arc: B2 H01W0100 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: W1_H02W0201 F0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: A5 V02N0101 +arc: A7 S1_V02N0101 +arc: B7 H02E0301 +arc: C7 V00T0100 +arc: D5 W1_H02E0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R48C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0101 +arc: A0 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C2 W1_H02E0401 +arc: C3 F6 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D2 F0 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: N1_V01N0101 F5 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R48C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H02E0501 +arc: A2 E1_H02W0701 +arc: A3 F7 +arc: A6 V02N0101 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0101 +arc: B2 N1_V02S0301 +arc: B3 H01W0100 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 F6 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: D0 H02W0001 +arc: D2 H01E0101 +arc: D3 F0 +arc: D6 S1_V02N0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 F5 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 V02S0501 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C0 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 F4 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: V01S0000 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R48C87:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 N1_V02S0301 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 N1_V02S0501 +arc: B7 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C3 V02S0401 +arc: C4 F6 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: D4 F2 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C88:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: A0 H00L0100 +arc: A1 E1_H02W0501 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A7 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 F1 +arc: B4 N1_V02S0701 +arc: B7 V02N0501 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C7 V00T0000 +arc: D0 H00R0000 +arc: D1 W1_H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F3 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R48C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 F5 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V02S0301 +arc: B0 W1_H02E0301 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C0 F4 +arc: C1 V02N0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 E1_H01E0101 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 N1_V02S0601 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000100001000100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R48C90:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0501 +arc: A2 F5 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 H00R0100 +arc: B5 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 V02S0601 +arc: C2 H02E0401 +arc: C5 W1_H02E0601 +arc: C7 N1_V02S0201 +arc: D0 V02S0001 +arc: D2 W1_H02E0201 +arc: D5 F0 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R48C91:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: A0 W1_H02E0701 +arc: A3 H02E0701 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C7 H02W0401 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D3 F0 +arc: D4 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0010000010100000 +word: SLICEA.K1.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K1.INIT 0000000000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 V01N0101 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 F5 +arc: B1 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C1 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: M0 V00T0100 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R48C93:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H02E0501 +arc: A3 F7 +arc: A4 V02S0301 +arc: A7 E1_H02W0501 +arc: B1 V02S0101 +arc: B4 W1_H02E0301 +arc: B7 V02S0701 +arc: C1 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C7 V02N0201 +arc: D1 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R48C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 N1_V01S0000 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F6 +arc: S3_V06S0003 F3 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: H00L0000 V02S0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 S1_V02N0201 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D6 E1_H02W0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R48C96:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R48C97:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 N1_V01S0000 +arc: B0 H02W0301 +arc: B1 H02E0101 +arc: B2 V02S0301 +arc: B3 H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C98:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A4 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B1 V02S0301 +arc: B4 E1_H02W0301 +arc: B6 F1 +arc: C0 W1_H02E0401 +arc: C1 H02E0601 +arc: C4 V02S0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C99:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B1 H02E0101 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 S1_V02N0701 +arc: B7 H01E0101 +arc: C0 W1_H02E0401 +arc: C1 V02N0401 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F2 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1101110100000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C100:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: A6 V02S0101 +arc: B1 H01W0100 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 V02S0501 +arc: C1 F6 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A6 S1_V02N0101 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 H02W0101 +arc: B6 E1_H02W0101 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C6 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D6 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C102:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V06S0203 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A3 F7 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B3 F1 +arc: B7 V02N0701 +arc: C1 H00L0000 +arc: C3 E1_H01W0000 +arc: C7 H02E0401 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D7 V02N0601 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C103:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H02W0701 +arc: A3 F7 +arc: A4 V02N0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 V02S0201 +arc: D4 N1_V02S0401 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: LSR1 H02W0301 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: V00T0100 F1 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C104:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02N0501 +arc: A2 S1_V02N0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 V01S0000 +arc: B7 F3 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C105:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 S1_V02N0301 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 E1_H02W0001 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C106:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C107:PLC2 +arc: E3_H06E0103 W1_H02E0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 Q5 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 S1_V02N0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02E0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C108:PLC2 +arc: E1_H02E0101 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: A2 V01N0101 +arc: B2 N1_V02S0301 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1011101100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R49C109:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C110:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R49C113:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R49C114:PLC2 +arc: N3_V06N0303 S1_V02N0601 + +.tile R49C29:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R49C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R49C31:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: A0 V02N0501 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R49C32:PLC2 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 S1_V02N0501 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C33:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 V02N0501 +arc: B1 N1_V02S0301 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C34:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02S0701 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C35:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C36:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 S1_V02N0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 E1_H01W0000 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C37:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B1 F3 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B5 H02W0301 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C5 V00T0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 F7 +arc: S3_V06S0003 Q0 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEB.K1.INIT 0001001100000010 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICED.K1.INIT 0011000000110001 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 S1_V02N0701 +arc: C0 F4 +arc: C2 E1_H02W0401 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEC.K1.INIT 0000000011110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C39:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 W1_H02E0701 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B6 V02S0701 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICED.K0.INIT 0000011100000010 +word: SLICEB.K0.INIT 0000011100000100 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0100010001000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C40:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C6 F4 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEB.K1.INIT 0000000000111010 +word: SLICEB.K0.INIT 0000001100001010 +word: SLICEA.K1.INIT 0101010100000001 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 0000110000001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C41:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: B0 H02W0101 +arc: B3 H02W0301 +arc: C0 H00L0000 +arc: C3 H02E0401 +arc: D0 V02N0001 +arc: D3 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R49C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06S0203 +arc: A1 H02E0701 +arc: B1 N1_V02S0301 +arc: B4 F1 +arc: C1 S1_V02N0401 +arc: C4 S1_V02N0001 +arc: D1 V00B0100 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R49C43:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 F7 +arc: A6 N1_V01N0101 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0100 +arc: C3 N1_V01N0001 +arc: C6 H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D3 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0301 F3 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0101001101011111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0303 F6 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000111000000100 +word: SLICEB.K1.INIT 1111110011111010 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICED.K1.INIT 1100000010100000 +word: SLICED.K0.INIT 1100110011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R49C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 N3_V06S0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 F7 +arc: A6 W1_H02E0701 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 W1_H02E0401 +arc: C1 F6 +arc: C6 E1_H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K1.INIT 1010111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C46:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A3 E1_H02W0501 +arc: A5 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: N3_V06N0203 F7 +arc: S1_V02S0401 F6 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 1111000011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C47:PLC2 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0101 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A5 H02E0501 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 V02N0701 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0201 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1000110010000000 +word: SLICED.K1.INIT 0000000001110111 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 S1_V02N0701 +arc: A5 E1_H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 1011100011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 E1_H01E0001 +arc: A2 F7 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: B6 H02W0301 +arc: B7 H02E0301 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: LSR0 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C50:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: A0 H02E0701 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 V02N0401 +arc: C4 V02S0201 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEC.K0.INIT 0000000011001010 +word: SLICED.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1111000011101110 +word: SLICEA.K1.INIT 0000000000110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R49C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W1_H02E0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V06S0203 +arc: A0 W1_H02E0501 +arc: A1 V02S0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 V02S0701 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 V01N0001 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N3_V06N0003 Q0 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000000011100100 +word: SLICEB.K1.INIT 1111111111100100 +word: SLICED.K0.INIT 1100111111001010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEC.K1.INIT 1101111111010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C52:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: A3 V00B0000 +arc: B0 W1_H02E0301 +arc: B3 H02E0101 +arc: C0 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 S1_V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000100011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C53:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V00T0100 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: C1 H02E0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: V01S0000 Q5 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R49C54:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02S0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V02S0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 F7 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C6 N1_V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: V01S0000 F1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 0000001011001110 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C55:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: F0 F5A_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101111111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C56:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 V02S0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000110000101110 +word: SLICEC.K1.INIT 0010111000101110 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A4 V00B0000 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: C0 V02S0601 +arc: C3 F6 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00B0000 F6 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEC.K0.INIT 0101010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C58:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0501 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEB.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C59:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A4 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B4 V01S0000 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C4 V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 1100100011001100 +word: SLICEA.K0.INIT 0101010100110000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R49C60:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 S1_V02N0601 +arc: C3 V02N0401 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0201 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 F1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R49C61:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 E1_H02W0501 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K1.INIT 0011001101011111 +word: SLICEA.K0.INIT 1111011110100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0100 V02S0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 F5 +arc: B0 E1_H02W0301 +arc: B3 H02W0301 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C0 F4 +arc: C1 F4 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 F6 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0001000010111010 +word: SLICEA.K1.INIT 0101000011111010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R49C63:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 N1_V02S0501 +arc: A1 H02W0701 +arc: A2 V00B0000 +arc: A4 V02N0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B4 V02N0501 +arc: B6 V02S0701 +arc: B7 F1 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V00T0100 +arc: D4 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F7 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C64:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B2 N1_V02S0301 +arc: B5 H02E0101 +arc: CLK0 G_HPBX0000 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0701 Q5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 W1_H02E0701 +arc: A1 N1_V02S0501 +arc: A3 V00T0000 +arc: A5 H02W0501 +arc: B2 H02W0301 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C66:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C67:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: A3 V00B0000 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B2 S1_V02N0301 +arc: B4 H00L0000 +arc: B6 V02S0701 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R49C68:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H02E0701 +arc: B0 V02S0101 +arc: B4 S1_V02N0501 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D4 H02W0001 +arc: E1_H02E0401 Q4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0201 F2 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R49C69:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0103 N1_V01S0100 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02S0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C70:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 V02S0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 1101100011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C71:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H00L0100 +arc: A7 H00L0000 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B7 H02W0301 +arc: C1 W1_H02E0601 +arc: C3 V02N0401 +arc: C7 V00T0000 +arc: D1 H02E0201 +arc: D3 H02W0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +arc: V01S0100 F3 +arc: W1_H02W0001 F0 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02S0301 + +.tile R49C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 F7 +arc: A3 V02N0701 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B5 F1 +arc: B6 V00B0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 N1_V02S0201 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0000010000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0010001000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V06N0203 + +.tile R49C75:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02N0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: A4 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: D2 F0 +arc: D3 W1_H02E0001 +arc: D4 H00R0100 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 F1 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: C7 V01N0101 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0101 F4 +arc: V00B0000 F6 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R49C77:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D6 S1_V02N0601 +arc: D7 F0 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +word: SLICED.K1.INIT 0000010000000111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 + +.tile R49C79:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: A2 W1_H02E0701 +arc: B2 V02S0101 +arc: C2 E1_H02W0601 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEB.K0.INIT 1111111000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 + +.tile R49C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0601 S1_V02N0601 + +.tile R49C82:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H02E0701 + +.tile R49C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 S3_V06N0303 + +.tile R49C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: A1 H02W0501 +arc: A2 V00T0000 +arc: A5 H02E0701 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B7 F1 +arc: C1 H00R0100 +arc: C2 E1_H02W0401 +arc: C5 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D5 F2 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C85:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02S0501 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A6 S1_V02N0301 +arc: A7 H02W0701 +arc: B2 H00R0100 +arc: B6 N1_V02S0701 +arc: B7 F3 +arc: C2 H00L0100 +arc: C3 F6 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D6 V00B0000 +arc: D7 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0100 F7 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R49C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A7 H02E0701 +arc: B0 H02E0301 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C2 H00L0100 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0401 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D2 V02S0201 +arc: D3 F0 +arc: D4 H02E0001 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R49C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 + +.tile R49C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B3 H00R0000 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00B0000 F4 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R49C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 V01N0101 +arc: A0 H00L0100 +arc: A2 H01E0001 +arc: A4 V02S0301 +arc: A5 E1_H01W0000 +arc: A6 H00R0000 +arc: A7 F5 +arc: B0 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: D0 V02N0201 +arc: D2 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R49C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0101 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A2 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B2 H00R0100 +arc: B4 H01E0101 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C2 F6 +arc: C4 V02N0201 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D2 F0 +arc: D4 H00L0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0001 F2 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C91:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0100 +arc: A2 W1_H02E0501 +arc: B0 H02W0301 +arc: B2 V02S0101 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C6 V00T0000 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: D6 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 W1_H02E0601 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000000000010 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1100001101000001 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R49C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0201 V02N0201 +arc: A1 H02W0501 +arc: B1 S1_V02N0301 +arc: C1 H02E0401 +arc: D1 V02S0001 +arc: F1 F1_SLICE +arc: N1_V01N0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R49C93:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 F5 +arc: A1 H00R0000 +arc: A2 H02E0501 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 E1_H01W0100 +arc: B2 F1 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 F6 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0101 F4 +arc: S3_V06S0003 F0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R49C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 E3_H06W0303 +arc: H00L0100 H02E0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H02W0001 +arc: A0 E1_H02W0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 E1_H02W0701 +arc: A5 H02E0701 +arc: A6 H02W0501 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: B2 F3 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 H00R0000 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: S1_V02S0401 F4 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R49C95:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 N1_V02S0501 +arc: A1 V02N0701 +arc: A3 V02N0501 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C96:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0501 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q5 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C97:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0501 +arc: A4 N1_V02S0101 +arc: A5 Q5 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 Q3 +arc: B6 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C98:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A2 E1_H02W0701 +arc: A3 H00L0100 +arc: A5 F7 +arc: A6 W1_H02E0501 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B5 F3 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D5 F2 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R49C99:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 F5 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C4 V02S0201 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 H02W0401 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F6 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000001000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R4C3:PLC2 +arc: W1_H02W0301 V02N0301 + +.tile R4C41:PLC2 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: B0 V02N0301 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: E1_H01E0001 Q2 +arc: F0 F5A_SLICE +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F0 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C42:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H01E0001 +arc: A0 V02N0701 +arc: A2 E1_H02W0701 +arc: B0 V02N0301 +arc: B2 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: M1 V01S0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C43:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 H02E0301 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A4 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 V02N0301 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R4C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 H02E0201 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C45:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 W1_H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 H02W0501 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H00L0100 +arc: A2 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B4 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1110010011100100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C47:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 H02W0001 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B4 V02N0501 +arc: B6 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 V02N0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 V02N0701 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C50:PLC2 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 V02N0701 +arc: A2 V01N0101 +arc: B0 V01N0001 +arc: C0 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111000001000100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C51:PLC2 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 V01N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V01N0001 + +.tile R4C7:PLC2 +arc: S3_V06S0103 W3_H06E0103 + +.tile R50C100:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0103 + +.tile R50C101:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 S3_V06N0103 + +.tile R50C102:PLC2 +arc: E1_H02E0001 V02N0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H02W0501 + +.tile R50C103:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A5 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H00R0100 +arc: B5 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C3 F6 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V00T0100 F1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C104:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 N1_V02S0601 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C105:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C3 H00R0100 +arc: C6 S1_V02N0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D6 H00L0100 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C106:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A5 Q5 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0501 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R50C107:PLC2 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H01E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A4 V02N0101 +arc: B2 V02N0101 +arc: C2 E1_H01W0000 +arc: C4 V02N0201 +arc: D2 V02N0201 +arc: D4 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICEC.K0.INIT 1111000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R50C108:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C109:PLC2 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R50C110:PLC2 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 N3_V06S0003 + +.tile R50C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R50C112:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R50C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R50C115:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R50C17:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R50C24:PLC2 +arc: E3_H06E0103 N3_V06S0103 + +.tile R50C29:PLC2 +arc: E1_H02E0201 E3_H06W0103 + +.tile R50C30:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 S3_V06N0203 + +.tile R50C31:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0100 S3_V06N0303 + +.tile R50C32:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0701 H06W0203 +arc: V00T0100 V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0003 Q0 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C33:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 + +.tile R50C34:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0100 V02N0701 +arc: B0 H02E0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C35:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 N1_V01S0100 +arc: A7 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 F0 +arc: D4 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 F3 +word: SLICEA.K1.INIT 0010101000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C36:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 N1_V02S0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H02W0701 +arc: A4 E1_H01W0000 +arc: B1 V00B0000 +arc: B4 N1_V01S0000 +arc: C1 S1_V02N0401 +arc: C4 V02N0201 +arc: D1 E1_H02W0001 +arc: D4 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A3 H02W0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B6 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C4 E1_H02W0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 0011001110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C38:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 E1_H02W0501 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0101010111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C39:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F7 +arc: A2 V02S0501 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C3 F4 +arc: C4 H02W0601 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 F2 +arc: D4 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0010001000100011 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEC.K0.INIT 0000001100100010 +word: SLICEB.K0.INIT 1010100000001000 +word: SLICEB.K1.INIT 0010001000100011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B2 V02N0101 +arc: B3 F1 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: C4 F6 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 F2 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K1.INIT 0100010001000101 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEC.K1.INIT 0101000001010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C41:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H01E0001 +arc: B0 V02S0301 +arc: B4 H02W0101 +arc: C0 V02S0401 +arc: C4 H01E0001 +arc: D0 H02E0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R50C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000010001010100 +word: SLICEC.K0.INIT 1110001000000000 +word: SLICEA.K1.INIT 0001000000110010 +word: SLICEB.K0.INIT 0011000000110001 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C43:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A3 F5 +arc: A4 F7 +arc: A5 H02W0501 +arc: A6 S1_V02N0101 +arc: B1 V02S0301 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C2 F6 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: V01S0000 F3 +arc: V01S0100 Q4 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000010100001111 +word: SLICED.K0.INIT 1100010010000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C44:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: A4 H02E0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 V01N0001 +arc: D5 E1_H02W0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F7 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000101100001000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C45:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A4 F5 +arc: A5 E1_H02W0501 +arc: B4 V00B0100 +arc: B5 V02N0701 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C46:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 N1_V02S0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 F1 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F6 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEB.K1.INIT 1111111111100010 +word: SLICEA.K1.INIT 0000000010111000 +word: SLICED.K0.INIT 1111111001010100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 0100010101000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A4 N1_V02S0301 +arc: B1 Q1 +arc: B4 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V02S0201 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C48:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A2 H00L0100 +arc: A4 H02W0701 +arc: A5 V02N0301 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 F1 +arc: B4 V00B0100 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 N1_V01S0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0201 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: S1_V02S0101 F1 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 0101010100001100 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 0001110100001100 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R50C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A3 V02N0501 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 0000110011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C50:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V01N0101 +arc: A3 N1_V02S0501 +arc: A4 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B4 V02S0701 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001010110111111 +word: SLICEA.K0.INIT 1111011110100010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C51:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0501 +arc: A4 V00B0000 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 Q6 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000111000000100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: B0 H02E0101 +arc: B3 F1 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: D0 H02W0001 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: S1_V02S0201 F0 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R50C53:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00R0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: B0 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0701 +arc: C0 H02W0601 +arc: C3 W1_H02E0401 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0101010100111111 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R50C54:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 F3 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 F2 +arc: D7 V02N0401 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 0100010101000000 +word: SLICED.K1.INIT 1010101011111100 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 1100111111001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C55:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A7 E1_H01W0000 +arc: B0 H02E0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02W0101 +arc: C0 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000000011100010 +word: SLICEB.K1.INIT 1111111111100010 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C56:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1110001011100010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 N3_V06S0303 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 F5 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1111111000110010 +word: SLICEA.K1.INIT 0000101000001100 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEC.K0.INIT 1100110011111010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C58:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C59:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: B0 H02W0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C60:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0701 +arc: B0 V01N0001 +arc: C0 H00R0100 +arc: D0 H00R0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1110010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C61:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H01E0001 +arc: A6 H02E0701 +arc: B6 V01S0000 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: M0 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: V01S0000 Q4 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R50C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 V00T0100 +arc: A6 F5 +arc: B0 H02E0101 +arc: B3 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C5 W1_H02E0401 +arc: C6 F4 +arc: D0 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 S1_V02N0301 +arc: A7 F5 +arc: B0 V01N0001 +arc: B2 S1_V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: B7 V01S0000 +arc: C0 H02W0601 +arc: C2 V02N0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D4 V01N0001 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 + +.tile R50C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B3 H02W0301 +arc: B5 H02E0301 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C3 H00L0100 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A3 V02N0501 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B1 V02S0301 +arc: B3 H02E0301 +arc: B5 H00R0000 +arc: B7 V02S0701 +arc: C1 V02N0401 +arc: C3 V02S0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: D1 N1_V02S0201 +arc: D3 V02S0001 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F5 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F6 +arc: V01S0000 F1 +word: SLICED.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1010010100000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F5 +arc: A1 V02S0701 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 E1_H01W0000 +arc: A7 H02E0501 +arc: B0 F3 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 F1 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: C7 N1_V02S0001 +arc: D0 V01S0100 +arc: D1 H01E0101 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R50C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: C1 F6 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: D1 H01E0101 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R50C69:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A6 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: B6 S1_V02N0701 +arc: C1 H02W0401 +arc: C3 W1_H02E0401 +arc: C6 S1_V02N0001 +arc: D1 W1_H02E0001 +arc: D3 V02S0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +arc: V00T0100 F3 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: A7 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B6 V00T0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 +arc: B7 H02W0301 +arc: C7 N1_V02S0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1100111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R50C73:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A7 V00T0100 +arc: B0 H02W0301 +arc: B2 N1_V02S0101 +arc: B3 V02N0301 +arc: B6 E1_H02W0301 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F7 +arc: V00T0100 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000100000001100 +word: SLICED.K1.INIT 0111111100000000 +word: SLICEA.K0.INIT 1000000010100000 +word: SLICED.K0.INIT 0011000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R50C74:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 N1_V02S0501 +arc: D2 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: N1_V01N0101 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R50C75:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0203 E1_H01W0000 + +.tile R50C76:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 N1_V02S0701 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 V01N0001 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V01N0101 +arc: B1 V01N0001 +arc: D0 S1_V02N0201 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R50C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 N3_V06S0003 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: V01S0000 Q3 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q6 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F7 +arc: A3 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A7 H00R0000 +arc: B1 F3 +arc: B3 H00R0100 +arc: B5 H02E0101 +arc: B7 H02E0301 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C5 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D5 H02W0001 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R50C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A6 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 N1_V02S0401 +arc: C2 H02W0401 +arc: C3 E1_H01W0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 W1_H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: V00T0000 F2 +arc: V01S0100 Q6 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111101000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0103 V06N0103 +arc: A2 W1_H02E0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: E1_H01E0101 F6 +arc: E3_H06E0203 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R50C83:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0003 +arc: W3_H06W0303 E3_H06W0303 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R50C84:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: A0 H02W0501 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: D0 V02S0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R50C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 E1_H02W0401 +arc: A1 H00L0100 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B7 S1_V02N0501 +arc: C1 W1_H02E0601 +arc: C7 H02E0401 +arc: D1 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R50C86:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C2 N1_V02S0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D2 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0001 F4 +arc: V00B0000 F6 +arc: V00B0100 F5 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1000001011000011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R50C87:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 + +.tile R50C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 W1_H02E0701 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A3 H02W0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 F1 +arc: B4 F3 +arc: B6 S1_V02N0501 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0100 +arc: C4 F6 +arc: C5 E1_H01E0101 +arc: C6 V02S0001 +arc: C7 V00B0100 +arc: D0 N1_V02S0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000010000000000 +word: SLICEC.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R50C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 V02N0301 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 H01W0100 +arc: B4 H00L0000 +arc: B5 F3 +arc: B6 F1 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H02E0601 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R50C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A2 F5 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B2 H00L0000 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C0 H02E0601 +arc: C2 F4 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: D0 H00R0000 +arc: D2 F0 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R50C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 H00R0100 +arc: B3 F1 +arc: B4 V02N0701 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 W1_H02E0201 +arc: D5 V02S0601 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R50C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0101 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: D0 V00T0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D6 N1_V02S0601 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R50C93:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 + +.tile R50C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V06N0303 +arc: A0 F5 +arc: A1 V02S0501 +arc: A3 E1_H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0101 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H00R0000 +arc: D1 W1_H02E0201 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000100000000000 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R50C95:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A4 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 V02S0601 +arc: C4 V02N0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D4 V02S0401 +arc: D6 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: W1_H02W0601 F4 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C96:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A2 F5 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICED.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C97:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02W0701 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C98:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: B1 N1_V02S0101 +arc: C0 H02W0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R50C99:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 H02W0301 +arc: B1 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C100:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0301 +arc: A1 N1_V02S0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 V02S0101 +arc: C0 H02W0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C101:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H02W0401 + +.tile R51C102:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 W1_H02E0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C103:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V00B0000 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C104:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02E0401 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q6 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C105:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A5 Q5 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C106:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: A6 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: C6 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: V01S0000 F2 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 F3 +word: SLICED.K0.INIT 1010111100000000 +word: SLICEB.K1.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R51C107:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C108:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 + +.tile R51C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: W1_H02W0501 S1_V02N0501 + +.tile R51C110:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C111:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C113:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R51C114:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 + +.tile R51C26:PLC2 +arc: E3_H06E0103 N3_V06S0103 + +.tile R51C28:PLC2 +arc: V00B0000 V02N0201 +arc: CLK0 G_HPBX0000 +arc: LSR0 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C29:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0001 Q2 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C30:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: V00B0000 V02S0001 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A7 F5 +arc: B3 H00R0000 +arc: B5 V02N0701 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C7 V02S0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +word: SLICEC.K1.INIT 1100101000000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C31:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 W1_H02E0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICED.K1.INIT 1110001000000000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICED.K0.INIT 0011001100000001 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C32:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B4 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 F2 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000110010000000 +word: SLICEA.K0.INIT 1111110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C33:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICED.K0.INIT 1010001010000000 +word: SLICEC.K1.INIT 0101000001010101 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICEC.K0.INIT 0000000001001110 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICED.K1.INIT 0100010001000101 +word: SLICEA.K1.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 F7 +arc: A2 F7 +arc: A3 H00L0100 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: D0 V01S0100 +arc: D2 V02N0201 +arc: D3 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F0 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICEB.K1.INIT 0000011100000010 +word: SLICEB.K0.INIT 0010001100100010 +word: SLICEA.K0.INIT 0000110000001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R51C35:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V02N0501 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 H02W0401 +arc: C3 V02S0601 +arc: D0 W1_H02E0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C36:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C37:PLC2 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V06N0203 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 N1_V02S0401 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C38:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 S1_V02N0101 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C39:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: A0 V02N0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C40:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C2 N1_V02S0601 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000010100001100 +word: SLICED.K0.INIT 0000000001001110 +word: SLICEB.K1.INIT 0001000101010101 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C41:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A2 F7 +arc: A4 F5 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B2 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 N1_V02S0501 +arc: B7 V02N0701 +arc: C0 F4 +arc: C2 F6 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D2 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +arc: W1_H02W0201 F2 +word: SLICED.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0000000011110001 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R51C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02N0501 +arc: A2 H01E0001 +arc: A3 F5 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B5 H01E0101 +arc: B6 V00T0000 +arc: C0 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C43:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 F5 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V02S0501 +arc: B6 N1_V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEC.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0011000000110001 +word: SLICEC.K0.INIT 0010001000100011 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0501 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0101 +arc: B2 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 F2 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010001010000000 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R51C45:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 N1_V02S0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 F7 +arc: A1 F5 +arc: A2 W1_H02E0501 +arc: A5 V02N0101 +arc: A6 H02W0501 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B5 V02N0501 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 V02S0401 +arc: C5 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011111110111 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEC.K1.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A6 V02S0301 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B6 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 H02W0701 +arc: A3 E1_H01E0001 +arc: A6 H02W0701 +arc: A7 N1_V01S0100 +arc: B1 E1_H02W0301 +arc: B5 H00R0000 +arc: B7 V02N0501 +arc: C1 H00L0100 +arc: C3 W1_H02E0601 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: S1_V02S0501 F7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R51C49:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: B7 S1_V02N0701 +arc: C1 E1_H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F7 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R51C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A3 F7 +arc: A7 V02N0301 +arc: B1 H02E0101 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D7 H00R0100 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q4 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 Q4 +arc: V01S0000 F2 +arc: V01S0100 Q6 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C51:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 1011111110110011 +word: SLICED.K1.INIT 1100010010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00R0000 +arc: B1 H02E0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: D1 V02N0201 +arc: D3 E1_H02W0001 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R51C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A5 F7 +arc: B0 V02S0301 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 F1 +arc: B5 H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F4 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C54:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02E0701 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A6 V00T0100 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D3 S1_V02N0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V00B0000 F6 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0011001101011111 +word: SLICED.K0.INIT 0011010100111111 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H01E0001 +arc: A2 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0000 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D7 V02S0401 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 H00L0100 +arc: A4 V00T0000 +arc: A6 H02W0501 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F4 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 0000000001011111 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C57:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 Q0 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICEC.K0.INIT 0100010101000000 +word: SLICEC.K1.INIT 1110111111101100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C58:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B3 V01N0001 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 V02S0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V00B0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C59:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 F5 +arc: A3 F5 +arc: A5 N1_V01N0101 +arc: B1 H02E0101 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010000010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R51C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 F7 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B1 H02W0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C61:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R51C62:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 E1_H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: B0 F3 +arc: B1 W1_H02E0101 +arc: B3 F1 +arc: B4 V02S0501 +arc: B6 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C6 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R51C63:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E3_H06W0003 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 W1_H02E0701 +arc: B0 H02E0101 +arc: B4 H02W0101 +arc: C0 V02N0401 +arc: C4 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 E1_H01W0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0001001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 V00B0000 +arc: A6 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B6 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C65:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C66:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 F7 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A6 H02W0701 +arc: B0 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B6 F3 +arc: C0 H02E0601 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0601 +arc: C6 V00T0000 +arc: D0 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02W0201 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F2 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111001100000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C68:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R51C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: A0 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: V00T0100 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R51C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0501 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00T0000 Q2 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C71:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 H02W0501 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 N1_V02S0101 +arc: B2 S1_V02N0101 +arc: B3 H02E0301 +arc: B5 F3 +arc: B6 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C5 F6 +arc: C6 V00T0100 +arc: D0 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H02E0701 +arc: A3 V02S0701 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: C0 H00L0100 +arc: C1 N1_V01N0001 +arc: C3 H00R0100 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0100 F3 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: A7 H00L0000 +arc: B0 V02N0301 +arc: B3 S1_V02N0301 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 H02W0601 +arc: C7 V00T0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 V00T0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111111111111100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000010110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C74:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R51C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0601 + +.tile R51C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N3_V06S0103 +arc: A4 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B5 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R51C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 W1_H02E0501 +arc: A3 H02W0701 +arc: A5 W1_H02E0501 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H02W0101 +arc: B6 V01S0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q7 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02W0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: V00B0000 F4 +arc: V01S0000 Q6 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V01N0101 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B4 F1 +arc: C4 V02S0201 +arc: D0 V00B0100 +arc: D4 E1_H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 0000111100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R51C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A4 F7 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B4 F3 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C1 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0401 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: D0 N1_V01S0000 +arc: D1 S1_V02N0001 +arc: D3 N1_V02S0201 +arc: D4 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: S1_V02S0001 F0 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000101011001111 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 N1_V01N0001 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: S1_V02S0501 F5 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C1 H02W0401 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C83:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile R51C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0203 E3_H06W0203 + +.tile R51C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A3 F5 +arc: A5 V00B0000 +arc: B0 V02S0101 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H02E0101 +arc: C0 H02E0601 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: D0 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 F0 +arc: D5 H00L0100 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: M0 V00B0100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1000001000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A2 H02E0501 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B1 F3 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 F1 +arc: B6 V00T0000 +arc: B7 H02W0301 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H01W0000 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0401 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H02E0501 +arc: A3 H01E0001 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B5 F3 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 W1_H02E0401 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: D0 H02W0001 +arc: D3 V02N0001 +arc: D5 F0 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 H02E0701 +arc: A4 V02N0101 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B4 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 H00R0100 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: D0 V02S0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: V00B0100 F5 +arc: V00T0000 F0 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1101000000001101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000001000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R51C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 V00B0000 +arc: A6 H02W0701 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 F1 +arc: C1 H02W0401 +arc: C2 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 V00T0100 +arc: C7 F6 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D4 H00L0100 +arc: D6 W1_H02E0201 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R51C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 H02E0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A2 F5 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: C2 F6 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D0 H00R0000 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000111111110000 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000110000100011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0010000000000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R51C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 F7 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B4 V00B0100 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C2 V02N0601 +arc: C4 H02E0401 +arc: C6 F4 +arc: C7 V00T0000 +arc: D2 H02E0201 +arc: D4 E1_H01W0100 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICED.K0.INIT 1001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 V01N0001 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R51C93:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: D0 H02E0201 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 H02W0601 +arc: N1_V01N0101 F3 +arc: S1_V02S0501 F5 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1101110100001101 +word: SLICEB.K0.INIT 1001000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R51C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N1_V02S0601 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S3_V06N0203 +arc: A3 V02S0701 +arc: B3 W1_H02E0301 +arc: C3 E1_H02W0601 +arc: D3 H02W0201 +arc: F3 F3_SLICE +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R51C95:PLC2 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A3 H00L0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B3 H02E0301 +arc: C0 V02S0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F3 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C96:PLC2 +arc: H00L0000 V02N0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B7 E1_H02W0301 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: C7 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 V01N0001 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F1 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100000000001100 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R51C97:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C98:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: A2 H02E0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R51C99:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 N1_V02S0701 +arc: B0 V02S0101 +arc: B1 N1_V02S0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C100:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 N1_V02S0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C101:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 V06N0103 +arc: A1 H02E0501 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A5 Q5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B6 V00B0000 +arc: C0 H02W0601 +arc: C2 N1_V01N0001 +arc: C4 Q4 +arc: C5 N1_V02S0001 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C102:PLC2 +arc: N1_V02N0701 H02W0701 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E1_H01W0100 + +.tile R52C103:PLC2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C104:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 V01N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02N0501 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C105:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: B1 H02W0101 +arc: C1 E1_H01W0000 +arc: D1 H02W0001 +arc: F1 F1_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: N1_V01N0001 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R52C106:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 E1_H01E0001 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02N0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C107:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 + +.tile R52C108:PLC2 +arc: N1_V02N0101 V01N0101 + +.tile R52C109:PLC2 +arc: N1_V02N0401 S1_V02N0101 + +.tile R52C110:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R52C113:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R52C116:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R52C22:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R52C23:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R52C25:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R52C26:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R52C28:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 H02W0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B3 H00L0000 +arc: B6 E1_H02W0101 +arc: C0 F6 +arc: C3 F6 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V02S0001 +arc: D3 H02W0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C29:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: A0 F5 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: A7 V02N0101 +arc: B1 H02W0101 +arc: B4 F1 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +word: SLICED.K1.INIT 1011000010000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C30:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02E0401 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 F5 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 F7 +arc: B0 W1_H02E0101 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0101 +arc: B5 F1 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 F2 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K1.INIT 1101000010000000 +word: SLICED.K0.INIT 0000000001011100 +word: SLICEB.K0.INIT 1111111011001110 +word: SLICEB.K1.INIT 0011001000000010 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C31:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A7 V00T0100 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H02W0101 +arc: B5 H00L0000 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 1110110011101100 +word: SLICEC.K1.INIT 1111111111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010001010000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R52C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: A2 H01E0001 +arc: A5 F7 +arc: A7 W1_H02E0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B5 H01E0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02E0401 +arc: M5 H02W0001 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q0 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K1.INIT 1110111010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R52C33:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A6 H02E0701 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R52C34:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: H01W0000 F6 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R52C35:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 N1_V02S0501 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B2 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D2 H02E0201 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C36:PLC2 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R52C37:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 + +.tile R52C38:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: A5 N1_V02S0301 +arc: B0 H02E0301 +arc: B5 S1_V02N0701 +arc: C0 H02W0601 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C39:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C40:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: B0 H01W0100 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C41:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 E1_H01E0001 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 F3 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1110000001000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 1110000001000000 +word: SLICEB.K1.INIT 0000111100000001 +word: SLICEA.K1.INIT 0011001110101010 +word: SLICEB.K0.INIT 0000101000001011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C42:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 H01E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02W0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q1 +arc: M1 H02W0001 +arc: MUXCLK0 CLK0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 V06S0103 +arc: A0 H02E0501 +arc: A2 H01E0001 +arc: A3 F7 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C3 V02N0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C45:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06N0103 +arc: A1 V02N0501 +arc: A3 F7 +arc: A7 V02N0301 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F7 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C46:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02W0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: B0 E1_H01W0100 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEB.K1.INIT 1000100010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C47:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H02W0501 +arc: A1 V02N0701 +arc: A2 F7 +arc: A3 F7 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V02S0301 +arc: B1 V02N0301 +arc: B2 F1 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 F6 +arc: C2 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 0011001100001010 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 1010110011111111 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K1.INIT 1011101110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R52C48:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 H02W0701 +arc: A2 F7 +arc: A5 V02S0301 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C3 V02S0601 +arc: C4 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: V00T0100 F1 +word: SLICEA.K0.INIT 1010110011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEB.K0.INIT 0010001010101010 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001000100110011 +word: SLICEC.K0.INIT 0000110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R52C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 F7 +arc: A4 V02N0301 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B4 H00R0000 +arc: B7 V00T0000 +arc: C0 F4 +arc: C4 V02S0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 0001001111011111 +word: SLICEA.K0.INIT 1111011111000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C50:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 V01N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B6 H02E0301 +arc: C0 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0011001100001010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C51:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A2 V01N0101 +arc: A4 H02E0701 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0203 F7 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1010010100100001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1100100000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 V02N0301 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 W1_H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q1 +arc: LSR1 H02W0301 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1000101010000000 +word: SLICEB.K1.INIT 1101111111010101 +word: SLICEC.K1.INIT 1100100001000000 +word: SLICED.K1.INIT 0001110100111111 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C53:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A4 V00T0100 +arc: A7 Q7 +arc: B4 H02W0101 +arc: C1 H00R0100 +arc: C4 H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D4 V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010101011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C54:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F5 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: C1 V02N0401 +arc: C2 W1_H02E0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D5 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 0001000100110011 +word: SLICEB.K0.INIT 0101000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A1 E1_H01E0001 +arc: B1 H02W0301 +arc: B2 W1_H02E0101 +arc: C2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R52C56:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEB.K0.INIT 0101001101010000 +word: SLICEB.K1.INIT 0101111101010000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C57:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 F7 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 W1_H02E0301 +arc: B5 F3 +arc: B7 V00B0000 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C4 V00T0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: S1_V02S0301 F3 +arc: V00T0100 F3 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000111100100010 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C58:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 H02W0501 +arc: A4 F5 +arc: A5 H02W0501 +arc: B0 V02N0301 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: C0 H00L0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEC.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R52C60:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 + +.tile R52C61:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: V00T0100 V02N0501 +arc: A0 H02W0701 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: B0 N1_V02S0101 +arc: B2 F3 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: C0 H02E0401 +arc: C2 F4 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 V02N0001 +arc: D0 H02W0001 +arc: D2 F0 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C62:PLC2 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H02W0301 + +.tile R52C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 + +.tile R52C64:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B4 H02E0101 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 N1_V02S0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R52C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A6 S1_V02N0301 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q4 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q2 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1011101100000000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: A2 H02E0701 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 H02W0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C68:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06N0303 +arc: A4 V02S0301 +arc: B4 V02N0501 +arc: C4 H02E0601 +arc: D4 S1_V02N0401 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A3 V02S0501 +arc: B1 E1_H02W0301 +arc: B3 H00R0000 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: LSR0 H02W0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 Q0 +arc: V00T0100 F1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C71:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 + +.tile R52C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 V02S0501 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: B2 H02E0101 +arc: B3 W1_H02E0101 +arc: B4 H01E0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 V01N0001 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: B7 W1_H02E0301 +arc: C3 V02N0401 +arc: C4 V02S0201 +arc: C5 F6 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F0 +arc: V01S0100 F5 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C74:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: A0 F5 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: B0 F3 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: C0 F6 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: D0 V01S0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C75:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 V01N0001 + +.tile R52C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: A1 H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 H02E0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C77:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 N1_V01S0100 + +.tile R52C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0501 +arc: A5 V02S0101 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C79:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A3 V02N0501 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 S1_V02N0701 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F4 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 F3 +arc: V01S0100 Q5 +word: SLICEB.K1.INIT 0001000100000101 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00R0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: C1 W1_H02E0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D5 H02E0001 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: V00B0000 Q6 +word: SLICEC.K0.INIT 1000001010000010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1101110100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R52C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A3 V02S0701 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 F2 +arc: V01S0000 Q4 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 E1_H02W0301 +arc: A4 H02E0501 +arc: A6 S1_V02N0101 +arc: A7 E1_H02W0701 +arc: B3 V02S0101 +arc: B4 E1_H02W0101 +arc: B5 F1 +arc: B6 V02S0501 +arc: B7 H02W0301 +arc: C0 V02S0601 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: C7 W1_H02E0601 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 E1_H01W0100 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: S3_V06S0303 F5 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K1.INIT 0000000011110011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: B0 H02E0301 +arc: C5 N1_V02S0001 +arc: D1 V00B0100 +arc: D4 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R52C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A4 V00T0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B4 H02E0101 +arc: C0 H02E0601 +arc: C1 V02S0401 +arc: C4 H02W0601 +arc: D0 H02W0001 +arc: D1 N1_V01S0000 +arc: D4 F0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C85:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A4 H02E0501 +arc: A7 V02N0101 +arc: B4 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C4 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0000 F4 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 0000000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R52C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F7 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: B7 W1_H02E0301 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 F4 +arc: C7 V00T0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 F2 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C87:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A6 V00T0100 +arc: B0 H01W0100 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: C0 V02N0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C6 V02S0201 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEA.K0.INIT 1100000000001100 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1000001000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R52C88:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 + +.tile R52C89:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06S0303 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A3 F5 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: B1 V02S0301 +arc: B2 H01W0100 +arc: B3 F1 +arc: B5 W1_H02E0301 +arc: B6 H02W0301 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R52C90:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 S1_V02N0501 +arc: A2 V00T0000 +arc: A4 V00T0100 +arc: A6 V02N0101 +arc: B1 V01N0001 +arc: B2 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B6 V02N0501 +arc: C1 H02E0401 +arc: C2 F4 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1101000011011101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEB.K0.INIT 0100000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R52C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F5 +arc: A1 W1_H02E0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 H00R0100 +arc: B4 N1_V02S0501 +arc: B5 H00R0000 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R52C92:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: D0 H01E0101 +arc: D4 V01N0001 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F0 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 0010000000000010 +word: SLICEC.K0.INIT 0011000100110011 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R52C93:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: B0 H02W0301 +arc: C0 H02E0601 +arc: C5 S1_V02N0201 +arc: D0 N1_V02S0001 +arc: D5 H02E0201 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C94:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 E1_H02W0701 +arc: A3 H02W0701 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C3 H00L0100 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: D0 H02W0201 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 H02W0601 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R52C95:PLC2 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 F1 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C96:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 V06N0203 +arc: A2 V00T0000 +arc: A6 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C97:PLC2 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A2 N1_V02S0701 +arc: A3 H02W0501 +arc: A5 Q5 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C98:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R52C99:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 Q5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C100:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C101:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0701 +arc: B0 H02E0301 +arc: B1 Q1 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C102:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 E1_H02W0401 + +.tile R53C103:PLC2 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 V02S0301 +arc: W3_H06W0003 N3_V06S0003 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B7 V00B0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0011001100000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C104:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0401 N1_V01S0000 + +.tile R53C105:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0501 V06N0303 + +.tile R53C106:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C107:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C108:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 S3_V06N0203 + +.tile R53C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C110:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C112:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C113:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C114:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C115:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C116:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C117:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C14:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C15:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R53C20:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R53C21:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C23:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R53C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C27:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: V00T0000 H02W0001 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0401 Q4 +arc: LSR0 E1_H02W0301 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C28:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 H02W0701 +arc: V00T0100 V02N0701 +arc: A0 H00L0000 +arc: A4 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 H00L0000 +arc: C0 F4 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 S1_V02N0701 +arc: C0 F6 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C30:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 F7 +arc: A1 E1_H02W0501 +arc: A3 F7 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R53C31:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 F7 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: A7 V02N0101 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M3 H00L0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1101100011110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1101100011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C32:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06W0003 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V06N0203 +arc: A1 H02E0501 +arc: A3 H02E0701 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B5 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C3 H00R0100 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 1100010011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C33:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q7 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000001001100 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0100000011000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 V01N0101 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V01S0000 F6 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R53C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 V02N0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 H02E0201 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F3 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1111100001110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1101100011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C36:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02N0501 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0100 F7 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R53C37:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 V06N0303 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: C3 N1_V01S0100 +arc: C4 H02E0401 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C38:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 E1_H01E0001 +arc: A5 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B5 N1_V02S0701 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C39:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 F5 +arc: A5 V02N0101 +arc: B0 V01N0001 +arc: B1 H00R0100 +arc: B2 F1 +arc: B4 F1 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010000001110 +word: SLICEB.K0.INIT 0100010101000100 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K0.INIT 0000000011110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R53C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R53C40:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06N0303 + +.tile R53C41:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 V06N0303 +arc: A0 S1_V02N0701 +arc: A1 N1_V02S0701 +arc: A2 S1_V02N0701 +arc: A3 E1_H01E0001 +arc: A5 N1_V01S0100 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H00L0000 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 F1 +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V01S0000 F3 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010000010001000 +word: SLICEC.K1.INIT 0000110000001101 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000000001011100 +word: SLICED.K0.INIT 0001000101010000 +word: SLICEB.K0.INIT 0010001000100011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C42:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 V02S0501 +arc: A2 F5 +arc: A7 F5 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B5 F1 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C5 S1_V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D5 V02N0401 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 0000000001011100 +word: SLICED.K1.INIT 0000000001110100 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C43:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0001 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C44:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C45:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 S1_V02N0601 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 V00T0000 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B3 W1_H02E0301 +arc: B5 H00R0000 +arc: B7 V02N0701 +arc: C0 S1_V02N0401 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 W1_H02E0201 +arc: D5 E1_H01W0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C47:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B3 F1 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: C0 H02W0601 +arc: C1 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K0.INIT 0011001100001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R53C48:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02W0501 +arc: B3 N1_V02S0301 +arc: C3 N1_V02S0401 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C49:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00R0000 +arc: A3 F5 +arc: B5 H02E0301 +arc: C0 H00R0100 +arc: C1 W1_H02E0601 +arc: C3 N1_V01S0100 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q5 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0100 Q1 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 E1_H02W0701 +arc: A3 V00T0000 +arc: B3 H00R0100 +arc: C1 H02E0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D3 V00B0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: M0 V00T0100 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1100101010101010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02E0701 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: C0 F6 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V02S0701 +arc: A3 F7 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 H00L0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: M2 H02W0601 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 0011001101010000 +word: SLICEB.K1.INIT 0011001110101010 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICED.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R53C54:PLC2 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A7 V00T0100 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C55:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 V01N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R53C56:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R53C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: B1 V02S0301 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02W0201 +arc: F0 F5A_SLICE +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C58:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R53C59:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile R53C60:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A2 H02W0501 +arc: A5 H02W0501 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 Q4 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0601 Q6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C61:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 E1_H01W0000 +arc: B5 S1_V02N0501 +arc: D5 V02N0601 +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1011101100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R53C62:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 S1_V02N0501 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 E1_H02W0301 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C1 S1_V02N0401 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000101011001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V02N0501 +arc: A2 H00L0100 +arc: A7 V02N0301 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C64:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 S1_V02N0301 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H02W0001 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C65:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: B0 H02E0101 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 H00L0100 +arc: C4 V01N0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R53C66:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A3 H02W0501 +arc: B3 V02S0101 +arc: C0 H02W0601 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R53C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 S1_V02N0301 +arc: B3 V02S0101 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C5 W1_H02E0401 +arc: C6 V00T0100 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 1000100000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R53C68:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 N1_V02S0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C69:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 H02E0701 +arc: A5 V00T0100 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 V00B0100 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 N1_V02S0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C71:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 N1_V02S0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B1 H00R0100 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C72:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R53C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02S0501 +arc: A7 H02W0701 +arc: B2 H00R0100 +arc: B7 N1_V02S0701 +arc: C2 H02E0601 +arc: C7 V02S0201 +arc: D2 V02N0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F6 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000100000001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0100000001000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C74:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R53C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile R53C76:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: A5 V02S0101 +arc: C0 N1_V01S0100 +arc: D1 N1_V01S0000 +arc: D4 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C77:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: S3_V06S0203 F7 +arc: V00B0000 Q6 +arc: V01S0000 F4 +arc: V01S0100 Q6 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111100000101 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: C0 H02E0601 +arc: C5 H01E0001 +arc: D1 H01E0101 +arc: D4 V02S0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 E1_H02W0601 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 V02S0101 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K1.INIT 0101000000110000 +word: SLICED.K1.INIT 0000000011111110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: C1 E1_H01W0000 +arc: C4 V02S0001 +arc: C6 V02S0001 +arc: D0 V02S0001 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D5 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R53C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H01W0100 +arc: C0 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D2 H01E0101 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q5 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C82:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 Q1 +arc: B4 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 N1_V02S0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q6 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 F4 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H01E0001 +arc: C4 V02N0201 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: D0 V02N0201 +arc: D2 H01E0101 +arc: D3 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R53C84:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A2 V00T0000 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 H02W0501 +arc: B0 H02E0301 +arc: B2 V02S0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0501 +arc: C0 S1_V02N0601 +arc: C2 H00L0100 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0401 +arc: D0 W1_H02E0001 +arc: D2 V02N0001 +arc: D5 H01W0000 +arc: D6 H02W0001 +arc: D7 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0101 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEB.K0.INIT 1011000010111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: B0 V00T0000 +arc: B1 S1_V02N0101 +arc: B5 V02S0501 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C5 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D4 H02E0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A2 V01N0101 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B2 V02S0101 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 W1_H02E0601 +arc: C5 E1_H02W0601 +arc: D0 H02E0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D5 N1_V02S0401 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0100 +arc: N1_V02N0001 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0100000100000000 +word: SLICEC.K1.INIT 0111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R53C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile R53C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 F5 +arc: A5 H02E0501 +arc: A7 H02W0701 +arc: B2 V01N0001 +arc: B5 H00L0000 +arc: B7 S1_V02N0501 +arc: C2 V02N0401 +arc: C5 W1_H02E0601 +arc: C7 V00T0100 +arc: D2 V00B0100 +arc: D5 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 F7 +arc: A5 F7 +arc: A6 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F6 +arc: H01W0100 F3 +arc: V00T0000 F0 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0010000000000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0101010100000101 +word: SLICEC.K0.INIT 0000001100001111 +word: SLICEC.K1.INIT 0101010100000101 +word: SLICEA.K1.INIT 0000000001011111 +word: SLICEB.K0.INIT 1100000010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A3 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: C4 W1_H02E0601 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 V00T0000 +arc: D0 F2 +arc: D1 N1_V02S0201 +arc: D2 H01E0101 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: V00T0100 F1 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F5 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010100000000000 +word: SLICEA.K0.INIT 1000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0201 +arc: A3 E1_H01E0001 +arc: A7 V02S0101 +arc: B2 V02N0101 +arc: B3 N1_V02S0101 +arc: B7 H02W0301 +arc: C3 H02E0401 +arc: C7 E1_H02W0401 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0701 F7 +arc: S1_V02S0201 F2 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICEB.K0.INIT 0011001111001100 +word: SLICED.K1.INIT 0000000011011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R53C92:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 S1_V02N0701 +arc: A2 V02N0501 +arc: A3 S1_V02N0701 +arc: A4 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0501 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 F4 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F2 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 1000110010101111 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R53C93:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: A2 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: B0 H02W0101 +arc: B1 N1_V02S0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C1 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: V00T0000 F2 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02E0501 +arc: B0 E1_H02W0301 +arc: C0 V02N0401 +arc: D0 E1_H02W0201 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111100011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C95:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 H02W0001 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 H02W0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 V02S0301 +arc: B2 H02W0101 +arc: B3 N1_V02S0101 +arc: B5 V02N0501 +arc: C0 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0601 +arc: C5 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: D0 N1_V01S0000 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D5 F2 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R53C96:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 E1_H02W0501 +arc: B0 N1_V02S0301 +arc: C0 E1_H02W0401 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R53C97:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A6 H02E0501 +arc: B0 S1_V02N0301 +arc: B1 H00R0100 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B6 E1_H02W0301 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H02E0001 +arc: D3 N1_V02S0001 +arc: D4 H00L0100 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C98:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A2 V00T0000 +arc: A5 F7 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B1 N1_V02S0101 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 V02S0601 +arc: C5 H01E0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D5 V02N0601 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R53C99:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: A5 Q5 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V02S0601 +arc: C4 V02S0001 +arc: C5 N1_V02S0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 1010000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C100:PLC2 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile R54C101:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0103 S1_V02N0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 W3_H06E0303 + +.tile R54C102:PLC2 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B5 V01S0000 +arc: C0 H00L0000 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C103:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 V06S0303 + +.tile R54C104:PLC2 +arc: H01W0000 W3_H06E0103 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 + +.tile R54C105:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 + +.tile R54C106:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C108:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C109:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R54C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R54C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R54C20:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R54C25:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R54C26:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R54C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02W0701 +arc: V01S0000 S3_V06N0103 +arc: B0 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C29:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICED.K0.INIT 1100010010000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1101100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 H02E0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B5 F1 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 S1_V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICEA.K1.INIT 0001010100010000 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICED.K1.INIT 0000110100001100 +word: SLICEC.K1.INIT 0000000011110001 +word: SLICEA.K0.INIT 1101111110000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C31:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H01E0001 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A5 S1_V02N0101 +arc: B2 V01N0001 +arc: B6 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D5 V01N0001 +arc: D6 F2 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C32:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00R0100 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1110101000101010 +word: SLICED.K1.INIT 0000110011111100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R54C33:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B3 E1_H02W0101 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 Q0 +arc: V00B0100 F5 +word: SLICEB.K1.INIT 0111010001110100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0111011100001111 +word: SLICEA.K0.INIT 0111111100001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C34:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 W1_H02E0501 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 F2 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0010111010101010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V06S0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H01E0001 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02W0501 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEC.K1.INIT 0011001111110011 +word: SLICEC.K0.INIT 0011001111111010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111001101010001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R54C36:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 V06N0303 +arc: A2 V02N0701 +arc: A7 V00T0100 +arc: B2 H00L0000 +arc: B7 W1_H02E0101 +arc: C2 V02N0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D7 V02N0601 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F7 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R54C37:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B6 W1_H02E0101 +arc: C0 F6 +arc: C3 V02N0601 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H00R0000 +arc: D6 H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +word: SLICEB.K1.INIT 1111111111000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1100100000001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 V02N0101 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B6 V02S0501 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C4 V00T0000 +arc: C6 H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: V00T0000 F2 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0101000101010000 +word: SLICEA.K0.INIT 1110111011100010 +word: SLICEC.K0.INIT 0000101000001011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R54C39:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 N1_V02S0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 V02S0501 +arc: B7 F1 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 E1_H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F2 +arc: S1_V02S0001 Q0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1111111011110010 +word: SLICEB.K1.INIT 0000111000000010 +word: SLICED.K1.INIT 0100000011000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C40:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0701 +arc: A4 V00B0000 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B1 V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 N1_V02S0701 +arc: C0 V02N0601 +arc: C1 F6 +arc: C4 V00T0100 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0100 Q0 +arc: W1_H02W0101 F1 +word: SLICEC.K0.INIT 1110101000101010 +word: SLICED.K0.INIT 1100100001000000 +word: SLICEA.K1.INIT 0000001100001111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C41:PLC2 +arc: E1_H02E0501 V06S0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A2 S1_V02N0501 +arc: A4 V02N0301 +arc: A6 N1_V01N0101 +arc: B0 N1_V02S0101 +arc: B2 H00R0000 +arc: B4 W1_H02E0101 +arc: B6 H02W0301 +arc: C0 E1_H02W0601 +arc: C2 F6 +arc: C4 S1_V02N0201 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D4 V02N0401 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C42:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 Q3 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0601 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00L0000 H02W0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C45:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S3_V06S0103 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C46:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 V02N0701 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B3 V01N0001 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1101110100000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C47:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02S0401 +arc: A0 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H01E0101 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: V00B0000 Q4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C48:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 + +.tile R54C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 V00T0000 +arc: A7 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00L0000 +arc: C0 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C50:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R54C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02E0501 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: B2 W1_H02E0301 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: N1_V02N0001 F2 +arc: V00T0100 Q3 +word: SLICEB.K0.INIT 0101010100110000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R54C52:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R54C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: B1 V00B0000 +arc: B4 V01S0000 +arc: C0 H02E0401 +arc: C1 F4 +arc: C4 H02E0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 Q5 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C54:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: C3 H02W0401 +arc: C6 V02N0001 +arc: C7 H02W0601 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 0101010101010101 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R54C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 V02N0301 +arc: B4 E1_H02W0101 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D3 W1_H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0101010101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R54C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0303 E3_H06W0203 +arc: C1 V02N0601 +arc: D3 E1_H02W0201 +arc: D5 E1_H02W0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F5 +arc: V01S0100 F3 +word: SLICEA.K1.INIT 0000111100001111 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R54C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R54C58:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 H02W0701 +arc: C3 N1_V01N0001 +arc: D3 V02N0201 +arc: F3 F3_SLICE +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 1010000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R54C59:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 V02S0501 +arc: A3 V02N0701 +arc: A5 V00T0100 +arc: A7 H00L0000 +arc: B0 F3 +arc: B1 V02N0101 +arc: B3 W1_H02E0301 +arc: B5 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H00R0100 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: C5 H02W0401 +arc: C7 S1_V02N0001 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D5 V02S0401 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F0 +arc: V01S0100 F1 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C60:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 N1_V01S0100 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 E1_H02W0101 +arc: B6 V00B0100 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: D3 H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q3 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R54C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0000 V02N0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A7 F5 +arc: B0 E1_H01W0100 +arc: B1 V02N0301 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F3 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100101000001010 +word: SLICEB.K1.INIT 1100111100000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1100000000001100 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C62:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A4 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEC.K0.INIT 1010000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R54C63:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C64:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0701 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1011100000110000 +word: SLICEA.K1.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F7 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 V02S0301 +arc: B0 F3 +arc: B2 V02S0101 +arc: B3 V02N0101 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C0 F6 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 F2 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D6 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0003 F0 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 + +.tile R54C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: A0 V01N0101 +arc: A2 V02S0501 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 H00L0000 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 S1_V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C71:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 E1_H01W0100 +arc: B2 H02E0301 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C72:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0701 F7 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R54C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 V00B0000 +arc: B0 N1_V02S0301 +arc: B2 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R54C74:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: C6 E1_H02W0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F0 +arc: V01S0100 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000111100001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R54C75:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0401 V01N0001 + +.tile R54C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 + +.tile R54C77:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A2 N1_V02S0701 +arc: A5 E1_H02W0701 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 N1_V02S0201 +arc: D2 V02N0001 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0003 F0 +arc: S1_V02S0701 F7 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R54C78:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R54C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 W3_H06E0203 + +.tile R54C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B6 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C2 V02S0401 +arc: C3 V02N0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 W1_H02E0201 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K1.INIT 0000000011001111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 N1_V01N0001 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 F4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H02E0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 F5 +arc: B0 H01W0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D3 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: E1_H01E0001 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q1 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010110010101100 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R54C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: A2 S1_V02N0501 +arc: B0 W1_H02E0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 Q4 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R54C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0601 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A7 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 F3 +arc: B7 V00B0000 +arc: C1 S1_V02N0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C7 V01N0101 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00B0100 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000110000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A5 V00T0100 +arc: B5 V00B0100 +arc: C3 H02W0401 +arc: C5 H02E0401 +arc: D3 W1_H02E0001 +arc: D5 E1_H02W0201 +arc: E1_H01E0101 F5 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F3 +arc: V01S0000 F3 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R54C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 N1_V02S0701 +arc: A2 H02W0501 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: C1 E1_H02W0601 +arc: C2 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 W1_H02E0001 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0010000000010000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R54C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 H01E0001 +arc: A3 F7 +arc: A4 N1_V02S0301 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 V02S0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B4 V00B0100 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 0010000110000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B2 V01N0001 +arc: B3 F1 +arc: B4 F3 +arc: B5 V00B0100 +arc: B6 S1_V02N0701 +arc: C1 H02W0601 +arc: C2 V02S0601 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0201 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110000110011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 W1_H02E0701 +arc: A2 F7 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C0 N1_V02S0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 W1_H02E0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R54C91:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H00R0000 +arc: A1 V01N0101 +arc: A2 V02N0701 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 F3 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R54C92:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H02W0501 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: D0 V02S0001 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R54C93:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B1 V02N0301 +arc: B3 H01W0100 +arc: B4 H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D3 N1_V02S0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C94:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: C3 V02S0601 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: D0 V02S0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R54C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V02N0701 +arc: A2 S1_V02N0501 +arc: A3 F5 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 H00L0000 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 V02N0701 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: D0 V02S0201 +arc: D2 W1_H02E0201 +arc: D3 F0 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F7 +arc: S1_V02S0401 F4 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C96:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00R0000 +arc: B1 N1_V02S0301 +arc: C1 H00L0000 +arc: C5 V02N0201 +arc: D1 V02N0001 +arc: D5 V00B0000 +arc: E1_H02E0501 F5 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F1 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R54C97:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 N1_V02S0501 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0101 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: D0 N1_V02S0001 +arc: D2 F0 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M0 V00B0100 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F7 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1001100100001001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R54C98:PLC2 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02W0601 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 F5 +arc: A2 W1_H02E0701 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 V00T0100 +arc: B1 H00R0100 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V02S0601 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: M0 H01E0001 +arc: N1_V01N0001 F0 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1101000011011101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R54C99:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 W1_H02E0601 +arc: C4 H01E0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0101 Q3 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C100:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 S3_V06N0103 + +.tile R55C101:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 + +.tile R55C102:PLC2 +arc: N1_V02N0301 S1_V02N0201 + +.tile R55C103:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R55C104:PLC2 +arc: N1_V02N0401 S1_V02N0401 + +.tile R55C28:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 V02S0401 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B4 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 F4 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 E1_H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C29:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 F7 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B4 H02W0101 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 S1_V02N0201 +arc: D4 N1_V02S0601 +arc: D6 H02E0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICED.K1.INIT 1000100010100000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R55C30:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B2 H01W0100 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 V01N0001 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M3 H02E0201 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q3 +arc: V01S0000 F2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEB.K1.INIT 0000010100001100 +word: SLICEC.K1.INIT 0100010101000100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000111100000001 +word: SLICEA.K0.INIT 0011111100110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R55C31:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 H00L0100 +arc: A4 N1_V01S0100 +arc: A6 H02E0501 +arc: A7 N1_V01S0100 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D5 H02W0001 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 1100101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C32:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0601 +arc: C4 V00T0100 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 W1_H02E0201 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F4 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0010001111101111 +word: SLICEB.K1.INIT 0000111110101111 +word: SLICEC.K0.INIT 0011001111110101 +word: SLICEC.K1.INIT 0000111111001111 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C33:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02E0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V02N0701 +arc: C0 W1_H02E0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 F0 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: LSR0 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 F7 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1110001000000000 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R55C34:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06N0203 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 H02E0701 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 E1_H02W0101 +arc: B2 V02N0101 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C35:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: V00B0100 Q7 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R55C36:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B4 H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: V00B0100 F5 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C37:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 H02W0301 +arc: B5 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: D5 V00B0000 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: LSR1 E1_H02W0501 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C38:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0301 Q1 +arc: V00B0000 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1110110001001100 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICED.K1.INIT 0000000000101110 +word: SLICEA.K0.INIT 1111111111100010 +word: SLICEA.K1.INIT 0101010000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C39:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: B0 E1_H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0301 Q3 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C40:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06N0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 F7 +arc: A3 V02S0701 +arc: A5 V02S0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H01W0000 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q2 +arc: V01S0000 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEB.K0.INIT 0101010111110000 +word: SLICEB.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C41:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0701 +arc: A1 F7 +arc: A2 S1_V02N0701 +arc: A3 H02E0501 +arc: A4 V00T0100 +arc: A6 H02W0501 +arc: A7 E1_H02W0501 +arc: B1 E1_H01W0100 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0303 F6 +arc: V00T0100 F1 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C42:PLC2 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: H01W0100 F4 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: A1 V02S0701 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S1_V02S0501 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 F1 +arc: W1_H02W0501 Q7 +word: SLICEA.K1.INIT 1010101000001010 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 N1_V02S0701 +arc: A1 S1_V02N0501 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: B1 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: C4 V01N0101 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q0 +arc: V00T0100 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 0001001100000010 +word: SLICEC.K1.INIT 0000000011001101 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C45:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 S3_V06N0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: B0 S1_V02N0101 +arc: C0 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: N1_V02N0601 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEB.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R55C46:PLC2 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 V02N0601 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C47:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: C0 S1_V02N0401 +arc: C1 H00L0100 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0103 Q2 +arc: S3_V06S0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C48:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A3 V02S0501 +arc: B0 H02E0101 +arc: B3 E1_H01W0100 +arc: C0 E1_H02W0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 H02E0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R55C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B3 Q3 +arc: B7 V00B0000 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F7 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R55C50:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0601 V01N0001 +arc: B2 E1_H02W0101 +arc: C2 V02N0401 +arc: D2 V00B0100 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R55C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 + +.tile R55C52:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 V06S0103 +arc: D0 H02E0201 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: H01W0100 F5 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R55C53:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: A0 N1_V02S0501 +arc: A2 H02W0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N1_V02S0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A3 S1_V02N0501 +arc: A4 W1_H02E0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C55:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 N1_V01S0100 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C57:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A1 F5 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R55C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 N1_V01S0000 +arc: A1 H00R0000 +arc: A3 E1_H01E0001 +arc: A6 V02N0301 +arc: B1 V02N0101 +arc: B3 V01N0001 +arc: B6 E1_H02W0301 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C6 V00T0000 +arc: D1 H02E0001 +arc: D3 V02S0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEA.K1.INIT 0000001000001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R55C59:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H02E0701 +arc: A2 E1_H01E0001 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 V02S0301 +arc: B1 V02N0301 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00T0000 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C61:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C62:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C63:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H06E0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02E0701 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C64:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C65:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A0 H01E0001 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B2 V02N0101 +arc: C0 N1_V02S0401 +arc: C2 H00L0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEB.K0.INIT 1111001100000000 +word: SLICED.K1.INIT 1111010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R55C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: W3_H06W0203 E3_H06W0103 + +.tile R55C67:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0501 +arc: A2 V02S0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B2 H00R0100 +arc: B3 H00L0000 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C70:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06N0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V02S0501 +arc: B7 H02W0301 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R55C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H00R0000 +arc: A1 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: N1_V01N0101 F7 +arc: V01S0100 F6 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R55C73:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0601 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: D0 V02N0201 +arc: D1 V02S0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R55C74:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 H06W0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0103 N1_V01S0100 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R55C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 + +.tile R55C76:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: A1 H02W0501 +arc: A2 V02N0501 +arc: A3 S1_V02N0501 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B4 F1 +arc: B6 V02S0501 +arc: B7 E1_H02W0101 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: D1 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R55C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 H02W0601 +arc: C4 S1_V02N0201 +arc: C6 H02W0401 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 F2 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 F7 +arc: N1_V01N0101 F4 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 1000110010101111 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1010010100000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0501 +arc: A2 V01N0101 +arc: A5 V00T0000 +arc: A6 S1_V02N0101 +arc: B0 H02E0301 +arc: B2 V02N0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D0 V02S0001 +arc: D2 V00B0100 +arc: D5 V01N0001 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F5 +arc: M0 H02W0601 +arc: V00T0000 F2 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0303 + +.tile R55C80:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A4 F7 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 E1_H01E0101 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000110001000100 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: B0 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 0000001100000101 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R55C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 W1_H02E0701 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R55C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 N1_V02S0001 + +.tile R55C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A6 N1_V01S0100 +arc: B0 H02E0301 +arc: B3 W1_H02E0101 +arc: B4 H01E0101 +arc: B5 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: D0 S1_V02N0001 +arc: D2 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEB.K1.INIT 1001000010010000 +word: SLICEB.K0.INIT 0000111111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R55C86:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02N0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 F3 +arc: B1 H02E0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 F6 +arc: C1 V02S0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: V01S0100 F1 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C87:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 H02E0701 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: B0 H00R0100 +arc: B1 E1_H02W0301 +arc: B2 V01N0001 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D2 F0 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F6 +arc: H01W0100 F3 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R55C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A3 F5 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: B0 H02W0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B6 V00T0000 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H02W0401 +arc: C6 H02W0601 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: D6 F0 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0101010110101010 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 0011001111001100 +word: SLICED.K0.INIT 0100000100000000 +word: SLICEB.K1.INIT 0100000100000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C89:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B4 V02N0501 +arc: B5 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 F0 +arc: D3 S1_V02N0001 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F2 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0601 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 E1_H02W0701 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 H02E0501 +arc: B0 V02S0301 +arc: B1 W1_H02E0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0201 +arc: D2 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICEC.K0.INIT 0100000100000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C91:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B5 V02N0701 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: V00T0000 F0 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0101101001011010 +word: SLICEB.K0.INIT 0000000011000011 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000110010101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R55C92:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 F7 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 H02E0501 +arc: B0 F1 +arc: B1 N1_V02S0301 +arc: B2 H02W0101 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 F4 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 W1_H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 W1_H02E0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: N1_V01N0001 F3 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C93:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01S0100 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: C4 H01E0001 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D0 H02W0201 +arc: D1 F2 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N3_V06N0103 F1 +arc: S1_V02S0301 F3 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R55C94:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 F5 +arc: A2 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 S1_V02N0301 +arc: A7 V02N0101 +arc: B1 H00R0100 +arc: B2 V01N0001 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0501 +arc: C1 W1_H02E0401 +arc: C2 F6 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F2 +arc: M0 V00B0100 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R55C95:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0501 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0401 +arc: C2 H00R0100 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 E1_H01W0100 +arc: D6 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F0 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R55C96:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H02W0701 +arc: A5 H02W0701 +arc: B1 H02W0301 +arc: B5 H02W0301 +arc: C1 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: D1 V00B0100 +arc: D5 V02N0401 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEA.K1.INIT 1010111100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R55C97:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02N0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A3 V02S0501 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: B0 V02N0301 +arc: B1 N1_V02S0301 +arc: B3 V02S0301 +arc: B5 F3 +arc: B6 N1_V02S0501 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: D0 N1_V02S0001 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: N1_V01N0001 F5 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C98:PLC2 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: V00B0100 H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F7 +arc: A1 H00R0000 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 V02S0101 +arc: B4 H02E0101 +arc: B5 E1_H02W0301 +arc: B7 V02S0501 +arc: C0 F4 +arc: C1 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C7 V00B0100 +arc: D0 V01S0100 +arc: D1 H02W0001 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 H02W0001 +arc: D5 F2 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: V01S0100 F1 +arc: W1_H02W0201 F0 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R55C99:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: B0 V00B0000 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C100:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: B0 H01W0100 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 S1_V02N0401 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEC.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R56C101:PLC2 +arc: N3_V06N0203 V01N0001 +arc: V00B0100 V02N0301 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C102:PLC2 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 + +.tile R56C103:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C105:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R56C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R56C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R56C109:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R56C111:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C112:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R56C114:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R56C115:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R56C17:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R56C28:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 N1_V02S0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02N0301 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D3 H02W0201 +arc: D5 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C29:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 V02N0201 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V02S0501 +arc: A3 V02N0701 +arc: A5 V02N0101 +arc: A7 N1_V01S0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 F1 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 F3 +arc: C0 V02N0401 +arc: C2 H02W0601 +arc: C3 N1_V01S0100 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q6 +arc: LSR0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F6 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 1110000001000000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K1.INIT 1110000001000000 +word: SLICEA.K0.INIT 0000010100001100 +word: SLICED.K1.INIT 0010001000100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C30:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 V01N0101 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02N0101 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F6 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 0000000000111010 +word: SLICEB.K1.INIT 1110101000101010 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 1111111110101100 +word: SLICEA.K1.INIT 0000000010101100 +word: SLICED.K0.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C31:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 H01E0001 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111011110000000 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R56C32:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V01N0001 +arc: A0 W1_H02E0501 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B5 F1 +arc: B6 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0401 +arc: C3 H02E0401 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D3 H02W0201 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000110111111101 +word: SLICED.K1.INIT 0000111110101111 +word: SLICEA.K1.INIT 1011101100001011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C33:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 H01E0101 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02E0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B5 H02W0301 +arc: B6 V02S0501 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 H02E0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: N1_V01N0001 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011001111110101 +word: SLICEA.K1.INIT 0011001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R56C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02N0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 N1_V02S0501 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A6 H02E0501 +arc: A7 W1_H02E0701 +arc: B1 V02S0101 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0401 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C35:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 W1_H02E0701 +arc: B3 W1_H02E0101 +arc: C3 V02N0401 +arc: D3 H00R0000 +arc: F3 F3_SLICE +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C36:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A3 H02E0701 +arc: A4 E1_H01W0000 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 V00B0100 +arc: C0 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0201 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M5 H00L0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F6 +arc: V00B0100 Q5 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001110101111 +word: SLICEA.K1.INIT 0011001110111011 +word: SLICEB.K1.INIT 0000011101110111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1110101000101010 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0101 +arc: A5 H02W0701 +arc: B0 H02E0301 +arc: B1 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B4 V00B0100 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0000110111111101 +word: SLICEC.K1.INIT 0000101011111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C39:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A1 H02W0701 +arc: A3 F7 +arc: A7 S1_V02N0101 +arc: B1 Q1 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C40:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 F5 +arc: B1 H02E0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 W1_H02E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C41:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B4 V00B0100 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEC.K0.INIT 0011000111111101 +word: SLICEC.K1.INIT 0101000011111111 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R56C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C43:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A4 S1_V02N0301 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H02W0401 +arc: C2 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: V01S0100 F4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1110001010101010 +word: SLICEC.K0.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C44:PLC2 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 Q2 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100100001000000 +word: SLICED.K1.INIT 0101010100000100 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C45:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A4 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B4 W1_H02E0101 +arc: C0 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEC.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C46:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C47:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 N1_V02S0401 +arc: C2 H00L0000 +arc: C4 V00B0100 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C49:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0701 +arc: A0 W1_H02E0701 +arc: A5 V02N0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B5 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C50:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V02N0001 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02E0701 +arc: B0 V02N0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 F2 +arc: H01W0000 F2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C51:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K1.INIT 0101101000111100 +word: SLICEB.K0.INIT 1111111111110011 +word: SLICEB.K1.INIT 1010101010100010 +word: SLICED.K0.INIT 1010010111000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C52:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06N0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: A0 H02E0701 +arc: A3 V01N0101 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C53:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A6 S1_V02N0101 +arc: B6 N1_V01S0000 +arc: C6 V00T0000 +arc: D0 V00T0100 +arc: D4 H02E0001 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0401 F4 +arc: V01S0100 F0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R56C54:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A5 V02N0301 +arc: B5 H02E0301 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0201 +arc: D2 V02S0001 +arc: D5 H02E0201 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R56C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0001 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R56C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C4 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D5 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R56C57:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B4 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D4 V02S0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R56C58:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A3 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V02S0101 +arc: B3 H00R0000 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C59:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R56C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 W1_H02E0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: C4 V00B0100 +arc: C5 N1_V02S0201 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: E1_H02E0501 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0000001000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 F7 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A5 H02E0501 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0401 +arc: C4 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 W1_H02E0401 +arc: D1 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0000 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02S0301 +arc: B4 N1_V02S0501 +arc: C4 V02N0201 +arc: D4 E1_H02W0001 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 0001010000101000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C63:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 N1_V02S0701 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: B0 H02E0301 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 F1 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001010000101000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000001000100000 +word: SLICEA.K1.INIT 0000000011110101 +word: SLICED.K0.INIT 1100000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R56C64:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 F7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 W1_H02E0301 +arc: B7 V00T0000 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R56C65:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q7 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A2 W1_H02E0701 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 H02W0701 +arc: A6 H00R0000 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0301 +arc: B6 V02S0501 +arc: B7 H02E0101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C68:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H02E0201 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 H02W0701 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C70:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R56C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 V01N0001 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C72:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06N0103 +arc: A0 V02N0701 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C73:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 N1_V02S0101 +arc: B3 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C74:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C75:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 E1_H01E0001 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: D4 H02W0001 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R56C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 F7 +arc: A3 H02E0701 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0701 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: B7 H02W0101 +arc: C2 F6 +arc: C3 H02E0601 +arc: C4 E1_H01E0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S3_V06S0103 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 V06N0303 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A6 E1_H02W0501 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H02E0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D6 N1_V02S0601 +arc: D7 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C78:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 V00B0000 +arc: A5 F7 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: B7 S1_V02N0701 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C5 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D2 H00R0000 +arc: D5 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V00T0100 F1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 H01W0000 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C80:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A2 S1_V02N0501 +arc: A3 V02N0501 +arc: A5 V00T0100 +arc: A7 W1_H02E0501 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 W1_H02E0101 +arc: B7 H02W0301 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C5 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 H02W0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100111101000101 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R56C81:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: C4 N1_V02S0201 +arc: D1 V00B0100 +arc: D5 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C82:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 H02E0101 +arc: B4 H02E0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C2 H02E0401 +arc: D1 N1_V01S0000 +arc: D3 V00T0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C83:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0203 +arc: C0 N1_V02S0601 +arc: C5 N1_V02S0201 +arc: D1 N1_V02S0001 +arc: D4 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R56C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 F5 +arc: A1 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 F4 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: S3_V06S0103 F1 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 0101000001010101 +word: SLICEC.K0.INIT 1000101011001111 +word: SLICEB.K0.INIT 1100000000110000 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICEA.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 V00T0000 +arc: B2 H00L0000 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B5 N1_V02S0501 +arc: B6 F1 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 H00L0100 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: C6 F4 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 F0 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F3 +arc: N1_V02N0601 F6 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C86:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 H02W0701 +arc: A5 F7 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 F3 +arc: B6 V02N0701 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 F0 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D6 V01N0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000010000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0000000010000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C87:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 V06N0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 H00R0000 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V00T0000 +arc: C0 H00R0100 +arc: C1 V02S0601 +arc: C2 S1_V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R56C88:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 W1_H02E0501 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H02W0301 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 F4 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F2 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C89:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 V02S0101 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 H01W0100 +arc: B2 H02W0301 +arc: B3 W1_H02E0101 +arc: B4 V01S0000 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 N1_V02S0501 +arc: C0 E1_H02W0601 +arc: C1 V02S0401 +arc: C2 N1_V02S0401 +arc: C3 H00L0000 +arc: C4 F6 +arc: C5 S1_V02N0201 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 0100000000000100 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R56C90:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 V01N0101 +arc: A1 H00R0000 +arc: A3 H02E0701 +arc: A4 H02E0501 +arc: A5 N1_V01N0101 +arc: A6 H02W0501 +arc: A7 V00T0100 +arc: B0 W1_H02E0301 +arc: B1 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 H02W0301 +arc: B5 F3 +arc: B6 V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C4 S1_V02N0001 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: D0 S1_V02N0201 +arc: D1 V02S0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: V01S0000 F7 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C91:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0301 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 F3 +arc: B7 V01S0000 +arc: C0 N1_V02S0401 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 V01N0101 +arc: D0 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 0100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R56C92:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 H02E0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 W1_H02E0701 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02W0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: N1_V01N0101 F2 +arc: N1_V02N0301 F3 +arc: V00T0000 F0 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111010100110001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R56C93:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H02E0701 +arc: A5 V00T0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C1 H00L0000 +arc: C2 F6 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 V02N0001 +arc: C7 F4 +arc: D1 H02W0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R56C94:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B1 V02S0301 +arc: B2 E1_H02W0101 +arc: B3 H02W0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: C1 V02N0601 +arc: C2 H02W0601 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V00T0000 +arc: C7 V02S0001 +arc: D1 H00R0000 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H00L0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R56C95:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 F7 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: D4 F0 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1111010100110001 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 0010000000000010 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C96:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H02W0701 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R56C97:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0401 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D4 F0 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1010111100100011 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R56C98:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H01W0100 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00T0100 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R56C99:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: B0 F3 +arc: B1 F3 +arc: B2 F3 +arc: B3 E1_H01W0100 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1101000011010000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C100:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1000111110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C101:PLC2 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C102:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V01S0100 + +.tile R57C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C104:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C106:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C107:PLC2 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C108:PLC2 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 + +.tile R57C109:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R57C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R57C111:PLC2 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 + +.tile R57C113:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R57C114:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R57C26:PLC2 +arc: E1_H02E0201 E3_H06W0103 + +.tile R57C27:PLC2 +arc: H00R0000 H02W0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q5 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 E1_H02W0601 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C28:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: A0 H00L0000 +arc: A1 S1_V02N0501 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: C0 F6 +arc: C3 F6 +arc: C4 H01E0001 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K1.INIT 1111110011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C29:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06N0203 +arc: A0 F5 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 H02E0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 N1_V02S0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 E1_H01W0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F7 +arc: V00B0000 F4 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 1010000011000000 +word: SLICED.K0.INIT 1010100000001000 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 0000110100001100 +word: SLICEA.K0.INIT 1111101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C2:PLC2 +arc: V01S0100 S3_V06N0303 + +.tile R57C30:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 F7 +arc: A1 S1_V02N0501 +arc: A3 E1_H01E0001 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C3 H00R0100 +arc: C5 V00T0100 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICED.K1.INIT 0000000011001110 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICED.K0.INIT 1110010011001100 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C31:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H06W0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 V06N0203 +arc: A0 F5 +arc: A4 N1_V01S0100 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: N3_V06N0203 Q4 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 1111111110111000 +word: SLICED.K1.INIT 0000000010111000 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1110010011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C32:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: A2 W1_H02E0701 +arc: A3 H02W0501 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H01E0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 N1_V01S0100 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: S1_V02S0401 F6 +arc: V00T0000 Q0 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C33:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02W0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A5 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B5 V02S0701 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D5 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: V00B0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R57C34:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A3 H02W0501 +arc: A4 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F7 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C35:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 H02W0701 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 V02S0701 +arc: B7 F3 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0601 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0201 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 E1_H02W0601 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0601 F4 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1101100000000000 +word: SLICEB.K1.INIT 0001010100000100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000000011110001 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R57C36:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0011001110101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C37:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: A7 H02E0701 +arc: B0 F1 +arc: B1 H00R0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0301 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 1110001000000000 +word: SLICEA.K1.INIT 0000000010111010 +word: SLICEA.K0.INIT 1111101011001010 +word: SLICED.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000011110001 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C38:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B4 F1 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111011110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V01N0101 +arc: A2 V00B0000 +arc: A4 V00T0100 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: B6 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C2 F4 +arc: C4 V02N0001 +arc: C6 E1_H02W0401 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D4 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q2 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C40:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 E1_H02W0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 V02N0401 +arc: C1 S1_V02N0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 H02W0001 +arc: D2 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H01W0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0011111100000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C41:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A3 H02E0701 +arc: A4 V00T0100 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0010000010100000 +word: SLICEA.K1.INIT 0100000011000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0010101000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C42:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V02S0701 +arc: A5 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 H01E0101 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M3 H02W0201 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 1100100001000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C43:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 V06N0303 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02W0601 +arc: C1 H02E0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011000011111100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011000011111100 +word: SLICEB.K0.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R57C44:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111101111111000 +word: SLICEB.K1.INIT 0000101100001000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111111001010 +word: SLICEC.K1.INIT 0000000011001010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 0100010011101110 +word: SLICED.K0.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R57C45:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C46:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A2 V02N0701 +arc: A5 H02E0701 +arc: A7 F5 +arc: B0 H02E0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEC.K0.INIT 1111000000110000 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEB.K0.INIT 0011001111110101 +word: SLICEB.K1.INIT 0011001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R57C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 Q6 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C48:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: B0 S1_V02N0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C49:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A3 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1011100000110000 +word: SLICEA.K1.INIT 1110001000100010 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C50:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C51:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 N1_V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0101 +arc: B5 V00B0100 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C52:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V02S0101 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 N1_V02S0301 +arc: B0 H02E0101 +arc: B1 H02W0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C54:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: D4 W1_H02E0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 0110010101101010 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0101011010100110 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 H00R0000 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 H01E0101 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 0011011011000110 +word: SLICEA.K0.INIT 0011110001100110 +word: SLICEB.K1.INIT 0001111011010010 +word: SLICEC.K1.INIT 0110010101101010 +word: SLICEA.K1.INIT 0110011000111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 H02W0701 +arc: A3 S1_V02N0501 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B0 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: E1_H02E0601 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C57:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H01E0101 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 W1_H02E0701 +arc: A2 H02W0501 +arc: A3 S1_V02N0501 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: B2 H00R0100 +arc: B3 W1_H02E0301 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: V01S0100 F1 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02W0701 +arc: A5 V02S0101 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B1 H00R0100 +arc: B5 S1_V02N0501 +arc: B7 V02S0701 +arc: C5 E1_H02W0401 +arc: C7 H02E0601 +arc: D5 W1_H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M4 V00B0100 +arc: S1_V02S0101 F1 +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: W3_H06W0103 F1 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C61:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0701 +arc: A1 F5 +arc: A2 F7 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 W1_H02E0701 +arc: A6 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: B1 F3 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0301 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 W1_H02E0001 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V02N0201 F2 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R57C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: B4 H02W0301 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C4 S1_V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C63:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 S1_V02N0701 +arc: A2 H02E0701 +arc: A3 F5 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 H02W0701 +arc: B1 N1_V02S0101 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 V02N0701 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C6 H01E0001 +arc: C7 V00T0100 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02N0401 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N1_V01N0101 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0000011001100000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R57C64:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V01N0101 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 W1_H02E0101 +arc: B7 H02W0101 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0601 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q3 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010000101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C65:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0701 Q5 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1011100010111000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111011100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C66:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 H02W0701 +arc: A7 H00R0000 +arc: B0 V02S0101 +arc: B1 E1_H02W0101 +arc: B4 V02N0701 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000000000100 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 0011001111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C67:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0501 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0301 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R57C68:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 H02W0101 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: F2 F2_SLICE +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 V02S0501 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C70:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C71:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C72:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02W0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0100 +arc: A1 W1_H02E0501 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B5 E1_H02W0101 +arc: C5 W1_H02E0401 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M4 V00B0100 +arc: N3_V06N0303 F6 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011001100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C73:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02W0701 +arc: A3 F7 +arc: A7 V02S0301 +arc: B1 V02N0101 +arc: B3 E1_H01W0100 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C7 S1_V02N0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: V00T0100 F1 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C74:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 W1_H02E0701 +arc: A3 F7 +arc: A5 V00T0100 +arc: A6 W1_H02E0501 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 F1 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C3 F6 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V02N0401 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000011001100000 +word: SLICEA.K0.INIT 0000001000001000 +word: SLICEA.K1.INIT 0001010000101000 +word: SLICEB.K0.INIT 0001001001001000 +word: SLICED.K0.INIT 0000011001100000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R57C75:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 W1_H02E0101 +arc: B3 F1 +arc: B4 V02N0701 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V00T0100 F3 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010110000001100 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 0000011001100000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R57C76:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 E1_H02W0101 +arc: C0 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C77:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 F7 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C2 H00L0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C78:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A4 V00T0100 +arc: B0 V00B0000 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F5 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1010111100000000 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R57C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 F7 +arc: A6 H00L0000 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B6 F3 +arc: B7 V00T0000 +arc: C2 V02N0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V01S0000 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A4 E1_H02W0701 +arc: A5 F7 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B3 W1_H02E0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C3 V02N0401 +arc: C5 F4 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 H02W0001 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N1_V01N0001 F0 +arc: V01S0000 F5 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1100010000110001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1000100001000100 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C81:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: B0 V00T0000 +arc: B3 S1_V02N0101 +arc: B6 H02W0301 +arc: C0 H00L0100 +arc: D0 V02N0001 +arc: D3 V00B0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R57C82:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02W0201 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A2 F7 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 F3 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 F6 +arc: C3 W1_H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: D0 V02S0001 +arc: D2 F0 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: N1_V01N0001 F2 +arc: V00B0000 F4 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R57C83:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R57C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A0 E1_H02W0701 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 F0 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000010000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 V02N0701 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 F3 +arc: B6 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 S1_V02N0201 +arc: D3 W1_H02E0201 +arc: D4 F0 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: V00B0000 F6 +arc: V00T0100 F1 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R57C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 F5 +arc: A1 W1_H02E0701 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 F7 +arc: A7 V00T0100 +arc: B1 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02S0701 +arc: B5 V00B0100 +arc: B6 F3 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 V00B0100 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 S1_V02N0201 +arc: D4 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R57C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0100 V02S0101 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 F5 +arc: A4 H02W0501 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0301 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 F1 +arc: C0 H02W0401 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C7 F4 +arc: D0 V02S0201 +arc: D1 V02S0001 +arc: D2 S1_V02N0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: S1_V02S0001 F2 +arc: V00T0100 F3 +arc: V01S0100 F7 +word: SLICED.K0.INIT 0110011001100110 +word: SLICEA.K0.INIT 0100000100000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R57C88:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 E3_H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A2 F5 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B3 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 V02S0501 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R57C89:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 E1_H02W0401 +arc: C7 W1_H02E0601 +arc: D0 V01S0100 +arc: D1 F2 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02S0401 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F0 +arc: V00B0000 F6 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R57C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 S1_V02N0501 +arc: A2 F5 +arc: A3 W1_H02E0701 +arc: A4 V00T0100 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 W1_H02E0301 +arc: B6 H02W0101 +arc: B7 V00B0100 +arc: C1 V02S0401 +arc: C2 F4 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1000001001000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R57C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A2 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 E1_H02W0701 +arc: A7 S1_V02N0301 +arc: B5 H00L0000 +arc: B6 W1_H02E0301 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C92:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 W1_H02E0501 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F5 +arc: V01S0100 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C93:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B5 H02E0301 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: N1_V02N0201 F0 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C94:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 S1_V02N0301 +arc: B2 H02E0301 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0301 F1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F6 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F5 +arc: V01S0100 F0 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R57C95:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0301 +arc: A6 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: C4 V00T0100 +arc: C6 S1_V02N0201 +arc: C7 W1_H02E0601 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W3_H06W0003 F0 +word: SLICED.K0.INIT 0000100000000100 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R57C96:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A6 W1_H02E0701 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B3 V02N0301 +arc: B6 F3 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C6 V02N0201 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D3 H02E0201 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M0 V00T0100 +arc: S1_V02S0201 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000010000000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R57C97:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: B5 W1_H02E0301 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R57C98:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 E1_H02W0701 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 Q3 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R57C99:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: C0 W1_H02E0401 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 F2 +arc: V01S0000 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C100:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A0 H02E0701 +arc: A2 H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1011100010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C101:PLC2 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0501 +arc: B0 H02E0301 +arc: B3 V01N0001 +arc: C0 W1_H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 F3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R59C102:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0201 H01E0001 + +.tile R59C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R59C104:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R59C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C107:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: C6 V02S0001 +arc: D6 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: N3_V06N0303 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R59C108:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C109:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C110:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 + +.tile R59C111:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C113:PLC2 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C115:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C116:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C117:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C14:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C15:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R59C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R59C21:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C23:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R59C26:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R59C28:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02N0701 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 S1_V02N0701 +arc: C0 F6 +arc: C3 F6 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1010101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R59C29:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S1_V02N0501 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K1.INIT 1100100000001000 +word: SLICEC.K1.INIT 0000001100100010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEB.K1.INIT 1110111010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C30:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0101 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEC.K1.INIT 1010110011001100 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C31:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A5 H02W0501 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B7 V02N0701 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICED.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1101000011011101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C32:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: A0 W1_H02E0701 +arc: A1 H02W0701 +arc: A2 H01E0001 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0501 +arc: A7 V00T0100 +arc: B1 E1_H02W0101 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 W1_H02E0001 +arc: D2 S1_V02N0001 +arc: D3 H01E0101 +arc: D4 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0103 Q2 +arc: V00T0100 F3 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0111010001110111 +word: SLICEC.K1.INIT 0111010101110101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 + +.tile R59C33:PLC2 +arc: E1_H02E0301 V02S0301 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 H01E0001 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A6 V02N0101 +arc: B0 V02N0301 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F5 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001111011111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICED.K0.INIT 0011001111110101 +word: SLICED.K1.INIT 0011001111110011 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R59C34:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B6 H02W0101 +arc: B7 V02N0501 +arc: C0 F6 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0501 F7 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111110011111010 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICED.K0.INIT 0011001100010000 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEC.K0.INIT 0101010111110011 +word: SLICEC.K1.INIT 0101010111110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R59C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 V02N0101 +arc: A7 N1_V01N0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 N1_V02S0301 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F0 +arc: N3_V06N0203 F4 +arc: V00T0000 F2 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000001100001111 +word: SLICEB.K1.INIT 1100100000001000 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110101 +word: SLICEA.K1.INIT 0011001111110011 +word: SLICEC.K0.INIT 0000110000001101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R59C36:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 V06N0303 +arc: A1 H02E0501 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 F1 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C37:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 F7 +arc: A5 V02S0301 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 H02E0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V01S0000 F6 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100000010001000 +word: SLICEC.K1.INIT 0000000000111010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R59C38:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 V01S0000 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C6 V01N0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICEC.K1.INIT 0000001100100010 +word: SLICEB.K0.INIT 1111111010101110 +word: SLICEB.K1.INIT 0101010000000100 +word: SLICEA.K1.INIT 0100010101000100 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICED.K1.INIT 1011111110000000 +word: SLICED.K0.INIT 0000111100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C39:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 W1_H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1111111110111000 +word: SLICEC.K1.INIT 0000000010111000 +word: SLICED.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111011110000000 +word: SLICEB.K1.INIT 1110010011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C3:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R59C40:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H02W0101 +arc: A1 V02S0701 +arc: A5 V00B0000 +arc: A7 W1_H02E0501 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B5 H02W0301 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C5 V00T0100 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: V01S0100 F0 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100010011110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C41:PLC2 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 H02E0101 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 N1_V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: V00T0100 F1 +word: SLICEB.K1.INIT 1101000010000000 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1000000010101010 +word: SLICEC.K0.INIT 0100010100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R59C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 H02W0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C3 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEC.K1.INIT 1111111110100000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111101010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0501 +arc: A2 V01N0101 +arc: A5 H02E0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0101 +arc: B3 Q3 +arc: B7 H02W0301 +arc: C0 V02N0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 H02E0601 +arc: C5 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101011001010 +word: SLICED.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A5 V02S0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 E1_H02W0301 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 Q5 +arc: N3_V06N0303 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F6 +arc: V00B0000 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111111110101100 +word: SLICED.K1.INIT 0000000010101100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0011001111110000 +word: SLICEC.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C45:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 V06N0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B5 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 1101100011110000 +word: SLICEB.K1.INIT 1010110011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C46:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 V06S0303 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C47:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V00T0000 +arc: A6 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B3 E1_H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S1_V02S0201 Q0 +arc: V01S0100 F2 +arc: W1_H02W0001 F2 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1100000010101010 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEB.K0.INIT 1010000011110000 +word: SLICEB.K1.INIT 1101000011011101 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R59C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H01E0001 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B6 H02E0101 +arc: C0 F6 +arc: C1 F6 +arc: C2 N1_V01N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D6 N1_V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0100 F7 +word: SLICED.K0.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R59C50:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A5 V00T0100 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0301 F3 +arc: V01S0000 Q2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111001111111111 +word: SLICEC.K1.INIT 0101000101010101 +word: SLICED.K0.INIT 1111111100111111 +word: SLICED.K1.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C51:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 H00L0000 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B1 H02E0301 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D4 V02S0401 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0101101000111100 +word: SLICEB.K0.INIT 1111111101011111 +word: SLICEB.K1.INIT 0000000011011111 +word: SLICEC.K0.INIT 1111111101011111 +word: SLICEC.K1.INIT 0000000011011111 +word: SLICEA.K1.INIT 1001100111000011 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R59C52:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B1 V02S0101 +arc: B3 H00R0100 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 H02W0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 N1_V02S0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111111101011111 +word: SLICEA.K1.INIT 0011001100010011 +word: SLICEB.K0.INIT 1111111101011111 +word: SLICEB.K1.INIT 0011001100010011 +word: SLICEC.K0.INIT 1111111101011111 +word: SLICEC.K1.INIT 0000000011011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C53:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0100 +arc: A2 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 N1_V02S0101 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B6 H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 F6 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D2 H02W0001 +arc: D3 F2 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0101 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0203 F7 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K1.INIT 0000100000000100 +word: SLICED.K0.INIT 0011110001011010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C54:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A7 H00R0000 +arc: B1 E1_H02W0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 H02W0101 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 V02S0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 H01E0101 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0010000000000010 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C55:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 H02E0101 +arc: B2 F3 +arc: B3 H00R0000 +arc: B4 F1 +arc: B5 H00L0000 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02W0401 +arc: C3 V02S0401 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 F2 +arc: D7 H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000000010000 +word: SLICED.K0.INIT 0000100100000000 +word: SLICEA.K1.INIT 0101011010011010 +word: SLICEC.K1.INIT 0000000011000011 +word: SLICEB.K1.INIT 0011110001011010 +word: SLICED.K1.INIT 0000100000000010 +word: SLICEB.K0.INIT 0011000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R59C56:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: V00B0100 H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V02S0301 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 V02N0501 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C57:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: V01S0000 F7 +arc: V01S0100 F1 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C58:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 N1_V02S0101 +arc: A7 V02S0301 +arc: B0 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +arc: V01S0100 F0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C59:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 H02W0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0701 +arc: A1 S1_V02N0701 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F6 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H00R0100 +arc: B1 V02S0101 +arc: B6 H01E0101 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: V01S0000 F1 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100101011001010 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A2 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 N1_V02S0401 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0101 +arc: B4 W1_H02E0101 +arc: B5 F3 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00T0100 +arc: N1_V01N0101 F0 +word: SLICED.K0.INIT 0000011001100000 +word: SLICEB.K0.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEB.K1.INIT 0001001001001000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010000101000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 F6 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F2 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEC.K0.INIT 0001010000101000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C65:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A5 S1_V02N0101 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 V02S0301 +arc: B2 H00R0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 F1 +arc: C0 S1_V02N0401 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 E1_H02W0001 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0001010000101000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEB.K0.INIT 0010000010000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R59C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: C1 H02E0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: N1_V01N0101 F1 +word: SLICEA.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R59C67:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00T0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F4 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C68:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 V00T0000 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C69:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 H02E0101 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0501 F7 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000111100001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 S1_V02N0701 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: V01S0000 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C71:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 V02S0501 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C72:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 V00T0100 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0101 F7 +arc: N3_V06N0103 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C73:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 H02E0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +arc: V01S0100 F0 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C74:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00R0000 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: B0 E1_H02W0301 +arc: B1 V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0301 F1 +arc: V01S0100 F0 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0001001001001000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C75:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 F5 +arc: A5 H02W0501 +arc: A7 V02N0101 +arc: B1 V00B0000 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C1 H00R0100 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: D1 V00B0100 +arc: D5 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: N1_V01N0001 F1 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0001001001001000 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C76:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C77:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 N1_V02S0701 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: C0 H00R0100 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C78:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 Q6 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C79:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A2 V02N0701 +arc: B0 S1_V02N0101 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 H02W0101 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 F1 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1100000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R59C80:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: B0 V02S0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: V00T0000 F0 +arc: V01S0000 Q6 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R59C81:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0501 +arc: A4 V00T0100 +arc: A7 V02S0301 +arc: B0 H02W0301 +arc: B1 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0003 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000000010100011 +word: SLICEA.K1.INIT 0000000011001111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R59C82:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A2 V01N0101 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0100 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICED.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R59C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A5 V00T0000 +arc: B0 H02W0101 +arc: B2 H00L0000 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C2 H00R0100 +arc: C5 W1_H02E0601 +arc: C7 N1_V02S0001 +arc: D0 H02E0201 +arc: D2 N1_V02S0201 +arc: D5 W1_H02E0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F0 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R59C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0101 +arc: A6 N1_V02S0301 +arc: B6 W1_H02E0301 +arc: C6 S1_V02N0201 +arc: D6 V02N0401 +arc: F6 F6_SLICE +arc: N1_V02N0401 F6 +word: SLICED.K0.INIT 0100000000000100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0501 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0701 +arc: A5 V00T0000 +arc: B4 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: E1_H01E0001 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F6 +arc: S3_V06S0003 F3 +arc: V01S0000 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A3 E1_H02W0501 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 V02N0301 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F0 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C87:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A3 W1_H02E0701 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B4 E1_H02W0301 +arc: B7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F0 +arc: N1_V02N0101 F1 +arc: N3_V06N0003 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B4 H00L0000 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: E1_H01E0101 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R59C89:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: A1 S1_V02N0501 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 V02N0101 +arc: B4 V00B0100 +arc: B5 F1 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D4 V00B0000 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F1 +arc: V00B0000 F6 +arc: V00B0100 F7 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R59C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02N0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0701 V02N0701 +arc: A0 N1_V02S0501 +arc: A1 F7 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 W1_H02E0701 +arc: A5 E1_H02W0501 +arc: A6 W1_H02E0701 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 V02S0601 +arc: C1 F6 +arc: C2 W1_H02E0601 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 V00B0100 +arc: C6 W1_H02E0401 +arc: C7 H02E0601 +arc: D0 H02W0001 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 N1_V02S0401 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R59C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 V01N0101 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C3 F4 +arc: C4 E1_H02W0601 +arc: C5 H01E0001 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 F0 +arc: D4 W1_H02E0001 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICED.K1.INIT 0000000011000011 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R59C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 N1_V02S0501 +arc: A2 F7 +arc: A3 W1_H02E0701 +arc: A4 N1_V02S0101 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 F1 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02S0401 +arc: C1 H00R0100 +arc: C2 F4 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D0 N1_V02S0001 +arc: D1 V02S0001 +arc: D2 F0 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R59C93:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A1 N1_V02S0501 +arc: A2 E1_H01E0001 +arc: A3 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 V02S0101 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 F1 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V02S0601 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 F2 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 1010000000001010 +word: SLICEA.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R59C94:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: B1 Q1 +arc: B4 V02S0701 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V02N0001 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 H02E0201 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000110000100011 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0000111111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R59C95:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A3 W1_H02E0501 +arc: A4 V02S0101 +arc: A6 H02W0701 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B6 V00T0000 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEC.K0.INIT 1100010000110001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C96:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 H02E0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H02W0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: B5 N1_V02S0501 +arc: C0 S1_V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V02S0001 +arc: D5 V02N0401 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C97:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: C0 H02E0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R59C98:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R59C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 S1_V02N0501 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q5 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q5 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C3:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 + +.tile R5C40:PLC2 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: B0 H02W0301 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V01S0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: F0 F5A_SLICE +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C42:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1000101110111000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C43:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A4 V00T0100 +arc: B0 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C2 S1_V02N0401 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q6 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A5 Q5 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00L0000 +arc: B4 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C45:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 V02N0501 +arc: A3 H00L0100 +arc: A4 H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0701 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B4 S1_V02N0501 +arc: B6 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1110010011100100 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C46:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 V02N0501 +arc: A4 E1_H02W0701 +arc: A5 Q5 +arc: A6 V02S0301 +arc: B0 V02S0101 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0001 +arc: D2 V00T0100 +arc: D3 H01E0101 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C47:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 N1_V02S0001 +arc: D3 V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100110001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C48:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H01E0001 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A4 V02S0101 +arc: B0 E1_H01W0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100010111001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C49:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0100 +arc: A6 S1_V02N0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0501 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1101000111100010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C50:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 E1_H01W0100 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 V02N0501 +arc: C0 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q5 +arc: V01S0000 F4 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C51:PLC2 +arc: H00L0000 V02N0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0401 E1_H02W0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C53:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 + +.tile R60C100:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02E0201 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 W1_H02E0601 +arc: V01S0000 S3_V06N0103 +arc: C7 V02S0001 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00R0100 +arc: M2 W1_H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R60C101:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 V06N0203 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1000111110000000 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K0.INIT 1010110000001100 +word: SLICEC.K1.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R60C102:PLC2 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 + +.tile R60C103:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R60C105:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R60C106:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R60C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R60C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C115:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R60C20:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R60C25:PLC2 +arc: E1_H02E0501 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R60C26:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R60C27:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 Q3 +arc: LSR1 E1_H02W0301 +arc: M3 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C28:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B3 H00L0000 +arc: B6 E1_H02W0101 +arc: C0 F6 +arc: C3 F6 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R60C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 N1_V01S0000 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D7 F2 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEC.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K1.INIT 0000101100001010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V01N0001 +arc: A2 H02W0501 +arc: A3 E1_H01E0001 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B4 W1_H02E0101 +arc: B5 F3 +arc: B6 H01E0101 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C4 V01N0101 +arc: C5 H02E0401 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0201 +arc: D3 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F5 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0601 F6 +arc: V01S0000 F7 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEC.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 0000010101000100 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110110001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 V02N0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B3 F1 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B7 S1_V02N0501 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 W1_H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0201 +arc: D2 V00T0100 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F7 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 1110001010101010 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1000101010000000 +word: SLICED.K1.INIT 1100111101000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C32:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A2 V02N0501 +arc: A4 V02N0101 +arc: A6 F7 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0101111100000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0011000111111101 +word: SLICEB.K1.INIT 0011111100001111 +word: SLICEA.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C33:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 F5 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B1 F3 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M4 V00T0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0201 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 H00L0100 +arc: C3 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +word: SLICED.K1.INIT 1011111110000000 +word: SLICEA.K1.INIT 1110101000101010 +word: SLICEC.K1.INIT 0101111101010000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1110101000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C35:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0501 +arc: A1 H02W0501 +arc: A2 H02E0701 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V02S0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q5 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R60C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 F5 +arc: A2 H02W0701 +arc: A5 S1_V02N0101 +arc: B1 H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F2 +arc: LSR0 H02E0501 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: V01S0000 F5 +arc: V01S0100 Q6 +word: SLICEA.K1.INIT 0111011101000100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 0011001111110101 +word: SLICEB.K1.INIT 0011001111110011 +word: SLICEC.K1.INIT 1011000010111011 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C37:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B4 V02N0701 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 F6 +arc: C3 F6 +arc: C4 V02N0001 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C38:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0000 +arc: A3 V02N0701 +arc: A5 V00T0100 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0101 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 W1_H02E0201 +arc: D3 F2 +arc: D5 E1_H02W0201 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 Q4 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000110010000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C39:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: A1 H02E0701 +arc: A5 E1_H02W0501 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 E1_H01W0100 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D3 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 1111100001110000 +word: SLICED.K1.INIT 0000111111001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C40:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0501 +arc: A4 H02E0501 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 E1_H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: V01S0000 F2 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000111110111011 +word: SLICEA.K1.INIT 0000111110101111 +word: SLICEB.K0.INIT 0010001111101111 +word: SLICEB.K1.INIT 0101111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R60C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B3 H00L0000 +arc: B6 V02N0501 +arc: B7 V00T0000 +arc: C1 H00L0100 +arc: C3 V02N0401 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D1 H02W0201 +arc: D3 V00T0100 +arc: D6 E1_H02W0001 +arc: D7 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F6 +arc: S3_V06S0203 F7 +arc: V01S0000 F3 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R60C42:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 N1_V02S0501 +arc: A4 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B4 V02N0501 +arc: B5 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D2 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +arc: S1_V02S0501 F5 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C43:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 E1_H01E0001 +arc: A2 N1_V02S0501 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 V02S0201 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +word: SLICEB.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEB.K0.INIT 1011000010000000 +word: SLICED.K1.INIT 0011001100000010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000100011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C44:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B1 S1_V02N0101 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 V02S0401 +arc: D7 H01W0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001010100000100 +word: SLICED.K0.INIT 0000110100001100 +word: SLICEC.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 0101000001010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C45:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0201 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 F3 +arc: B7 W1_H02E0101 +arc: C1 H00L0000 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 F4 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1000101010000000 +word: SLICED.K0.INIT 0001001100010011 +word: SLICED.K1.INIT 1010100000100000 +word: SLICEC.K0.INIT 0000111111011101 +word: SLICEC.K1.INIT 0101010111011101 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 1110010011001100 +word: SLICEB.K0.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C46:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 E3_H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A2 V01N0101 +arc: A7 V02S0101 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D7 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR1 V00T0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0101110001011111 +word: SLICEB.K1.INIT 0011111100110011 +word: SLICED.K1.INIT 1101000011011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C47:PLC2 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 S1_V02N0501 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: C0 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEB.K0.INIT 0011101000111111 +word: SLICEB.K1.INIT 0011111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R60C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 H01E0001 +arc: A2 H02W0701 +arc: A3 H01E0001 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 F3 +arc: V01S0100 F3 +arc: W1_H02W0201 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEB.K1.INIT 1010111100000000 +word: SLICEB.K0.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R60C49:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 H02W0701 +arc: A3 E1_H02W0501 +arc: A4 E1_H01W0000 +arc: A6 F7 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 H02W0601 +arc: C4 V02S0001 +arc: C5 W1_H02E0401 +arc: C6 V00T0000 +arc: C7 H02W0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: V00T0000 F2 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1100001110011001 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICED.K1.INIT 0100101101111000 +word: SLICEB.K1.INIT 0001111011010010 +word: SLICEB.K0.INIT 1100001110100101 +word: SLICED.K0.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R60C51:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 V00T0000 +arc: B2 S1_V02N0301 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 V01N0001 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: V00B0100 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1111111101011111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 0100101101111000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C52:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 H01E0001 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B1 E1_H01W0100 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C1 V02N0601 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 H02E0001 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: M0 V00B0000 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 0000000010000010 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C53:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H02E0501 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H02W0301 +arc: B6 V02S0701 +arc: B7 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 N1_V01S0100 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 N1_V02S0001 +arc: D0 V02S0201 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V00T0100 +arc: D4 N1_V02S0401 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1010110001010011 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C54:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02N0101 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A4 F7 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C4 H02E0601 +arc: C5 V00T0100 +arc: C6 H02W0401 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0100000000000100 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0101101000111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C55:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 N1_V02S0701 +arc: A1 V02N0701 +arc: A3 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 F7 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0101 +arc: B3 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 F1 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0011010111001010 +word: SLICEB.K1.INIT 1100001110100101 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K1.INIT 0011010111001010 +word: SLICEA.K1.INIT 0011110001011010 +word: SLICEC.K0.INIT 1010110001010011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R60C56:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 + +.tile R60C57:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V01S0000 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0003 Q3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C58:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A4 S1_V02N0101 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 Q3 +arc: B4 H01E0101 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D6 H02W0201 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q3 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C59:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H00L0000 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 V06N0303 +arc: A4 V00T0100 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 N1_V01S0100 +arc: B1 Q1 +arc: B5 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R60C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 N1_V02S0701 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0401 +arc: C2 H02E0601 +arc: C4 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D7 H00R0100 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000011001100000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C64:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V02S0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R60C66:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V01N0101 +arc: A4 V02S0301 +arc: A6 E1_H02W0501 +arc: B2 V02S0101 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C2 H02E0401 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 H02E0001 +arc: D4 V02S0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C67:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R60C68:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06W0003 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: B1 Q1 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C69:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H02W0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 F3 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 W1_H02E0601 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0001 +arc: D7 H02E0001 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C70:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A7 H02E0701 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C71:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A7 H02E0701 +arc: B0 H01W0100 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C72:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 H00R0100 +arc: C5 H02E0401 +arc: C6 S1_V02N0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F7 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V00T0100 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000011001100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R60C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 Q1 +arc: C0 N1_V01S0100 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C74:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0101 V02N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V00B0000 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C75:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile R60C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: B6 H02W0101 +arc: C5 F6 +arc: C6 S1_V02N0201 +arc: D5 V01N0001 +arc: D6 E1_H02W0001 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R60C77:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 H01E0101 +arc: V00B0000 V02S0201 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 V02S0701 +arc: A3 F7 +arc: A4 V02S0301 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B3 H00R0000 +arc: B4 H01E0101 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C3 F6 +arc: C4 H02W0601 +arc: C6 N1_V02S0001 +arc: C7 H02W0401 +arc: D0 H02E0001 +arc: D3 F0 +arc: D4 E1_H02W0201 +arc: D6 V02S0401 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R60C78:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H02W0501 +arc: A4 V02S0301 +arc: B0 H02E0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V02S0401 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C79:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B3 H01W0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q7 +arc: S1_V02S0701 Q7 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C80:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A5 W1_H02E0501 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B2 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 W1_H02E0601 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 Q5 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F2 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000100010100000 +word: SLICED.K1.INIT 1101110111110101 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C81:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02E0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00R0000 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B1 N1_V02S0301 +arc: B2 H00R0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 W1_H02E0601 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 Q6 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H02E0501 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 V02N0301 +arc: B5 V01S0000 +arc: B7 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H00R0100 +arc: C2 S1_V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 V02S0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q5 +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M5 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1100000011001100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C83:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 H01E0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: C0 V02N0401 +arc: C2 E1_H01W0000 +arc: C3 V02S0401 +arc: C4 H02W0601 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F4 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C84:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R60C85:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A2 F5 +arc: A5 W1_H02E0701 +arc: A6 S1_V02N0301 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B2 H01W0100 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C5 H02E0601 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: D0 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F7 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICED.K1.INIT 0100000000010000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C86:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 F5 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B1 F3 +arc: B3 H00R0100 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: B7 H02E0101 +arc: C0 V02N0401 +arc: C1 F4 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V02S0201 +arc: C6 V00T0100 +arc: C7 H02E0401 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D3 V02S0201 +arc: D4 H02W0201 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R60C87:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 V02S0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A5 V02N0301 +arc: A6 F7 +arc: A7 E1_H02W0501 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C1 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: D1 V02S0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0601 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: V00T0100 F3 +arc: V01S0000 F2 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000100000100010 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C88:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A2 V01N0101 +arc: A4 S1_V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B2 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 V01S0000 +arc: B6 W1_H02E0101 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: C5 W1_H02E0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F4 +arc: V00T0100 F3 +arc: V01S0000 F6 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010010100100001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000000000100000 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C89:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 H02W0501 +arc: A4 V02N0301 +arc: A5 F7 +arc: A6 E1_H01W0000 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C2 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: C7 H02E0401 +arc: D0 V02N0001 +arc: D2 E1_H02W0201 +arc: D3 H01E0101 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0001 +arc: D6 F0 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F3 +arc: V01S0000 F4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEA.K0.INIT 1010001001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R60C90:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0001 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: B0 H00R0100 +arc: B1 N1_V02S0301 +arc: B2 H02E0301 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 N1_V02S0401 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: D0 V02S0201 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: V01S0000 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R60C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 V06N0103 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 H01W0100 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q5 +arc: M0 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F7 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R60C92:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A4 V00T0100 +arc: A5 E1_H01W0000 +arc: B1 N1_V02S0301 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: C0 H02W0401 +arc: C1 N1_V01N0001 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K1.INIT 0101000000110000 +word: SLICEC.K0.INIT 0000001100000101 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B4 H02W0101 +arc: B5 H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C94:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 V00T0100 +arc: B0 V02N0301 +arc: B4 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C95:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 E1_H02W0101 +arc: B3 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F4 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C96:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E1_H02W0201 +arc: A0 H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A7 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 Q4 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C97:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 N1_V02S0501 +arc: A2 V00T0000 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0100 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0103 Q1 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C98:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 V06N0103 +arc: A0 H02W0501 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C99:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: C0 W1_H02E0401 +arc: C4 W1_H02E0401 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 W1_H02E0201 +arc: M4 H02E0401 +arc: M5 H00R0100 +arc: M6 H02E0401 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R61C100:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C101:PLC2 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1011001110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R61C107:PLC2 +arc: N1_V02N0601 S1_V02N0601 + +.tile R61C28:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 H02W0701 +arc: B1 E1_H01W0100 +arc: C1 V02N0401 +arc: D1 E1_H02W0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R61C29:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 F5 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: A7 F5 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 F1 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEA.K1.INIT 1100000010100000 +word: SLICEC.K1.INIT 1100000010001000 +word: SLICED.K0.INIT 0000000001001110 +word: SLICEB.K0.INIT 1111111111001010 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K1.INIT 0000101100001010 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEC.K0.INIT 0011001100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C30:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E3_H06W0003 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: B0 V01N0001 +arc: B2 V02N0101 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1011100000000000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEB.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 0000001100110011 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C31:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: A1 W1_H02E0501 +arc: A3 H00L0100 +arc: A5 W1_H02E0501 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 N1_V02S0301 +arc: B3 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02S0001 +arc: D4 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q3 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F6 +arc: V00T0100 F1 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0010111000101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0010111000101110 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0101010111110011 +word: SLICED.K1.INIT 0101010111110101 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C32:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 V02N0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 F7 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C2 F6 +arc: C3 V02N0601 +arc: C4 W1_H02E0401 +arc: C6 H01E0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 H00L0100 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: LSR0 V00B0000 +arc: M1 W1_H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R61C33:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 H02W0701 +arc: B0 F1 +arc: B1 N1_V02S0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 F3 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C1 F4 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 V01N0001 +arc: D7 E1_H01W0100 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1000100010100000 +word: SLICEC.K0.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010100001100 +word: SLICEA.K1.INIT 0011000000110010 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K1.INIT 0011001100000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C34:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02N0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: A7 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 N1_V02S0701 +arc: B7 H02W0101 +arc: C0 V02S0601 +arc: C1 V02S0401 +arc: C2 V02S0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 F3 +arc: V01S0000 Q1 +word: SLICEB.K1.INIT 0000010101010101 +word: SLICEC.K0.INIT 1111111110101100 +word: SLICEC.K1.INIT 0011000000100010 +word: SLICED.K1.INIT 0010001011101110 +word: SLICED.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1011111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C35:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 W1_H02E0101 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F4 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0000110111111101 +word: SLICEC.K1.INIT 0011111100110011 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C36:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V01N0001 +arc: A1 H01E0001 +arc: A4 N1_V01S0100 +arc: B1 E1_H02W0301 +arc: B4 V02S0501 +arc: C1 N1_V01S0100 +arc: C4 V02N0201 +arc: D1 S1_V02N0001 +arc: D4 H02E0001 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0011000100010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C37:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0101 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F5 +arc: A1 S1_V02N0701 +arc: A2 V02S0501 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 H02E0701 +arc: A7 S1_V02N0301 +arc: B0 F3 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 V02S0701 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 F2 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M1 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F7 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0100110000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0111000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R61C38:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A3 V02N0701 +arc: A6 S1_V02N0301 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B6 E1_H02W0301 +arc: B7 H02E0301 +arc: C0 H02W0401 +arc: C1 F6 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C6 V00B0100 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H01E0101 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0010001100000011 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C40:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0201 E3_H06W0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V01N0001 +arc: A0 V01N0101 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 S1_V02N0101 +arc: A7 V02N0301 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 H02W0101 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M2 V00T0000 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F6 +arc: V00T0000 F0 +arc: V01S0000 F7 +arc: W1_H02W0601 F6 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 0001000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C41:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 H02W0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: A5 N1_V01N0101 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B1 V01N0001 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 H01E0001 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F0 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000010000000 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C42:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B4 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V01S0000 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R61C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A1 F5 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 F1 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C6 V01N0101 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N3_V06N0203 F7 +arc: V01S0000 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +word: SLICEC.K1.INIT 1011101110001000 +word: SLICEA.K1.INIT 1110001000000000 +word: SLICED.K0.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 0011001100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: B6 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 F6 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0303 Q6 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q4 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111101011111100 +word: SLICEB.K1.INIT 0000101000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1011100011110000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C45:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: A7 H00L0000 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B7 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C4 F6 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 F2 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1101100000000000 +word: SLICEA.K1.INIT 1110000000100000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEB.K0.INIT 0011001110101111 +word: SLICEB.K1.INIT 0011001110111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R61C46:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: B6 W1_H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 N1_V01S0000 +arc: D2 V02N0001 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 1111111111100010 +word: SLICEC.K1.INIT 0000000011100010 +word: SLICED.K1.INIT 0000000011011100 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICED.K0.INIT 1110101000101010 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1100101010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C47:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N3_V06S0303 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: A0 H01E0001 +arc: A3 H01E0001 +arc: A4 V00T0100 +arc: B0 H02E0301 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: C0 V02N0601 +arc: C3 S1_V02N0401 +arc: C4 H02W0601 +arc: C6 H02E0601 +arc: D0 V01S0100 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: N3_V06N0203 F4 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICED.K0.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000001100001010 +word: SLICEC.K0.INIT 0100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R61C48:PLC2 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 S1_V02N0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A2 H02W0501 +arc: A5 N1_V01S0100 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R61C49:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile R61C50:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S3_V06N0103 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: A5 V00T0100 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 N1_V02S0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 N1_V02S0001 +arc: C6 S1_V02N0001 +arc: C7 N1_V02S0201 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: D6 N1_V02S0401 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 1100001110100101 +word: SLICED.K0.INIT 0001111011010010 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICEC.K0.INIT 1111111100111111 +word: SLICEC.K1.INIT 0000101100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C51:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06N0203 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A4 F5 +arc: A5 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 N1_V02S0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 W1_H02E0201 +arc: D5 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICEC.K1.INIT 0101101000111100 +word: SLICEC.K0.INIT 0000000000000100 +word: SLICEA.K0.INIT 1111111100111111 +word: SLICEA.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0100010101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R61C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: V00B0000 V02S0001 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 1100001110100101 +word: SLICED.K0.INIT 0011110001100110 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010111111111111 +word: SLICEA.K1.INIT 0010001100110011 +word: SLICEB.K0.INIT 1111111100111111 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICEC.K1.INIT 1100001110011001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C53:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: A1 S1_V02N0701 +arc: B1 H00R0100 +arc: B2 W1_H02E0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: V01S0000 F2 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010111111111 +word: SLICEA.K1.INIT 0101000101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C54:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A2 N1_V02S0501 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: A7 F5 +arc: B2 V02S0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 V01S0000 +arc: C0 S1_V02N0401 +arc: C2 H00L0000 +arc: C4 V02S0201 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0701 F7 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C55:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H02W0201 +arc: B0 V00T0000 +arc: B6 H02E0301 +arc: C0 H02W0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R61C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0303 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: B0 V02S0301 +arc: B5 H00R0000 +arc: C0 N1_V01N0001 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D5 H02E0201 +arc: D6 W1_H02E0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0101000001011111 +word: SLICEC.K1.INIT 0000000001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C57:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 E1_H01E0001 +arc: A2 S1_V02N0501 +arc: A3 V02N0501 +arc: A4 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 E1_H02W0301 +arc: B4 F3 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q2 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEC.K0.INIT 0000000001011100 +word: SLICEA.K0.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C58:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 W1_H02E0501 +arc: A5 Q5 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 V00B0000 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0303 Q5 +arc: V00T0000 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C59:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H02E0101 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A7 N1_V01S0100 +arc: B0 N1_V02S0101 +arc: C0 H00L0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C60:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 W1_H02E0501 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B6 H01E0101 +arc: C0 S1_V02N0601 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D6 H02E0201 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C61:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N1_V01S0000 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0201 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: C0 N1_V01N0001 +arc: C2 W1_H02E0601 +arc: C3 H00L0000 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C63:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A2 V02S0701 +arc: B1 Q1 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q4 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 V00T0000 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A5 V00T0100 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C66:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A6 N1_V01S0100 +arc: B1 V01N0001 +arc: B6 H01E0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A4 V00T0100 +arc: A5 E1_H02W0501 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C68:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0000 E1_H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C69:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00R0000 +arc: A1 S1_V02N0501 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02W0501 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C70:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H02E0701 +arc: A2 N1_V02S0701 +arc: A3 H02E0501 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 E1_H02W0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C71:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A1 V02S0701 +arc: A2 N1_V02S0501 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 H02E0701 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 E1_H02W0101 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 E1_H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C72:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A5 E1_H01W0000 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B4 H00R0000 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C4 N1_V02S0201 +arc: C5 V02S0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 F7 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 Q4 +arc: S3_V06S0303 F5 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001110100111111 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R61C73:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H06E0203 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 F4 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C74:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E1_H02W0601 +arc: B0 N1_V02S0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C75:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H02W0701 + +.tile R61C76:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R61C77:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 N1_V02S0701 + +.tile R61C78:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02W0701 + +.tile R61C79:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 W1_H02E0701 +arc: B1 Q1 +arc: B4 V02S0701 +arc: B5 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C80:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B5 H02W0301 +arc: C0 W1_H02E0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICEB.K1.INIT 1010111111001111 +word: SLICEA.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C81:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0701 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: B1 Q1 +arc: B5 V02S0501 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02E0501 +arc: A1 H01E0001 +arc: A2 V02N0701 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q7 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 1010000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06S0203 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100111110101111 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 V01N0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: A3 H02W0501 +arc: A4 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 Q7 +arc: B0 W1_H02E0101 +arc: B1 H02E0101 +arc: B2 H01W0100 +arc: B5 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R61C85:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 N1_V02S0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 F7 +arc: A6 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C5 V02S0001 +arc: C6 H02E0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 Q4 +arc: V00B0000 Q4 +arc: V01S0000 F5 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A5 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 F5 +arc: B2 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C2 H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q3 +arc: V00B0000 F4 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 1001100100001001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R61C87:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 H02W0001 +arc: H00L0100 W1_H02E0301 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N1_V01S0100 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 H00L0100 +arc: A5 F7 +arc: A7 V00T0100 +arc: B0 E1_H01W0100 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C7 E1_H01E0101 +arc: D0 V02N0201 +arc: D3 H02E0001 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: V00T0100 F3 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 1000010010100101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R61C88:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A5 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: C0 S1_V02N0601 +arc: C1 H02W0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0000 Q6 +arc: V00T0000 F2 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000001100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R61C89:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A6 H02W0701 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: B5 H01E0101 +arc: B6 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D6 V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q5 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0011000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 E1_H01W0100 +arc: B5 V02N0701 +arc: C1 E1_H01W0000 +arc: C5 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D5 V00B0000 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: S3_V06S0103 F1 +word: SLICEC.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R61C91:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 W3_H06E0103 +arc: A2 H00L0100 +arc: A3 W1_H02E0701 +arc: A4 H02E0701 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 V02S0601 +arc: C3 H00L0100 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q3 +arc: V01S0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R61C92:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 S1_V02N0701 + +.tile R61C93:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: F0 F5A_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +arc: V01S0100 F0 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101000001010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R61C94:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 N1_V01S0000 +arc: C0 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C95:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B3 V02N0101 +arc: C0 S1_V02N0601 +arc: C1 H00R0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: V01S0000 F0 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R61C96:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02S0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: V01S0000 F2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R61C97:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: B0 W1_H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 V01S0000 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1011101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R61C98:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: C5 V02N0201 +arc: C7 V02N0201 +arc: D0 W1_H02E0201 +arc: D1 V02N0201 +arc: D4 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R61C99:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 E1_H01W0000 +arc: S3_V06S0003 H06E0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C100:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02W0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C101:PLC2 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 + +.tile R62C102:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R62C105:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C106:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R62C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R62C109:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R62C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R62C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R62C114:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R62C115:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R62C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R62C28:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B6 V02S0701 +arc: C0 F6 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C29:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: A0 H02W0701 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: B0 V01N0001 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICEC.K0.INIT 1111111010101110 +word: SLICEC.K1.INIT 0011001000000010 +word: SLICED.K0.INIT 0010001000110010 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 H02W0501 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 H02E0701 +arc: A6 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 H01E0101 +arc: B6 W1_H02E0101 +arc: B7 F3 +arc: C0 S1_V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 F6 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F7 +word: SLICEC.K0.INIT 1110010011001100 +word: SLICEB.K1.INIT 1100000010100000 +word: SLICED.K1.INIT 0000001100110011 +word: SLICED.K0.INIT 0000001000001110 +word: SLICEC.K1.INIT 0000000010101011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C31:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A3 V01N0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B1 H02E0301 +arc: B3 H00L0000 +arc: B5 F1 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C5 V00T0100 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 Q7 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111110011001100 +word: SLICED.K1.INIT 0101010111110000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1010100000001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C32:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 H01E0101 +arc: A1 H02W0701 +arc: A2 H02E0701 +arc: A6 N1_V01S0100 +arc: A7 H02E0501 +arc: B1 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: S1_V02S0701 F7 +word: SLICED.K0.INIT 0010000010100000 +word: SLICEB.K0.INIT 0000110111111101 +word: SLICEB.K1.INIT 0000110011111111 +word: SLICED.K1.INIT 1011101100001011 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C33:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R62C34:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0701 +arc: A2 H00L0100 +arc: A3 V01N0101 +arc: A4 F5 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0501 +arc: C1 F6 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 V01N0101 +arc: C6 V00T0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F6 +arc: LSR0 H02W0301 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F3 +arc: S1_V02S0001 F2 +arc: V01S0000 F7 +arc: V01S0100 Q5 +word: SLICED.K1.INIT 0011000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEB.K0.INIT 1101110100001101 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R62C35:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0100 H02W0101 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A3 E1_H02W0501 +arc: A7 V02N0301 +arc: B3 V01N0001 +arc: B7 V01S0000 +arc: C0 S1_V02N0601 +arc: C3 N1_V01S0100 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: D7 H00L0100 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F3 +arc: V01S0100 F3 +word: SLICED.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 1110010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C36:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B4 N1_V01S0000 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02W0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: LSR0 H02E0501 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0010000010100000 +word: SLICED.K1.INIT 1000101000001010 +word: SLICEC.K0.INIT 1111110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R62C37:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 S1_V02N0501 +arc: A4 E1_H02W0501 +arc: B4 V02N0501 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 Q6 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 0000000011001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R62C38:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02E0701 +arc: A1 F7 +arc: A3 H02W0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B1 Q1 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q3 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1010110011001100 +word: SLICEC.K1.INIT 0010001011101110 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R62C39:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A6 V02S0301 +arc: A7 H02E0701 +arc: B1 H02E0301 +arc: B2 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 F5 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1010001000100010 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEC.K1.INIT 1101000011011101 +word: SLICEA.K1.INIT 1101111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C40:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02N0501 +arc: A1 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B2 E1_H02W0101 +arc: B4 V02N0701 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F1 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C41:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 N1_V01S0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 V02S0701 +arc: A4 E1_H02W0701 +arc: A6 H02E0701 +arc: B1 V02S0101 +arc: B2 S1_V02N0101 +arc: B5 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 H02W0401 +arc: D0 S1_V02N0201 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100110011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R62C42:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 H02W0101 +arc: B3 E1_H01W0100 +arc: B4 N1_V01S0000 +arc: B7 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V01N0101 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N3_V06N0103 F1 +arc: V01S0000 F7 +arc: V01S0100 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 0000000010001111 +word: SLICEC.K0.INIT 0100110000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R62C43:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A3 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B1 Q1 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 V02N0601 +arc: C3 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0201 +arc: D2 H01E0101 +arc: D3 N1_V02S0001 +arc: D5 V00B0000 +arc: D6 W1_H02E0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 0000110011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C44:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0501 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 F2 +arc: V01S0100 F6 +arc: W1_H02W0401 F6 +word: SLICEC.K1.INIT 1110001010101010 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K0.INIT 1011000010111011 +word: SLICEA.K1.INIT 1010110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 1110010011001100 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEC.K0.INIT 0011001110101111 +word: SLICEC.K1.INIT 0011001110111011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R62C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 F5 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 E1_H02W0501 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 H02E0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q3 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 0011111100011101 +word: SLICED.K1.INIT 0011111100001111 +word: SLICEB.K0.INIT 0011111100110000 +word: SLICEC.K1.INIT 1010111100100011 +word: SLICEB.K1.INIT 0101110001011100 +word: SLICEC.K0.INIT 1110010011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C47:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V02S0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V02N0601 +arc: D5 W1_H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 Q7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F7 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 1010111100000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R62C48:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0501 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 V02N0401 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S3_V06S0103 Q1 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R62C49:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00B0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 F3 +arc: V01S0100 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R62C50:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0101 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0103 N1_V01S0100 + +.tile R62C51:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: C1 S1_V02N0401 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: F0 F5A_SLICE +arc: M0 H02E0601 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1111111101110111 +word: SLICEA.K1.INIT 0000111100000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C52:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: B2 S1_V02N0101 +arc: C2 H02W0401 +arc: D2 S1_V02N0201 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +arc: V01S0100 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C53:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02W0701 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C54:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A4 V02S0301 +arc: C0 V02N0401 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R62C55:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B2 V02S0101 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B6 E1_H02W0101 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C57:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 N3_V06S0103 +arc: A3 V02S0701 +arc: A4 V00B0000 +arc: A7 V02N0301 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B2 H00L0000 +arc: B5 H00R0000 +arc: B6 V02N0701 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C58:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 V06S0303 +arc: A3 H02W0501 +arc: B0 V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B4 V02N0501 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C59:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H02W0701 +arc: A4 H02W0501 +arc: B0 E1_H02W0301 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C60:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C4 W1_H02E0401 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: E1_H01E0001 Q5 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C61:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 S1_V02N0601 +arc: C1 H02E0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C62:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 V02N0301 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 N1_V02S0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0000 Q0 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0011000000111111 +word: SLICED.K1.INIT 0001000100110000 +word: SLICED.K0.INIT 0001000100110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C63:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C64:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 E1_H02W0701 +arc: B2 H02W0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C65:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 N1_V02S0301 +arc: B2 V02S0301 +arc: B3 V02N0101 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 V00T0000 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0501 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C67:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 E1_H02W0501 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 H02W0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C68:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0100 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 N1_V02S0301 +arc: B0 H02E0101 +arc: B1 E1_H02W0301 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C4 Q4 +arc: C6 Q6 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q5 +arc: V01S0100 Q6 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C69:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V00B0000 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V02S0101 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 H01E0001 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C70:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A0 V02S0501 +arc: A2 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A7 V02N0101 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: B5 S1_V02N0701 +arc: B7 H02W0101 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 E1_H02W0401 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F6 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00T0000 H02E0201 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 V06S0303 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A6 W1_H02E0701 +arc: A7 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 F6 +arc: V00B0000 Q4 +arc: V00B0100 F7 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000001010011 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C72:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C73:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 H02E0701 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 V06S0303 +arc: A0 H00R0000 +arc: A1 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A3 H02E0501 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 V00T0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C75:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 N1_V02S0501 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 N1_V02S0101 +arc: A6 H02W0701 +arc: A7 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 H02W0301 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 V02S0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R62C77:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: S1_V02S0201 F0 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R62C78:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R62C79:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 F5 +arc: A3 H02W0501 +arc: A5 V02S0301 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B1 H00R0100 +arc: B3 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C1 F6 +arc: C3 V02N0601 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: D1 V01S0100 +arc: D3 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 V02S0401 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R62C80:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +word: SLICEA.K0.INIT 1111000001110000 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICEB.K0.INIT 1100000001000000 +word: SLICEB.K1.INIT 0000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R62C81:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: B1 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C1 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: D1 H02E0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: S1_V02S0401 F4 +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011010111111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011010100000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R62C82:PLC2 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A6 E1_H01W0000 +arc: B5 H02W0301 +arc: D4 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R62C83:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 W3_H06E0203 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: A6 V02S0301 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEB.K1.INIT 0000001100000101 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C84:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0501 +arc: A1 H02W0501 +arc: A2 H00L0100 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C2 H02W0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A4 V02S0101 +arc: B1 Q1 +arc: B6 V01S0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V02S0601 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C86:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R62C87:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0501 +arc: A5 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +word: SLICEA.K1.INIT 1000100011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0100010000001100 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R62C89:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B1 H01W0100 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V00T0100 Q3 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0011000001010000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C90:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02E0701 +arc: A1 E1_H02W0701 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 F5 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R62C91:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A4 N1_V01N0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0501 +arc: B6 S1_V02N0501 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 H01E0001 +arc: C5 E1_H01E0101 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q5 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000000011101111 +word: SLICEA.K1.INIT 0000000011100000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R62C93:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B4 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q7 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V00B0000 F4 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C94:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: B6 H02E0301 +arc: CLK0 G_HPBX0000 +arc: D2 H01E0101 +arc: D3 H02E0001 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C95:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: A0 V02S0501 +arc: A2 W1_H02E0501 +arc: A6 N1_V01N0101 +arc: B1 W1_H02E0101 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C6 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 Q5 +arc: V01S0000 F6 +word: SLICED.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C96:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0501 +arc: A0 H02E0501 +arc: A1 W1_H02E0501 +arc: A2 V00B0000 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 H01W0100 +arc: B4 V00B0100 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F2 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C97:PLC2 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C98:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 V06N0003 +arc: B0 V00B0000 +arc: B1 S1_V02N0301 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R62C99:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06N0203 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C100:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 V02S0401 +arc: A4 N1_V01N0101 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02E0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D4 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111010100000000 +word: SLICEA.K1.INIT 0000000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R63C101:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: B1 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C2 E1_H02W0401 +arc: D0 H02E0001 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R63C102:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R63C103:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R63C104:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R63C106:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R63C107:PLC2 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 + +.tile R63C108:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R63C109:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R63C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R63C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R63C114:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R63C27:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 + +.tile R63C28:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: A0 F7 +arc: A4 E1_H01W0000 +arc: A7 H00L0000 +arc: B3 H02E0301 +arc: B5 H00L0000 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 N1_V01S0100 +arc: C5 E1_H01E0101 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 N1_V01S0000 +arc: D5 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111110011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111110011110000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R63C29:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06N0203 +arc: A0 V02N0701 +arc: A3 V01N0101 +arc: A5 F7 +arc: B0 V01N0001 +arc: B3 W1_H02E0301 +arc: B5 V02S0701 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C5 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 F0 +arc: D5 E1_H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H01E0001 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q6 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100000010100000 +word: SLICEB.K1.INIT 1111111110001000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1110010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C2:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R63C30:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H02W0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02N0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A6 H02E0701 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: C0 V02S0401 +arc: C1 F6 +arc: C3 F6 +arc: C4 H02E0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D6 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1101100000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R63C31:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: A1 H00R0000 +arc: A3 H02E0501 +arc: A4 H02E0501 +arc: A5 F7 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C3 F4 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 E1_H02W0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D4 N1_V02S0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0101 F1 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1100100000001000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000100010001000 +word: SLICEC.K0.INIT 1111010100110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R63C32:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 V02S0501 +arc: A4 N1_V01N0101 +arc: A6 H02E0501 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B1 V02S0101 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C3 F6 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111100001110000 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0011000111111101 +word: SLICED.K1.INIT 0111011101010101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R63C33:PLC2 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B4 H02E0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0501 +arc: B7 H02W0101 +arc: C0 F4 +arc: C1 H02W0601 +arc: C3 F4 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M2 W1_H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0101111101010011 +word: SLICEC.K1.INIT 0011111100001111 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C34:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0701 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B1 V01N0001 +arc: B4 W1_H02E0101 +arc: B5 H00L0000 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: M3 E1_H02W0201 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q4 +arc: V01S0000 F2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111110101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R63C35:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A3 H00L0100 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B3 H00L0000 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C3 H02W0401 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0201 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0101010111001111 +word: SLICED.K1.INIT 0101010111011101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C36:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B3 H01W0100 +arc: B5 H02E0301 +arc: B6 E1_H02W0301 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C3 F6 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 V00B0000 +arc: D6 H02E0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0100010100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C37:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 F7 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 V02N0101 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C4 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V01S0100 +arc: D4 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F2 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q0 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010100000001000 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 0100010001000101 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C38:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H01E0001 +arc: A1 V02N0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 N1_V02S0501 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0100 F4 +word: SLICEA.K1.INIT 1110010000000000 +word: SLICED.K1.INIT 0000010100001111 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K0.INIT 0000101100001010 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEC.K0.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R63C39:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A6 H02E0501 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B6 H02W0301 +arc: C0 H02E0401 +arc: C3 V02N0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 H00R0000 +arc: D6 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S3_V06S0003 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 0101010111001100 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R63C40:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B4 V02S0701 +arc: B5 E1_H02W0101 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0001 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: N3_V06N0303 F5 +arc: V01S0000 F0 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K0.INIT 0010001111101111 +word: SLICEA.K1.INIT 0000101011111111 +word: SLICEB.K0.INIT 0000101111111011 +word: SLICEB.K1.INIT 0000101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R63C41:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 F5 +arc: A2 H00L0100 +arc: A7 S1_V02N0301 +arc: B1 E1_H01W0100 +arc: B2 H02W0301 +arc: B3 S1_V02N0101 +arc: B5 H02W0101 +arc: B7 E1_H02W0101 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D5 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q1 +arc: V01S0000 F7 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0303 F5 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C42:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02W0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B1 E1_H01W0100 +arc: B3 H02W0301 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: C1 H02E0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 H02W0601 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F4 +arc: V01S0000 F0 +arc: V01S0100 Q6 +arc: W1_H02W0401 Q6 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICEA.K1.INIT 1111111111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R63C43:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 V00T0000 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: C0 N1_V01N0001 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEB.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 H02W0701 +arc: A3 V02N0501 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q2 +arc: V01S0100 F7 +arc: W3_H06W0103 Q1 +word: SLICED.K1.INIT 0000011100000010 +word: SLICEC.K0.INIT 1111101011111100 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICED.K0.INIT 0000000011011100 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111111001100 +word: SLICEB.K1.INIT 0011000000110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C45:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 F7 +arc: A1 V02S0501 +arc: A2 E1_H01E0001 +arc: A3 F7 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 V02N0101 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 E1_H01W0000 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0101 F3 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0010001000110010 +word: SLICEC.K0.INIT 0000010000001110 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEB.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 1110010011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C46:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A4 F7 +arc: A7 H00L0000 +arc: B0 H02E0301 +arc: B1 E1_H01W0100 +arc: B7 H01E0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C4 V02S0001 +arc: C7 V00B0100 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 N1_V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N3_V06N0103 F2 +arc: V00B0000 F4 +arc: V01S0000 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111110101100 +word: SLICEA.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEC.K0.INIT 0000010101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R63C47:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H02W0701 +arc: A3 V02N0701 +arc: B1 V02N0301 +arc: B3 H02E0301 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D3 N1_V01S0000 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F2 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R63C48:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0501 +arc: A6 V02N0301 +arc: B6 H02W0101 +arc: C0 S1_V02N0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R63C49:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: A4 E1_H02W0501 +arc: B0 V00T0000 +arc: B3 V02N0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R63C50:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W1_H02E0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: B3 S1_V02N0101 +arc: D3 V02S0001 +arc: F3 F3_SLICE +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R63C51:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H00L0100 +arc: A7 V02S0301 +arc: B2 V02S0301 +arc: B5 N1_V02S0701 +arc: B7 E1_H02W0101 +arc: C1 N1_V01S0100 +arc: C2 H02E0601 +arc: C5 W1_H02E0401 +arc: C7 H02E0601 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D5 N1_V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F1 +arc: N3_V06N0103 F1 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000111100001110 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000111100001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R63C52:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02S0701 +arc: A3 V01N0101 +arc: B0 E1_H01W0100 +arc: B3 V02S0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1000100000000000 +word: SLICEA.K0.INIT 1111110110101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C53:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0501 +arc: B2 H02E0101 +arc: C2 N1_V02S0401 +arc: D2 V02S0001 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 0000111000000010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R63C54:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: W3_H06W0103 E3_H06W0003 +arc: B0 S1_V02N0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C55:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0203 +arc: A7 H02E0501 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 E1_H02W0701 +arc: A3 V02S0501 +arc: A4 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 N1_V02S0501 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: V00B0100 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 0001111100010000 +word: SLICEA.K1.INIT 0000110001011100 +word: SLICEB.K0.INIT 0001111100010000 +word: SLICEB.K1.INIT 0100010001001110 +word: SLICEC.K0.INIT 0001000111110000 +word: SLICEC.K1.INIT 1110111011110000 +word: SLICED.K0.INIT 0000001110101010 +word: SLICED.K1.INIT 0000001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C57:PLC2 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 H02E0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: A1 V02S0701 +arc: A3 V00T0000 +arc: A4 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 E1_H01W0100 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +word: SLICEC.K0.INIT 0000001100001010 +word: SLICED.K0.INIT 0011001100001111 +word: SLICED.K1.INIT 0000010100001100 +word: SLICEB.K1.INIT 0000001000001110 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C58:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A7 V02S0101 +arc: B1 V02S0101 +arc: B7 H01E0101 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 H00R0000 +arc: D7 V02S0401 +arc: E1_H01E0001 Q0 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C59:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02E0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B5 N1_V01S0000 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D5 V00B0000 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q1 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C60:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B5 H02E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S3_V06S0303 F5 +arc: V00T0000 Q0 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C61:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A1 H00L0100 +arc: A7 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 H02W0401 +arc: C2 E1_H02W0601 +arc: C7 V00B0100 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F0 +arc: V01S0000 F7 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000101000001100 +word: SLICEB.K0.INIT 0011000000111111 +word: SLICED.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 0011000000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R63C62:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H01E0001 +arc: A2 V00B0000 +arc: A5 V02S0301 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 0011000000111111 +word: SLICEC.K1.INIT 0000000001011100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C63:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 E3_H06W0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 W1_H02E0301 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C64:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V00T0000 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B5 H02E0301 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 N1_V01S0100 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 W1_H02E0201 +arc: D5 H02W0001 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B1 S1_V02N0301 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C66:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0501 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: V00T0100 Q3 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C67:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 H02E0401 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 S1_V02N0701 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 Q3 +arc: B4 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0701 Q5 +arc: S1_V02S0201 Q2 +arc: S3_V06S0203 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q7 +arc: V00B0000 Q6 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V01N0101 +arc: A3 N1_V02S0701 +arc: A5 N1_V02S0101 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B2 H02E0101 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 H02W0601 +arc: C5 H02W0401 +arc: C6 N1_V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D5 V02S0601 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011111110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 V00B0100 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 H02E0201 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C72:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A5 H02W0501 +arc: A7 H00L0000 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B5 H02E0101 +arc: B7 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D5 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0401 F6 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 F4 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C73:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 N1_V01S0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02S0301 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 H02E0301 +arc: B6 H02W0301 +arc: B7 H02E0101 +arc: C0 N1_V02S0601 +arc: C3 V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 H02W0201 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C74:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 N1_V02S0701 +arc: A5 V00B0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B3 H02E0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00T0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M2 W1_H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C75:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A5 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: B5 H00R0000 +arc: C0 H02E0601 +arc: C1 W1_H02E0401 +arc: C3 H02E0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D3 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 W1_H02E0601 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001110100111111 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 V02S0501 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C77:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: B1 H02E0301 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C78:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B7 F3 +arc: C2 S1_V02N0401 +arc: C3 H02W0601 +arc: C7 E1_H01E0101 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C79:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0701 +arc: A4 V02N0101 +arc: B1 W1_H02E0301 +arc: B4 H02E0301 +arc: C1 V02N0601 +arc: C4 E1_H02W0601 +arc: D1 H00R0000 +arc: D4 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: M0 V00B0000 +arc: N3_V06N0003 F0 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R63C80:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R63C81:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V00T0100 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02E0001 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M5 W1_H02E0001 +arc: M6 V00B0100 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1111000001110000 +word: SLICEA.K1.INIT 0011000001110000 +word: SLICEB.K0.INIT 1100000001000000 +word: SLICEB.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 1011000011110000 +word: SLICEC.K1.INIT 0001111100000000 +word: SLICED.K0.INIT 1000000011000000 +word: SLICED.K1.INIT 0000000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R63C82:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 N1_V02S0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S1_V02S0501 F5 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 1011111100000000 +word: SLICEC.K1.INIT 0001111100000000 +word: SLICED.K0.INIT 1011000000000000 +word: SLICED.K1.INIT 0001000000000000 +word: SLICEA.K0.INIT 0000110000001111 +word: SLICEA.K1.INIT 0000101000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R63C83:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C84:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 V02S0501 +arc: A4 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C85:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B1 E1_H01W0100 +arc: B3 H02W0101 +arc: C0 V02N0601 +arc: D2 H02W0001 +arc: D4 V02N0601 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R63C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: C0 H02E0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C87:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B4 N1_V02S0501 +arc: B5 V01S0000 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 W1_H02E0601 +arc: C2 V02S0401 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000001100000101 +word: SLICED.K1.INIT 1111000011100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R63C88:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0501 F5 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C89:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 N1_V02S0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0501 +arc: B0 V02S0101 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C5 H01E0001 +arc: D0 W1_H02E0001 +arc: D4 H00L0100 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: S1_V02S0701 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEA.K0.INIT 0000000000101111 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R63C90:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02E0501 +arc: A6 E1_H02W0701 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: S1_V02S0001 Q0 +arc: V01S0000 F6 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C91:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 V02N0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02W0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V01S0100 +arc: A7 V02S0101 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C92:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 H00R0100 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00R0100 +arc: C3 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0100 Q5 +arc: M2 H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C93:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: B7 W1_H02E0101 +arc: C0 E1_H02W0401 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D6 W1_H02E0201 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C94:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0701 +arc: A5 N1_V02S0101 +arc: C0 V02N0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D5 S1_V02N0401 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C95:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: W1_H02W0401 W3_H06E0203 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 V02N0401 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C96:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02E0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C97:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C98:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R63C99:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C100:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 V02N0401 +arc: A6 N1_V02S0301 +arc: C7 H02E0601 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 W1_H02E0201 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C101:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0101 V02N0101 + +.tile R64C107:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R64C110:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 + +.tile R64C113:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R64C116:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R64C23:PLC2 +arc: N3_V06N0003 E3_H06W0003 + +.tile R64C26:PLC2 +arc: N3_V06N0003 H06W0003 + +.tile R64C28:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 + +.tile R64C29:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 H00L0000 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V02S0001 +arc: D4 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C30:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: A0 F7 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICED.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 V02S0401 +arc: A0 N1_V02S0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 H01E0101 +arc: B6 V01S0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F7 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K0.INIT 0000001100110011 +word: SLICEA.K1.INIT 1000110010000000 +word: SLICEC.K1.INIT 0000010100001100 +word: SLICEB.K0.INIT 1111111010101110 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K1.INIT 0011001100000001 +word: SLICEA.K0.INIT 1111011110000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C32:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A0 F7 +arc: A3 H02W0501 +arc: A4 S1_V02N0301 +arc: A7 H02E0501 +arc: B3 H00L0000 +arc: B4 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1110110001001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0100000011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R64C33:PLC2 +arc: E1_H02E0201 V02S0201 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 E1_H02W0501 +arc: A1 F7 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B6 N1_V02S0701 +arc: B7 V02N0501 +arc: C1 H02E0401 +arc: C6 H01E0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M3 H00L0000 +arc: M5 H00R0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q7 +arc: S1_V02S0501 Q7 +arc: V01S0000 F7 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0100000011000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 H02E0501 +arc: A7 V02N0301 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B7 V00T0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C5 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D5 H02E0201 +arc: D7 N1_V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q2 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1010110011001100 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110101000101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C35:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A6 S1_V02N0301 +arc: B0 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000000111111 +word: SLICEB.K0.INIT 1111111110101100 +word: SLICEB.K1.INIT 0000000010101100 +word: SLICEC.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 0000000010000000 +word: SLICEA.K0.INIT 1100101010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C36:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 F5 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A5 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D5 N1_V02S0401 +arc: D6 V02S0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111100011110000 +word: SLICEB.K0.INIT 0000111110111011 +word: SLICEB.K1.INIT 0000111110101111 +word: SLICEC.K1.INIT 0100000011000000 +word: SLICEA.K1.INIT 1100010001000100 +word: SLICED.K0.INIT 1111110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R64C37:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0100 +arc: A3 V02S0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D5 S1_V02N0401 +arc: D6 N1_V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0011001111111100 +word: SLICEA.K1.INIT 1001100111111010 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C38:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: A3 N1_V02S0701 +arc: A6 V02N0101 +arc: B0 H01W0100 +arc: B3 E1_H02W0301 +arc: B6 H02W0301 +arc: C0 S1_V02N0401 +arc: C3 H02W0601 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D3 H02E0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 F6 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1000100010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C39:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: A0 V02N0701 +arc: A2 H02E0501 +arc: A5 H02E0501 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B5 H00L0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D5 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 1110110001001100 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1110110001001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C40:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A6 V02N0101 +arc: D6 E1_H02W0201 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: N3_V06N0303 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000001010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R64C41:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V06N0103 +arc: W3_H06W0003 N1_V01S0000 +arc: A0 F5 +arc: A1 V02N0501 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0101 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02W0601 +arc: C3 N1_V01N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D3 H00R0000 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: V00T0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C42:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 V00T0000 +arc: A6 N1_V02S0301 +arc: B0 V00T0000 +arc: B6 V00T0000 +arc: C0 F6 +arc: C2 N1_V01S0100 +arc: C3 F6 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R64C43:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V02S0701 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A6 E1_H02W0501 +arc: B1 H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C6 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D6 N1_V02S0601 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEB.K0.INIT 0010000000000000 +word: SLICEA.K1.INIT 1110110000000000 +word: SLICEB.K1.INIT 0010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C44:PLC2 +arc: E1_H02E0101 V06N0103 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: A3 V00T0000 +arc: A5 V02S0301 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 V00T0000 +arc: B3 V02S0301 +arc: B5 F1 +arc: B7 N1_V01S0000 +arc: C1 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C5 E1_H02W0601 +arc: C6 E1_H01E0101 +arc: C7 H02E0401 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +word: SLICEB.K1.INIT 1100101000000000 +word: SLICED.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICED.K1.INIT 1000101010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R64C45:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 + +.tile R64C46:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V02N0101 +arc: B5 H02W0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R64C47:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: A3 N1_V02S0701 +arc: B3 H00L0000 +arc: C0 H00L0000 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C48:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C49:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: B4 V02N0501 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 E1_H02W0201 +arc: D4 N1_V02S0401 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0203 F4 +arc: V01S0100 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R64C50:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0701 N1_V02S0701 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 H02W0501 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0003 E1_H02W0301 +arc: A7 S1_V02N0301 +arc: C6 E1_H01E0101 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N3_V06N0303 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0303 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R64C51:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A5 H02E0701 +arc: C7 V02S0201 +arc: D5 V02S0401 +arc: D7 V02S0601 +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F5 +arc: S3_V06S0303 F5 +arc: V01S0100 F7 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R64C52:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 H02E0501 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 E1_H02W0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02N0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: M0 H02E0601 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1011101110110001 +word: SLICEA.K1.INIT 1010101010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R64C53:PLC2 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 S3_V06N0203 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: B1 H00R0100 +arc: B3 E1_H01W0100 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111101000110011 +word: SLICEA.K1.INIT 1110111000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R64C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S3_V06N0303 +arc: A1 E1_H02W0501 +arc: A3 V02S0501 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: C0 N1_V01N0001 +arc: C2 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000111111011 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000110000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 E1_H01W0100 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: V00T0000 H02E0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: A1 V02S0501 +arc: A3 H01E0001 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B3 H01W0100 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 H01W0000 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: V01S0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K1.INIT 1110000000100000 +word: SLICED.K0.INIT 0000110000001010 +word: SLICEB.K1.INIT 1100000010001000 +word: SLICEC.K1.INIT 1100000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R64C56:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B4 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C57:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: A2 H02W0501 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B1 E1_H02W0101 +arc: B3 V02S0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D6 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C58:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 E1_H02W0201 +arc: H00R0100 H02W0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0501 +arc: A4 E1_H01W0000 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C4 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R64C59:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: A2 N1_V02S0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: A0 N1_V02S0701 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: V00B0000 Q4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 0011011100000100 +word: SLICEA.K1.INIT 0001000111110000 +word: SLICEB.K0.INIT 0101011100000010 +word: SLICEB.K1.INIT 0000001110101010 +word: SLICEC.K0.INIT 0000001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C61:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A4 V02S0101 +arc: B0 H02W0101 +arc: C0 H00L0000 +arc: C4 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R64C62:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 F5 +arc: A3 V02S0501 +arc: A5 V02N0101 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: D5 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000110000111111 +word: SLICEB.K1.INIT 0000011100000100 +word: SLICEC.K1.INIT 0000010110101111 +word: SLICEA.K1.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R64C63:PLC2 +arc: E3_H06E0303 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: B0 H01W0100 +arc: B2 V02S0301 +arc: C0 H02W0601 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R64C64:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V06S0303 + +.tile R64C65:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V01N0001 + +.tile R64C66:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 V01N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 H02E0101 +arc: B7 V02N0701 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0100 +arc: C4 N1_V02S0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 Q5 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C67:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0601 +arc: W3_H06W0103 E1_H02W0101 +arc: B0 H02E0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: S1_V02S0501 F5 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C68:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C69:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V00B0000 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C70:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: B0 H02W0101 +arc: B4 E1_H02W0101 +arc: B7 N1_V02S0501 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C71:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 H00R0000 +arc: A4 V00B0000 +arc: A5 H02E0701 +arc: A7 Q7 +arc: B0 V02S0301 +arc: B6 V01S0000 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 H02E0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q6 +arc: V00B0000 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q6 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R64C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 V01N0001 +arc: A0 H01E0001 +arc: A3 E1_H02W0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0011001101011111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V00T0000 +arc: A5 H02E0701 +arc: A7 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: B7 N1_V02S0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C5 S1_V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D5 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M4 W1_H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010110111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C74:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02S0501 +arc: A2 N1_V02S0501 +arc: A3 V00T0000 +arc: A5 N1_V01S0100 +arc: A7 V02N0301 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B4 N1_V02S0701 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 Q4 +arc: C5 H02E0401 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 F5 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0003 Q3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C76:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N1_V01S0100 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0701 V02S0701 +arc: A4 V02N0101 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 F6 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 1010000000001010 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C77:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C78:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C79:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0201 H01E0001 +arc: A0 H00L0000 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: C0 H02E0601 +arc: C3 H00L0000 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0011001100110011 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C80:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R64C81:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 N1_V01S0000 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R64C82:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 E1_H02W0301 + +.tile R64C83:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: A3 E1_H02W0501 +arc: A5 V02N0101 +arc: A7 E1_H02W0701 +arc: B3 N1_V02S0101 +arc: B5 V02S0701 +arc: B7 V02S0501 +arc: C3 H02E0601 +arc: C5 S1_V02N0001 +arc: C7 V02N0201 +arc: D3 S1_V02N0001 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001111110111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1011101011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R64C84:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: B1 N1_V02S0101 +arc: B4 N1_V01S0000 +arc: D0 V02S0001 +arc: D5 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C85:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R64C86:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C87:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 S1_V02N0501 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R64C88:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H06W0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V00B0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: C0 H00L0000 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R64C89:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A4 W1_H02E0501 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B4 V02N0501 +arc: B6 W1_H02E0301 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D6 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q7 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W3_H06W0303 F5 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0010111101111111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0100000001110000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1101110110001000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C90:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0203 H06W0203 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0303 E3_H06W0203 + +.tile R64C91:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E3_H06W0003 +arc: V00B0000 H02W0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 N1_V02S0701 +arc: C6 V02S0201 +arc: D3 V00T0100 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R64C92:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: D0 V02N0001 +arc: D2 V02N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0011010111111111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011010100000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R64C93:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 N1_V02S0501 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 V02N0101 +arc: A6 W1_H02E0501 +arc: B0 V02S0301 +arc: B2 S1_V02N0101 +arc: B4 V02S0501 +arc: B6 W1_H02E0301 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: C4 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D6 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0011010111111111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101001100000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100101011001010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1011101110001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R64C94:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: B1 H02W0101 +arc: B5 H02W0101 +arc: B7 H02W0101 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D6 H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: S1_V02S0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C95:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: C7 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 V02S0201 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C96:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R64C97:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B4 H01E0101 +arc: C0 H00L0000 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N3_V06N0003 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000001100110011 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R64C98:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V02N0501 +arc: H00L0100 H02E0101 +arc: H00R0000 H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 V01N0001 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: C3 N1_V02S0401 +arc: D2 V00T0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R64C99:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C100:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V02N0101 + +.tile R65C101:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R65C102:PLC2 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R65C103:PLC2 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 + +.tile R65C104:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 + +.tile R65C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C107:PLC2 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C108:PLC2 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C109:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C110:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: C3 H02E0601 +arc: D3 H02E0001 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R65C112:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C113:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C114:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C115:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C116:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C117:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C118:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R65C14:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C15:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R65C20:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C21:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R65C23:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R65C26:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C29:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 + +.tile R65C30:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02W0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H02W0101 +arc: A3 H00L0100 +arc: B1 F3 +arc: B3 E1_H01W0100 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: D1 S1_V02N0201 +arc: D3 H00R0000 +arc: E1_H01E0001 F1 +arc: E1_H02E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1010110000000000 +word: SLICEA.K1.INIT 0000001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R65C31:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0100 H02E0101 +arc: A0 F7 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0701 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 F6 +arc: C6 H01E0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 1000100010100000 +word: SLICED.K0.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICED.K1.INIT 0100010001010100 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEC.K1.INIT 0101010100000001 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C32:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V02S0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0101 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 H02E0101 +arc: B7 W1_H02E0301 +arc: C1 H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 V01S0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 F3 +arc: S1_V02S0301 Q1 +arc: V01S0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 0000000000111010 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1101000010000000 +word: SLICEB.K1.INIT 0101000001010001 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEA.K1.INIT 0000111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C33:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0701 +arc: A1 F7 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 V02N0301 +arc: A6 N1_V02S0301 +arc: A7 V02S0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C5 F6 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K0.INIT 1111111111100100 +word: SLICEB.K1.INIT 0000000011100100 +word: SLICEA.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K0.INIT 1011000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C34:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0201 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 F5 +arc: A5 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B1 H02W0301 +arc: B2 H02E0101 +arc: B5 H01E0101 +arc: B7 H02W0101 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D5 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: N3_V06N0003 F3 +arc: V01S0000 Q2 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1010000011000000 +word: SLICEA.K1.INIT 0001000101010101 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1011100000000000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C35:PLC2 +arc: E1_H02E0501 V06S0303 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 F5 +arc: A6 H00L0000 +arc: A7 N1_V02S0301 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 W1_H02E0401 +arc: C2 F4 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 H02W0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F6 +arc: V00T0100 F3 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICED.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0000001100100010 +word: SLICEA.K1.INIT 0010001100100010 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEB.K0.INIT 0000110000001101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C36:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 V00B0000 +arc: C0 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C37:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: V01S0000 F4 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1111111110001000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K0.INIT 1010101011111100 +word: SLICEA.K1.INIT 1100110011111010 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R65C38:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 S3_V06N0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0103 N3_V06S0103 +arc: A2 V00T0000 +arc: A4 H02W0701 +arc: A5 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1101100000000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICEB.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C39:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E1_H01W0000 +arc: V00T0100 H02W0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 F7 +arc: A1 S1_V02N0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H02W0301 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 F4 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0001 +arc: D4 H02E0201 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEC.K0.INIT 0000010100001111 +word: SLICEA.K1.INIT 0000010101000100 +word: SLICEB.K0.INIT 1111111011110100 +word: SLICEB.K1.INIT 0000111000000100 +word: SLICED.K1.INIT 0101000101010000 +word: SLICEA.K0.INIT 1111101011001100 +word: SLICEC.K1.INIT 0100010001000101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R65C3:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C40:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 S1_V02N0701 +arc: A3 H02W0701 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B3 E1_H01W0100 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 N1_V02S0601 +arc: C5 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: V00B0000 Q4 +arc: V00B0100 F5 +arc: V01S0000 F2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110101011101010 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R65C41:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: A3 H00L0100 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V02S0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1110000000100000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C42:PLC2 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 V06N0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 E1_H02W0301 +arc: C0 F6 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D6 V02N0401 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1100000010100000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C43:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 + +.tile R65C44:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile R65C45:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0303 +arc: C7 V01N0101 +arc: D7 V02S0601 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R65C46:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 H02E0701 +arc: A4 F5 +arc: A5 V02N0301 +arc: A7 H02W0701 +arc: B5 S1_V02N0501 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F1 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K0.INIT 1111101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R65C47:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: A5 V02N0301 +arc: C5 H02E0601 +arc: E1_H02E0501 F5 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0000010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R65C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 V06S0103 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 W1_H02E0601 +arc: A2 V02S0701 +arc: A4 H02E0501 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C5 V00T0000 +arc: C7 H02E0401 +arc: D0 H00R0000 +arc: D1 F2 +arc: D2 H02W0201 +arc: D4 N1_V02S0601 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: N1_V01N0001 F4 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F5 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 F0 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0101000101010101 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R65C49:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 H02W0501 +arc: A3 V02N0501 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0501 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B2 H02W0101 +arc: B4 H00R0000 +arc: B5 N1_V02S0501 +arc: B6 F3 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 V02S0201 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +word: SLICEB.K1.INIT 1010000010101010 +word: SLICEA.K0.INIT 0000111000001100 +word: SLICEA.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1101000011010101 +word: SLICEC.K1.INIT 1100111000000000 +word: SLICED.K1.INIT 0000000010001111 +word: SLICED.K0.INIT 1010001010101010 +word: SLICEC.K0.INIT 0000000010101011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C50:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A4 E1_H01W0000 +arc: A6 V02N0301 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B4 H02W0301 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0101001101010000 +word: SLICEB.K0.INIT 1101000001010000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000010100001101 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0011000100000001 +word: SLICED.K1.INIT 0011001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R65C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0501 +arc: A2 H02E0501 +arc: A4 F7 +arc: A5 V00T0100 +arc: A6 E1_H02W0501 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: C0 F6 +arc: C1 F6 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D2 N1_V02S0201 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F7 +arc: V00B0100 F5 +arc: V01S0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1000101010001000 +word: SLICEA.K0.INIT 0100000011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0010000000100010 +word: SLICED.K0.INIT 1010101010001010 +word: SLICEB.K0.INIT 0001000001010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C52:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0401 H01E0001 +arc: W3_H06W0203 E3_H06W0203 +arc: C1 E1_H02W0401 +arc: C6 V01N0101 +arc: D1 V00B0100 +arc: D6 H02E0001 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +arc: S3_V06S0103 F1 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R65C53:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: A3 V02S0701 +arc: B0 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 E1_H02W0201 +arc: D6 V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0111000000000000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEA.K0.INIT 0101011100000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C54:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: A2 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0301 +arc: C0 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101000001111 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C55:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02W0701 +arc: A2 N1_V02S0701 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 H02E0101 +arc: B5 V02N0501 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 V02S0401 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111001111110101 +word: SLICEA.K1.INIT 0001000001010100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R65C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A6 N1_V01S0100 +arc: A7 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D6 H00L0100 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0000110001000100 +word: SLICED.K0.INIT 0000100001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C57:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0501 F5 +word: SLICED.K0.INIT 0011000010100000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K1.INIT 0100000001110000 +word: SLICEC.K0.INIT 0101000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C58:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 N3_V06S0203 +arc: A2 S1_V02N0701 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 0011000001010000 +word: SLICED.K0.INIT 0011000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C59:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A5 N1_V01S0100 +arc: B2 V02N0301 +arc: B5 H00L0000 +arc: B7 N1_V01S0000 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C5 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEB.K0.INIT 0011010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R65C60:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 V01N0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0001000010110000 +word: SLICED.K1.INIT 0011000001010000 +word: SLICEC.K1.INIT 0001000010110000 +word: SLICED.K0.INIT 0010000001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C61:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: A1 H02E0501 +arc: A4 V00B0000 +arc: B4 V00B0100 +arc: C1 H02W0601 +arc: C4 H02W0401 +arc: D1 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000001100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R65C62:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: B7 N1_V01S0000 +arc: C7 V00T0000 +arc: D7 S1_V02N0601 +arc: F7 F7_SLICE +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R65C63:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0701 S3_V06N0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile R65C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E1_H02W0201 + +.tile R65C65:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N3_V06S0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R65C66:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00L0000 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: A4 N1_V02S0101 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B4 V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 N1_V02S0001 +arc: D4 H02W0201 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C67:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E3_H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 V02N0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 F5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0000 F4 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C68:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0501 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0601 Q6 +arc: S1_V02S0001 Q0 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q2 +arc: V01S0000 Q4 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C70:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 N1_V02S0501 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 W1_H02E0501 +arc: A5 H02E0701 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 N1_V02S0301 +arc: B4 F3 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: D1 V02N0201 +arc: D2 H02W0001 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00T0100 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0100011101110111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R65C71:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A5 H02W0501 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H00R0100 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C72:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06N0203 +arc: A1 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: A7 F5 +arc: B1 W1_H02E0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V02S0501 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: C6 V00T0000 +arc: C7 F4 +arc: D1 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0100011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C73:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 H02W0501 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0701 +arc: B7 V00B0100 +arc: C0 V02S0401 +arc: C1 S1_V02N0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F1 +arc: V01S0000 Q0 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C74:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 S1_V02N0301 +arc: A7 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B5 H00L0000 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 V02S0601 +arc: C5 H02E0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 W1_H02E0201 +arc: D5 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R65C75:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02S0501 +arc: A5 S1_V02N0101 +arc: A7 N1_V01S0100 +arc: B0 V00T0000 +arc: B2 N1_V02S0101 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C2 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H01E0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D7 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C76:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V01S0100 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A2 V02N0501 +arc: A3 F5 +arc: A4 W1_H02E0501 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C1 V02N0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0401 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S3_V06S0203 F7 +arc: V00B0000 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1101110100001101 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R65C77:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 E1_H01E0001 +arc: A2 V00T0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1100000000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R65C78:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C79:PLC2 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 V02S0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02S0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C80:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 H00R0100 +arc: B3 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00R0100 Q7 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010110011111111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C81:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R65C82:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: W3_H06W0003 E3_H06W0003 + +.tile R65C83:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0101 E3_H06W0103 + +.tile R65C84:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0100 E1_H02W0101 +arc: V01S0100 N3_V06S0303 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 1111010011110111 +word: SLICEB.K1.INIT 0011010000110111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C85:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R65C86:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 W1_H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02S0101 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 N1_V01S0100 +arc: B5 N1_V01S0000 +arc: C4 N1_V02S0201 +arc: C6 N1_V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V02S0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C87:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 H02E0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: M2 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C88:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: E1_H01E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00L0100 +arc: M2 W1_H02E0601 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R65C89:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0601 N3_V06S0303 +arc: A2 E1_H01E0001 +arc: A3 N1_V02S0701 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B6 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0601 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 H01E0101 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0100 F0 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000000001110100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R65C90:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 N1_V02S0701 +arc: A2 H02W0501 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A7 Q7 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0301 +arc: B6 V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0401 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D4 H02E0201 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 F4 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000111110000000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R65C91:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B2 H02E0301 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: D3 H02E0001 +arc: E1_H02E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: N1_V01N0101 F1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R65C92:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 N1_V02S0101 +arc: C5 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C93:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C4 V02S0001 +arc: C6 V02S0001 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 N1_V02S0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 W1_H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C94:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06W0203 +arc: W3_H06W0003 V06N0003 + +.tile R65C95:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 S3_V06N0103 +arc: B2 H02W0301 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D3 V02S0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 N1_V01N0001 +arc: M3 E1_H02W0201 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R65C96:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N3_V06N0003 H06W0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 + +.tile R65C97:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V00B0000 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C98:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S3_V06N0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 S3_V06N0303 +arc: A1 H00L0100 +arc: A5 E1_H01W0000 +arc: B0 H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 S1_V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0201 +arc: E1_H01E0101 Q5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1110001011100010 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R65C99:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: B0 V00B0000 +arc: B6 H02W0101 +arc: C0 H02E0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1100000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C100:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0701 V06N0203 + +.tile R66C103:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C105:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R66C106:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C108:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C109:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R66C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R66C112:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R66C20:PLC2 +arc: N3_V06N0303 E3_H06W0303 + +.tile R66C25:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R66C26:PLC2 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R66C28:PLC2 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R66C29:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0401 H06W0203 + +.tile R66C30:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02S0101 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H00L0000 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D3 V02N0001 +arc: D5 V02N0401 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010110000000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C31:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A3 H00L0100 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B6 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 F6 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D3 H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R66C32:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B1 V01N0001 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C1 F6 +arc: C2 H00L0100 +arc: C3 F4 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: C6 E1_H02W0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 F7 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0601 Q4 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111110011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1101000010000000 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R66C33:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0701 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 E1_H01W0000 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0301 Q1 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C34:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 F7 +arc: A3 H02W0701 +arc: A4 V02N0101 +arc: A7 H00L0000 +arc: B4 H02E0101 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 F4 +arc: C4 H01E0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEC.K0.INIT 1000101010000000 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C35:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0303 E3_H06W0303 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H01E0001 +arc: A7 N1_V01S0100 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D3 H01E0101 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0100 F7 +word: SLICEB.K1.INIT 1111111110100000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1011101111111111 +word: SLICEA.K0.INIT 1111111111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R66C36:PLC2 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0103 H06E0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 N1_V02S0501 +arc: A5 V02S0101 +arc: B0 V02N0301 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B6 N1_V01S0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: LSR0 H02E0501 +arc: M3 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C37:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 E3_H06W0303 +arc: B3 E1_H01W0100 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0201 +arc: E1_H01E0101 Q7 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R66C38:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A1 E1_H02W0501 +arc: A3 S1_V02N0701 +arc: B0 E1_H02W0301 +arc: B1 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 E1_H01W0000 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 N1_V01S0000 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F1 +arc: V00T0000 Q0 +arc: W1_H02W0401 F4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 0101111111001100 +word: SLICEA.K1.INIT 1100101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R66C39:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06N0203 +arc: A0 H01E0001 +arc: A6 N1_V01N0101 +arc: B6 H02E0101 +arc: C0 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 0101110000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C40:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: A5 V02N0301 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 V00B0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +word: SLICEB.K1.INIT 1111101010101010 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R66C41:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 V06S0103 +arc: A6 V02N0301 +arc: B6 E1_H02W0101 +arc: C6 V02N0001 +arc: D6 V00B0000 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F6 +arc: N3_V06N0303 F6 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R66C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02S0301 +arc: W3_H06W0303 E3_H06W0303 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0001 F2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B5 E1_H02W0101 +arc: C2 H02W0401 +arc: C5 E1_H02W0401 +arc: D2 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R66C44:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: A0 H00L0000 +arc: A3 F7 +arc: A4 F5 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B3 H02E0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0001010101010101 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1100000011101010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R66C45:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 H02W0701 +arc: A2 V02S0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A6 H00R0000 +arc: B0 H02E0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B6 V00B0100 +arc: C0 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0601 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0100 F7 +arc: V01S0000 F1 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1000100000001000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000100010001000 +word: SLICED.K0.INIT 0010001000101010 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 1011001110100000 +word: SLICEC.K1.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R66C46:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: A1 E1_H02W0701 +arc: A2 V02S0701 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 H02E0501 +arc: A6 H02W0501 +arc: A7 F5 +arc: B1 V02S0101 +arc: B3 V02N0301 +arc: B4 F3 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: C1 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 H00R0100 +arc: D6 W1_H02E0001 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0201 F0 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R66C47:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 N1_V02S0501 +arc: B7 S1_V02N0701 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D1 H02W0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D7 F2 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: M0 V00B0000 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V01S0000 F3 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0001000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000001000000010 +word: SLICEC.K1.INIT 0000010100000101 +word: SLICEB.K0.INIT 0011000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R66C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 V06N0303 +arc: A1 F5 +arc: A2 V02S0501 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C1 H02W0401 +arc: C2 H00L0100 +arc: C3 V02S0401 +arc: C4 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 W1_H02E0201 +arc: D4 H02W0001 +arc: D5 V02S0601 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F5 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: S1_V02S0001 F0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 0101000001010101 +word: SLICED.K0.INIT 0000110000001000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 0001001100110011 +word: SLICEB.K0.INIT 0011000001110000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000110100000000 +word: SLICEC.K0.INIT 1101010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R66C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 V06S0003 +arc: A0 H02E0701 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B4 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 V02S0401 +arc: C2 V02S0601 +arc: C3 V02N0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 H01E0101 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 F0 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 H01E0001 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 0100000000000000 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICED.K1.INIT 0011001100100000 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICED.K0.INIT 1100100010001000 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R66C50:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0501 +arc: A1 F5 +arc: A2 V02N0701 +arc: A3 N1_V02S0701 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B3 V02N0101 +arc: B6 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 S1_V02N0601 +arc: C3 F6 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 F4 +arc: D0 V02S0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F3 +arc: V00B0100 F7 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICED.K0.INIT 0101010100000001 +word: SLICEA.K0.INIT 0001001100010001 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICEB.K1.INIT 0011000100110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R66C51:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 V06S0303 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V02S0501 +arc: A4 H02W0701 +arc: A5 E1_H02W0701 +arc: A7 V00T0100 +arc: B1 W1_H02E0301 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M0 H02W0601 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0011001000110000 +word: SLICEB.K0.INIT 0000101000001111 +word: SLICEC.K0.INIT 1010000010110000 +word: SLICEB.K1.INIT 0000100010101010 +word: SLICED.K1.INIT 0101010101010100 +word: SLICEC.K1.INIT 0000001010101010 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R66C52:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A4 S1_V02N0101 +arc: A6 E1_H01W0000 +arc: B1 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 V00B0100 +arc: B6 V00B0000 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02S0001 +arc: D4 H02W0201 +arc: D6 W1_H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F3 +arc: S3_V06S0103 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0011011100000000 +word: SLICEB.K1.INIT 1100000011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010000011100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R66C53:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 F5 +arc: A1 F5 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A7 S1_V02N0101 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: C1 H00R0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C5 V02S0001 +arc: C7 F4 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 0011001011111010 +word: SLICEB.K0.INIT 0111000000000000 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICED.K1.INIT 0000010100000000 +word: SLICEB.K1.INIT 0010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R66C54:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02N0101 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: B0 V02S0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEA.K1.INIT 0000000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R66C55:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: A3 V02S0501 +arc: B0 N1_V02S0101 +arc: B3 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0201 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C56:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: B0 H00R0100 +arc: B2 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C2 S1_V02N0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F2 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 0101011100000010 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A5 E1_H01W0000 +arc: B0 V00B0000 +arc: B3 S1_V02N0101 +arc: B5 V02S0501 +arc: C0 H02W0601 +arc: C3 V02S0601 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D5 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F3 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K1.INIT 0101000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R66C58:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H02W0701 +arc: A6 V02N0101 +arc: B0 E1_H02W0101 +arc: B3 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 H02W0301 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: V01S0000 Q6 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C59:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 H02W0201 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: A3 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H02W0301 +arc: B2 H00L0000 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F3 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C60:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06N0303 +arc: A5 Q5 +arc: B0 E1_H02W0301 +arc: B4 H02W0101 +arc: C4 Q4 +arc: C5 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 S1_V02N0601 +arc: D5 E1_H01W0100 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F0 +arc: S1_V02S0701 Q5 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C61:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: A2 V02N0701 +arc: B0 V00T0000 +arc: B3 V02N0101 +arc: B7 E1_H02W0301 +arc: C7 E1_H01E0101 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: V01S0000 F3 +word: SLICED.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R66C62:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 W1_H02E0701 +arc: B1 Q1 +arc: B6 S1_V02N0501 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C63:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A2 V02S0501 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C64:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B4 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R66C65:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: B0 H01W0100 +arc: B6 H02W0101 +arc: C0 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R66C66:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A3 W1_H02E0501 +arc: A4 V00T0000 +arc: B3 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0301 F3 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R66C67:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0100 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C2 H02E0401 +arc: C7 V00B0100 +arc: D0 V02N0001 +arc: D2 N1_V02S0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: S3_V06S0003 F0 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C68:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0003 V06S0003 +arc: A1 V02S0501 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 W1_H02E0101 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F5 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C69:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A5 V02N0101 +arc: A7 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C1 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D1 N1_V01S0000 +arc: D3 N1_V02S0001 +arc: D5 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M2 W1_H02E0601 +arc: M4 H02W0401 +arc: M6 V00T0100 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R66C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 V00B0100 +arc: C6 H01E0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 F2 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001110100111111 +word: SLICED.K0.INIT 0011001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C71:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A3 S1_V02N0501 +arc: A5 N1_V02S0101 +arc: A7 V02S0101 +arc: B1 V00B0000 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B7 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0601 +arc: C3 V02N0601 +arc: C5 V00T0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 V01S0100 +arc: D5 W1_H02E0001 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V01S0000 F1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0000111101110111 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C72:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0303 V06S0303 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 H00R0000 +arc: A7 N1_V01N0101 +arc: B1 S1_V02N0301 +arc: B2 H02E0301 +arc: B3 S1_V02N0301 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 N1_V01S0000 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0001 +arc: D1 V02N0001 +arc: D2 W1_H02E0201 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0101010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 1010000011000000 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R66C73:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 V01N0101 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A5 N1_V02S0101 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V02S0501 +arc: E1_H01E0001 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C74:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A6 V02S0301 +arc: B0 V00B0000 +arc: B1 H02W0301 +arc: B2 V02S0101 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C75:PLC2 +arc: E1_H02E0101 V01N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0101 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B7 N1_V02S0701 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C76:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A5 V02N0101 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B3 S1_V02N0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: V00T0000 H02E0001 +arc: A0 V02S0501 +arc: A5 Q5 +arc: A6 H02E0501 +arc: A7 H02E0701 +arc: B1 N1_V02S0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: C4 V00T0000 +arc: C6 Q6 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R66C78:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B4 W1_H02E0101 +arc: B5 V01S0000 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K1.INIT 0000010111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R66C79:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 N1_V02S0401 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 W1_H02E0701 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B6 W1_H02E0101 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M3 H01W0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0201 Q2 +arc: V00T0100 Q3 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C80:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: A0 H02W0701 +arc: B1 V02S0101 +arc: B7 H01E0101 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0000001111110011 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C81:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 N1_V02S0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 W1_H02E0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: S1_V02S0301 F1 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R66C82:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0701 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1101000011110000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0001000000000000 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 1101000011110000 +word: SLICED.K1.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R66C83:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 E3_H06W0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 N1_V02S0601 + +.tile R66C84:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H06W0203 +arc: W1_H02W0401 S1_V02N0401 + +.tile R66C85:PLC2 +arc: E3_H06E0003 V06N0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0303 V06N0303 +arc: A3 V00T0000 +arc: B3 H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R66C86:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0101 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 V06N0003 + +.tile R66C87:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0301 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C3 N1_V01S0100 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R66C88:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R66C89:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V06S0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R66C90:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: A2 H00L0100 +arc: A5 Q5 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 V00B0100 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0401 H06W0203 +arc: N3_V06N0003 H06W0003 + +.tile R66C92:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: V00B0100 H02W0701 +arc: W3_H06W0203 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: B0 W1_H02E0101 +arc: B1 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R66C93:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000001101011111 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 1111001101011111 +word: SLICED.K1.INIT 1111000001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R66C94:PLC2 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A5 W1_H02E0501 +arc: C0 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 S1_V02N0601 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K1.INIT 1010111100000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C95:PLC2 +arc: H00R0100 H02E0501 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A4 H02E0701 +arc: A5 Q5 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H00R0100 +arc: C3 H00R0100 +arc: C4 Q4 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: E1_H02E0301 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R66C96:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 + +.tile R66C97:PLC2 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 + +.tile R66C98:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0103 H06E0103 + +.tile R66C99:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 + +.tile R67C100:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R67C101:PLC2 +arc: W1_H02W0001 N3_V06S0003 + +.tile R67C103:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R67C28:PLC2 +arc: S1_V02S0701 H02W0701 + +.tile R67C29:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0701 E3_H06W0203 + +.tile R67C30:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 + +.tile R67C31:PLC2 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 W1_H02E0401 + +.tile R67C32:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C33:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: B1 E1_H01W0100 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: F0 F5A_SLICE +arc: LSR0 E1_H02W0501 +arc: M0 E1_H02W0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: V00T0000 F0 +arc: V01S0100 Q2 +word: SLICEA.K1.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111111100000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R67C34:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0601 E3_H06W0303 +arc: A0 H00L0000 +arc: A6 H00L0000 +arc: B6 H02W0101 +arc: C0 F6 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D6 H02E0201 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1100000010001000 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C35:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0203 E3_H06W0103 + +.tile R67C36:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0401 N3_V06S0203 + +.tile R67C37:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: A7 N1_V01N0101 +arc: B7 N1_V02S0501 +arc: C7 S1_V02N0001 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 0101110000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C38:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 H02E0701 +arc: A5 E1_H01W0000 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B3 V02S0101 +arc: B6 E1_H02W0301 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N3_V06N0003 Q0 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K1.INIT 1111101011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010001010000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C39:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 H01E0001 +arc: B0 H01W0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C40:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 E3_H06W0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 S3_V06N0303 + +.tile R67C41:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0003 N3_V06S0003 +arc: C1 H00L0000 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: N1_V01N0001 F1 +arc: N3_V06N0103 F1 +arc: S3_V06S0103 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R67C42:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 H02W0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02W0701 +arc: A0 H00L0000 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 F3 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: V01S0000 F3 +arc: W1_H02W0101 F3 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000011111010 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R67C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H01E0101 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H02E0701 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B0 W1_H02E0101 +arc: B1 H02W0101 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V02N0501 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 F6 +arc: C1 H00L0100 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0701 F7 +arc: V00T0100 F1 +arc: V01S0000 F7 +arc: W1_H02W0201 Q0 +word: SLICED.K1.INIT 0000000000001100 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010101010101 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEA.K0.INIT 1100111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C44:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0003 V06N0003 +arc: A2 V01N0101 +arc: A3 H02W0501 +arc: A4 V02S0301 +arc: A6 H02W0701 +arc: A7 V00T0100 +arc: B0 S1_V02N0301 +arc: B2 F1 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 V02S0001 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0100000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000001000001010 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R67C45:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0000 +arc: A3 S1_V02N0501 +arc: A5 H02W0501 +arc: A7 V02S0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 V00B0100 +arc: C7 E1_H02W0601 +arc: D0 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 H00L0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: N1_V02N0201 F2 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0100000000000000 +word: SLICEA.K1.INIT 1100000011000000 +word: SLICEB.K0.INIT 0011001100111111 +word: SLICEB.K1.INIT 0001000100010011 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111111000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C46:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 W1_H02E0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02N0701 +arc: A3 H02W0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: C0 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: D0 V00B0100 +arc: D1 H02W0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: N1_V01N0001 F6 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F1 +arc: S1_V02S0401 F4 +arc: V01S0100 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEC.K1.INIT 0000000010100000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICED.K0.INIT 1010101000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000010001000 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R67C47:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 V01N0001 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A4 V02S0101 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B2 F3 +arc: B4 F1 +arc: B5 E1_H02W0101 +arc: C1 V02S0401 +arc: C2 F4 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C7 V02N0201 +arc: D0 V00T0100 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 F5 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 0000000000000101 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R67C48:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 F7 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C6 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D6 E1_H02W0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F0 +arc: S3_V06S0303 F6 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0100010001000100 +word: SLICED.K0.INIT 0000000010101011 +word: SLICEA.K0.INIT 0000100000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R67C49:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0103 H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A7 H02E0701 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N3_V06N0303 F6 +arc: V01S0100 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R67C50:PLC2 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0501 +arc: A2 H02E0701 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F1 +arc: N3_V06N0103 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEB.K0.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R67C51:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 F7 +arc: A3 H01E0001 +arc: A5 N1_V02S0301 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 N1_V02S0301 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B6 F3 +arc: C0 H00L0000 +arc: C3 V02N0401 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 N1_V01S0000 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: W1_H02W0001 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K1.INIT 0000101000001011 +word: SLICED.K0.INIT 1111111001010100 +word: SLICED.K1.INIT 0000101000001010 +word: SLICEC.K1.INIT 0111000011110000 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C52:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S3_V06S0303 H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: C0 E1_H02W0401 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H01W0100 F0 +arc: W1_H02W0001 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R67C53:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: A0 H02W0501 +arc: A2 S1_V02N0701 +arc: A3 N1_V02S0501 +arc: A7 H02W0501 +arc: B1 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C4 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D6 V01N0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: V01S0000 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R67C54:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B1 N1_V02S0101 +arc: C1 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: H00R0000 Q4 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C55:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 V02S0501 +arc: B0 V00B0000 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: C0 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R67C56:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 F5 +arc: A2 V01N0101 +arc: A3 F5 +arc: A5 H02W0701 +arc: B1 H02W0101 +arc: B3 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 V01S0100 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 F2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1011101110001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R67C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A5 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: C1 V02S0401 +arc: C2 S1_V02N0601 +arc: C3 V02S0401 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R67C58:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 V06S0203 +arc: A0 H00L0000 +arc: B3 H00L0000 +arc: B5 E1_H02W0301 +arc: C0 H02E0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D5 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F4 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R67C59:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0301 +arc: B0 F1 +arc: B5 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 H00R0100 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C60:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0701 +arc: A3 H02E0501 +arc: B2 V02N0101 +arc: B6 S1_V02N0501 +arc: C1 V02S0601 +arc: C2 H02E0401 +arc: C3 E1_H02W0601 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D6 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR1 H02E0301 +arc: M0 H02W0601 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 Q5 +arc: V01S0000 F0 +arc: V01S0100 Q5 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000111100110011 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000111110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C61:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H00L0000 +arc: B1 Q1 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 H02E0201 +arc: E1_H01E0101 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C62:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S3_V06N0203 +arc: B0 V00T0000 +arc: B3 E1_H01W0100 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C5 H02E0401 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F6 +arc: W1_H02W0401 F4 +word: SLICED.K0.INIT 0011000000111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R67C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02E0701 +arc: A5 N1_V02S0301 +arc: B3 H01W0100 +arc: C0 N1_V01N0001 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D5 V02S0601 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R67C64:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R67C65:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: S1_V02S0301 E1_H01W0100 +arc: V00T0100 N1_V02S0501 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C66:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00R0000 +arc: B1 Q1 +arc: B2 H02W0101 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C67:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 V02S0501 +arc: B6 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R67C68:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: A2 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02E0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 W1_H02E0601 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V02S0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 F1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R67C69:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 V00T0100 +arc: B0 V02S0301 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C5 V02N0201 +arc: D0 V02S0001 +arc: D5 V02N0601 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 0011010100111111 +word: SLICEC.K1.INIT 0101000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R67C70:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 V00T0000 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B3 V02N0101 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 F3 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 1100010010000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C71:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H01E0001 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: B0 N1_V02S0301 +arc: B1 E1_H02W0101 +arc: B2 F3 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B5 H02W0301 +arc: B6 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0601 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: D0 V02S0201 +arc: D1 E1_H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F6 +arc: W1_H02W0201 F0 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0100011101110111 +word: SLICEA.K1.INIT 1010000011000000 +word: SLICEC.K0.INIT 1110000001000000 +word: SLICED.K0.INIT 1000100010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C72:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 V01N0001 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 N1_V02S0701 +arc: A2 E1_H02W0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 V01N0001 +arc: B5 V02S0701 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: D1 H02W0201 +arc: D2 E1_H02W0001 +arc: D3 V02N0201 +arc: D4 F2 +arc: D5 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0401 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F3 +arc: S3_V06S0303 F5 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 1010000010001000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1100010011110101 +word: SLICEC.K0.INIT 1010010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R67C73:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06W0103 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A2 V02S0501 +arc: A4 H02E0701 +arc: A5 N1_V02S0101 +arc: A6 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 V02S0701 +arc: C1 V02S0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R67C74:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0203 V06S0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: C5 W1_H02E0401 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R67C75:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H02E0701 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B7 H01E0101 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: S1_V02S0701 Q7 +arc: S3_V06S0103 Q2 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q5 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H00L0100 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 W1_H02E0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0201 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 Q1 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q0 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100001101000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R67C77:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W1_H02E0001 +arc: H00L0000 N1_V02S0001 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A3 H01E0001 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0101 +arc: B6 H02E0101 +arc: C1 E1_H02W0401 +arc: C2 N1_V01N0001 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0100 Q2 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C78:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 H02E0501 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0401 +arc: C3 H02E0601 +arc: C5 V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R67C79:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0203 V06S0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A5 Q5 +arc: A6 N1_V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: V00B0100 Q5 +arc: V00T0000 F2 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R67C80:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 H01E0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0701 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 N1_V01S0000 +arc: E1_H02E0001 F0 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEA.K1.INIT 1111101100111011 +word: SLICEB.K0.INIT 1110010000000000 +word: SLICEB.K1.INIT 1111011110110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C81:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 N1_V02S0101 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1011000011110000 +word: SLICEB.K1.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C82:PLC2 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0100 H02E0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 S1_V02N0301 +arc: A6 V02N0101 +arc: A7 S1_V02N0301 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 E1_H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H02W0001 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 1101000011110000 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 1101000011110000 +word: SLICEA.K1.INIT 1011000011110000 +word: SLICEB.K0.INIT 0001000000000000 +word: SLICEB.K1.INIT 1011000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R67C83:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V00T0000 +arc: B5 H00L0000 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R67C84:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V06S0303 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C5 F6 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: V00B0100 F7 +arc: V01S0000 Q1 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C85:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 W3_H06E0303 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: C2 H00L0000 +arc: C5 V02S0201 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C86:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0601 V02S0601 + +.tile R67C87:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0701 +arc: A5 H02W0701 +arc: A7 V02S0101 +arc: B0 S1_V02N0301 +arc: B2 V02S0301 +arc: B4 V02S0501 +arc: B6 H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R67C88:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 H02E0701 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B5 H02W0301 +arc: C3 E1_H02W0601 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 W1_H02E0201 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0100 F0 +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F0 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C89:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E3_H06W0003 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 V02N0301 +arc: B4 V02N0501 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C4 V00B0100 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 E1_H02W0001 +arc: M2 W1_H02E0601 +arc: M3 H00R0100 +arc: M4 W1_H02E0401 +arc: M5 E1_H02W0001 +arc: M6 W1_H02E0401 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 0000000001010000 +word: SLICED.K0.INIT 1010011111110111 +word: SLICED.K1.INIT 0001010100011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C90:PLC2 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 V02S0701 +arc: A4 V02S0101 +arc: A5 N1_V01S0100 +arc: A6 V02S0101 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: C1 N1_V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R67C91:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 N1_V02S0701 +arc: B0 H01W0100 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICED.K1.INIT 1111001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R67C92:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 H01E0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0203 S1_V02N0401 +arc: V00B0100 V02S0301 +arc: A0 H02E0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 Q3 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q3 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010110010101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C93:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 N1_V02S0301 +arc: W3_H06W0303 V06S0303 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEC.K1.INIT 0000001100000000 +word: SLICED.K0.INIT 1111001101011111 +word: SLICED.K1.INIT 0000001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R67C94:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0401 H06E0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: B0 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C95:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 V06S0003 +arc: A0 H02E0501 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R67C96:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0101 V02N0101 + +.tile R67C97:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S1_V02N0201 + +.tile R67C98:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0103 S1_V02N0201 + +.tile R67C99:PLC2 +arc: N1_V02N0001 E1_H02W0001 + +.tile R68C100:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R68C102:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R68C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C106:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C109:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R68C111:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C112:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R68C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R68C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R68C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R68C28:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: B4 V02S0701 +arc: C0 F4 +arc: C4 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1111001100000000 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C29:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 H01E0001 +arc: S1_V02S0201 H01E0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A2 H00L0100 +arc: A5 V00T0000 +arc: A6 F5 +arc: A7 V02N0101 +arc: B2 V02N0301 +arc: B5 V02N0501 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 E1_H01W0000 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R68C30:PLC2 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: A2 V00T0000 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 V02N0701 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: MUXCLK0 CLK0 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C31:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0101 H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0401 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C32:PLC2 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 H02E0401 +arc: V00T0000 V02S0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 S1_V02N0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V00T0100 Q1 +word: SLICED.K1.INIT 0000001000000000 +word: SLICEC.K1.INIT 0101010100010101 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEB.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 1101111110001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C33:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: A0 H01E0001 +arc: A1 H00L0000 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: B0 V02S0101 +arc: B1 F3 +arc: B2 V01N0001 +arc: B3 V02S0101 +arc: B4 H01E0101 +arc: B5 H00R0000 +arc: B6 V02N0701 +arc: C0 W1_H02E0401 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 W1_H02E0401 +arc: C4 H01E0001 +arc: C5 E1_H02W0401 +arc: C6 V02S0001 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 V02S0001 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: V01S0000 F4 +arc: V01S0100 F2 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 0101010100010101 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICED.K0.INIT 0000000011110111 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEA.K1.INIT 0010001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C34:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 H01W0100 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0000000011011111 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICED.K0.INIT 0000000001000000 +word: SLICEB.K1.INIT 0101010100010101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K1.INIT 1011101111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C35:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 E1_H01W0000 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0103 + +.tile R68C36:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 V02S0701 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A6 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 V01N0101 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D3 H02W0001 +arc: D5 F0 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1111101111111011 +word: SLICEB.K1.INIT 1100100011111011 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100000011110011 +word: SLICEA.K0.INIT 1111001111111111 +word: SLICEA.K1.INIT 1100010011110111 +word: SLICED.K1.INIT 0000000011000000 +word: SLICED.K0.INIT 0000111100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R68C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00L0000 V02N0201 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H00R0100 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00R0100 Q7 +arc: M0 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V00T0000 F2 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 Q7 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111111110111000 +word: SLICEA.K1.INIT 1100111110001000 +word: SLICEB.K0.INIT 0000000001010111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C38:PLC2 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0201 N1_V01S0000 + +.tile R68C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 + +.tile R68C40:PLC2 +arc: N1_V02N0201 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V01S0000 S3_V06N0103 +arc: A0 H02E0701 +arc: A4 F5 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0401 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F1 +arc: S1_V02S0201 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1000101010001000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R68C41:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0100 H02E0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 V01N0001 +arc: A2 V01N0101 +arc: A7 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C7 H02W0601 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02N0001 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0301 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V01S0100 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R68C42:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 S1_V02N0701 +arc: A3 V01N0101 +arc: A4 F7 +arc: A5 V00T0000 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 F1 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H01E0001 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 H01E0101 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: M2 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V00B0100 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F4 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICED.K1.INIT 0000001100000000 +word: SLICEC.K0.INIT 0000000100000101 +word: SLICEB.K0.INIT 1111111111111100 +word: SLICEB.K1.INIT 1111110111111100 +word: SLICEA.K0.INIT 1111111100001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R68C43:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A6 V02S0301 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B3 E1_H01W0100 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: B7 E1_H02W0101 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: D6 H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F5 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000100000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0111111100000000 +word: SLICED.K1.INIT 0000001100000000 +word: SLICEB.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R68C44:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 N1_V01S0000 +arc: A1 H02W0701 +arc: A2 E1_H02W0701 +arc: A5 V02N0101 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B1 V02S0301 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0301 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 F6 +arc: C3 V02N0401 +arc: C5 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 E1_H01E0101 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 F2 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: V00B0000 F4 +arc: V01S0100 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000001110000 +word: SLICEC.K1.INIT 0000001000100010 +word: SLICEB.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 0111111100000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R68C45:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 V02S0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H02E0701 +arc: A1 V02S0501 +arc: A3 V01N0101 +arc: A5 F7 +arc: B0 V01N0001 +arc: B3 E1_H02W0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: V01S0000 F1 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001111100111111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0011111111111111 +word: SLICEC.K1.INIT 0001010101010101 +word: SLICEA.K0.INIT 1111001111110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 H02W0501 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C1 S1_V02N0601 +arc: C2 V02N0401 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 V02S0001 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 F0 +arc: D3 V00B0100 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: W1_H02W0301 F1 +word: SLICED.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 0101000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R68C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 V02S0301 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H01E0001 +arc: A1 H02E0501 +arc: A2 W1_H02E0701 +arc: A3 H01E0001 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: B0 H02W0301 +arc: B1 S1_V02N0101 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 F1 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K1.INIT 0001000001010000 +word: SLICED.K1.INIT 0000000011000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1010000010100000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEB.K0.INIT 0001001100110011 +word: SLICEA.K0.INIT 0010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R68C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0303 V01N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H02E0701 +arc: A3 H02W0701 +arc: A6 F7 +arc: B0 H00R0100 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: C0 H02W0401 +arc: C2 F4 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C5 F6 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 F0 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: N1_V01N0001 F5 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +arc: V01S0100 F7 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R68C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 E1_H02W0501 +arc: B2 H02W0301 +arc: C2 S1_V02N0601 +arc: D2 V02N0201 +arc: F2 F2_SLICE +arc: S3_V06S0103 F2 +word: SLICEB.K0.INIT 0000000000011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R68C50:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0301 N1_V02S0301 + +.tile R68C51:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E3_H06W0203 + +.tile R68C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0101 V06S0103 + +.tile R68C53:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 V02N0501 +arc: W3_H06W0303 E3_H06W0303 +arc: A7 N1_V01S0100 +arc: B3 V02S0301 +arc: B5 N1_V01S0000 +arc: B7 V02S0501 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q1 +arc: V00T0000 F2 +arc: V01S0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C54:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 E3_H06W0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0601 E3_H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0103 E3_H06W0103 +arc: A5 V02N0301 +arc: B0 F1 +arc: B1 H02W0301 +arc: B2 V01N0001 +arc: B3 F1 +arc: B4 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: M2 H02W0601 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +word: SLICEA.K1.INIT 0011000000111111 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0011001111110000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R68C55:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B5 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V01N0001 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0001 F2 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R68C56:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 V02S0101 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 E1_H01W0100 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02W0201 +arc: D5 V02S0401 +arc: E1_H01E0001 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q7 +arc: V00T0000 F2 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C57:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 V01N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 N1_V02S0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H02W0401 +arc: C3 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: M2 W1_H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: S3_V06S0203 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R68C58:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A2 V02N0501 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 V02S0601 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D4 V01N0001 +arc: D5 H01W0000 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0601 F4 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R68C59:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 N1_V02S0101 +arc: A7 V02S0101 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B6 H02E0301 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 0101010100001111 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R68C60:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06W0303 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0101 +arc: A7 V02S0101 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B6 V00B0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 H00L0100 +arc: C4 Q4 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: V00B0000 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C61:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A3 H00L0100 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F7 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0011101000111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R68C62:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A5 V00B0000 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B3 H00L0000 +arc: B6 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C3 H00R0100 +arc: C5 V00T0000 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 N1_V01S0000 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R68C63:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 F5 +arc: A4 V02N0301 +arc: A6 N1_V02S0101 +arc: B1 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B5 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C3 S1_V02N0601 +arc: C5 V02N0001 +arc: C6 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: W1_H02W0301 F1 +word: SLICEC.K0.INIT 0011001101010101 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEC.K1.INIT 0000001111110011 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K0.INIT 0101010100001111 +word: SLICEB.K1.INIT 0011001100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R68C64:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 V02S0701 +arc: B5 N1_V02S0501 +arc: C2 S1_V02N0401 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0001 +arc: D5 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0401 Q6 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q3 +arc: V01S0100 Q4 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 0101010100001111 +word: SLICEC.K1.INIT 0011001100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C65:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B2 V02S0301 +arc: B5 H02W0101 +arc: C0 V02N0601 +arc: C2 V02N0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V01S0000 Q0 +arc: W3_H06W0303 F5 +word: SLICEB.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0100000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R68C66:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: B0 N1_V02S0301 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A2 V00T0000 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C2 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0103 F2 +arc: V01S0000 F7 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C68:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 V06N0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: V00B0100 W1_H02E0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C69:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 S1_V02N0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C70:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00T0000 W1_H02E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C71:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: D0 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0001 F2 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0401 F4 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F0 +arc: W3_H06W0203 F4 +word: SLICEB.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEC.K0.INIT 0000000010100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R68C72:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C4 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +arc: N1_V02N0301 F1 +arc: N1_V02N0601 F4 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0011000000000000 +word: SLICEA.K0.INIT 0000000000110000 +word: SLICEC.K0.INIT 0000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R68C73:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N1_V01S0000 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A6 V02N0101 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B5 V02N0701 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C5 V02N0201 +arc: C6 H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M7 E1_H01W0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0303 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 Q7 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 0000101000000000 +word: SLICEA.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 1100110011001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R68C74:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 V02S0101 +arc: B0 H00R0100 +arc: B1 V02S0301 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C4 S1_V02N0001 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 F1 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1110110000000000 +word: SLICEA.K1.INIT 1000010000100001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C75:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0701 +arc: A3 H00L0100 +arc: B0 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B4 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0100 F2 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C76:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 N1_V01S0000 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: V01S0000 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K1.INIT 1000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R68C77:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A4 N1_V01N0101 +arc: A5 V02S0301 +arc: B0 N1_V02S0101 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 W1_H02E0301 +arc: B6 V02S0701 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 V02S0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 S1_V02N0001 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: S1_V02S0101 Q1 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C78:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02N0701 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D6 V02S0401 +arc: D7 H02E0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 Q0 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R68C79:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0003 +arc: B1 W1_H02E0301 +arc: D0 H02E0001 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0011001100110011 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R68C80:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: V00B0100 H02W0701 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C81:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0003 S3_V06N0003 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 S3_V06N0303 + +.tile R68C82:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A5 V02N0101 +arc: B0 H02W0101 +arc: B2 S1_V02N0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B6 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C83:PLC2 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0101 H06W0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C84:PLC2 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C85:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C86:PLC2 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 H01E0001 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: V01S0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R68C87:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R68C88:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: D0 V00B0100 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M1 H00R0100 +arc: M2 W1_H02E0601 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C89:PLC2 +arc: H00L0000 H02W0201 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: B0 V02N0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C90:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 V06N0103 +arc: A0 E1_H01E0001 +arc: A4 V02N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: S3_V06S0003 Q3 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 1000100011001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C91:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0201 H01E0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 V06N0203 +arc: A0 H01E0001 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C92:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V06N0303 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: B0 N1_V02S0101 +arc: C2 N1_V01S0100 +arc: C5 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D3 N1_V01S0000 +arc: D4 H00L0100 +arc: D6 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R68C93:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C94:PLC2 +arc: E1_H02E0201 V06N0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R68C95:PLC2 +arc: N1_V02N0201 H02E0201 +arc: W1_H02W0101 V06N0103 + +.tile R68C96:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0301 S3_V06N0003 + +.tile R68C97:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 + +.tile R68C98:PLC2 +arc: N1_V02N0501 H02E0501 + +.tile R68C99:PLC2 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R69C100:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R69C101:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R69C103:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R69C104:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C105:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R69C106:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R69C107:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C108:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R69C110:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R69C111:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R69C28:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C29:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: V00B0000 V02S0201 +arc: A2 V02N0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C4 Q4 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 Q7 +arc: H01W0000 Q6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q4 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C2:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R69C30:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N3_V06N0003 E3_H06W0003 +arc: A5 Q5 +arc: A7 Q7 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 Q4 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C31:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: V00B0000 V02S0001 +arc: V00B0100 W1_H02E0701 +arc: A0 F5 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 N1_V01S0100 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B2 F3 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H02W0601 +arc: C3 N1_V02S0401 +arc: C4 H02E0601 +arc: C5 V02N0001 +arc: C6 N1_V02S0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V00T0000 Q0 +arc: V01S0000 F7 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICEB.K0.INIT 0011001100010011 +word: SLICEC.K1.INIT 1000001000000000 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R69C32:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0100 H02W0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B4 H00R0000 +arc: B5 F3 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 H00R0100 +arc: C1 E1_H02W0401 +arc: C2 E1_H01W0000 +arc: C3 N1_V02S0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 H00R0000 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0011001100010011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEC.K0.INIT 1000000000100000 +word: SLICEB.K0.INIT 1010111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C33:PLC2 +arc: H00L0000 V02N0201 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 H01E0001 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 H02E0101 +arc: B6 V00T0000 +arc: B7 H01E0101 +arc: C0 N1_V01S0100 +arc: C1 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F6 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEB.K0.INIT 0101010100010101 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0101000101010101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1101111110001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C34:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 N1_V01S0100 +arc: B4 N1_V01S0000 +arc: C4 E1_H02W0401 +arc: D4 V02S0401 +arc: F4 F4_SLICE +arc: H01W0000 F4 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R69C35:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0401 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile R69C36:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0701 +arc: A2 H02E0701 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B3 V02S0101 +arc: C0 V02N0401 +arc: C2 V02S0601 +arc: C3 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +word: SLICEA.K0.INIT 1101110110000000 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 1101100011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C37:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 N1_V01S0100 +arc: A1 H01E0001 +arc: B1 H02E0301 +arc: B3 N1_V02S0101 +arc: B6 V02S0701 +arc: B7 H01E0101 +arc: C3 F6 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 F7 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 0000110000000011 +word: SLICEB.K1.INIT 0011111100001100 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100110001010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C38:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0100 V02S0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: A1 H01E0001 +arc: A4 H02E0501 +arc: B1 V02S0101 +arc: B4 V02S0701 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02S0201 +arc: D4 H00L0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0111011101000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C39:PLC2 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: V00B0100 H02W0701 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: B2 W1_H02E0101 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 F2 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R69C40:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: C0 V02N0601 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F1 +word: SLICEA.K0.INIT 1111000011111010 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C41:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 H01E0001 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 E1_H02W0501 +arc: A3 H02E0501 +arc: A5 H02E0501 +arc: B1 F3 +arc: B2 H00L0000 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C4 V02S0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 1111010111110000 +word: SLICEA.K1.INIT 1100110011111100 +word: SLICEB.K0.INIT 1111000011111100 +word: SLICEB.K1.INIT 0000000001000100 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C42:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 H00L0100 +arc: A3 H01E0001 +arc: A5 V02S0101 +arc: A6 F7 +arc: A7 F5 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C1 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C6 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 H02W0201 +arc: D4 E1_H02W0001 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00B0100 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K1.INIT 0011001100110001 +word: SLICEB.K0.INIT 0000000011001111 +word: SLICEC.K0.INIT 0000110000001111 +word: SLICEC.K1.INIT 1010101000000000 +word: SLICED.K1.INIT 0000000010001000 +word: SLICED.K0.INIT 0000010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R69C43:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 V02S0101 +arc: B1 H02E0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B5 F1 +arc: B6 H01E0101 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 V02S0401 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 F3 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0000000000110000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0011000100110011 +word: SLICED.K0.INIT 1000100000001000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K1.INIT 0101111100000000 +word: SLICEA.K0.INIT 0111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C44:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0100 +arc: A1 W1_H02E0701 +arc: A2 F5 +arc: A3 E1_H02W0501 +arc: A7 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 V00B0000 +arc: C0 F6 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: D0 H02E0201 +arc: D1 N1_V02S0201 +arc: D3 H02E0001 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: V01S0100 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEB.K1.INIT 0000000010100000 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 1010000010100000 +word: SLICEA.K0.INIT 0000000000000100 +word: SLICEC.K0.INIT 0000110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R69C45:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V00T0000 +arc: B1 H02E0301 +arc: B2 N1_V02S0301 +arc: B3 E1_H02W0301 +arc: C0 V02N0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: D0 W1_H02E0001 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 F0 +arc: D5 F2 +arc: D6 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F6 +arc: V00T0000 F0 +arc: V01S0100 F1 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000010100000101 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0001000100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000101000000000 +word: SLICEB.K1.INIT 1100000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R69C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B5 V02N0501 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C7 H02E0401 +arc: D0 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D5 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F1 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F7 +arc: V01S0100 F3 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 0000001000000010 +word: SLICED.K1.INIT 0100000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICEB.K0.INIT 0000001100000000 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R69C47:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H00L0100 +arc: A3 V02N0501 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: B0 H02W0101 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B6 H02E0301 +arc: B7 V02S0701 +arc: C0 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C7 V02S0001 +arc: D0 H02E0001 +arc: D3 H01E0101 +arc: D4 H02E0201 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N1_V02N0501 F7 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V00B0100 F5 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 0011000000000000 +word: SLICED.K0.INIT 0100010000000000 +word: SLICEA.K0.INIT 0000000000000010 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000010100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R69C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H01E0001 +arc: A4 H02W0501 +arc: A7 E1_H01W0000 +arc: B1 V02S0101 +arc: B4 H02W0101 +arc: B5 H01E0101 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C1 N1_V01S0100 +arc: C4 N1_V02S0001 +arc: D1 H00R0000 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F4 +arc: V00B0100 F7 +arc: V01S0000 F6 +arc: V01S0100 F6 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0010000000110000 +word: SLICED.K1.INIT 1000100010001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R69C49:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 H01E0001 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A4 S1_V02N0101 +arc: A5 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 V00B0100 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: D1 H02E0001 +arc: D2 N1_V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F0 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F2 +arc: V01S0000 F0 +arc: V01S0100 F0 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1010000000100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICEC.K0.INIT 0001000100110001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R69C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: H01W0000 E3_H06W0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R69C51:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H02W0701 +arc: A2 H02E0501 +arc: A3 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 N1_V02S0701 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0401 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: D0 S1_V02N0001 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 H02E0001 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F3 +arc: V01S0100 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R69C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: A4 H02W0701 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M5 H02W0001 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W3_H06W0203 F4 +word: SLICED.K0.INIT 1011000010000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R69C53:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A5 N1_V01S0100 +arc: A7 E1_H01W0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H01E0101 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0101010111110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R69C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 V06S0203 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B6 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 N1_V02S0601 +arc: D6 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M3 H00L0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0401 F4 +arc: S3_V06S0303 F6 +arc: V00T0000 Q2 +arc: V01S0000 F6 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0000000011001010 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111001111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A3 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 V00T0000 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B6 H02E0301 +arc: C1 H00L0100 +arc: C4 V00B0100 +arc: C5 H02W0601 +arc: C6 H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 V02S0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 F5 +arc: V00T0000 Q2 +arc: V01S0000 Q7 +arc: V01S0100 Q6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 F7 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 0101000001011111 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R69C56:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 N1_V02S0701 +arc: A2 V02S0701 +arc: A5 V02N0301 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 Q7 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 0000000000010000 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R69C57:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: A7 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B5 H02W0101 +arc: B6 V00T0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 H02E0201 +arc: D3 V00T0100 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q5 +arc: N1_V02N0601 Q6 +arc: S1_V02S0401 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0301 Q3 +word: SLICED.K0.INIT 0011001000000010 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R69C58:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 H02E0001 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 S1_V02N0301 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D5 N1_V02S0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 Q6 +arc: V01S0000 F2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q5 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000110011111100 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C59:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A5 V00T0000 +arc: B1 V02N0301 +arc: B3 S1_V02N0101 +arc: B7 V00B0000 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 H01E0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0000110011111100 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R69C60:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0501 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: A4 W1_H02E0701 +arc: A5 N1_V01N0101 +arc: B1 Q1 +arc: B3 V02S0101 +arc: B7 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C5 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D5 N1_V02S0601 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F6 +arc: V01S0000 F4 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEB.K0.INIT 0000111110101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R69C61:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: A1 E1_H02W0501 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 H02W0101 +arc: C0 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0401 +arc: C4 V00T0000 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 Q6 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 H02E0301 +arc: M6 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q5 +arc: S3_V06S0303 Q5 +arc: V00T0000 Q0 +arc: V01S0100 Q7 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 0011001100001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1110111000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C62:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 S1_V02N0701 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H02E0201 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +word: SLICED.K0.INIT 0000111100110011 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R69C63:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A4 V00B0000 +arc: A5 N1_V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 S1_V02N0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q3 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0101010100001111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0011001111110000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: A5 E1_H01W0000 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B6 S1_V02N0501 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: C3 V02S0601 +arc: C5 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000111110101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R69C65:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 H02E0501 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 0101111101010000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000101011111010 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R69C66:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 S1_V02N0501 +arc: A5 E1_H01W0000 +arc: B0 F1 +arc: B3 V02S0301 +arc: B5 H02W0301 +arc: B7 E1_H02W0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F6 +word: SLICEA.K1.INIT 0000111101010101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R69C67:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 H02E0701 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 W1_H02E0101 +arc: B5 H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: C5 H02E0401 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 0000000011100000 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C68:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A4 S1_V02N0101 +arc: B0 H02E0301 +arc: B1 N1_V02S0301 +arc: B2 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C4 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02N0601 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 F2 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 0011001100001111 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R69C69:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: S1_V02S0501 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 + +.tile R69C70:PLC2 +arc: E1_H02E0201 V02S0201 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H02W0401 +arc: A0 H00L0000 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C71:PLC2 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H01E0001 +arc: B0 V00T0000 +arc: B7 V00T0000 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0401 F4 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111000000001111 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICED.K1.INIT 1100110000001111 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R69C72:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 V06S0203 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A5 Q5 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C73:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0103 E3_H06W0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0303 + +.tile R69C74:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 F7 +arc: A3 V00T0000 +arc: B0 H00R0100 +arc: B2 F1 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V01S0100 +arc: D5 V00B0000 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F1 +arc: N1_V02N0701 F5 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000010100000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C75:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F7 +arc: A5 Q5 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C1 W1_H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 S1_V02N0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: W1_H02W0401 Q6 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C76:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S1_V02N0201 +arc: V00B0000 H02W0601 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 E3_H06W0103 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 H02E0401 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0011001100110011 +word: SLICED.K1.INIT 0011001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C77:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 H02E0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: A3 F5 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 V02S0301 +arc: C0 H02E0601 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V00B0100 +arc: D5 V02N0601 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C78:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0301 +arc: B2 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C6 V02S0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D5 V02S0401 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +word: SLICEA.K0.INIT 1010110000000000 +word: SLICEA.K1.INIT 1110010011111111 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000111100001111 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C79:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 V00B0000 +arc: A6 H02E0501 +arc: B2 V02S0101 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C6 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 N1_V01S0000 +arc: D6 H02E0001 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000001000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R69C80:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V01S0100 +arc: A6 N1_V01S0100 +arc: B5 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C3 H02E0401 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 0101010101010101 +word: SLICEC.K1.INIT 0011001100110011 +word: SLICED.K0.INIT 0101010101010101 +word: SLICED.K1.INIT 0011001100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C81:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: B3 E1_H02W0301 +arc: B7 H01E0101 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 S1_V02N0001 +arc: C7 V02S0001 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D6 V00B0000 +arc: D7 V02S0601 +arc: E1_H02E0701 F7 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: W1_H02W0401 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0001000010110000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R69C82:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: S3_V06S0003 N3_V06S0003 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0501 +arc: A0 H02W0701 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H02W0501 +arc: A6 V02S0101 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02E0401 +arc: C6 V02N0001 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D6 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: M0 H01E0001 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: V01S0100 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000000000000 +word: SLICEA.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 1011000011110000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICED.K0.INIT 0101000000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R69C83:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 W1_H02E0701 +arc: A1 F7 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C7 V02N0201 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: M0 H02W0601 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: N1_V02N0701 F7 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0001000011010000 +word: SLICEA.K1.INIT 0000000001010000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R69C84:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +arc: N3_V06N0203 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 1100110011000011 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R69C85:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0101 +arc: B2 E1_H01W0100 +arc: B3 H02E0301 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R69C86:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: D0 H02E0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: N3_V06N0003 F0 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0110011000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R69C87:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W3_H06W0003 V06S0003 +arc: A3 V02N0701 +arc: A4 H02W0501 +arc: B0 E1_H02W0301 +arc: B2 V02N0301 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C88:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C89:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 S1_V02N0201 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C90:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R69C91:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 W3_H06E0103 +arc: V00B0000 V02S0201 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B5 W1_H02E0101 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 F2 +arc: N1_V02N0701 Q5 +arc: N3_V06N0303 Q6 +arc: S3_V06S0303 Q6 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R69C92:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 S1_V02N0401 +arc: W1_H02W0301 S1_V02N0301 + +.tile R69C93:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 H06E0303 + +.tile R69C94:PLC2 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 H06E0103 + +.tile R69C95:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0101 S3_V06N0103 + +.tile R69C96:PLC2 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R69C97:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R69C98:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R69C99:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R6C40:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02W0401 +arc: A0 V02N0701 +arc: B0 V02N0101 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 1101110000010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C41:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02W0501 +arc: A6 E1_H01W0000 +arc: B0 V00T0000 +arc: B2 V02N0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V02N0001 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 V01N0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111011000000110 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110000001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C42:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A4 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: C0 N1_V02S0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H02E0101 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C43:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A4 V02S0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 H02E0101 +arc: C0 F4 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICED.K0.INIT 1010001110101100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1100110001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C44:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: H00L0000 V02N0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02S0301 +arc: A0 H00L0000 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 H00R0100 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V02N0701 +arc: C0 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0401 Q6 +arc: V00B0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C45:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 W1_H02E0201 +arc: V01S0100 S3_V06N0303 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 W1_H02E0701 +arc: B0 H00R0100 +arc: B2 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H00R0000 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F0 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F2 +arc: V01S0000 Q6 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1110111001000100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C46:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V01N0101 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C47:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: A6 V02S0301 +arc: B0 H02E0101 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 H02E0301 +arc: C0 E1_H01W0000 +arc: C2 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 Q3 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEB.K0.INIT 1100101011001010 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C48:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 H02E0001 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A6 H02W0701 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 H02E0101 +arc: B7 V01S0000 +arc: C0 V02N0401 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V01N0101 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H02E0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICED.K0.INIT 1110010011100100 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C49:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02N0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: C0 H00R0100 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C50:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 E1_H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C51:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V02N0101 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: B0 E1_H01W0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: C0 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0201 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1000110111011000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C52:PLC2 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 E1_H02W0001 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R6C53:PLC2 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0401 V02N0401 + +.tile R6C54:PLC2 +arc: W1_H02W0001 W3_H06E0003 + +.tile R71C100:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C101:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R71C102:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R71C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C104:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C105:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C107:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C108:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R71C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C110:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C111:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R71C112:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C113:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C115:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C116:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C117:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R71C118:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C14:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C15:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R71C20:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C21:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R71C23:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C30:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 + +.tile R71C31:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 S1_V02N0001 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1010111111001100 +word: SLICEA.K1.INIT 1100111110101010 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0101010100010101 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEB.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 1011101111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C32:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H01E0001 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 H00R0000 +arc: B0 H02W0101 +arc: B3 H02W0101 +arc: B4 F3 +arc: B5 H02W0101 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: D0 S1_V02N0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 S1_V02N0401 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICED.K0.INIT 0101010100010101 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 0010001100110011 +word: SLICED.K1.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C33:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A3 F7 +arc: A4 S1_V02N0101 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 S1_V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 F6 +arc: C4 W1_H02E0401 +arc: C5 V00T0100 +arc: C6 H02W0601 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEB.K0.INIT 1011101111110000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICED.K0.INIT 0101010100010101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 1010111111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C34:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02W0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 S1_V02N0501 +arc: A2 H01E0001 +arc: A3 V02N0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 V02N0701 +arc: B5 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 H01E0101 +arc: C0 H00R0100 +arc: C2 H02E0401 +arc: C3 S1_V02N0401 +arc: C4 N1_V02S0201 +arc: C5 E1_H01E0101 +arc: C6 V00T0100 +arc: C7 N1_V02S0201 +arc: D0 H02E0201 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: V00B0000 F4 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEA.K0.INIT 0011000100110011 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000101100001111 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K0.INIT 0011001100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C35:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V01N0101 +arc: A7 N1_V02S0301 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0601 +arc: C1 F4 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1101111110001010 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICEA.K1.INIT 1111010111001100 +word: SLICEC.K1.INIT 1000010000000000 +word: SLICEB.K0.INIT 1010111111001100 +word: SLICED.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 1010111111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C36:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C4 V00B0100 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F7 +arc: V01S0000 F4 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEA.K0.INIT 0000000000100000 +word: SLICED.K0.INIT 0000000011011111 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEC.K1.INIT 0010001100110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R71C37:PLC2 +arc: W1_H02W0701 V06S0203 +arc: A6 V00T0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B6 V01S0000 +arc: C0 V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D6 H01W0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C38:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N1_V02S0001 +arc: A0 N1_V02S0701 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0101010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: A2 H01E0001 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B7 H02E0101 +arc: C2 H00L0000 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D2 V02S0201 +arc: D7 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R71C3:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C40:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 N1_V02S0601 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02W0501 +arc: V00T0000 E1_H02W0201 +arc: A0 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B2 F1 +arc: B3 F1 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V02S0601 +arc: C5 V00T0000 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 W1_H02E0001 +arc: D4 V01N0001 +arc: D5 F2 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +arc: V01S0100 F3 +word: SLICED.K1.INIT 0000111100000101 +word: SLICED.K0.INIT 0010001000101010 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0001010100000000 +word: SLICEB.K0.INIT 0011001100000011 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000000110011 +word: SLICEC.K0.INIT 1010101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R71C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 V02N0101 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 F6 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0001 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D0 F2 +arc: D1 N1_V02S0201 +arc: D2 H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 F2 +arc: D6 W1_H02E0201 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +word: SLICEB.K0.INIT 0000000000001100 +word: SLICEC.K0.INIT 0000001000001010 +word: SLICEC.K1.INIT 0001101100000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000001100001111 +word: SLICED.K0.INIT 0000001000110010 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEB.K1.INIT 0100111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C42:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V01N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: A4 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02W0101 +arc: B3 H02E0101 +arc: B4 E1_H02W0301 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D0 H02E0001 +arc: D3 H02E0201 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: N1_V02N0401 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0100110011001100 +word: SLICEC.K0.INIT 1110000000000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C43:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02N0101 +arc: A1 H02E0701 +arc: A3 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 H02W0701 +arc: B0 E1_H02W0101 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 N1_V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100000011111111 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0000001000000011 +word: SLICEC.K0.INIT 0010001010101010 +word: SLICEA.K1.INIT 0111000000000000 +word: SLICED.K0.INIT 0000000000011111 +word: SLICEB.K0.INIT 1111110011001100 +word: SLICEB.K1.INIT 1111111111100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C44:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 N1_V02S0201 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: A0 H01E0001 +arc: A2 F7 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A5 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B3 H02W0301 +arc: B5 H02W0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 N1_V02S0201 +arc: C6 H02E0401 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 F2 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 0001000000110000 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R71C45:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A5 N1_V02S0101 +arc: B1 V02N0101 +arc: B2 H02W0301 +arc: B5 H01E0101 +arc: C0 V02N0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 H02E0201 +arc: D3 V02N0201 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: N1_V02N0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +arc: V01S0000 F4 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111010100000000 +word: SLICEA.K1.INIT 1111110100000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C46:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 S3_V06N0003 +arc: A2 N1_V02S0701 +arc: A4 H02E0701 +arc: A7 N1_V02S0101 +arc: B3 H02W0101 +arc: B4 N1_V02S0501 +arc: B5 V02S0501 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 N1_V02S0401 +arc: C4 H02E0601 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 N1_V02S0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 F2 +arc: D7 H02E0001 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0701 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0011000000000000 +word: SLICEC.K0.INIT 0111000011110000 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000000110011 +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R71C47:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 S1_V02N0501 +arc: A1 W1_H02E0501 +arc: A2 V00T0000 +arc: A4 H02W0501 +arc: A6 V00T0100 +arc: B0 W1_H02E0301 +arc: B2 H02E0301 +arc: B6 F1 +arc: B7 W1_H02E0301 +arc: C0 H00R0100 +arc: C1 V02S0401 +arc: C2 V02N0401 +arc: C3 F4 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 W1_H02E0001 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000000000110000 +word: SLICEA.K0.INIT 1111111100000010 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000101000000000 +word: SLICEC.K0.INIT 0000000001010000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0111111111111111 +word: SLICEB.K0.INIT 0000000001000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R71C48:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V06N0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 N1_V01N0001 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: D0 V00T0100 +arc: D1 E1_H02W0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 F0 +arc: V01S0000 F4 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1010101010001010 +word: SLICEA.K1.INIT 1010000011110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000101100000011 +word: SLICEC.K0.INIT 0010001000000010 +word: SLICEB.K0.INIT 0010001000000010 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R71C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 V02N0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H02E0501 +arc: A2 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: B2 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: C1 V02S0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F6 +arc: V00B0100 F7 +arc: V00T0100 F1 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000010100000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 0111111111111111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C50:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 E3_H06W0303 +arc: B6 W1_H02E0101 +arc: D6 H02E0001 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: V01S0100 F6 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R71C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V01S0100 N3_V06S0303 +arc: A6 N1_V02S0301 +arc: B1 V02S0301 +arc: B6 F1 +arc: C1 E1_H02W0401 +arc: C6 N1_V02S0001 +arc: D1 V01S0100 +arc: D6 S1_V02N0401 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C52:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A5 N1_V02S0301 +arc: B1 H02W0301 +arc: B3 H02E0301 +arc: B5 V02S0501 +arc: C1 N1_V02S0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: E1_H02E0501 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: V01S0000 F2 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R71C53:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 V02N0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A5 V02N0101 +arc: B3 Q3 +arc: B5 H02W0101 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C5 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: V01S0000 F4 +arc: V01S0100 Q5 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C54:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02E0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A5 V02S0101 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B3 H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 V02S0601 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V02N0301 Q3 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1000100011000000 +word: SLICEA.K1.INIT 1011101111110011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C55:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 V01N0101 +arc: A2 V00B0000 +arc: A5 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 H02W0101 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B5 N1_V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0401 +arc: C3 H02W0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0001 F2 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 F6 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R71C56:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 E1_H02W0501 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 V02S0301 +arc: A7 W1_H02E0501 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 W1_H02E0101 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0501 Q7 +arc: S3_V06S0303 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0000111000000010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C57:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: B0 E1_H02W0101 +arc: B1 N1_V02S0301 +arc: B3 H02E0101 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 N1_V02S0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02W0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: D7 H01W0000 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q3 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K1.INIT 1100001100000000 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R71C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A3 E1_H02W0501 +arc: A4 N1_V01N0101 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B6 S1_V02N0501 +arc: B7 V02S0501 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 N1_V02S0601 +arc: C5 V02S0001 +arc: C6 N1_V02S0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D3 V02S0001 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 F0 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F6 +arc: V00B0000 F4 +arc: V01S0000 Q5 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 0111000011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R71C59:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 V02S0501 +arc: A7 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 H02W0001 +arc: D3 E1_H02W0201 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 W1_H02E0601 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 Q3 +arc: V00T0100 Q1 +arc: V01S0000 F1 +arc: V01S0100 F6 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 1001000000001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R71C60:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A7 E1_H02W0701 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B5 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C3 H00L0100 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 E1_H02W0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0501 Q5 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 0000101000001100 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1110111000100010 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R71C61:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 V00B0000 +arc: A4 N1_V02S0101 +arc: B0 H02E0101 +arc: B2 H02E0301 +arc: B5 H02W0101 +arc: B6 V02S0701 +arc: B7 V02N0701 +arc: CLK0 G_HPBX0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 V00T0000 +arc: M0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F4 +arc: V01S0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C62:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H02W0501 +arc: A1 V02N0701 +arc: A2 H02E0501 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: B0 S1_V02N0101 +arc: B3 H02E0301 +arc: B4 V02N0501 +arc: B7 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: LSR0 V00B0000 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0401 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C63:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0201 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02E0501 +arc: A5 E1_H02W0501 +arc: A7 V02N0301 +arc: B2 V02S0101 +arc: B3 H02W0301 +arc: B4 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q3 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C64:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A2 S1_V02N0701 +arc: A3 V02S0501 +arc: A6 V02N0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B7 V02N0701 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F1 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H02W0601 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 F2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0701 Q5 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C65:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 V02N0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0303 E3_H06W0303 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: B1 H02E0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B7 H02W0101 +arc: C4 H02E0601 +arc: C5 E1_H02W0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 V01N0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: M6 V00T0100 +arc: MUXCLK2 CLK0 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0000 Q4 +word: SLICEC.K1.INIT 0000111100110011 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 0011111100110000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R71C66:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W3_H06E0203 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0501 +arc: A7 E1_H01W0000 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B3 V02S0301 +arc: B5 E1_H02W0101 +arc: B7 H02W0301 +arc: C0 W1_H02E0601 +arc: C1 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 W1_H02E0401 +arc: C5 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D3 N1_V02S0001 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 0000111100110011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R71C67:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A7 H00L0000 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C3 H02W0601 +arc: C5 H02E0601 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0000111100110011 +word: SLICED.K1.INIT 0000101001011111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1110010011100100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C68:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0501 +arc: A5 Q5 +arc: A6 E1_H02W0501 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q5 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 0000010111110101 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C69:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 + +.tile R71C70:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 E1_H02W0701 +arc: A4 H02W0701 +arc: B0 H02E0101 +arc: B3 V02S0301 +arc: B4 N1_V02S0501 +arc: C0 H02W0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F3 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000100000101 +word: SLICEB.K1.INIT 0000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R71C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0203 H01E0001 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 E1_H01E0001 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0101 +arc: B3 Q3 +arc: B6 H02E0101 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 F6 +arc: C5 V02N0201 +arc: C6 W1_H02E0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D5 W1_H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0001 Q2 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111001100000000 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000000001010 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R71C72:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V02N0701 +arc: B0 V02N0101 +arc: B1 Q1 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0003 Q0 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C73:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S1_V02N0601 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 W1_H02E0701 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0201 +arc: D4 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: V00T0000 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1010000011001100 +word: SLICEA.K1.INIT 1100111100000000 +word: SLICEC.K0.INIT 0000010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R71C74:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F5 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R71C75:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H01W0000 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: B0 H02W0301 +arc: B2 E1_H02W0301 +arc: B3 H02E0301 +arc: B5 H01E0101 +arc: B6 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C76:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: B2 E1_H02W0101 +arc: C2 S1_V02N0401 +arc: D2 V02S0201 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R71C77:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0301 S1_V02N0301 +arc: B0 S1_V02N0101 +arc: D0 V02N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R71C78:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02W0701 +arc: B1 E1_H02W0101 +arc: B7 H01E0101 +arc: C1 H02W0601 +arc: C7 V02N0001 +arc: D1 H02E0201 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F7 +arc: N3_V06N0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000001100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R71C79:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A2 H02W0501 +arc: B0 N1_V02S0301 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C80:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02E0701 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A5 S1_V02N0301 +arc: A7 V02S0101 +arc: B1 H02E0101 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C81:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 S1_V02N0701 +arc: B1 V02S0101 +arc: B6 V02S0501 +arc: C6 W1_H02E0601 +arc: D6 V01N0001 +arc: E3_H06E0303 F6 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: N1_V02N0201 F2 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R71C82:PLC2 +arc: N1_V01N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 + +.tile R71C83:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C84:PLC2 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R71C85:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: C2 V02N0601 +arc: D2 V02N0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 1111000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R71C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: A0 H02W0501 +arc: B0 H02E0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R71C87:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0501 S3_V06N0303 +arc: B5 H02W0301 +arc: C5 V02N0001 +arc: D5 H00R0100 +arc: F5 F5_SLICE +arc: N1_V02N0501 F5 +word: SLICEC.K1.INIT 1100001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R71C88:PLC2 +arc: E1_H02E0501 V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0301 V01N0101 + +.tile R71C89:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H01W0000 +arc: A2 V02S0701 +arc: A4 H02E0501 +arc: B0 S1_V02N0301 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R71C90:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: W3_H06W0003 V06S0003 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: F2 F2_SLICE +arc: H01W0000 F2 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R71C91:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R71C92:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C93:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R71C94:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: V01S0000 S3_V06N0103 + +.tile R71C95:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C96:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R71C97:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R71C98:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R71C99:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R72C100:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile R72C103:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C105:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R72C106:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R72C108:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C109:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R72C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R72C112:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C115:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R72C28:PLC2 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 + +.tile R72C30:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R72C31:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A4 V02N0301 +arc: A5 V02S0101 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B4 H00L0000 +arc: B5 H00R0000 +arc: B6 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 F2 +arc: D5 F0 +arc: D6 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEC.K0.INIT 0000000010111111 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000011110111 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C32:PLC2 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 V01N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0701 V06S0203 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D5 H01W0000 +arc: D6 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 1011111110110000 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K1.INIT 1100101011111010 +word: SLICEB.K0.INIT 1010110011111100 +word: SLICEB.K1.INIT 1101111111010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C33:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0100 H02W0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0103 E3_H06W0103 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0100 +arc: A2 V02S0701 +arc: A3 V00T0000 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B2 F3 +arc: B3 V02N0101 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C2 H00R0100 +arc: C3 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0201 +arc: D5 V02S0401 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F7 +arc: V00B0000 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0011000100110011 +word: SLICEA.K0.INIT 1000000000001000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 0010001100110011 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R72C34:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A3 E1_H02W0701 +arc: B3 V02S0301 +arc: C3 W1_H02E0601 +arc: D3 H02E0001 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C35:PLC2 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0701 H06W0203 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A0 E1_H01E0001 +arc: A1 V01N0101 +arc: A2 F5 +arc: A3 H00L0100 +arc: A4 F7 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 E1_H02W0101 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H01W0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1110111000101110 +word: SLICEA.K1.INIT 1011101111110000 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 0101010100010101 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICEB.K0.INIT 1010111111001100 +word: SLICEB.K1.INIT 1111011110100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C36:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N3_V06N0103 H06W0103 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 H01E0101 +arc: A2 V02S0701 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 W1_H02E0501 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: V00B0000 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICEB.K1.INIT 0101000101010101 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0011001100010011 +word: SLICEC.K0.INIT 1000000000001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R72C37:PLC2 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W3_H06W0003 E3_H06W0303 + +.tile R72C38:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: D0 V02S0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R72C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 E3_H06W0103 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 E1_H02W0401 +arc: V01S0000 N3_V06S0103 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A2 E1_H02W0701 +arc: A4 V00B0000 +arc: B0 V00B0000 +arc: B1 S1_V02N0101 +arc: B2 F1 +arc: B4 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H02W0401 +arc: C4 S1_V02N0201 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 V02S0001 +arc: D4 V02N0601 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F2 +arc: N3_V06N0103 F2 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F2 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000100 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICEA.K0.INIT 0000000011110111 +word: SLICEB.K0.INIT 1000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R72C40:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02N0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: A1 V02S0701 +arc: A3 V02S0701 +arc: A4 F5 +arc: A5 N1_V01S0100 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B1 S1_V02N0301 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 V00T0000 +arc: C1 N1_V01N0001 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: D1 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: N1_V02N0601 F4 +arc: N3_V06N0203 F4 +arc: V01S0000 F2 +arc: W1_H02W0201 F2 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111011111111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011001100010000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R72C41:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: A1 H02E0701 +arc: A3 H02W0701 +arc: A4 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 V02N0301 +arc: B1 H00R0100 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0701 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C4 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V00B0100 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: D4 F2 +arc: D6 H01W0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011000000010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0010000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R72C42:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 W1_H02E0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0701 +arc: A4 V02N0301 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 S1_V02N0101 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 W1_H02E0401 +arc: C1 V02S0401 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F0 +arc: S3_V06S0303 F6 +arc: V00B0000 F4 +arc: V01S0000 F3 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K0.INIT 0011111100000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1111000011010000 +word: SLICEB.K0.INIT 0011001100000011 +word: SLICED.K1.INIT 0000001100110011 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C43:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 F7 +arc: A1 F5 +arc: A2 F5 +arc: A6 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B6 H02E0301 +arc: B7 H02E0101 +arc: C0 N1_V02S0401 +arc: C1 H00L0100 +arc: C3 F4 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 E1_H02W0401 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N3_V06N0303 F6 +arc: V01S0100 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F0 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICED.K1.INIT 0000000000110011 +word: SLICEA.K0.INIT 0011000000100000 +word: SLICED.K0.INIT 0000010001000100 +word: SLICEC.K1.INIT 0000000000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R72C44:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H02W0701 +arc: A1 F5 +arc: A2 V02S0701 +arc: A4 S1_V02N0101 +arc: A7 F5 +arc: B0 F1 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C0 V02S0601 +arc: C1 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V02N0201 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 F7 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0111111101001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111111110110011 +word: SLICEB.K1.INIT 1111001100110011 +word: SLICEC.K0.INIT 0101000001010000 +word: SLICED.K1.INIT 0000010101010101 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0001000001010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C45:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02S0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A5 V02N0301 +arc: A7 H02W0501 +arc: B1 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B5 F1 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 N1_V02S0001 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F4 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: M2 V00T0100 +arc: M4 W1_H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 Q4 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICEB.K1.INIT 0001000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000010000000 +word: SLICEC.K1.INIT 0101010000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1110000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 F5 +arc: A1 H00L0100 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B1 V02S0101 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0101 +arc: C0 W1_H02E0401 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 H02W0401 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: MUXCLK0 CLK0 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C47:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 W1_H02E0501 +arc: A2 H02E0701 +arc: A4 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B3 H02W0101 +arc: B6 F3 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 H02W0601 +arc: C3 S1_V02N0601 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 V02N0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02E0201 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: S1_V02S0201 F2 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 0000101000000000 +word: SLICED.K0.INIT 1000100011001000 +word: SLICEB.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111000011100000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000111100001111 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICED.K1.INIT 1010001000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C48:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A3 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 V02N0101 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02E0401 +arc: C4 F6 +arc: C5 H02W0601 +arc: C7 V02S0201 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 H01W0000 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F6 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0001000011011100 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEC.K1.INIT 1000000010101010 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K0.INIT 1000110000001100 +word: SLICED.K1.INIT 0000010001000100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000000010111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C49:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V06S0303 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A3 W1_H02E0701 +arc: A6 H02E0501 +arc: B0 H02E0101 +arc: B1 F3 +arc: B3 W1_H02E0301 +arc: B5 V02S0501 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 V02S0201 +arc: D0 V02N0001 +arc: D2 S1_V02N0001 +arc: D3 W1_H02E0001 +arc: D5 V02S0601 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0100 F5 +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F7 +arc: N1_V02N0601 F6 +arc: V01S0000 F0 +word: SLICEC.K1.INIT 0011000000110011 +word: SLICEA.K0.INIT 0000110100000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEA.K1.INIT 1000000010000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R72C50:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: S3_V06S0003 H01E0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 V02N0601 +arc: D0 H02E0201 +arc: D1 S1_V02N0201 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: M0 W1_H02E0601 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R72C51:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V06S0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0501 +arc: A2 V02S0701 +arc: A5 H02W0701 +arc: B0 S1_V02N0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C5 N1_V02S0001 +arc: D0 F2 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 1100000010000000 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R72C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 E3_H06W0103 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V02S0701 +arc: A2 F5 +arc: A4 N1_V02S0301 +arc: A5 W1_H02E0701 +arc: A6 V00T0100 +arc: A7 E1_H02W0501 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0501 +arc: B7 N1_V02S0701 +arc: C1 H00L0100 +arc: C2 N1_V01S0100 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D4 H02W0001 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: N1_V02N0401 F6 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 F1 +arc: V00T0100 F1 +arc: V01S0000 F1 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0100000011000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A1 H02W0701 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 N1_V02S0101 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B6 V02S0501 +arc: B7 W1_H02E0101 +arc: C1 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C6 H02E0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0301 F1 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q0 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111111001100 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C54:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0303 V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 S1_V02N0501 +arc: A1 V02S0501 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 H02E0101 +arc: B6 H02E0101 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C6 E1_H02W0601 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D6 V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R72C55:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 V02N0101 +arc: H00R0000 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 N1_V02S0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A4 N1_V02S0301 +arc: A5 H02E0701 +arc: A6 H02W0501 +arc: A7 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 H00R0000 +arc: B3 N1_V02S0101 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 W1_H02E0101 +arc: C0 H00R0100 +arc: C2 F4 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0001 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 Q5 +arc: LSR1 H02W0301 +arc: M0 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A4 V02S0101 +arc: A5 W1_H02E0501 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B0 V00B0000 +arc: B3 S1_V02N0301 +arc: B4 N1_V02S0501 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0701 +arc: C0 F6 +arc: C3 N1_V02S0601 +arc: C4 W1_H02E0401 +arc: C5 V02S0001 +arc: C6 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V01S0100 +arc: D3 N1_V02S0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 E1_H01W0100 +arc: D7 V02S0601 +arc: E1_H01E0101 F5 +arc: E1_H02E0701 Q7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q7 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00B0000 F4 +arc: V01S0100 Q7 +arc: W3_H06W0003 F0 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C57:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A2 H02E0501 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 N1_V02S0101 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 N1_V02S0701 +arc: B7 V02S0501 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 E1_H02W0001 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 E1_H01W0100 +arc: D5 V02S0601 +arc: D6 H02W0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: LSR0 H02E0301 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F0 +arc: S1_V02S0501 F5 +arc: V01S0100 Q2 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +arc: W3_H06W0103 Q2 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111111111100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R72C58:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00R0000 +arc: A3 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A6 V02S0301 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C1 N1_V01S0100 +arc: C3 H00R0100 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D5 H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q7 +arc: V01S0000 F0 +arc: V01S0100 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +word: SLICED.K1.INIT 1000110010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C59:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02S0701 +arc: A3 N1_V02S0701 +arc: A7 E1_H01W0000 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B3 E1_H02W0101 +arc: B5 W1_H02E0101 +arc: C1 H02E0401 +arc: C5 V00T0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 F4 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C60:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 V02S0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02S0701 +arc: A1 H02W0501 +arc: A7 V02S0101 +arc: B1 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 V01S0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C5 H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M6 H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: S1_V02S0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C61:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0501 +arc: A2 H02E0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A7 N1_V02S0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 W1_H02E0401 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q7 +arc: W1_H02W0501 Q7 +word: SLICEC.K0.INIT 1101000010000000 +word: SLICEC.K1.INIT 1101111110001111 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C62:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 H02W0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0203 V06N0203 +arc: B1 H02W0301 +arc: B3 W1_H02E0101 +arc: B5 V02S0701 +arc: B7 N1_V02S0701 +arc: C1 H02W0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 N1_V02S0001 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D5 E1_H02W0001 +arc: D6 H01W0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q7 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 H01E0001 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0201 F0 +arc: S1_V02S0701 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C63:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A7 V02N0301 +arc: B1 E1_H02W0301 +arc: B3 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: C0 V02S0401 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0601 +arc: C5 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000111110101010 +word: SLICEA.K1.INIT 0001110100011101 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011001111110000 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R72C64:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 S1_V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A5 V02S0101 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C5 V02S0001 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D3 V02S0001 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1100110011001100 +word: SLICEC.K1.INIT 1100101011001010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R72C65:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 E1_H02W0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A1 V02N0701 +arc: A2 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B3 V02S0301 +arc: B5 N1_V01S0000 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 H02W0601 +arc: C3 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D3 V02S0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 W1_H02E0001 +arc: M6 W1_H02E0401 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 Q7 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 0000110011111100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R72C66:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H00R0000 +arc: A3 W1_H02E0501 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0601 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F6 +arc: V00T0000 Q0 +arc: V01S0000 F3 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000111110101010 +word: SLICEB.K1.INIT 0000110000001010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R72C67:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A3 V00T0000 +arc: A4 V02S0101 +arc: A6 E1_H02W0501 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B4 H02W0301 +arc: B6 H02E0301 +arc: B7 N1_V02S0501 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: C4 H02W0601 +arc: C6 H02E0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 N1_V02S0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0101000101010101 +word: SLICEA.K0.INIT 0101010111001100 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEA.K1.INIT 0000111000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000101011111010 +word: SLICED.K1.INIT 0000110000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R72C68:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 V00T0000 +arc: A6 F7 +arc: A7 N1_V01S0100 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D6 H02W0201 +arc: D7 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q2 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 1101100000000000 +word: SLICED.K0.INIT 0000111000000000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R72C69:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0501 + +.tile R72C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0401 H02E0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A3 H02W0501 +arc: B3 H02E0301 +arc: C3 H02E0401 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000000100010001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R72C71:PLC2 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V02S0501 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V00B0100 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0100 +arc: M5 H00R0100 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEB.K1.INIT 1100110000001000 +word: SLICEB.K0.INIT 1100110010001000 +word: SLICEC.K1.INIT 1100000011001000 +word: SLICEA.K1.INIT 1100110000001000 +word: SLICEA.K0.INIT 1100110010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R72C72:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: A5 H02W0501 +arc: B0 V02N0301 +arc: B4 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1110111011101110 +word: SLICEB.K1.INIT 1110111011101110 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C73:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0501 N1_V02S0501 +arc: B0 H02W0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C74:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V02S0601 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 V06S0003 + +.tile R72C75:PLC2 +arc: E1_H02E0501 V02N0501 +arc: N3_V06N0103 S3_V06N0103 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: D3 S1_V02N0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F4 +arc: N1_V02N0301 F3 +arc: N1_V02N0601 F6 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 0000111100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R72C76:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 H02W0301 +arc: B2 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 W1_H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C77:PLC2 +arc: N1_V02N0001 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0301 V06S0003 +arc: A0 V02N0701 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B2 H02W0101 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C78:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 V02N0701 +arc: F0 F0_SLICE +arc: N1_V01N0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R72C79:PLC2 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 S3_V06N0003 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N1_V01S0100 +arc: A2 V02S0501 +arc: A4 S1_V02N0301 +arc: B0 V02S0301 +arc: B3 S1_V02N0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C80:PLC2 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 S1_V02N0701 +arc: A2 V02S0701 +arc: A5 V02N0301 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B6 V00B0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C81:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: A0 V02N0701 +arc: B1 S1_V02N0101 +arc: F2 F2_SLICE +arc: N1_V01N0001 F2 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C82:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S3_V06N0003 +arc: B3 H02E0301 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R72C83:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 H01E0001 + +.tile R72C84:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: A3 V00B0000 +arc: A5 H02E0701 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B2 S1_V02N0301 +arc: B4 W1_H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C85:PLC2 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0003 +arc: A6 H02W0501 +arc: B0 E1_H02W0101 +arc: C6 E1_H02W0601 +arc: D6 F0 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V02N0001 F0 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010101010100101 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C86:PLC2 +arc: E1_H02E0701 W1_H02E0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C87:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R72C88:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: A6 E1_H01W0000 +arc: B0 V02N0301 +arc: B7 V02N0501 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1010101010100101 +word: SLICED.K1.INIT 1100001111000000 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R72C89:PLC2 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: C3 H02W0601 +arc: D3 V00B0100 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +word: SLICEB.K1.INIT 1111000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R72C90:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0601 N1_V01S0000 + +.tile R72C93:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R72C94:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 N1_V01S0000 + +.tile R72C96:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R72C99:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R73C30:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 + +.tile R73C31:PLC2 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H02E0301 + +.tile R73C32:PLC2 +arc: H00L0100 V02S0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: A0 F7 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 N1_V01S0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B3 V02S0101 +arc: B4 F3 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 V02N0401 +arc: C4 E1_H02W0601 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F1 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0000000001000000 +word: SLICEB.K0.INIT 0010001100110011 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 0101010100010101 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 0011001100010011 +word: SLICEA.K1.INIT 1000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C33:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 N3_V06S0103 + +.tile R73C34:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: W1_H02W0601 E3_H06W0303 + +.tile R73C35:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A6 V02S0101 +arc: B1 V00B0000 +arc: B3 V02S0101 +arc: B6 V01S0000 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C6 V00T0100 +arc: D1 N1_V01S0000 +arc: D3 V02N0001 +arc: D6 V02N0401 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0000000000100000 +word: SLICEA.K1.INIT 0010001100110011 +word: SLICEB.K1.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C36:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 + +.tile R73C37:PLC2 +arc: S1_V02S0501 N3_V06S0303 + +.tile R73C39:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0701 V01N0101 +arc: C5 V02S0001 +arc: D5 V02S0401 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R73C40:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 H02E0101 +arc: A0 H02E0501 +arc: A1 V01N0101 +arc: A4 H02W0501 +arc: A5 N1_V02S0101 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 N1_V02S0701 +arc: B5 E1_H02W0301 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 F0 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F2 +arc: N3_V06N0303 F5 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0011001000000000 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICEA.K0.INIT 0001000100010001 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0000001100000001 +word: SLICEA.K1.INIT 0000000000101010 +word: SLICED.K1.INIT 0000000001110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R73C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V01N0101 +arc: A0 H00L0100 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: B0 S1_V02N0101 +arc: B4 V02N0501 +arc: B7 F3 +arc: C0 W1_H02E0601 +arc: C2 H00L0000 +arc: C3 F6 +arc: C4 V01N0101 +arc: C5 N1_V02S0001 +arc: C6 N1_V02S0001 +arc: C7 H01E0001 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +arc: V01S0100 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 1011101000000000 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0011000000110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R73C42:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 H02E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A4 V00B0000 +arc: A7 H02E0701 +arc: B1 H01W0100 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0601 +arc: C2 F4 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C7 V02N0001 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 V01S0100 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 H02E0601 +arc: N1_V01N0101 F6 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R73C43:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: A0 H00L0100 +arc: A2 V02N0701 +arc: A3 V02S0701 +arc: A4 V02N0301 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B0 E1_H01W0100 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0101 +arc: B6 H01E0101 +arc: B7 S1_V02N0701 +arc: C0 V02N0601 +arc: C2 N1_V01N0001 +arc: C3 H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 N1_V02S0201 +arc: D0 H00R0000 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M0 V00T0100 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 0000000001010001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0111000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011101000000000 +word: SLICEC.K0.INIT 0000000011101100 +word: SLICED.K0.INIT 0000000000001100 +word: SLICEC.K1.INIT 0000000011111101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C44:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02N0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D1 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M0 H01E0001 +arc: M2 V00B0000 +arc: N1_V01N0001 F7 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0100 F2 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0101010101000000 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 0010000000110000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1100100010001000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C45:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 V01N0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0101 +arc: A5 N1_V01N0101 +arc: A7 N1_V01S0100 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 S1_V02N0001 +arc: C5 V00T0000 +arc: C7 H02E0601 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F0 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000011110111 +word: SLICEB.K1.INIT 1010000010100000 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000100000001 +word: SLICEA.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C46:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: A2 F5 +arc: A3 S1_V02N0501 +arc: A6 V00T0100 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B4 F1 +arc: B6 V02N0501 +arc: C0 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: D3 W1_H02E0001 +arc: D5 V02N0601 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F7 +arc: V00T0100 F1 +arc: W1_H02W0201 F0 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0000000010100000 +word: SLICEB.K1.INIT 0111111100000000 +word: SLICEA.K1.INIT 1000100000000000 +word: SLICED.K0.INIT 0111000011110000 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R73C47:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 H02W0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A6 V02S0301 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C3 F4 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 H02W0201 +arc: D4 V02S0401 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0501 F5 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: W1_H02W0301 F3 +word: SLICED.K0.INIT 1100010011001100 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEA.K0.INIT 1101010111000000 +word: SLICEA.K1.INIT 1010000011101100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111001100000011 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R73C48:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 V01N0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: A1 N1_V02S0501 +arc: A2 V01N0101 +arc: A3 H02W0701 +arc: A4 S1_V02N0101 +arc: A5 F7 +arc: A6 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 H00R0000 +arc: B3 H00L0000 +arc: B4 F1 +arc: B5 V02S0701 +arc: B6 F3 +arc: C0 H02W0401 +arc: C2 S1_V02N0401 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D2 V02N0201 +arc: D3 W1_H02E0001 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0201 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F4 +arc: N1_V01N0101 F0 +arc: S1_V02S0101 F1 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1000101000001010 +word: SLICEA.K1.INIT 1000100010001000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 1100010000000000 +word: SLICEB.K0.INIT 0111111100000000 +word: SLICEB.K1.INIT 0101110011111100 +word: SLICED.K0.INIT 0101000100000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 F7 +arc: A5 V02S0301 +arc: B2 S1_V02N0101 +arc: B5 H01E0101 +arc: B7 V02N0501 +arc: C0 F4 +arc: C2 S1_V02N0601 +arc: C3 W1_H02E0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 V02S0001 +arc: D0 H01E0101 +arc: D2 H00R0000 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F0 +arc: N1_V02N0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000110011 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R73C50:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0201 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 S3_V06N0203 + +.tile R73C51:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 H02W0301 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 N3_V06S0303 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A3 V02S0701 +arc: A4 W1_H02E0701 +arc: A6 N1_V02S0301 +arc: B0 F3 +arc: B1 H02W0301 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 F6 +arc: C4 H02E0601 +arc: C6 N1_V02S0201 +arc: C7 W1_H02E0401 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D4 W1_H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N3_V06N0203 F4 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEA.K1.INIT 0000001100000010 +word: SLICEA.K0.INIT 0000000011111110 +word: SLICEB.K1.INIT 1000111100000000 +word: SLICED.K1.INIT 0000000000001100 +word: SLICED.K0.INIT 0000000000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R73C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02S0601 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 F5 +arc: A5 E1_H02W0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 E1_H02W0301 +arc: B5 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 S1_V02N0401 +arc: C5 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: D0 S1_V02N0201 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V00B0100 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V02N0601 +arc: A0 N1_V02S0701 +arc: A1 E1_H02W0501 +arc: A2 H02E0701 +arc: A3 V00B0000 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 F5 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B2 V02S0101 +arc: B3 W1_H02E0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 F3 +arc: B7 V02S0701 +arc: C0 S1_V02N0401 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 V01N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F2 +arc: V01S0000 F6 +arc: V01S0100 F7 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F0 +word: SLICEB.K0.INIT 0000000010101000 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R73C54:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 V02S0101 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: A0 H00R0000 +arc: A2 F5 +arc: A3 V02S0701 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 E1_H01W0100 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B3 W1_H02E0101 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 E1_H02W0401 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 W1_H02E0601 +arc: C7 H02W0601 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H00L0100 +arc: D6 V02N0401 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0101010011111110 +word: SLICEA.K1.INIT 1111111111111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R73C55:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0701 +arc: A1 V02N0701 +arc: A2 H02E0701 +arc: A3 E1_H02W0701 +arc: A4 F5 +arc: A5 W1_H02E0701 +arc: A6 H02W0501 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 N1_V02S0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0101 +arc: B7 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02S0601 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: C6 H02E0401 +arc: C7 F6 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000100010001 +word: SLICED.K0.INIT 1110111100100011 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K1.INIT 0000000001000111 +word: SLICEA.K1.INIT 1100010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C56:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 S1_V02N0501 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 V02S0301 +arc: B3 S1_V02N0301 +arc: B5 H02W0101 +arc: B6 V02N0501 +arc: B7 V02S0501 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 H02W0601 +arc: C4 F6 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: D0 V02S0201 +arc: D1 V00T0100 +arc: D2 N1_V02S0201 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 F2 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: N1_V02N0001 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C57:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0701 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 V02S0701 +arc: B5 S1_V02N0701 +arc: B6 V00B0100 +arc: B7 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 V02S0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: N1_V01N0001 F2 +arc: V00B0000 F6 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0701 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R73C58:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B6 W1_H02E0301 +arc: B7 V01S0000 +arc: C1 H02E0401 +arc: C2 F6 +arc: C3 V02N0401 +arc: C5 V02N0001 +arc: C6 V02S0001 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 V02S0601 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q1 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R73C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A3 N1_V02S0501 +arc: A4 E1_H01W0000 +arc: A6 F5 +arc: A7 H02E0701 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V01S0000 +arc: B5 H01E0101 +arc: B6 F3 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 F2 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00T0100 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1100100000001000 +word: SLICEA.K1.INIT 1111101100111011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 1000100001000100 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R73C60:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 N1_V02S0701 +arc: A2 H02E0501 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02W0501 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C2 N1_V02S0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 F2 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICED.K0.INIT 1000101011001111 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010111100100011 +word: SLICEB.K0.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C61:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: A7 H02E0501 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B5 V02S0701 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C1 W1_H02E0401 +arc: C2 V02N0601 +arc: C3 F6 +arc: C4 N1_V02S0001 +arc: C5 V02S0001 +arc: C6 S1_V02N0001 +arc: C7 H02E0601 +arc: D1 E1_H02W0201 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 N1_V02S0601 +arc: D6 V00B0000 +arc: D7 N1_V02S0401 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0100 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICEC.K0.INIT 0011000000100010 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1000110010101111 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R73C62:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 S1_V02N0701 +arc: A1 V02S0701 +arc: A2 H02E0701 +arc: A3 H02W0501 +arc: A7 V02N0101 +arc: B1 S1_V02N0301 +arc: B2 N1_V02S0101 +arc: B3 H02E0101 +arc: B5 H02W0301 +arc: C0 V02S0601 +arc: C1 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0201 +arc: D2 N1_V02S0001 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 N1_V01N0001 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 Q7 +word: SLICEB.K1.INIT 0000111000001111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R73C63:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02S0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H02W0001 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 S1_V02N0701 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 E1_H02W0501 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 N1_V02S0301 +arc: B1 Q1 +arc: B3 S1_V02N0301 +arc: B4 V02N0501 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 N1_V02S0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 N1_V02S0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q6 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICED.K1.INIT 1100010011110101 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R73C64:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 H02W0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B5 V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H02E0601 +arc: C3 N1_V02S0401 +arc: C5 V00B0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 V02S0001 +arc: D4 V01N0001 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F1 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 0101111100001010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0011111100110000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C65:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 H02W0501 +arc: A5 V02S0301 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 N1_V02S0101 +arc: B3 H02W0101 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C3 H00R0100 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D5 H00R0100 +arc: D7 S1_V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F2 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0011101000111010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C66:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0301 +arc: A1 H02E0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A7 E1_H01W0000 +arc: B3 Q3 +arc: B5 E1_H02W0101 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: C4 S1_V02N0201 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0501 Q5 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 F6 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 0011001000110011 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0000101011111010 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R73C67:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 V01N0101 +arc: A3 H02E0501 +arc: A4 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 H01E0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F4 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +word: SLICEB.K1.INIT 0000000011110111 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 1010000011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R73C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B3 N1_V02S0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 W1_H02E0601 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 F4 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111111001111 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R73C69:PLC2 +arc: E1_H02E0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0601 W3_H06E0303 +arc: C1 E1_H02W0401 +arc: D1 V00B0100 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: S3_V06S0103 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R73C70:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: V01S0100 N3_V06S0303 + +.tile R73C71:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0100 H02W0101 +arc: H00R0100 H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 E1_H02W0101 +arc: A1 H02W0701 +arc: A3 H02W0701 +arc: A5 V02N0101 +arc: B0 H02E0101 +arc: B1 V02N0101 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H00L0100 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000011000000 +word: SLICEA.K1.INIT 1010101000100000 +word: SLICEB.K0.INIT 1111000011000000 +word: SLICEB.K1.INIT 1010101000100000 +word: SLICEC.K0.INIT 1111000011000000 +word: SLICEC.K1.INIT 1111010000000000 +word: SLICED.K0.INIT 1111000011000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R73C72:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0701 H01E0101 + +.tile R73C73:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E3_H06W0103 +arc: A0 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B4 E1_H02W0101 +arc: C0 H02W0601 +arc: C2 H02W0601 +arc: C4 V02N0201 +arc: C6 V00T0100 +arc: D0 V02N0201 +arc: D1 E1_H02W0201 +arc: D2 V02N0201 +arc: D3 E1_H02W0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S3_V06S0003 F3 +word: SLICED.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000010100000000 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 0001000100000001 +word: SLICEB.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0001000000010001 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0001000000010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R73C74:PLC2 +arc: E1_H02E0301 V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0601 E1_H01W0000 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 V02S0701 +arc: A4 W1_H02E0501 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: B0 W1_H02E0301 +arc: B3 H02E0301 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C75:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R73C76:PLC2 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 V02N0701 +arc: A5 V00B0000 +arc: A7 F5 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B5 S1_V02N0701 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C5 E1_H02W0601 +arc: C7 V00T0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D5 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: V00T0000 F0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEA.K0.INIT 0100000000000100 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R73C77:PLC2 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: A2 S1_V02N0501 +arc: B0 V02S0301 +arc: B3 E1_H02W0101 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H02W0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C78:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 V00T0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0501 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C79:PLC2 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0203 V06N0203 +arc: A0 H02W0701 +arc: A5 H02W0701 +arc: A7 S1_V02N0301 +arc: B1 E1_H02W0101 +arc: B5 V02N0501 +arc: B7 S1_V02N0701 +arc: C5 V02N0001 +arc: C7 V02N0201 +arc: D5 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M4 E1_H01E0101 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R73C80:PLC2 +arc: E1_H02E0701 V06N0203 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 V06N0203 + +.tile R73C81:PLC2 +arc: E1_H02E0101 V01N0101 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0101 V02N0101 + +.tile R73C82:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 + +.tile R73C83:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 N3_V06S0003 +arc: A3 V01N0101 +arc: B3 V01N0001 +arc: D3 V00B0100 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1010101000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R73C84:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0001 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: B3 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C85:PLC2 +arc: V00B0000 W1_H02E0401 +arc: A0 H02E0701 +arc: A2 V00B0000 +arc: A6 W1_H02E0501 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 H02E0101 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C86:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0101 N3_V06S0103 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: A1 W1_H02E0501 +arc: B0 V00B0000 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: D6 F2 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F7 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: V00T0000 F2 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1111000000001111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R73C87:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 + +.tile R73C88:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: A0 H00L0000 +arc: A4 V00T0000 +arc: A6 H02E0501 +arc: B2 W1_H02E0101 +arc: B3 H02E0301 +arc: B5 V02N0501 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R73C89:PLC2 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 F7 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B4 V02N0701 +arc: C4 N1_V02S0201 +arc: C7 N1_V02S0001 +arc: D4 V02N0401 +arc: D7 V02N0401 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1100001111000000 +word: SLICED.K1.INIT 1010101010100101 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R73C90:PLC2 +arc: N1_V02N0101 V01N0101 +arc: V00B0100 S1_V02N0301 +arc: B0 V01N0001 +arc: B3 V02N0301 +arc: C3 V02N0401 +arc: D0 V00B0100 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F0 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F3 +word: SLICEB.K1.INIT 1100001111000000 +word: SLICEA.K0.INIT 1100110000110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R73C91:PLC2 +arc: N1_V02N0301 S1_V02N0301 + +.tile R73C92:PLC2 +arc: N3_V06N0003 S1_V02N0301 + +.tile R74C100:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R74C102:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R74C103:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R74C105:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C106:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R74C108:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C109:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R74C111:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R74C112:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R74C114:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 + +.tile R74C115:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R74C17:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R74C31:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R74C32:PLC2 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 + +.tile R74C33:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0303 + +.tile R74C35:PLC2 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 + +.tile R74C36:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0401 H02W0401 + +.tile R74C37:PLC2 +arc: H01W0100 E3_H06W0303 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 H01W0100 +arc: C0 H02E0601 +arc: D0 V02N0201 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0000110010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R74C38:PLC2 +arc: E1_H02E0601 V06N0303 + +.tile R74C39:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: A1 H00R0000 +arc: A4 V02N0301 +arc: A7 V02N0101 +arc: B1 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C1 E1_H02W0401 +arc: C2 F6 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D4 H02W0001 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F1 +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000000100000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R74C40:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: W1_H02W0001 N3_V06S0003 +arc: A0 E1_H01E0001 +arc: B0 H02W0101 +arc: B3 H02W0301 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H02W0601 +arc: C7 F4 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +arc: N3_V06N0103 F1 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000011110001 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: A4 V00T0100 +arc: A6 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: C1 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D1 V02S0001 +arc: D3 H02W0001 +arc: D4 W1_H02E0201 +arc: D5 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E3_H06E0303 F6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V01N0001 F3 +arc: N1_V02N0101 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +arc: V00T0100 F1 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 1010000010100000 +word: SLICEC.K0.INIT 1101000011110000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R74C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02S0301 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A6 V02S0101 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 W1_H02E0101 +arc: B3 S1_V02N0301 +arc: B5 H02W0101 +arc: C0 H00L0100 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0401 +arc: C6 W1_H02E0601 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F3 +arc: N3_V06N0303 F6 +arc: V01S0000 F0 +arc: W1_H02W0401 F4 +word: SLICEA.K0.INIT 0001000100110001 +word: SLICEA.K1.INIT 0101010111011101 +word: SLICED.K1.INIT 1010101000000000 +word: SLICEB.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICEB.K0.INIT 0000001100110011 +word: SLICED.K0.INIT 1111101001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R74C43:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0701 +arc: A2 H02E0701 +arc: A4 W1_H02E0501 +arc: A5 H02W0701 +arc: A6 V02S0101 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 F4 +arc: C5 F4 +arc: C6 H02E0601 +arc: D0 V02N0001 +arc: D1 E1_H02W0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 V01N0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: N3_V06N0203 F7 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0301 F1 +word: SLICED.K1.INIT 1100110000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000010001010101 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0000000000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R74C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 H02E0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 H01E0101 +arc: A0 V02N0501 +arc: A2 E1_H02W0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 W1_H02E0101 +arc: B2 H01W0100 +arc: B3 V02S0301 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 W1_H02E0401 +arc: C3 H00R0100 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 W1_H02E0601 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 F2 +arc: D4 H00L0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F0 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: S1_V02S0101 F3 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +word: SLICEB.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 0100110000000000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 1010000000000000 +word: SLICED.K1.INIT 0010101000000000 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R74C45:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 H02E0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V06S0203 +arc: A1 H00R0000 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 V00T0100 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 V02S0301 +arc: B1 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B6 H02E0101 +arc: B7 V02S0501 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C7 V02S0201 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 N1_V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: M0 V00T0100 +arc: V00B0000 F4 +arc: V01S0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEB.K0.INIT 0001000100010101 +word: SLICED.K0.INIT 0100010011001100 +word: SLICED.K1.INIT 0000000000000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C46:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02N0501 +arc: A1 S1_V02N0501 +arc: A2 F5 +arc: A3 V00T0000 +arc: A7 H02W0501 +arc: B0 V01N0001 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 E1_H02W0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: B7 F1 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0401 +arc: C5 F4 +arc: C7 F6 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D6 V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEB.K0.INIT 0000000000010001 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K1.INIT 1000110000001100 +word: SLICEA.K1.INIT 0000010100000001 +word: SLICEA.K0.INIT 1000101010101010 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R74C47:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V06S0303 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A4 H02E0701 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B0 H02W0101 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B3 N1_V02S0301 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 V00B0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: D0 V00B0100 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: M0 W1_H02E0601 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 F3 +arc: S1_V02S0701 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F7 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 0000000001000000 +word: SLICEC.K0.INIT 0000000001010001 +word: SLICEC.K1.INIT 0000000000010000 +word: SLICED.K1.INIT 1111101000000000 +word: SLICED.K0.INIT 0101000101000000 +word: SLICEA.K0.INIT 0001000101010101 +word: SLICEA.K1.INIT 0000000000010101 +word: SLICEB.K1.INIT 0000000000000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C48:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H02E0501 +arc: A1 S1_V02N0501 +arc: A2 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 F1 +arc: B4 H02E0301 +arc: B6 V02N0501 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02E0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: N3_V06N0203 F7 +arc: V01S0000 Q0 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 0001010100000100 +word: SLICEA.K1.INIT 0101111100010011 +word: SLICEA.K0.INIT 0011011100000101 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1011101100011011 +word: SLICEC.K1.INIT 1010101000001010 +word: SLICEB.K0.INIT 0000010001000100 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C49:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 H06E0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02W0701 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: C1 H00L0100 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 N1_V02S0201 +arc: D2 H02E0201 +arc: E1_H01E0001 Q7 +arc: E1_H02E0201 F2 +arc: E1_H02E0501 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00L0000 F0 +arc: LSR0 H02W0301 +arc: M0 H02W0601 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 0001000100010011 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0000111100001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C50:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H00L0000 +arc: B0 H01W0100 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0011011100000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C51:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H06W0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 F5 +arc: A2 V00B0000 +arc: A3 W1_H02E0501 +arc: A6 H02E0701 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 W1_H02E0301 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: C1 N1_V02S0401 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: D1 V00T0100 +arc: D2 H02E0001 +arc: D3 S1_V02N0201 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E3_H06E0103 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: N1_V02N0601 F6 +word: SLICEC.K1.INIT 0011000011110000 +word: SLICEB.K1.INIT 1000000011001100 +word: SLICED.K0.INIT 1000110000001100 +word: SLICEB.K0.INIT 0000111100001110 +word: SLICEA.K1.INIT 0000101000000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R74C52:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: A0 F7 +arc: A2 F5 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 W1_H02E0101 +arc: B3 N1_V02S0301 +arc: B4 W1_H02E0101 +arc: B5 H02E0101 +arc: B6 V00B0100 +arc: B7 V00T0000 +arc: C0 V02S0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0001 +arc: C7 E1_H02W0601 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 N1_V01S0000 +arc: D4 E1_H01W0100 +arc: D5 V02S0401 +arc: D6 W1_H02E0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: V00B0000 F4 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000000100000011 +word: SLICEC.K1.INIT 0000000000000010 +word: SLICEB.K0.INIT 1010111110100011 +word: SLICEC.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 1100100011000000 +word: SLICEA.K0.INIT 0000001000001110 +word: SLICEA.K1.INIT 0000000000111111 +word: SLICEB.K1.INIT 0000001111001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C53:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 V02N0501 +arc: A1 F5 +arc: A2 F7 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V01S0100 +arc: A7 W1_H02E0501 +arc: B0 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 S1_V02N0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C2 E1_H01W0000 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0601 +arc: C7 V02S0001 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F0 +arc: H01W0100 F2 +arc: N1_V02N0601 F6 +arc: V01S0100 F1 +arc: W1_H02W0001 F0 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEA.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C54:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 W1_H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 V02N0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F0 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: M0 V00B0100 +arc: V00B0000 F6 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R74C55:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N1_V02S0101 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A1 H02W0701 +arc: A2 N1_V02S0701 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 W1_H02E0501 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 E1_H02W0301 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 W1_H02E0101 +arc: B5 N1_V02S0501 +arc: B6 N1_V02S0701 +arc: B7 F1 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 N1_V02S0201 +arc: C6 H02E0601 +arc: C7 S1_V02N0201 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 F0 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H00L0100 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R74C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0100 H02W0501 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 F5 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V02S0101 +arc: A6 S1_V02N0101 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 N1_V02S0501 +arc: B7 F1 +arc: C0 F4 +arc: C1 H02W0601 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D3 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: V00B0000 F6 +arc: V01S0000 F7 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R74C57:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 V02N0301 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 V02N0701 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B2 H02E0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V02S0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: N1_V01N0101 F2 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K0.INIT 1100100000000000 +word: SLICEA.K0.INIT 0111011101110010 +word: SLICEA.K1.INIT 1111111111111010 +word: SLICEB.K0.INIT 0000000000010101 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000010000000 +word: SLICEC.K0.INIT 0101111101001110 +word: SLICEC.K1.INIT 1111111111101110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R74C58:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 V06N0003 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 W3_H06E0203 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 V02N0501 +arc: A1 F7 +arc: A2 W1_H02E0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H01W0100 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 N1_V02S0701 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 V02N0201 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 N1_V02S0001 +arc: D3 F2 +arc: D4 V02S0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F3 +word: SLICEC.K1.INIT 0000100010001000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C59:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 V06N0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A1 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 F7 +arc: A6 N1_V02S0101 +arc: A7 V00T0100 +arc: B1 N1_V02S0101 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 V02S0701 +arc: B5 H00L0000 +arc: B6 S1_V02N0701 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02E0001 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEC.K1.INIT 0010000010100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C60:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 E1_H02W0701 +arc: A6 F5 +arc: A7 H02W0701 +arc: B2 V02N0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B5 W1_H02E0301 +arc: B6 V01S0000 +arc: B7 N1_V02S0501 +arc: C1 H02W0601 +arc: C2 N1_V02S0401 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F3 +arc: LSR1 H02E0301 +arc: M0 V00T0100 +arc: M5 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F7 +arc: V01S0100 Q5 +arc: W3_H06W0303 Q5 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEB.K0.INIT 1000101011001111 +word: SLICED.K0.INIT 1000000000001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C61:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02W0001 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V01N0101 +arc: A1 H00R0000 +arc: A2 H02W0501 +arc: A3 V02S0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 H00L0000 +arc: A7 F5 +arc: B1 E1_H02W0301 +arc: B2 N1_V02S0301 +arc: B3 H00R0100 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 F4 +arc: D1 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F6 +arc: W1_H02W0001 F0 +arc: W3_H06W0203 F7 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1011000010111011 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K0.INIT 1011000010111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R74C62:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0100 V02N0101 +arc: H00R0100 N1_V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0501 +arc: A2 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 H02W0701 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0301 +arc: B7 H02W0301 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C5 S1_V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0001 +arc: D2 V02N0001 +arc: D3 H01E0101 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q7 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 N1_V01N0001 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H02W0001 +arc: M6 V00T0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0701 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0100010011101110 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C63:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H00L0000 +arc: A3 E1_H02W0701 +arc: A4 H02E0701 +arc: A7 N1_V01S0100 +arc: B0 H01W0100 +arc: B1 V02S0101 +arc: B3 V02S0301 +arc: B5 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 H01E0001 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0201 +arc: D2 E1_H02W0001 +arc: D3 H00R0000 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +word: SLICEA.K1.INIT 0011001100100011 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0101010111001100 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R74C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H01W0000 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 S1_V02N0701 +arc: A2 F5 +arc: A3 V01N0101 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B0 E1_H02W0301 +arc: B1 H00R0100 +arc: B2 F1 +arc: B3 H02E0101 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0401 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 H02E0001 +arc: D5 S1_V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: H01W0100 Q2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0601 Q4 +arc: S1_V02S0701 Q7 +arc: V00B0000 F6 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 Q4 +word: SLICEB.K1.INIT 0011001100100011 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R74C65:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 S1_V02N0501 +arc: A5 H02W0501 +arc: A6 V02S0101 +arc: A7 H02W0501 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B3 V02N0101 +arc: B6 V01S0000 +arc: B7 V02N0701 +arc: C0 H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V02N0201 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 H02E0001 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q7 +arc: S1_V02S0601 F4 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEB.K1.INIT 1110001000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C66:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 N1_V01S0000 +arc: A6 V00T0100 +arc: A7 V02S0101 +arc: B2 H02W0101 +arc: B3 Q3 +arc: B4 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 H01E0001 +arc: C6 V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D6 V02N0601 +arc: D7 V02S0601 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 F4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 1100000010001000 +word: SLICED.K1.INIT 0101010101000101 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C67:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0101 V01N0101 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 V02N0701 +arc: A3 E1_H02W0501 +arc: B3 H00R0100 +arc: C0 E1_H01W0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +word: SLICEB.K1.INIT 0101000101010101 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C68:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C69:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 E1_H02W0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H00L0100 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R74C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 W1_H02E0401 +arc: N3_V06N0203 H06E0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 H00R0000 +arc: A3 V00T0000 +arc: A5 V00T0000 +arc: A7 H02E0701 +arc: B1 H02W0101 +arc: B3 H02W0101 +arc: B5 H02W0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 W1_H02E0401 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 E1_H02W0401 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111011100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111011100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111011100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1010111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R74C71:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 H02E0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 V06S0303 +arc: A1 V02S0501 +arc: A3 V02S0501 +arc: A5 V02N0301 +arc: B1 V02N0301 +arc: B3 V02N0301 +arc: B5 V02S0501 +arc: B7 V02S0501 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1101111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1101111100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1011000011110000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R74C72:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 H02E0101 +arc: W1_H02W0401 W3_H06E0203 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 V00B0100 +arc: B7 V00B0100 +arc: C1 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 1101111100000000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEB.K1.INIT 1100110001001100 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100010011001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100010011000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R74C73:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0303 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: A4 V02S0101 +arc: B3 V02S0101 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: D3 E1_H02W0201 +arc: D4 H02E0201 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F4 +word: SLICEC.K0.INIT 0000101000001111 +word: SLICEB.K1.INIT 0000110000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R74C74:PLC2 +arc: S1_V02S0601 H02W0601 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile R74C75:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R74C76:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R74C77:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R74C78:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V01N0101 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B2 S1_V02N0101 +arc: B3 H02W0101 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 S3_V06N0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: B2 E1_H02W0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C80:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V01N0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0303 V01N0101 +arc: A1 S1_V02N0701 +arc: B0 V02N0301 +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C81:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0101 V02N0101 +arc: A4 S1_V02N0301 +arc: B0 V02S0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F5 +arc: S1_V02S0701 F5 +arc: V01S0100 F6 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C82:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: A0 S1_V02N0701 +arc: A2 V02N0501 +arc: A5 W1_H02E0501 +arc: B1 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B4 S1_V02N0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C83:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: A0 S1_V02N0701 +arc: B1 W1_H02E0101 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: V01S0100 F1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R74C84:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 H00L0000 +arc: A5 V00T0000 +arc: A7 H02E0501 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0101 +arc: B6 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C85:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A7 H02W0701 +arc: B0 V02N0301 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B6 E1_H02W0101 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C86:PLC2 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 V02S0001 +arc: A0 F5 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B7 N1_V01S0000 +arc: C5 H02E0601 +arc: C7 V02N0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: V01S0000 F0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1100110011000011 +word: SLICEC.K1.INIT 1100110000110000 +word: SLICEC.K0.INIT 1100110000110011 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R74C87:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 H01E0101 + +.tile R74C88:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 W3_H06E0303 + +.tile R74C89:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 W3_H06E0003 +arc: V00T0000 W1_H02E0001 +arc: A3 V00T0000 +arc: A4 H02E0501 +arc: A5 W1_H02E0501 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B2 W1_H02E0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R74C90:PLC2 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: V00T0000 V02N0601 +arc: A1 V01N0101 +arc: A3 V00T0000 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B7 F3 +arc: C7 V02N0001 +arc: D7 S1_V02N0401 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F7 +arc: N1_V02N0301 F3 +word: SLICED.K1.INIT 1111110000000011 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R74C91:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C93:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C96:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 + +.tile R74C97:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R74C99:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R75C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C101:PLC2 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0103 + +.tile R75C103:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C104:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R75C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R75C107:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R75C110:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R75C2:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R75C32:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R75C35:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R75C37:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 + +.tile R75C38:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V06S0003 + +.tile R75C39:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02W0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 H00R0000 +arc: A1 H00R0000 +arc: A2 N1_V02S0701 +arc: A4 E1_H02W0701 +arc: A6 N1_V01S0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B4 H02E0101 +arc: B6 H02W0301 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 N1_V01S0000 +arc: D4 F2 +arc: D6 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1010101000100010 +word: SLICEA.K0.INIT 0000001100100011 +word: SLICEA.K1.INIT 0000000000100000 +word: SLICEB.K0.INIT 1111010100000000 +word: SLICEC.K0.INIT 0000111100000100 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R75C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 V02S0601 +arc: A1 H00L0100 +arc: A5 H02E0501 +arc: B1 V00T0000 +arc: B5 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C5 H01E0001 +arc: C7 V02N0001 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V01N0001 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0011101100000000 +word: SLICEC.K1.INIT 0000010000001111 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R75C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 N3_V06S0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V02N0501 +arc: A3 F7 +arc: A4 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 H00L0000 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 H00R0100 +arc: B4 H01E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C6 V02N0001 +arc: C7 F4 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V02S0001 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D6 E1_H02W0201 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +word: SLICED.K0.INIT 0001010100010001 +word: SLICEC.K0.INIT 0100110001000100 +word: SLICED.K1.INIT 0000000100000101 +word: SLICEB.K1.INIT 0100000001010101 +word: SLICEA.K0.INIT 0100010001011111 +word: SLICEA.K1.INIT 0101011101011111 +word: SLICEB.K0.INIT 0100111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R75C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 W1_H02E0301 +arc: C1 V02N0401 +arc: C4 V00B0100 +arc: C7 V02S0201 +arc: D1 V02S0001 +arc: D2 W1_H02E0001 +arc: D3 E1_H02W0201 +arc: D4 V01N0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F2 +arc: S1_V02S0401 F4 +arc: V00B0100 F7 +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0010001010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R75C43:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 F5 +arc: A7 H02E0701 +arc: B3 H02E0301 +arc: B6 H02E0301 +arc: B7 H01E0101 +arc: C0 H02E0601 +arc: C3 S1_V02N0401 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: C7 F6 +arc: D0 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F0 +arc: S1_V02S0201 F2 +arc: S3_V06S0103 F2 +arc: V01S0000 F7 +arc: V01S0100 F5 +arc: W1_H02W0001 F2 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1111010100110001 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R75C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A1 V01N0101 +arc: A2 H00L0100 +arc: A4 H02E0701 +arc: A5 V02N0301 +arc: A6 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H01E0101 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V01N0101 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0010001000000010 +word: SLICEA.K1.INIT 0100010000000000 +word: SLICEC.K0.INIT 1100110011000100 +word: SLICEB.K0.INIT 0000101110111011 +word: SLICEB.K1.INIT 0000001100110011 +word: SLICED.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0000110000001101 +word: SLICEC.K1.INIT 0011000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: A0 V02N0501 +arc: A2 N1_V02S0501 +arc: A3 F7 +arc: B0 E1_H02W0301 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 F1 +arc: B7 F1 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 V02N0601 +arc: C3 F4 +arc: C4 N1_V02S0001 +arc: C6 V02N0001 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 N1_V02S0201 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: S3_V06S0003 F3 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000010011 +word: SLICEA.K0.INIT 0101010100010000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000001110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R75C46:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A3 N1_V02S0501 +arc: A6 H00R0000 +arc: A7 N1_V02S0301 +arc: B0 V02N0301 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 V00T0000 +arc: D0 W1_H02E0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 F0 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: S3_V06S0303 F6 +arc: V01S0000 F7 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000000011001100 +word: SLICED.K1.INIT 0011000100000001 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111111001010100 +word: SLICEA.K1.INIT 1111000011111111 +word: SLICED.K0.INIT 0000101100001000 +word: SLICEB.K1.INIT 0101010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R75C47:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 F7 +arc: A7 V02N0101 +arc: B0 V00B0000 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0701 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: C7 V00T0100 +arc: D0 H02W0201 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02S0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 E1_H01E0101 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000010000000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEB.K0.INIT 0001000100000000 +word: SLICEB.K1.INIT 0001000100110000 +word: SLICEC.K0.INIT 0100010100000000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K1.INIT 0000011100000011 +word: SLICED.K0.INIT 0000101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R75C48:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06S0303 +arc: A1 H00R0000 +arc: A2 V02S0501 +arc: A4 H02E0701 +arc: A5 N1_V01S0100 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H00R0000 +arc: C0 F6 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C4 V02N0001 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: D1 V02N0001 +arc: D2 W1_H02E0001 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: D6 E1_H01W0100 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: N1_V01N0101 F7 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V01S0100 F3 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1010101011110011 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000000011001100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 0010000000000000 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEC.K1.INIT 1010101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R75C49:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02N0701 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 H02W0501 +arc: B1 V00T0000 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: B5 S1_V02N0701 +arc: C1 V02S0401 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 H02E0401 +arc: C5 E1_H01E0101 +arc: D1 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +word: SLICEC.K0.INIT 1110000011000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1100100010001000 +word: SLICEC.K1.INIT 1010100010100000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C50:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H01E0001 +arc: A3 V00B0000 +arc: B3 N1_V02S0101 +arc: C0 V02S0601 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 F3 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C51:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: V01S0100 N3_V06S0303 +arc: B0 H02E0101 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C52:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: A1 V01N0101 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A7 H02E0501 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B4 H02W0101 +arc: B5 V02N0501 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D7 F2 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0701 F5 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 1000000011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R75C53:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W1_H02E0301 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 N3_V06S0303 +arc: A1 E1_H02W0501 +arc: A2 H02W0701 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 W1_H02E0501 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B3 W1_H02E0101 +arc: B4 H02E0301 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C2 F4 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 W1_H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: D5 W1_H02E0001 +arc: D6 V01N0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0011110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0011111100000000 +word: SLICEC.K0.INIT 0011111100001100 +word: SLICEB.K0.INIT 0001000000110010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R75C54:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A6 S1_V02N0301 +arc: A7 E1_H01W0000 +arc: B1 F3 +arc: B2 E1_H02W0301 +arc: B3 V02S0301 +arc: B4 S1_V02N0501 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0701 +arc: B7 H02W0301 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 H02W0401 +arc: C5 N1_V02S0201 +arc: C6 V01N0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F5 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: V01S0100 F6 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 0100000011000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000000000001100 +word: SLICED.K1.INIT 0111011101110100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R75C55:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0501 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A6 W1_H02E0701 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C6 E1_H02W0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0100 F3 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0011001100000011 +word: SLICEC.K0.INIT 0011000100000001 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C56:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 H02W0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B5 E1_H02W0301 +arc: B6 V00B0100 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICED.K0.INIT 0011010111110101 +word: SLICED.K1.INIT 0101111111111111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V01N0101 +arc: A1 F7 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 W1_H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: A7 V02S0101 +arc: B0 V01N0001 +arc: B1 V02S0301 +arc: B2 E1_H01W0100 +arc: B3 H00R0100 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B6 H02W0101 +arc: B7 F3 +arc: C0 H02E0601 +arc: C2 H00L0100 +arc: C3 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001000111011101 +word: SLICED.K1.INIT 1111010111100100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000100110001 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100111111000101 +word: SLICED.K0.INIT 0000000100110001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C58:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: A0 N1_V02S0701 +arc: A1 F5 +arc: A2 V00T0000 +arc: A3 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A5 H02E0701 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B0 H02E0301 +arc: B1 V02N0301 +arc: B2 N1_V02S0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: B6 V00B0100 +arc: B7 H01E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 V02S0601 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0100 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: N1_V01N0101 F4 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +word: SLICEB.K0.INIT 1000000011001100 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1000000010101010 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C59:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A1 V02S0701 +arc: A2 V02N0501 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 V02N0101 +arc: B0 H02W0301 +arc: B1 S1_V02N0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 F3 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 H02W0601 +arc: C3 S1_V02N0401 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 F2 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R75C60:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 E1_H02W0501 +arc: A5 N1_V01N0101 +arc: A6 V00T0100 +arc: A7 N1_V01N0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 H02W0101 +arc: B6 V02S0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02E0201 +arc: D6 N1_V02S0401 +arc: D7 H02E0201 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 F3 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 V06S0203 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A4 H02W0701 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: B7 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C3 V02N0601 +arc: C4 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0001 +arc: D6 N1_V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q6 +arc: V01S0100 F6 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100101011001010 +word: SLICEC.K0.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R75C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: A2 V01N0101 +arc: A5 H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V02S0101 +arc: B2 V02N0101 +arc: B5 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C2 V02N0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 S1_V02N0001 +arc: D4 H02W0001 +arc: D5 H02E0001 +arc: D6 H00L0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H01W0000 F0 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0101 Q3 +arc: V00B0000 F4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C63:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E1_H02W0001 +arc: A1 V02N0701 +arc: A6 H02W0501 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B3 V02N0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 N1_V02S0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 N1_V02S0401 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 F1 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 0000000010111000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100000000110000 +word: SLICEA.K1.INIT 1010001011110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C64:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 N3_V06S0103 +arc: A0 E1_H02W0701 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 V02N0301 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B4 H02E0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 E1_H02W0301 +arc: C1 H00L0000 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F6 +arc: N1_V02N0501 F5 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q4 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEC.K0.INIT 0011001000110011 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R75C65:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 V06N0003 +arc: CLK0 G_HPBX0000 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: W1_H02W0001 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C66:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 V00B0000 +arc: A5 N1_V01N0101 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 1010100000001000 +word: SLICEC.K1.INIT 1100101011111111 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C67:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +arc: A3 H02E0701 +arc: A6 F7 +arc: A7 H00R0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: C0 H00L0000 +arc: C4 Q4 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1000100011000000 +word: SLICED.K0.INIT 0000111000001111 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R75C68:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 V02S0401 +arc: D0 V00B0100 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +word: SLICEA.K0.INIT 0101010100010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R75C69:PLC2 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V02S0501 +arc: B0 W1_H02E0301 +arc: B5 S1_V02N0701 +arc: C0 H02E0401 +arc: C5 V00T0000 +arc: D0 V00B0100 +arc: D5 H00R0100 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +word: SLICEA.K0.INIT 0101010100010101 +word: SLICEC.K1.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R75C70:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N1_V01S0100 + +.tile R75C71:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: A1 V02N0501 +arc: A3 S1_V02N0501 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: C1 S1_V02N0401 +arc: C2 H00L0100 +arc: C3 V02N0401 +arc: D1 H00R0000 +arc: D2 V02N0001 +arc: D3 H02E0201 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 F3 +word: SLICEA.K1.INIT 0000000100001111 +word: SLICEB.K1.INIT 0000010100000111 +word: SLICEB.K0.INIT 0000000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R75C72:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 N1_V02S0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A5 V00B0000 +arc: B1 H02E0101 +arc: B3 H02E0101 +arc: B5 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 V02S0201 +arc: C6 N1_V02S0201 +arc: C7 N1_V02S0201 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111011100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111011100000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1010101000101010 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R75C73:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 H02W0601 +arc: W1_H02W0201 V06S0103 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 H02E0501 +arc: A3 H02E0501 +arc: A5 S1_V02N0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B1 H02W0301 +arc: B3 H02W0301 +arc: B4 H00L0000 +arc: B5 H02W0301 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C5 N1_V02S0201 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 N1_V02S0201 +arc: D2 V02N0001 +arc: D3 N1_V02S0201 +arc: D5 V02S0401 +arc: D7 H02W0001 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00R0100 +arc: M2 H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1011111100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1011111100000000 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICEC.K1.INIT 1011000011110000 +word: SLICED.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1010000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R75C74:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: A3 W1_H02E0701 +arc: A5 V02N0301 +arc: B3 H02E0101 +arc: B5 S1_V02N0501 +arc: C3 N1_V02S0601 +arc: C5 V00T0000 +arc: D3 E1_H02W0001 +arc: D5 V02S0601 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +word: SLICEC.K1.INIT 0000111100001000 +word: SLICEB.K1.INIT 0000010100001101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R75C75:PLC2 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 + +.tile R75C76:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: W1_H02W0001 V06S0003 + +.tile R75C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 S1_V02N0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: B1 S1_V02N0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 V00B0000 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000101000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C78:PLC2 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H01E0101 +arc: A1 S1_V02N0501 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: D0 W1_H02E0001 +arc: D1 H02E0001 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C79:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V01S0100 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R75C80:PLC2 +arc: N1_V02N0301 V01N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 S1_V02N0501 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: F0 F5A_SLICE +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F0 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R75C81:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06E0003 + +.tile R75C82:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0401 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 S1_V02N0601 + +.tile R75C83:PLC2 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0501 +arc: B0 V02N0101 +arc: B2 V02N0301 +arc: B3 V02S0301 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C84:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02S0401 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: A2 V00T0000 +arc: A5 E1_H01W0000 +arc: A7 H02W0501 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B6 H02W0301 +arc: E1_H01E0101 F7 +arc: F7 F7_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C85:PLC2 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 N3_V06S0303 +arc: A3 V02S0701 +arc: B2 H00R0000 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 V02S0501 +arc: C2 H02E0601 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D5 H00L0100 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 F6 +arc: H01W0000 F6 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEB.K0.INIT 1100110011000011 +word: SLICED.K1.INIT 1100001111000000 +word: SLICEB.K1.INIT 1010101010100101 +word: SLICEC.K1.INIT 1100110000110000 +word: SLICEC.K0.INIT 1100001111000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R75C86:PLC2 +arc: E1_H02E0001 V02S0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S1_V02N0501 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 + +.tile R75C87:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0501 W3_H06E0303 +arc: B4 V02N0501 +arc: B7 H02W0101 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C7 H02W0601 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1111110000000011 +word: SLICEC.K0.INIT 1100001111000000 +word: SLICEB.K1.INIT 1111000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R75C88:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 H01E0101 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: A5 H02E0501 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B2 V02N0101 +arc: B3 H02E0301 +arc: B4 V02S0501 +arc: B6 V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C89:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0301 N1_V02S0301 +arc: A3 H02E0701 +arc: A4 V00B0000 +arc: B0 H02E0301 +arc: B1 H02E0101 +arc: B2 W1_H02E0101 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F4 +arc: F4 F4_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R75C90:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: V00B0000 V02S0201 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: C2 H02E0601 +arc: C4 V02S0201 +arc: C5 W1_H02E0401 +arc: D2 V02S0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F4 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 1111000000001111 +word: SLICEC.K0.INIT 1100110000110000 +word: SLICEC.K1.INIT 1111000011000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R75C91:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: W3_H06W0303 N3_V06S0303 + +.tile R75C92:PLC2 +arc: N1_V02N0301 S1_V02N0301 + +.tile R75C94:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R75C95:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R75C98:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R76C101:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R76C104:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R76C107:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R76C110:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R76C113:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R76C116:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R76C38:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0201 E1_H01W0000 + +.tile R76C39:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: A0 F5 +arc: A4 F5 +arc: A7 F5 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B3 S1_V02N0101 +arc: B4 V00B0100 +arc: B5 S1_V02N0501 +arc: B6 F3 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: N3_V06N0003 F0 +arc: N3_V06N0203 F4 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000001100000000 +word: SLICEC.K1.INIT 0000000000110011 +word: SLICEB.K1.INIT 0000110000000000 +word: SLICED.K0.INIT 0000110011001100 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 0010000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C40:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0201 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A4 V00T0000 +arc: B0 H00R0100 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 V02S0401 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0100 F6 +arc: M0 E1_H02W0601 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1010000011110000 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 1010001010101010 +word: SLICEB.K0.INIT 0000000011110011 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R76C41:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 V02N0301 +arc: V00T0100 W1_H02E0301 +arc: A1 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H01W0100 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: V01S0000 Q0 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000111111001100 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0101010111110000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000100000000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R76C42:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0103 H01E0101 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V01S0000 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: A0 H00R0000 +arc: A1 F5 +arc: A2 H00L0100 +arc: A4 E1_H02W0501 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 E1_H02W0701 +arc: B1 E1_H02W0301 +arc: B2 F1 +arc: B4 V02S0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 V02N0601 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 H01W0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F7 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 F3 +arc: V01S0000 Q0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101111101001100 +word: SLICEC.K1.INIT 0000100010101010 +word: SLICEA.K1.INIT 0000111000001010 +word: SLICEB.K0.INIT 0011001100010011 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K0.INIT 0000101010001010 +word: SLICED.K1.INIT 1111010111000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C43:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: A0 H00R0000 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 W1_H02E0501 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 F4 +arc: C3 V02S0401 +arc: C4 E1_H02W0401 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: C7 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D6 F0 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: H01W0100 F7 +arc: M0 V00T0000 +arc: W1_H02W0301 F3 +arc: W1_H02W0501 F5 +word: SLICEC.K1.INIT 0111001011111010 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEA.K0.INIT 1010101010111111 +word: SLICEA.K1.INIT 0011000000110011 +word: SLICED.K0.INIT 0010001010100010 +word: SLICED.K1.INIT 0101110011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C44:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A5 S1_V02N0101 +arc: B0 H02E0301 +arc: B3 F1 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D3 V00B0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: S1_V02S0301 F1 +arc: V01S0000 F3 +arc: V01S0100 F5 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 0101000001010000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111011111000100 +word: SLICED.K0.INIT 0011000000110000 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R76C45:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 H06E0003 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A3 V02N0501 +arc: A5 W1_H02E0701 +arc: B0 F3 +arc: B1 F3 +arc: B5 V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 E1_H02W0601 +arc: C5 N1_V02S0001 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 H02E0001 +arc: D3 S1_V02N0001 +arc: D5 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: N3_V06N0003 F3 +arc: V00B0100 F5 +arc: V01S0000 F3 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0001001100010000 +word: SLICEA.K0.INIT 0101011101011111 +word: SLICEA.K1.INIT 0101011100010011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C46:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H01E0001 +arc: A5 S1_V02N0301 +arc: B0 H01W0100 +arc: B2 V02N0101 +arc: B3 H02W0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0201 +arc: D7 H01W0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 F4 +arc: W1_H02W0501 F7 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 0000011100000011 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICED.K0.INIT 0000110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R76C47:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 H02W0501 +arc: B0 H02E0101 +arc: B1 W1_H02E0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 H02W0401 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0101 Q1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 1100110001001100 +word: SLICED.K0.INIT 0000110000001110 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000001110101010 +word: SLICEB.K0.INIT 1110111011110000 +word: SLICEB.K1.INIT 1111111111001100 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C48:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: A0 H02W0701 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: A6 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B6 F3 +arc: C0 V02N0401 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0401 Q6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N3_V06N0303 F6 +arc: W1_H02W0401 Q6 +word: SLICEB.K1.INIT 1011111100000000 +word: SLICED.K0.INIT 1000101000000000 +word: SLICEC.K0.INIT 1010111000000000 +word: SLICEA.K0.INIT 1011111110001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C49:PLC2 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A6 W1_H02E0501 +arc: A7 H00L0000 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C2 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 V00T0000 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICED.K0.INIT 0000100000000000 +word: SLICEB.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C50:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 V01N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: B3 V01N0001 +arc: D3 N1_V02S0001 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0011001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R76C51:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: A2 W1_H02E0701 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 Q2 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C52:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 V02N0301 +arc: A3 S1_V02N0501 +arc: A6 E1_H02W0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B3 S1_V02N0101 +arc: B6 V02N0701 +arc: C3 S1_V02N0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 H02E0201 +arc: D6 N1_V02S0601 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: LSR0 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F6 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011001100000000 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R76C53:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V01N0101 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 V06S0203 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 F3 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 F4 +arc: C3 V02S0401 +arc: C4 N1_V02S0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 H02W0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02S0601 +arc: D6 V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F2 +arc: N1_V02N0701 F5 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEB.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R76C54:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 V01N0101 +arc: H00L0000 H02E0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: A3 V00T0000 +arc: A7 H00L0000 +arc: B0 V02S0101 +arc: B2 N1_V02S0101 +arc: B4 E1_H02W0301 +arc: B5 H02W0301 +arc: B6 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C55:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 V01N0101 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 V01N0101 +arc: A0 H00L0000 +arc: A2 H02E0701 +arc: B1 V02N0101 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C56:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H02E0301 +arc: B5 V02N0701 +arc: B7 V02S0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C57:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V01N0101 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 V00B0000 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 H00L0000 +arc: B7 H02E0101 +arc: E1_H01E0101 F5 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: V01S0000 F3 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C58:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0201 V02S0201 +arc: A1 V02N0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C4 V02N0201 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H01W0000 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: LSR1 H02W0301 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: S1_V02S0001 F0 +arc: V00B0000 F6 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C59:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 H06W0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H01E0001 +arc: A1 W1_H02E0701 +arc: A2 V01N0101 +arc: A3 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 V00T0000 +arc: A6 H00L0000 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B1 H00R0100 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 W1_H02E0101 +arc: B7 F3 +arc: C0 E1_H01W0000 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 H02W0401 +arc: C6 V01N0101 +arc: C7 F4 +arc: D0 V02S0201 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0101 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 F6 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R76C60:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A1 E1_H02W0701 +arc: A4 N1_V02S0101 +arc: A7 S1_V02N0301 +arc: B1 V02N0301 +arc: B4 V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 S1_V02N0401 +arc: C4 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D4 V00B0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C61:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0701 +arc: B1 V01N0001 +arc: C0 V02S0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C62:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 V02S0501 +arc: B1 Q1 +arc: B3 N1_V02S0301 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C63:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 W3_H06E0303 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 N1_V01S0000 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B3 H02W0301 +arc: B6 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D6 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q5 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R76C64:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0101 W1_H02E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 N1_V01S0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 V02N0301 +arc: B3 Q3 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 H00R0100 +arc: C4 H01E0001 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 0000000011001100 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C65:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0203 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 E1_H01E0001 +arc: B1 H02W0101 +arc: C1 H02E0601 +arc: D1 H00R0000 +arc: F1 F1_SLICE +arc: S1_V02S0301 F1 +word: SLICEA.K1.INIT 1000010000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C66:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 H02E0101 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 E1_H02W0501 +arc: A2 V02N0501 +arc: A4 E1_H02W0701 +arc: A7 V02N0101 +arc: B1 W1_H02E0101 +arc: B2 H02E0301 +arc: B7 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C4 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D4 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1010000001010000 +word: SLICEA.K1.INIT 1010111100100011 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C67:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02W0101 +arc: A1 V02S0501 +arc: A5 S1_V02N0301 +arc: A6 H02E0701 +arc: A7 F5 +arc: B0 H01W0100 +arc: B1 E1_H02W0301 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00B0100 +arc: D5 H00L0100 +arc: D6 E1_H02W0001 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 F7 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +word: SLICEC.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1100010011110101 +word: SLICED.K1.INIT 1000000000001000 +word: SLICEA.K0.INIT 0011110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R76C68:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: V00B0100 V02S0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0000110000001010 +word: SLICEA.K0.INIT 0011001111001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R76C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 S1_V02N0201 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 H02W0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 S1_V02N0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 Q2 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000000011001010 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010110011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R76C70:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1011111110110011 +word: SLICED.K0.INIT 1000110010000000 +word: SLICEC.K1.INIT 1111101100111011 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100010010000000 +word: SLICEB.K1.INIT 1111011110110011 +word: SLICEC.K0.INIT 1100100000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C71:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 H01E0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 V01N0101 +arc: A1 V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 V02N0301 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H02E0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q2 +arc: V01S0100 F6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010110010101100 +word: SLICED.K1.INIT 1100100001000000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100000010100000 +word: SLICEC.K1.INIT 1111001110111011 +word: SLICED.K0.INIT 1000100011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R76C72:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A2 V02N0501 +arc: B2 W1_H02E0301 +arc: C2 H02E0401 +arc: D2 H02W0201 +arc: F2 F2_SLICE +arc: S1_V02S0001 F2 +word: SLICEB.K0.INIT 0000111100001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R76C73:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 N1_V02S0201 +arc: A0 F5 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A4 W1_H02E0501 +arc: A5 V02N0101 +arc: B0 H00R0100 +arc: B1 E1_H02W0101 +arc: B2 H00R0100 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 V02N0401 +arc: C1 W1_H02E0601 +arc: C2 H02E0601 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: V00B0000 F4 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 0011001000110011 +word: SLICEC.K0.INIT 0011001100100000 +word: SLICEC.K1.INIT 0011001100100000 +word: SLICEA.K0.INIT 0011001100100011 +word: SLICEA.K1.INIT 0011001100100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C74:PLC2 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 V01N0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0701 +arc: A2 S1_V02N0501 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: A5 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 H02W0701 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000000001010000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001000000010011 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICEC.K0.INIT 0000010100000100 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K0.INIT 0000010100010101 +word: SLICED.K1.INIT 0000000100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C75:PLC2 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 E1_H02W0601 + +.tile R76C76:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 + +.tile R76C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0701 +arc: C6 V02N0201 +arc: D0 V00B0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R76C78:PLC2 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H01E0001 +arc: S3_V06S0103 H01E0101 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: A1 W1_H02E0501 +arc: A3 W1_H02E0701 +arc: A5 H02W0501 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 H02E0001 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 0000000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R76C79:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V01S0100 +arc: A1 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F6 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICEC.K0.INIT 0000101000000000 +word: SLICEC.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000010100000 +word: SLICED.K1.INIT 0000000010000000 +word: SLICEA.K0.INIT 1111111111110011 +word: SLICEA.K1.INIT 1111111111110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R76C80:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0101 V01N0101 +arc: A0 V02N0501 +arc: A1 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A7 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 E1_H02W0601 +arc: M2 E1_H02W0601 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000010100000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICED.K1.INIT 0000000000100000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0100000000000000 +word: SLICEC.K0.INIT 0001000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R76C81:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H01E0101 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 + +.tile R76C82:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 + +.tile R76C83:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0701 H06E0203 + +.tile R76C84:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: A4 N1_V02S0101 +arc: A5 H02E0701 +arc: B0 H02E0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0301 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: A4 N1_V01S0100 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B2 V02S0101 +arc: B3 N1_V02S0301 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C86:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B7 H01E0101 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1100110000110011 +word: SLICEC.K1.INIT 1100001111000000 +word: SLICEC.K0.INIT 1111000011000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R76C87:PLC2 +arc: E1_H02E0101 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: A4 H02W0501 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B2 W1_H02E0301 +arc: B3 N1_V02S0301 +arc: B5 N1_V02S0501 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C88:PLC2 +arc: N1_V02N0101 H06E0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A3 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 N1_V02S0101 +arc: B2 H02W0301 +arc: B4 H02E0101 +arc: F5 F5_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R76C89:PLC2 +arc: N3_V06N0103 H06E0103 +arc: W1_H02W0301 N1_V02S0301 + +.tile R76C90:PLC2 +arc: N1_V02N0401 N1_V01S0000 + +.tile R76C91:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R76C92:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R76C98:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R77C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C101:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R77C102:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C103:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R77C104:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C105:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C106:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C107:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 + +.tile R77C108:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C109:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C110:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R77C111:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C112:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C113:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 + +.tile R77C114:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C115:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C116:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R77C117:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C118:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C14:PLC2 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C15:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C20:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R77C21:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R77C23:PLC2 +arc: N3_V06N0303 H06W0303 + +.tile R77C26:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R77C32:PLC2 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: W3_H06W0303 S3_V06N0303 + +.tile R77C35:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R77C36:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R77C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C39:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0401 +arc: A0 H02W0501 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 F5 +arc: A7 N1_V01S0100 +arc: B0 H00R0100 +arc: B2 V02S0301 +arc: B3 H00R0000 +arc: B4 V01S0000 +arc: B5 F3 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 S1_V02N0401 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: D0 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 F2 +arc: D7 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: V01S0000 F7 +word: SLICEB.K1.INIT 0000000000010000 +word: SLICEB.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICED.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 0000001000100010 +word: SLICEA.K0.INIT 0000000000000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R77C3:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R77C40:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0501 V02S0501 +arc: A1 V02N0501 +arc: A2 V00B0000 +arc: A3 F7 +arc: A4 H02E0501 +arc: A5 H02W0701 +arc: A6 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 E1_H01W0100 +arc: B2 E1_H02W0301 +arc: B3 H02W0301 +arc: B4 V02S0501 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C1 V02N0601 +arc: C2 H00R0100 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 H02E0601 +arc: C7 V02N0001 +arc: D1 F2 +arc: D2 V02N0201 +arc: D3 H01E0101 +arc: D4 V02S0401 +arc: D5 F0 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: N3_V06N0303 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000010101000 +word: SLICEC.K1.INIT 1110101000000000 +word: SLICED.K1.INIT 0000111100001110 +word: SLICEB.K1.INIT 0100010001000000 +word: SLICEB.K0.INIT 1111101100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R77C41:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 W1_H02E0701 +arc: A6 F7 +arc: B1 F3 +arc: B2 V02S0301 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0501 +arc: B5 V00B0100 +arc: B7 V02S0501 +arc: C0 V02S0401 +arc: C1 F4 +arc: C3 W1_H02E0601 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 W1_H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 F6 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEC.K0.INIT 0011001100110010 +word: SLICEB.K1.INIT 0000000011111110 +word: SLICEA.K1.INIT 0000001100000001 +word: SLICED.K0.INIT 0000101000001010 +word: SLICEC.K1.INIT 0000000100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 N1_V01N0101 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B5 H00R0000 +arc: B7 N1_V02S0501 +arc: C0 H00L0100 +arc: C2 H02W0601 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: LSR1 H02E0301 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F6 +arc: V00B0100 F7 +arc: V01S0000 F7 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1110111011110000 +word: SLICEA.K1.INIT 1111111111001100 +word: SLICEB.K0.INIT 0101111111111111 +word: SLICEB.K1.INIT 0000011100001111 +word: SLICED.K1.INIT 1100110000000000 +word: SLICEC.K1.INIT 0100110011001100 +word: SLICEC.K0.INIT 0101111111111111 +word: SLICED.K0.INIT 0000010100000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R77C43:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 V01N0001 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A2 H00L0100 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B6 H02E0101 +arc: B7 W1_H02E0101 +arc: C0 H02E0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D6 H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR0 E1_H02W0301 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: W1_H02W0601 F6 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEB.K0.INIT 1111111100010101 +word: SLICEB.K1.INIT 0000110000001111 +word: SLICED.K1.INIT 0000100011001100 +word: SLICEA.K0.INIT 1011111110001100 +word: SLICED.K0.INIT 0011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R77C44:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 H02E0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 W1_H02E0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A5 V00T0100 +arc: A6 V02N0301 +arc: A7 V02S0101 +arc: B1 W1_H02E0301 +arc: B3 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C1 W1_H02E0601 +arc: C3 H00L0100 +arc: C5 V02S0001 +arc: C6 H02W0601 +arc: C7 F6 +arc: D0 W1_H02E0001 +arc: D1 H02W0001 +arc: D3 H02E0001 +arc: D4 E1_H02W0001 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 F0 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: E3_H06E0103 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 1101000111110011 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEA.K0.INIT 0101010111111111 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000011100001111 +word: SLICED.K1.INIT 0011000100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C45:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0103 V01N0101 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V02N0701 +arc: B5 V02S0501 +arc: B6 H02W0101 +arc: C0 F6 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H01E0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: LSR0 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 0011011101110111 +word: SLICEB.K1.INIT 0011000001110111 +word: SLICED.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0101011100000000 +word: SLICEC.K0.INIT 1111000010110000 +word: SLICEC.K1.INIT 1110000011000000 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEA.K1.INIT 0000000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R77C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 V06N0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 V06N0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: A2 H02E0501 +arc: A6 H02W0501 +arc: A7 V02S0101 +arc: B1 H02W0101 +arc: B2 F1 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: B7 V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 V01N0001 +arc: D6 F2 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V00B0100 F7 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEA.K1.INIT 1100000011001100 +word: SLICEB.K0.INIT 1010000010110000 +word: SLICEC.K0.INIT 0011000000000000 +word: SLICED.K0.INIT 1010111110001101 +word: SLICED.K1.INIT 0000000000110010 +word: SLICEA.K0.INIT 0000101011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C47:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 V02N0701 +arc: A3 V02N0501 +arc: A4 H02W0501 +arc: A5 F7 +arc: A6 F5 +arc: B0 H02W0301 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C3 F4 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 W1_H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 N1_V02S0201 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F6 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEC.K0.INIT 0001010101010101 +word: SLICEB.K1.INIT 0000101000101010 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEC.K1.INIT 0000000000010101 +word: SLICED.K0.INIT 0000000000011111 +word: SLICEA.K1.INIT 0000000001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R77C48:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: B4 H00R0000 +arc: B5 H02W0301 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H00R0100 F5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V02N0101 F1 +arc: V00B0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K1.INIT 1100100011000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111000010000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R77C49:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 F5 +arc: A1 F5 +arc: A5 E1_H01W0000 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: C1 H02E0401 +arc: D0 H00R0000 +arc: D1 V02N0201 +arc: D5 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +word: SLICEC.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0101010101111111 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R77C50:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H01E0001 +arc: A1 H00R0000 +arc: A4 N1_V02S0101 +arc: A6 F7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B4 V00B0100 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 F4 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D4 H00L0100 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 0111001101000000 +word: SLICED.K1.INIT 0000000011110011 +word: SLICEC.K0.INIT 0100010101010101 +word: SLICEA.K1.INIT 0000101011001100 +word: SLICED.K0.INIT 0101000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R77C51:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 V02N0001 +arc: H00R0100 V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0203 H06W0203 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0000 +arc: A3 S1_V02N0701 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B1 V02N0301 +arc: B3 W1_H02E0301 +arc: B4 W1_H02E0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V01N0101 +arc: C5 W1_H02E0601 +arc: C6 V00T0100 +arc: C7 S1_V02N0001 +arc: D1 H02W0201 +arc: D3 V02N0201 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0401 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N1_V01N0001 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0701 F7 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICED.K0.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C52:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02N0401 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 H02E0301 +arc: B4 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C3 N1_V01N0001 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 F3 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0100 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 1111111111000000 +word: SLICEA.K0.INIT 1111111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C53:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 V02S0601 +arc: C1 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R77C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A5 E1_H02W0701 +arc: B0 V02N0301 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C0 V02S0601 +arc: C5 N1_V02S0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 H00R0100 +arc: E1_H01E0101 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N3_V06N0203 F7 +arc: S3_V06S0203 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000110000001100 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C55:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0501 V01N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 H02E0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B5 V02N0501 +arc: B6 V02S0701 +arc: C0 E1_H02W0401 +arc: C2 N1_V01S0100 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D5 H02E0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 0000000001011111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R77C56:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02S0701 +arc: A4 V02S0101 +arc: A5 Q5 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B2 W1_H02E0301 +arc: B3 Q3 +arc: B5 V02S0501 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0203 Q4 +arc: W1_H02W0601 Q4 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C57:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E3_H06W0103 +arc: A7 H02E0501 +arc: B0 H02W0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 N1_V01S0100 +arc: C6 V02N0201 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 N1_V02S0601 +arc: D7 H02W0201 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0501 F7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0011000011110000 +word: SLICED.K1.INIT 0001010100111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R77C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W1_H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 V01N0101 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: A4 H02E0701 +arc: A6 N1_V02S0301 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B4 V01S0000 +arc: B7 S1_V02N0501 +arc: C1 N1_V02S0401 +arc: C4 V00T0100 +arc: C6 F4 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D4 W1_H02E0001 +arc: D6 H01W0000 +arc: D7 H02E0001 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 1010000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R77C59:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02E0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 H01E0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A6 F5 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 N1_V02S0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 V02S0701 +arc: B6 F3 +arc: B7 V02N0501 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V01S0100 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 F2 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R77C60:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 + +.tile R77C61:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 N1_V02S0301 +arc: A7 V02S0101 +arc: C0 N1_V01N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICED.K1.INIT 0000000010101111 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R77C62:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 N1_V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0003 N1_V01S0000 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B6 V01S0000 +arc: C0 H02E0401 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 W1_H02E0001 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R77C63:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V06N0203 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: V00T0100 H02E0101 +arc: A1 V01N0101 +arc: B0 H02W0301 +arc: B1 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V02N0001 +arc: D2 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1011101100000000 +word: SLICEB.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R77C64:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 H01E0001 +arc: A5 F7 +arc: A7 V02S0101 +arc: B1 H02W0301 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 H02E0201 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 1111001100000000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R77C65:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A3 H02W0701 +arc: B0 W1_H02E0101 +arc: B3 V02S0301 +arc: C0 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D3 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 F2 +word: SLICEA.K0.INIT 1000100011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 W3_H06E0103 +arc: A0 E1_H01E0001 +arc: A1 W1_H02E0701 +arc: A2 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 H02W0501 +arc: A6 F7 +arc: B0 F1 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 F3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 W1_H02E0601 +arc: C4 H02W0601 +arc: C5 F6 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D0 V02S0001 +arc: D1 H02E0201 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 E1_H02W0001 +arc: D5 F0 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: W1_H02W0701 F5 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1000000000001000 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R77C67:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: A6 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B7 S1_V02N0501 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02N0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0601 E3_H06W0303 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 S1_V02N0701 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C69:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 H02E0401 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: A1 H00R0000 +arc: A3 V01N0101 +arc: A4 V02S0301 +arc: B0 V02N0101 +arc: B2 H02E0101 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 V00T0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C70:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 E1_H01W0000 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B6 V00T0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F4 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C71:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0501 +arc: A4 H02E0701 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 H00R0100 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C4 Q4 +arc: C5 H02W0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H01W0100 +arc: D5 F0 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR1 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q4 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1101000010000000 +word: SLICED.K1.INIT 1101100011111111 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R77C72:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 S3_V06N0003 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 E1_H02W0701 +arc: B1 H02E0101 +arc: C1 S1_V02N0601 +arc: D1 V02S0001 +arc: E1_H01E0001 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 0011001100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R77C73:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0201 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02W0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 V02S0701 +arc: A0 H00L0000 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V00T0100 +arc: A7 H00R0000 +arc: B0 H01W0100 +arc: B1 S1_V02N0301 +arc: B3 V02S0101 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 E1_H02W0601 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 N1_V02S0001 +arc: C6 H02W0401 +arc: C7 N1_V02S0001 +arc: D0 E1_H02W0001 +arc: D1 N1_V01S0000 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: D5 S1_V02N0601 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 W1_H02E0601 +arc: M4 V00T0000 +arc: M5 W1_H02E0001 +arc: M6 V00T0000 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1000110011001100 +word: SLICEC.K1.INIT 1011111100000000 +word: SLICED.K0.INIT 1000100011001000 +word: SLICED.K1.INIT 1101111100000000 +word: SLICEA.K0.INIT 0010111100000000 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEB.K1.INIT 0101010101000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R77C74:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A6 F5 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: C0 H02E0401 +arc: C1 E1_H02W0601 +arc: C3 V02N0401 +arc: C5 S1_V02N0201 +arc: C6 V00B0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 V02N0601 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: M0 H02E0601 +arc: S1_V02S0301 F3 +word: SLICEC.K0.INIT 0010001000110011 +word: SLICEB.K1.INIT 0101010001010101 +word: SLICEA.K0.INIT 0010101000100010 +word: SLICEA.K1.INIT 1111000000110000 +word: SLICEC.K1.INIT 0000111100001000 +word: SLICED.K0.INIT 0011001100100011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R77C75:PLC2 +arc: H00L0100 N1_V02S0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00T0000 +arc: V01S0000 F1 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010101000 +word: SLICEA.K0.INIT 1010101010101000 +word: SLICEA.K1.INIT 1010101010101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R77C76:PLC2 +arc: E1_H02E0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: C2 W1_H02E0401 +arc: D2 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F2 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R77C77:PLC2 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0103 N1_V01S0100 +arc: A1 V02N0701 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: A7 H00L0000 +arc: B0 V02N0101 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B7 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: D0 H02W0001 +arc: D1 V02N0001 +arc: D2 H02W0001 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000110000000000 +word: SLICEA.K1.INIT 0000101100001000 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 0000110100001000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 0100010001010000 +word: SLICED.K0.INIT 0000000010101111 +word: SLICED.K1.INIT 0000000011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R77C78:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: A2 S1_V02N0501 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F7 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C79:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H01E0001 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 N3_V06S0003 +arc: A7 E1_H02W0501 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 E1_H02W0101 +arc: B5 S1_V02N0501 +arc: B6 V02N0701 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F5 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F7 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0101010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R77C80:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0203 W3_H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 S3_V06N0303 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0701 +arc: A5 H02W0701 +arc: A7 H02W0701 +arc: B4 E1_H02W0101 +arc: B5 W1_H02E0301 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C4 W1_H02E0601 +arc: C5 H02E0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: D4 H02W0201 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: V01S0100 F1 +arc: W1_H02W0601 F4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICED.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 0000000001000000 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R77C81:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H02W0701 + +.tile R77C82:PLC2 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 S1_V02N0401 + +.tile R77C83:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 + +.tile R77C84:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C85:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C87:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C88:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R77C89:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R77C90:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C91:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R77C92:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C93:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R77C94:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R77C95:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06E0303 + +.tile R77C96:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R77C97:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R77C98:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R77C99:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 + +.tile R78C100:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R78C103:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R78C105:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C106:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R78C108:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R78C109:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C111:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R78C112:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C115:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R78C38:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: A1 V01N0101 +arc: A5 V02N0101 +arc: B1 V01N0001 +arc: B5 H00L0000 +arc: C1 S1_V02N0601 +arc: C5 V01N0101 +arc: D1 V02N0001 +arc: D5 V01N0001 +arc: E1_H01E0001 F1 +arc: E3_H06E0303 F5 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R78C39:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H01E0001 + +.tile R78C40:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0501 +arc: A0 F5 +arc: A1 F5 +arc: A3 V01N0101 +arc: A7 N1_V01S0100 +arc: B1 V00B0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C3 F4 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 F4 +arc: C7 V02N0201 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: D6 W1_H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0601 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: N1_V02N0501 F7 +arc: N3_V06N0103 F2 +arc: V01S0100 F0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000011 +word: SLICEB.K1.INIT 0000000010000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000010101010101 +word: SLICEA.K1.INIT 0000000100010001 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K1.INIT 1111101011001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R78C41:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 H02E0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02N0101 +arc: A5 V00B0000 +arc: B1 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: C1 H02E0601 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: D1 F2 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 F2 +arc: E1_H01E0001 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEB.K0.INIT 0000000001010000 +word: SLICEC.K1.INIT 0000100000000000 +word: SLICEA.K1.INIT 0001000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R78C42:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0601 E1_H01W0000 +arc: A6 V02S0101 +arc: C6 W1_H02E0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +word: SLICED.K0.INIT 0000000011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R78C43:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 V01N0101 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 V06S0203 +arc: A2 H00L0100 +arc: A4 F5 +arc: A5 H02W0501 +arc: A7 V02S0101 +arc: B0 V02N0101 +arc: B2 H00R0000 +arc: B4 H01E0101 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C5 V02S0001 +arc: C7 V02S0201 +arc: D0 E1_H02W0001 +arc: D2 V02N0001 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: N3_V06N0003 F0 +word: SLICEA.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 0001001100110011 +word: SLICED.K1.INIT 0000001010101010 +word: SLICEC.K1.INIT 0001010101010101 +word: SLICEC.K0.INIT 1100000001000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R78C44:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 H01E0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A2 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 N1_V02S0301 +arc: B1 V02N0101 +arc: B2 H00R0100 +arc: B3 H02E0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C1 H02W0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0001 F2 +arc: V00T0100 F1 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 1111000011010000 +word: SLICEB.K1.INIT 1111000010000000 +word: SLICED.K1.INIT 0000111100000011 +word: SLICEC.K0.INIT 0000000000001011 +word: SLICEC.K1.INIT 0000000011001111 +word: SLICEA.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R78C45:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 E1_H01E0001 +arc: A2 E1_H02W0501 +arc: A4 H02E0501 +arc: A5 V02S0301 +arc: A6 F5 +arc: A7 V00T0100 +arc: B1 Q1 +arc: B4 H02W0301 +arc: B6 N1_V02S0701 +arc: B7 W1_H02E0301 +arc: C0 V02N0401 +arc: C1 V02S0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 F4 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 S1_V02N0601 +arc: D6 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 F3 +arc: V00T0100 Q1 +arc: V01S0000 F3 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111100001010 +word: SLICED.K1.INIT 0000000001110011 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 0101000101010101 +word: SLICED.K0.INIT 0100000011001100 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K1.INIT 1111110001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C46:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 H00L0000 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0401 +arc: C2 W1_H02E0601 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: C6 H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: V00B0000 F6 +arc: V01S0000 F4 +word: SLICED.K1.INIT 0000011100000011 +word: SLICEC.K0.INIT 1111000010100000 +word: SLICEC.K1.INIT 1000101010101010 +word: SLICED.K0.INIT 0000000011110010 +word: SLICEA.K0.INIT 1111110010101010 +word: SLICEA.K1.INIT 1111001110101010 +word: SLICEB.K0.INIT 0100000001010001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R78C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 N1_V02S0501 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06S0303 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A2 E1_H02W0501 +arc: A4 F7 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: B0 E1_H02W0101 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0101 +arc: B5 V01S0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C3 H02E0401 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 F2 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: D5 E1_H02W0001 +arc: D6 H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: N3_V06N0203 F4 +arc: S1_V02S0601 F4 +arc: V01S0100 F1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 1101100011111010 +word: SLICEB.K0.INIT 0010001000000000 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEA.K1.INIT 0000000000011111 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 0000101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R78C48:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W1_H02E0101 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V02S0601 +arc: A0 H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 F1 +arc: C0 W1_H02E0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H02E0201 +arc: D5 V02S0401 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR1 E1_H02W0501 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1111110010101010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0011011100111111 +word: SLICEC.K1.INIT 0000010101010101 +word: SLICEA.K0.INIT 1010111111001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C49:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: A0 H00R0000 +arc: B0 H02E0301 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111101101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C50:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N1_V01S0000 +arc: A6 E1_H01W0000 +arc: C2 N1_V02S0601 +arc: C6 V02N0201 +arc: D2 H02E0201 +arc: D6 H02E0001 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R78C51:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0401 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: B0 V00T0000 +arc: B4 S1_V02N0701 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H00L0100 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 W1_H02E0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 Q2 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001000110110011 +word: SLICEA.K1.INIT 0000101011111010 +word: SLICEB.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C52:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 H01E0001 + +.tile R78C53:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V02N0401 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B4 S1_V02N0701 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D4 E1_H02W0201 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0401 F4 +arc: V00T0100 Q1 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 0011111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C54:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N1_V01S0100 +arc: S3_V06S0103 H01E0101 +arc: A0 F7 +arc: A3 S1_V02N0501 +arc: A6 V02N0301 +arc: A7 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B3 V02N0101 +arc: B6 W1_H02E0101 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C6 H02W0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 H02W0201 +arc: D3 N1_V01S0000 +arc: D6 V02S0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F1 +arc: V00B0000 F6 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0000010111010101 +word: SLICEA.K0.INIT 0101010111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A6 N1_V01N0101 +arc: B0 E1_H02W0101 +arc: B1 V02S0101 +arc: B6 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C6 V02S0001 +arc: D0 W1_H02E0201 +arc: D1 H02E0201 +arc: D6 H02E0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0001 F6 +arc: N1_V02N0101 F1 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R78C56:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 V01N0101 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C57:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: A1 H02W0701 +arc: A2 V02N0501 +arc: A7 V00T0100 +arc: B1 H01W0100 +arc: B2 W1_H02E0101 +arc: B7 V00B0000 +arc: C1 E1_H02W0601 +arc: C2 H02W0401 +arc: C7 H02W0401 +arc: D1 N1_V01S0000 +arc: D2 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0101 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R78C58:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V01N0101 +arc: A1 V02N0501 +arc: A3 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B1 H02E0101 +arc: B3 V02S0301 +arc: B7 V00B0000 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C7 V02N0001 +arc: D1 V02N0001 +arc: D3 S1_V02N0201 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: V00T0100 F3 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R78C59:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02S0201 +arc: W1_H02W0601 S1_V02N0601 +arc: A1 V01N0101 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B1 V02S0301 +arc: B6 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C1 W1_H02E0601 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: D1 V02S0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: N1_V02N0001 F0 +arc: N1_V02N0401 F6 +arc: V00B0100 F7 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICED.K0.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R78C60:PLC2 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 H06E0103 +arc: W1_H02W0701 N3_V06S0203 + +.tile R78C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H06E0003 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0201 N3_V06S0103 + +.tile R78C62:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 V06N0003 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 V01N0101 +arc: N1_V02N0201 H02E0201 +arc: N3_V06N0303 S1_V02N0501 +arc: V00B0000 V02S0201 +arc: W1_H02W0201 N3_V06S0103 +arc: B0 V02N0101 +arc: C0 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 H02E0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 W3_H06E0003 +arc: A2 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 Q7 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B6 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 W1_H02E0601 +arc: C4 Q4 +arc: C5 W1_H02E0401 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 N1_V01S0000 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q5 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q6 +arc: S1_V02S0701 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C65:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 W1_H02E0301 +arc: A2 V02N0701 +arc: B0 W1_H02E0301 +arc: B1 W1_H02E0301 +arc: B3 Q3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C66:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02N0501 +arc: A1 H02W0501 +arc: A2 E1_H02W0701 +arc: A4 N1_V02S0301 +arc: A5 S1_V02N0301 +arc: A6 F5 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 V00B0100 +arc: B5 N1_V02S0501 +arc: B6 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 V02S0601 +arc: C2 H02E0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D4 V02N0401 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 H02E0501 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1001000010011001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C67:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V02S0501 +arc: A1 H00L0000 +arc: A2 H02E0501 +arc: A5 H02E0501 +arc: A6 F5 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H02W0101 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: C0 E1_H02W0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0401 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 F2 +arc: D2 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0100 F7 +arc: V01S0100 Q0 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100010000110001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010000000000 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C68:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 V02S0301 +arc: B5 V02S0701 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H00L0100 +arc: C4 H02W0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C69:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V02S0601 +arc: A0 H00R0000 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 V02N0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B5 W1_H02E0301 +arc: B7 H02E0101 +arc: C0 W1_H02E0601 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100101011001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R78C70:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: V00T0100 H02W0101 +arc: B0 V02S0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C71:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0501 W1_H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 V06S0103 + +.tile R78C72:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: B0 E1_H02W0101 +arc: B2 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 V02N0401 +arc: C1 H02W0401 +arc: C2 V02N0401 +arc: C3 H02W0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H02E0001 +arc: M2 H02W0601 +arc: M3 W1_H02E0201 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: S3_V06S0003 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000011001110 +word: SLICEA.K1.INIT 0000000011111010 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICEB.K1.INIT 0000000011111010 +word: SLICEC.K0.INIT 0000110000001110 +word: SLICEC.K1.INIT 0000110000001110 +word: SLICED.K0.INIT 0000110000001110 +word: SLICED.K1.INIT 0000111100001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R78C73:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 E1_H02W0101 +arc: H01W0000 W3_H06E0103 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0100 H02W0701 +arc: V00T0100 H02E0301 +arc: W1_H02W0601 V02S0601 +arc: A0 H02E0701 +arc: A1 H00L0000 +arc: A2 H00L0100 +arc: A5 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: S3_V06S0103 F2 +arc: V01S0100 Q1 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEA.K1.INIT 1110111100100000 +word: SLICEB.K1.INIT 1100000011001100 +word: SLICEB.K0.INIT 0010000010101010 +word: SLICEC.K1.INIT 0000101000001111 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R78C74:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02N0001 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0100 V02S0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02E0501 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 H01E0001 +arc: C6 S1_V02N0201 +arc: C7 H02W0401 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000010101110 +word: SLICEA.K1.INIT 0000000011111010 +word: SLICEB.K0.INIT 0000000010101110 +word: SLICEB.K1.INIT 0000000011111010 +word: SLICEC.K0.INIT 0000101000001110 +word: SLICEC.K1.INIT 0000000011110100 +word: SLICED.K0.INIT 0000101000001110 +word: SLICED.K1.INIT 0000000011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R78C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W1_H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: A4 V00B0000 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: D1 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: N1_V01N0101 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +word: SLICEB.K1.INIT 0000000011001111 +word: SLICEA.K1.INIT 0000000011001111 +word: SLICED.K0.INIT 0101010100000101 +word: SLICED.K1.INIT 0000111100000101 +word: SLICEC.K0.INIT 0000000010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R78C76:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 H02W0301 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W1_H02E0401 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 H01E0101 +arc: A0 H00L0100 +arc: B0 V01N0001 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R78C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: A0 W1_H02E0701 +arc: A2 E1_H02W0701 +arc: B0 V02S0301 +arc: B2 E1_H02W0301 +arc: C0 S1_V02N0601 +arc: C2 E1_H02W0401 +arc: C4 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D4 E1_H01W0100 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R78C78:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 H01E0101 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: A2 V00B0000 +arc: A3 W1_H02E0701 +arc: A4 N1_V01S0100 +arc: A5 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F5 +arc: V01S0000 F3 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R78C79:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A3 H00L0100 +arc: A4 N1_V02S0301 +arc: A5 V00T0100 +arc: A6 N1_V01S0100 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0301 +arc: B7 V02S0701 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: V01S0100 F6 +arc: W1_H02W0001 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R78C80:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 N1_V01S0100 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A4 H02E0701 +arc: A5 N1_V02S0301 +arc: A6 F5 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B4 H01E0101 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0101 +arc: B7 H02E0101 +arc: C4 H02E0601 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 S1_V02N0401 +arc: D6 E1_H01W0100 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: S3_V06S0203 F7 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0001 F0 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R78C81:PLC2 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0203 S3_V06N0203 +arc: V00T0100 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V02N0701 +arc: A4 V00T0100 +arc: A6 E1_H02W0501 +arc: B2 H00R0100 +arc: B4 H00R0000 +arc: B6 V02N0701 +arc: C2 V02N0401 +arc: C4 V01N0101 +arc: C6 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 F2 +arc: D6 S1_V02N0601 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 F4 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEB.K0.INIT 1000110010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R78C82:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 S1_V02N0701 + +.tile R78C83:PLC2 +arc: W1_H02W0501 V02N0501 + +.tile R78C84:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R78C85:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C87:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R78C88:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R78C90:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C91:PLC2 +arc: N1_V02N0001 S3_V06N0003 + +.tile R78C93:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C94:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R78C96:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R78C99:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R79C35:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R79C36:PLC2 +arc: E1_H02E0701 S1_V02N0701 + +.tile R79C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 S1_V02N0501 +arc: A0 W1_H02E0701 +arc: A2 V01N0101 +arc: B1 V01N0001 +arc: B3 Q3 +arc: C0 H02W0401 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C39:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: W1_H02W0401 V01N0001 +arc: A0 V01N0101 +arc: A2 H02W0501 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: LSR0 E1_H02W0301 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C40:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 S1_V02N0501 +arc: A4 S1_V02N0101 +arc: C0 S1_V02N0601 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEC.K0.INIT 0000101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R79C41:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 N1_V02S0301 +arc: A1 H00L0000 +arc: A5 V02N0301 +arc: B1 V02N0101 +arc: B5 V02N0701 +arc: C1 N1_V02S0601 +arc: C5 S1_V02N0201 +arc: D1 H02W0201 +arc: D5 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: S3_V06S0003 F0 +arc: V00B0100 F5 +arc: V01S0100 F0 +word: SLICEC.K1.INIT 1111111000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C42:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0601 H06E0303 +arc: V00T0000 E1_H02W0001 +arc: A0 S1_V02N0501 +arc: C0 H02E0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110101010 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R79C43:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: V00T0000 H02W0001 +arc: C0 H00L0000 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D5 H00R0100 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R79C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0301 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: A0 N1_V02S0701 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 F7 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H02E0501 +arc: B0 V02N0301 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 H02W0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 H02W0401 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 V02S0601 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111010111001100 +word: SLICEB.K1.INIT 0000100011001100 +word: SLICED.K0.INIT 0000101100001111 +word: SLICEB.K0.INIT 0100111100000000 +word: SLICEC.K1.INIT 1111000010100000 +word: SLICED.K1.INIT 1010001000100010 +word: SLICEC.K0.INIT 1111101000000000 +word: SLICEA.K1.INIT 0000011100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C45:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A2 V02N0701 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 H00R0000 +arc: B0 S1_V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: B6 F1 +arc: B7 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 F1 +arc: H01W0100 F5 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V02N0401 F6 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111101111001000 +word: SLICEC.K0.INIT 0000110000000000 +word: SLICED.K1.INIT 1100110011001000 +word: SLICED.K0.INIT 0000010100000001 +word: SLICEC.K1.INIT 0000011100000101 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 1100110001000000 +word: SLICEB.K1.INIT 1100110011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R79C46:PLC2 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0601 N1_V02S0301 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 H01E0001 +arc: A0 S1_V02N0701 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 W1_H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: V01S0000 Q2 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEA.K1.INIT 1010101011001010 +word: SLICEB.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C47:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0501 V02N0501 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0501 +arc: B0 N1_V02S0101 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1100111110001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C48:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: A3 H01E0001 +arc: D3 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: F3 F3_SLICE +arc: H01W0100 F3 +word: SLICEB.K1.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R79C49:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 H01E0101 +arc: A4 F7 +arc: A6 V00T0100 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C4 V02N0001 +arc: C6 F4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D4 S1_V02N0601 +arc: D6 F2 +arc: D7 V02S0401 +arc: E1_H01E0101 F2 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q7 +arc: LSR0 H02W0501 +arc: M0 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0501 Q7 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000000110011 +word: SLICEC.K0.INIT 1110000000100000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1100100011000000 +word: SLICEA.K1.INIT 1111000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C50:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02S0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00L0000 +arc: A1 V02N0501 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 V01N0001 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 H02W0101 +arc: C0 H00L0100 +arc: C1 V02N0601 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 V02S0201 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H02W0001 +arc: D3 N1_V01S0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F7 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +word: SLICEA.K0.INIT 1111101101000000 +word: SLICED.K1.INIT 0101010111111100 +word: SLICEB.K0.INIT 1100110011110101 +word: SLICEB.K1.INIT 1100101011000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +word: SLICED.K0.INIT 0010000000111111 +word: SLICEA.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C51:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0203 E1_H01W0000 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H01W0100 +arc: B1 H02W0101 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0501 +arc: C1 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 W1_H02E0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0601 F6 +arc: V00B0000 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 1111110100001101 +word: SLICEC.K1.INIT 1111100000001000 +word: SLICED.K0.INIT 0000000000100000 +word: SLICED.K1.INIT 0000000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C52:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 F5 +arc: A2 V02S0501 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 F1 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V00B0100 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H00R0000 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F2 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0100 F7 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: M5 H02E0001 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 0101111101011100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100010100000000 +word: SLICEB.K1.INIT 0001110100111111 +word: SLICED.K0.INIT 1110111001001110 +word: SLICED.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 0101111101011100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R79C53:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A1 N1_V02S0501 +arc: A2 V02N0501 +arc: A3 H02E0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 E1_H02W0501 +arc: A7 S1_V02N0101 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B2 H02W0101 +arc: B3 N1_V02S0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 N1_V02S0501 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: C6 F4 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: N3_V06N0103 F2 +arc: V01S0100 F3 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEB.K1.INIT 0000000010111000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0001101110111011 +word: SLICEC.K0.INIT 0000000001000000 +word: SLICEC.K1.INIT 0000000001010001 +word: SLICED.K0.INIT 0000101100110011 +word: SLICED.K1.INIT 0001110111011101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C54:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 N1_V02S0301 +arc: B0 H02W0101 +arc: B1 V01N0001 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 Q5 +arc: V00B0000 F4 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 1110111000000000 +word: SLICEB.K0.INIT 1010101011001111 +word: SLICEB.K1.INIT 1010101011000000 +word: SLICEA.K0.INIT 0000111011111110 +word: SLICEC.K0.INIT 1010110010101111 +word: SLICEC.K1.INIT 1010110010100000 +word: SLICED.K0.INIT 0000000001000000 +word: SLICED.K1.INIT 0000000000110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C55:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V02N0701 +arc: A2 E1_H01E0001 +arc: A3 H02E0701 +arc: A6 H02E0501 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B6 H02E0301 +arc: C0 E1_H02W0401 +arc: C2 H02E0401 +arc: C3 H00R0100 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 W1_H02E0001 +arc: D3 V00B0100 +arc: D6 H02W0201 +arc: E1_H01E0001 Q4 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 Q6 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K0.INIT 0011010111110101 +word: SLICEB.K1.INIT 1101110100001101 +word: SLICEB.K0.INIT 0000011101110111 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R79C56:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 V06S0003 +arc: A0 F5 +arc: A1 F5 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 N1_V01S0100 +arc: A6 F7 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B6 H02E0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0201 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0100 F7 +arc: LSR0 V00B0100 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 F6 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 F7 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 Q6 +arc: V00T0000 F0 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000000000110001 +word: SLICED.K0.INIT 0000100000111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R79C57:PLC2 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: A2 H01E0001 +arc: A5 E1_H01W0000 +arc: B2 H02W0301 +arc: C2 V02N0401 +arc: C5 H02W0601 +arc: D2 S1_V02N0201 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000100000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R79C58:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 V02S0601 +arc: A0 H01E0001 +arc: A1 F5 +arc: A5 V00T0000 +arc: B1 Q1 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: C0 H00L0000 +arc: C5 V01N0101 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D5 H00R0100 +arc: D6 V02S0601 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101111101010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 0100000001011111 +word: SLICEA.K1.INIT 0101010111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C59:PLC2 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 W3_H06E0103 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B6 H02E0301 +arc: C0 F6 +arc: C6 V02N0201 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H00L0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 F7 +word: SLICED.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 0000100000111111 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C60:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0701 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C61:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 V01N0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: V00T0000 H02W0201 +arc: A0 E1_H01E0001 +arc: B2 V01N0001 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V02S0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 1100111100000000 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C62:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 N1_V02S0001 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 V02N0601 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: C0 V02N0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q5 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 Q4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q5 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEC.K0.INIT 1010110010101100 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C63:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: A0 H00R0000 +arc: A2 H02E0501 +arc: A4 V00T0000 +arc: B3 S1_V02N0301 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C64:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: A4 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V00T0000 +arc: B2 W1_H02E0301 +arc: B3 H00L0000 +arc: B5 W1_H02E0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C65:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0001 +arc: V00T0000 H02E0201 +arc: A0 W1_H02E0701 +arc: A3 V00B0000 +arc: A7 H00L0000 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 W1_H02E0301 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C66:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 V02N0201 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 W1_H02E0701 +arc: A3 V00B0000 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: B0 H02E0301 +arc: B2 V02S0101 +arc: B6 V00T0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0101010101010000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06S0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: A4 N1_V02S0101 +arc: A7 V02S0101 +arc: B2 V02N0101 +arc: B4 V00B0100 +arc: B7 H02W0101 +arc: C2 H02E0401 +arc: C4 E1_H02W0401 +arc: C7 H02E0601 +arc: D2 V02N0201 +arc: D4 S1_V02N0401 +arc: D7 H02W0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V02N0201 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R79C68:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02N0701 +arc: A4 V02S0101 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B5 H02W0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C69:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 H02E0401 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 W3_H06E0203 +arc: A3 V02S0701 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 V02S0101 +arc: B5 H00R0000 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C70:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: V00B0000 H02E0401 +arc: A2 H02E0701 +arc: A4 V02S0301 +arc: A7 V02S0101 +arc: B0 V00B0000 +arc: B1 H02E0301 +arc: B3 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C71:PLC2 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 V02S0601 +arc: S3_V06S0003 H06W0003 +arc: V00T0000 N1_V02S0601 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: B0 V02S0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B4 V02S0701 +arc: B7 N1_V02S0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C72:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0103 N1_V01S0100 +arc: F0 F0_SLICE +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R79C73:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 H02W0701 +arc: A0 V02S0501 +arc: B0 V00T0000 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110010101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C74:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A6 H00R0000 +arc: B1 H01W0100 +arc: B3 H01W0100 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: D0 H00R0000 +arc: D1 S1_V02N0201 +arc: D2 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D6 V00B0000 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0101000001010101 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0101000001010101 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0011000000110011 +word: SLICEC.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 0000101000000000 +word: SLICED.K1.INIT 0000110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C75:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0003 W1_H02E0001 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: A5 V02N0101 +arc: B1 Q1 +arc: B5 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V01S0100 +arc: E1_H01E0001 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R79C76:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0601 W3_H06E0303 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R79C77:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H06W0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0003 H06E0003 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H01E0001 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A7 F5 +arc: B0 N1_V02S0301 +arc: B1 F3 +arc: B2 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02S0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 V00T0000 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F7 +arc: V01S0000 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEB.K1.INIT 0101000000000000 +word: SLICEB.K0.INIT 0010100000111100 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 0000100000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R79C78:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 V02S0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H01E0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02N0701 +arc: A3 H02W0501 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: B1 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: C1 H02W0401 +arc: C3 H00L0000 +arc: C5 H02E0601 +arc: C6 V02S0201 +arc: D1 E1_H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 F0 +arc: D6 V02N0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F2 +arc: M0 V00T0100 +arc: M2 E1_H02W0601 +arc: S1_V02S0601 F4 +arc: S3_V06S0303 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEC.K0.INIT 1100110000110011 +word: SLICED.K0.INIT 1010101000000010 +word: SLICEC.K1.INIT 1010010100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C79:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 E1_H02W0701 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H02E0101 +arc: B6 W1_H02E0301 +arc: B7 V02N0701 +arc: F2 F2_SLICE +arc: W1_H02W0001 F2 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C80:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H02E0701 +arc: A3 H02W0501 +arc: A4 V00T0000 +arc: A5 E1_H02W0501 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R79C81:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 V01N0101 +arc: A0 E1_H02W0701 +arc: A1 W1_H02E0501 +arc: A4 E1_H02W0501 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 V00T0000 +arc: B4 H02E0101 +arc: B7 V00B0000 +arc: C4 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 W1_H02E0401 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M4 E1_H01E0101 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: V00B0000 F4 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 1000010010100101 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1000010000000000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R79C82:PLC2 +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0501 H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 V01N0001 +arc: W3_H06W0303 V01N0101 +arc: A1 V01N0101 +arc: B1 S1_V02N0101 +arc: B7 H02E0101 +arc: C1 V02N0401 +arc: C7 V01N0101 +arc: D1 S1_V02N0001 +arc: E1_H02E0501 F7 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: W1_H02W0201 F0 +word: SLICED.K1.INIT 0000001100000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R79C83:PLC2 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0501 S1_V02N0401 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: B2 H00R0000 +arc: C2 W1_H02E0401 +arc: D2 V02N0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: S3_V06S0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C101:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R7C104:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R7C107:PLC2 +arc: S3_V06S0303 W3_H06E0303 + +.tile R7C11:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R7C17:PLC2 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: S3_V06S0303 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R7C23:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R7C29:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R7C35:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C39:PLC2 +arc: E1_H02E0201 E1_H01W0000 + +.tile R7C40:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06W0203 +arc: V00B0100 V02S0101 +arc: A0 H02W0701 +arc: A1 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 E1_H01W0000 +arc: A7 Q7 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H01W0100 +arc: B4 V01S0000 +arc: B6 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H02W0201 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1000100010111000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C41:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A2 H02W0501 +arc: A4 V02N0301 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C6 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: S1_V02S0501 Q7 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C42:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 V02S0301 +arc: A7 N1_V01N0101 +arc: B0 H00R0100 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 V02S0701 +arc: C0 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 Q5 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011111000010100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C43:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0203 S3_V06N0203 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V01S0100 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C44:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 E1_H01W0000 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 H02E0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02W0501 +arc: A6 V02S0101 +arc: B0 V00T0000 +arc: B2 H01W0100 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V01N0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0701 Q7 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C45:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0100 E1_H02W0701 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 H02W0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 H02E0301 +arc: B6 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C5 V00B0100 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C46:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S3_V06N0203 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02W0701 +arc: A2 V02S0501 +arc: A4 V00T0000 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0100 F4 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1100010111000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C47:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 N1_V01N0101 +arc: A6 E1_H02W0701 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H01W0100 +arc: B4 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 H02W0401 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q1 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: W1_H02W0301 Q1 +word: SLICEB.K0.INIT 1011111000010100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1110111001000100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C48:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V00T0100 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 E1_H01W0100 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q1 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1100110000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C49:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0100 +arc: A2 H02E0501 +arc: A3 V02S0501 +arc: A6 E1_H01W0000 +arc: B0 H02W0101 +arc: B2 H02E0301 +arc: B4 V00B0100 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: M5 V01S0000 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 1101000111100010 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011101000010000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C4:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R7C50:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A6 H02W0701 +arc: B0 H02E0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 H00L0000 +arc: B6 V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V02S0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C51:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: B0 E1_H01W0100 +arc: B2 S1_V02N0301 +arc: C0 H00R0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010111000000100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C52:PLC2 +arc: H00L0000 S1_V02N0001 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: A0 H02E0701 +arc: A1 E1_H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00B0000 +arc: A5 V00T0100 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 H00L0000 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0201 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q1 +arc: H01W0100 F2 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0501 Q5 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000001000100 +word: SLICEC.K0.INIT 1000110111011000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100000011001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C53:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 + +.tile R7C59:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R7C5:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R7C62:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R7C65:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R7C68:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R7C71:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C77:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C83:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R7C89:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R7C95:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R80C102:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C105:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R80C108:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C111:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R80C114:PLC2 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C17:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R80C33:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R80C37:PLC2 +arc: S1_V02S0701 S3_V06N0203 +arc: V01S0000 S3_V06N0103 + +.tile R80C38:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02N0401 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H06W0203 +arc: V00T0100 V02N0701 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 V02N0001 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0101 F4 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: V00B0000 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C39:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02W0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V01N0101 +arc: A5 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0401 +arc: C5 H02E0601 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q7 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +arc: V00B0000 Q6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C40:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A3 V01N0101 +arc: A4 H02W0701 +arc: A6 H00L0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B4 H02W0301 +arc: B6 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C4 H02E0601 +arc: C6 E1_H02W0401 +arc: D0 V01S0100 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F4 +arc: S3_V06S0003 F3 +arc: V01S0000 F0 +arc: V01S0100 F1 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0010000000000000 +word: SLICEA.K0.INIT 1011001100000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000011100000 +word: SLICEB.K1.INIT 0000000001000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R80C41:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 H06E0203 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 N1_V01S0100 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 H00L0100 +arc: A1 V01N0101 +arc: A4 H02E0501 +arc: B4 V02N0701 +arc: C0 H02W0601 +arc: C4 F6 +arc: C5 V00T0100 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0701 Q5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q5 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0100 F0 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0001000000000000 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111111111010 +word: SLICEA.K1.INIT 1111111101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R80C42:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00L0000 V02N0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B2 H02E0101 +arc: B5 S1_V02N0501 +arc: B6 S1_V02N0501 +arc: C0 F6 +arc: C3 H02E0401 +arc: C5 V02N0001 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 F2 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F5 +arc: V01S0100 F3 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 1000110000001100 +word: SLICEA.K0.INIT 1111000011111100 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R80C43:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0001 +arc: A1 W1_H02E0701 +arc: A5 V02N0301 +arc: B3 V02N0301 +arc: C1 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0100 F0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110000001100 +word: SLICEC.K1.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R80C44:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0401 +arc: A0 V02N0701 +arc: A2 F5 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0301 +arc: B0 V00T0000 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H00L0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 V02N0601 +arc: C4 N1_V02S0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0001 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 N1_V02S0601 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: V01S0000 F4 +word: SLICEA.K0.INIT 1111110110101000 +word: SLICEC.K1.INIT 1111110000000000 +word: SLICEB.K1.INIT 0000101100001111 +word: SLICEB.K0.INIT 0111001100000000 +word: SLICEC.K0.INIT 0001000100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C45:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 N1_V02S0401 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 F5 +arc: A5 N1_V02S0301 +arc: B1 V00T0000 +arc: C1 H02E0401 +arc: C5 N1_V02S0001 +arc: D1 V01S0100 +arc: D5 H02W0201 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0001 F1 +word: SLICEC.K1.INIT 1010000010101010 +word: SLICEA.K1.INIT 1111000000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C46:PLC2 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 E3_H06W0303 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V06S0003 +arc: A0 V02N0501 +arc: B0 H02E0301 +arc: C0 H02W0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0100 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0103 F2 +arc: S3_V06S0103 F2 +word: SLICEA.K0.INIT 1110111101000000 +word: SLICEB.K0.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R80C47:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 V02N0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0601 V06S0303 +arc: A0 N1_V02S0701 +arc: B0 H02W0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111101100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C48:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 N3_V06S0303 +arc: A4 S1_V02N0101 +arc: A5 V00T0100 +arc: A6 F5 +arc: A7 F5 +arc: B0 V01N0001 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B7 S1_V02N0501 +arc: C0 E1_H02W0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V00T0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 H02W0001 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: N3_V06N0203 Q4 +arc: V00B0100 F7 +arc: V00T0100 Q3 +arc: V01S0000 Q0 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICED.K0.INIT 1010000010101111 +word: SLICEC.K0.INIT 1010000011000000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1100100011000000 +word: SLICEB.K1.INIT 1111111100001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C49:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 V02N0401 +arc: A1 F5 +arc: A3 H02W0701 +arc: A4 F7 +arc: A5 E1_H01W0000 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 E1_H02W0301 +arc: B2 V02N0101 +arc: B3 F1 +arc: B4 H02E0301 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C2 H02W0401 +arc: C3 H00L0100 +arc: C4 V02S0001 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 F2 +arc: D5 N1_V02S0401 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +word: SLICED.K0.INIT 1010000010101111 +word: SLICED.K1.INIT 1100101000000000 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1100100010001000 +word: SLICEC.K1.INIT 1010101000001111 +word: SLICEA.K1.INIT 1100101000000000 +word: SLICEB.K1.INIT 1110000011000000 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C50:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0501 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 H01E0001 +arc: A4 V02N0301 +arc: A5 N1_V02S0301 +arc: A7 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 H02W0301 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 E1_H02W0101 +arc: C1 N1_V02S0401 +arc: C3 N1_V02S0401 +arc: C4 H02E0401 +arc: C5 N1_V02S0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q7 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00R0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 Q7 +arc: S3_V06S0203 Q7 +arc: V00T0000 F2 +arc: V01S0000 F0 +arc: V01S0100 Q7 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111010101110 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100001100 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 0001000111010101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C51:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: A3 H02E0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B3 H02E0301 +arc: B4 N1_V02S0701 +arc: B5 H01E0101 +arc: B6 V00T0000 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C4 E1_H02W0601 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M5 H02W0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N3_V06N0103 Q1 +arc: N3_V06N0303 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 Q5 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0010011110101111 +word: SLICEC.K0.INIT 0010011110101111 +word: SLICED.K0.INIT 0001101110111011 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R80C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02W0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0303 E3_H06W0303 +arc: A3 V02S0501 +arc: A4 E1_H01W0000 +arc: A5 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 H00L0000 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V02S0401 +arc: C3 V02S0601 +arc: C4 V00T0000 +arc: C5 H02E0401 +arc: C6 V00T0100 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 H02W0001 +arc: D4 H01W0000 +arc: D5 V02N0601 +arc: D6 F2 +arc: D7 H00R0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 Q1 +arc: S1_V02S0301 F3 +arc: V00B0000 F6 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 0100110001111111 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100010100000000 +word: SLICED.K0.INIT 0001001111011111 +word: SLICED.K1.INIT 1111001110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R80C53:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 H02E0701 +arc: A7 H00R0000 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 V02S0301 +arc: B5 S1_V02N0501 +arc: B6 F1 +arc: B7 W1_H02E0101 +arc: C0 E1_H01W0000 +arc: C1 H02W0601 +arc: C2 H02E0601 +arc: C3 V02N0401 +arc: C5 H01E0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 V02S0401 +arc: D7 H00R0100 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F6 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1010110000000000 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K1.INIT 0011001111111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R80C54:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H02W0601 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 S1_V02N0301 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H02W0101 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 S1_V02N0401 +arc: C1 V02S0601 +arc: C3 V02N0401 +arc: C4 W1_H02E0401 +arc: C5 V01N0101 +arc: C6 F4 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 F6 +arc: V01S0000 Q1 +word: SLICED.K1.INIT 1010100000001000 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1000110010101111 +word: SLICED.K0.INIT 0111011101110100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R80C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 V02N0501 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A5 W1_H02E0501 +arc: A6 V02S0101 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B3 E1_H01W0100 +arc: B6 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C3 V02N0401 +arc: C5 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D4 V02S0601 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 F2 +arc: N1_V02N0601 F4 +arc: S3_V06S0103 F1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000100001000100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R80C56:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V01N0101 +arc: A7 H02W0701 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H00R0100 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 F4 +arc: C3 H02W0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0000 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 H01E0101 +arc: D4 V02N0601 +arc: D5 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0010101001111111 +word: SLICEB.K0.INIT 1010001011110011 +word: SLICEB.K1.INIT 0101111101011100 +word: SLICEA.K1.INIT 0101111101011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 N3_V06S0303 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 W1_H02E0501 +arc: A7 H02W0701 +arc: B1 W1_H02E0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q3 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q5 +arc: H01W0100 F0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M2 W1_H02E0601 +arc: M3 H01W0100 +arc: M4 E1_H01E0101 +arc: M5 H00L0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F6 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q5 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0001000110110011 +word: SLICEB.K0.INIT 1111101100001011 +word: SLICEB.K1.INIT 1111100000001000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010000000101 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H01E0001 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 H02E0501 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V01S0100 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02S0601 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F4 +arc: S3_V06S0303 Q5 +arc: V00B0100 F7 +arc: V00T0100 F1 +arc: V01S0000 Q5 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0101010111110000 +word: SLICED.K1.INIT 0011010111110101 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEA.K1.INIT 0101111101011100 +word: SLICEB.K0.INIT 1010101011110011 +word: SLICEB.K1.INIT 1010101011000000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010000000101 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C59:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0003 H06E0003 +arc: V00T0000 V02N0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A3 S1_V02N0701 +arc: A6 W1_H02E0501 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B3 H02E0101 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C3 H00L0100 +arc: C6 V02N0001 +arc: C7 W1_H02E0401 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D3 W1_H02E0201 +arc: D6 V02N0401 +arc: D7 H02W0201 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: N1_V02N0201 F0 +arc: N3_V06N0003 F3 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K1.INIT 1111110000000000 +word: SLICED.K0.INIT 1100101000000000 +word: SLICEA.K0.INIT 0000010000000000 +word: SLICEA.K1.INIT 0000010000000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R80C60:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 + +.tile R80C61:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0203 E1_H01W0000 +arc: A0 H02E0701 +arc: B0 V02N0101 +arc: B2 V02N0101 +arc: C0 V02N0601 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEB.K0.INIT 1100111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R80C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A3 E1_H02W0501 +arc: B1 Q1 +arc: B3 H00R0100 +arc: C0 N1_V01N0001 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D3 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q1 +arc: LSR1 V00B0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1110111001000100 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R80C63:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: A0 H00L0000 +arc: A1 H02W0701 +arc: A5 V00B0000 +arc: A6 H02W0701 +arc: B1 S1_V02N0301 +arc: B3 F1 +arc: B5 F3 +arc: B6 H02W0301 +arc: C0 V02S0601 +arc: C1 H00L0100 +arc: C3 V02N0601 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: D6 E1_H02W0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: V00B0000 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEB.K1.INIT 1100000000001100 +word: SLICED.K0.INIT 1111010100110001 +word: SLICEC.K1.INIT 1000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R80C64:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 E1_H02W0701 +arc: A5 H02W0701 +arc: A6 S1_V02N0101 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0601 +arc: C6 V00B0100 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +arc: V00T0100 F3 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C65:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A1 H02W0501 +arc: A2 N1_V02S0701 +arc: A4 V00B0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0101 +arc: A7 N1_V02S0301 +arc: B0 E1_H01W0100 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B7 H02E0301 +arc: C0 H02E0601 +arc: C1 F6 +arc: C2 H02E0401 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V02N0201 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0101 F7 +arc: S1_V02S0601 F4 +arc: V00B0000 F6 +arc: V01S0100 F1 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1000110010101111 +word: SLICEB.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 0000000010100000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1000010000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R80C66:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: A0 W1_H02E0501 +arc: A1 V01N0101 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 F5 +arc: A5 V02S0101 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 N1_V02S0301 +arc: B5 N1_V02S0501 +arc: B6 H02E0101 +arc: B7 S1_V02N0501 +arc: C0 H02W0401 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02S0001 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0201 +arc: D6 V01N0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: W1_H02W0401 F4 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 1000001000000000 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICEB.K1.INIT 1011101100001011 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C67:PLC2 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V06S0203 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 F5 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0301 +arc: B3 S1_V02N0101 +arc: B4 H01E0101 +arc: B5 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 F3 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 N1_V02S0601 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 N1_V02S0001 +arc: C6 N1_V02S0201 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0000 F7 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K0.INIT 1111001101010001 +word: SLICEB.K1.INIT 1010111100100011 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000000000001000 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 N1_V01S0100 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H01E0001 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: B0 V01N0001 +arc: B4 V02N0501 +arc: C0 V02S0601 +arc: C3 S1_V02N0601 +arc: C4 H02W0601 +arc: D0 V02N0001 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0100 F4 +arc: W1_H02W0101 F3 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1001000000001001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R80C69:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 H01E0001 + +.tile R80C70:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0601 H06W0303 + +.tile R80C71:PLC2 +arc: E1_H02E0301 V06N0003 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H02W0201 +arc: C7 H02E0601 +arc: D7 H02W0201 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R80C72:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0103 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: B5 H02E0301 +arc: C5 W1_H02E0401 +arc: D5 V02N0601 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEC.K1.INIT 1111111100110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R80C73:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00L0100 +arc: B0 V02N0301 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1110111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C74:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H00L0000 +arc: A4 F5 +arc: A5 N1_V02S0101 +arc: B1 E1_H02W0301 +arc: B4 V00B0100 +arc: B5 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: C1 H02E0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D4 E1_H01W0100 +arc: D5 H02W0201 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F4 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R80C75:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: W1_H02W0201 E1_H02W0701 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 E1_H01E0001 +arc: A4 V02S0301 +arc: A6 H00L0000 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 E1_H01W0100 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C6 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0100 F6 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1110111100100000 +word: SLICEA.K1.INIT 1010101011100010 +word: SLICEB.K0.INIT 1011101010001010 +word: SLICEB.K1.INIT 1010101011100010 +word: SLICEC.K0.INIT 1100101011001100 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R80C76:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 H01E0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 N1_V01S0100 +arc: A3 V02S0701 +arc: A4 H02W0701 +arc: B0 E1_H02W0301 +arc: B2 N1_V02S0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 H02W0301 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: B0 V02S0101 +arc: B1 H02E0301 +arc: B4 W1_H02E0301 +arc: B5 H00L0000 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C78:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0301 V06N0003 +arc: A0 H02E0701 +arc: A6 H00R0000 +arc: B1 V00B0000 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D6 H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F2 +arc: LSR1 E1_H02W0501 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 Q6 +arc: V01S0100 Q6 +word: SLICED.K0.INIT 0000111110101010 +word: SLICED.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R80C79:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E3_H06E0303 V06N0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V06S0203 +arc: A0 V02N0501 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: B2 S1_V02N0101 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B7 W1_H02E0101 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C80:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0303 H01E0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0501 W1_H02E0501 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 V06N0303 +arc: A0 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 H02W0701 +arc: A6 N1_V02S0301 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 H02W0301 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N3_V06N0103 F2 +arc: V01S0000 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R80C81:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 W1_H02E0701 +arc: A6 H00L0000 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 H02E0601 +arc: C6 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR1 H02E0501 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 Q4 +arc: S1_V02S0101 Q3 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 1100001101000001 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100111101000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R80C82:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V01N0101 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D5 H02E0201 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q3 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R80C83:PLC2 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 H06E0303 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V02N0001 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R80C84:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C87:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R80C90:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C96:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R80C99:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R81C100:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C101:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C103:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C104:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R81C106:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C107:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R81C110:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R81C2:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R81C35:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 S3_V06N0103 + +.tile R81C36:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: A4 H02W0701 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B5 H00R0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C37:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H02W0501 +arc: A2 E1_H02W0701 +arc: B1 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0101 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C38:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0401 E1_H02W0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 V02S0701 +arc: A5 Q5 +arc: A7 S1_V02N0301 +arc: B1 V02S0301 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q6 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101010101010000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C39:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02W0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0701 E1_H02W0601 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0101 +arc: B6 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C40:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 E1_H02W0501 +arc: A2 H00L0100 +arc: A7 V02S0101 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 V02N0501 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 F6 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N3_V06N0003 Q3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000100000000000 +word: SLICEA.K0.INIT 1111000000001100 +word: SLICEA.K1.INIT 0000111111000000 +word: SLICEB.K0.INIT 0100111110000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C41:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02W0201 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02E0701 +arc: A1 H02W0701 +arc: A2 H01E0001 +arc: A5 V00T0000 +arc: A7 H00R0000 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C5 H01E0001 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0601 F4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000011100001111 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1110110011111100 +word: SLICEA.K1.INIT 1111101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C42:PLC2 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0303 N1_V01S0100 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0401 V02N0401 +arc: A0 V02S0501 +arc: A1 H00R0000 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A5 V02S0301 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H00R0100 +arc: C5 V02S0201 +arc: C6 W1_H02E0601 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F7 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111111110100000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000011110000 +word: SLICEB.K0.INIT 0000000100000000 +word: SLICEB.K1.INIT 0000010100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R81C43:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: B0 W1_H02E0301 +arc: C0 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C44:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0103 +arc: B0 H02E0301 +arc: C0 S1_V02N0401 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: N3_V06N0003 F0 +arc: S1_V02S0001 F0 +word: SLICEA.K0.INIT 1100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R81C45:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 + +.tile R81C46:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S3_V06S0303 N3_V06S0203 + +.tile R81C47:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 F3 +arc: B5 F3 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V02S0001 +arc: D2 N1_V02S0201 +arc: D3 E1_H02W0001 +arc: D4 V02S0601 +arc: D5 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: S3_V06S0103 Q2 +arc: V00T0100 F3 +word: SLICEA.K0.INIT 1111001011010000 +word: SLICEA.K1.INIT 1111001011010000 +word: SLICEB.K0.INIT 1111001011010000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010101011001111 +word: SLICEC.K1.INIT 1010101011000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C48:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 H02W0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 E1_H02W0701 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B3 E1_H02W0301 +arc: B6 S1_V02N0701 +arc: B7 H02E0301 +arc: C0 N1_V02S0601 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 H02E0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D3 S1_V02N0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F5 +arc: V01S0100 Q0 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011001111111010 +word: SLICEA.K1.INIT 0000001110110011 +word: SLICED.K0.INIT 1111101000111010 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R81C49:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0701 +arc: A7 V02N0301 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 S1_V02N0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 V02N0401 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 Q1 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 F4 +word: SLICEC.K1.INIT 0101111101011100 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICED.K0.INIT 1010111100100011 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0000111111001100 +word: SLICEC.K0.INIT 0000111011111110 +word: SLICEB.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C50:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0000 H02W0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0501 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 V02S0101 +arc: A7 V02S0101 +arc: B1 Q1 +arc: B3 H02W0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C0 V02S0601 +arc: C1 H02W0601 +arc: C2 N1_V01S0100 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 W1_H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D3 V02N0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: M2 H02E0601 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: V00B0000 F4 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1110111101000101 +word: SLICEC.K1.INIT 1110101001000000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C51:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 H01E0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02S0701 +arc: A1 V02S0501 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 F7 +arc: A6 V02N0301 +arc: A7 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 H02E0101 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 N1_V02S0601 +arc: C1 H02E0401 +arc: C3 V02N0601 +arc: C4 V00B0100 +arc: C5 V02S0001 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 N1_V01S0000 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00B0100 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011001100 +word: SLICEC.K1.INIT 0100011101110111 +word: SLICEC.K0.INIT 1110111001001110 +word: SLICED.K0.INIT 1111010100110001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 Q7 +arc: B1 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 V02N0701 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 H00L0100 +arc: C5 V00T0100 +arc: C6 Q6 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q5 +arc: S1_V02S0701 Q5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +word: SLICEA.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C53:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E3_H06W0103 +arc: A3 H01E0001 +arc: A5 N1_V01N0101 +arc: A6 N1_V01S0100 +arc: A7 S1_V02N0301 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B5 H02W0301 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 H00L0100 +arc: C2 V02S0401 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q5 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: M4 V00T0000 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N3_V06N0303 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K1.INIT 1111001101010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C54:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 S1_V02N0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A5 S1_V02N0101 +arc: A6 W1_H02E0701 +arc: B0 H01W0100 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 S1_V02N0601 +arc: C3 V02N0601 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D6 S1_V02N0601 +arc: D7 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q1 +arc: N1_V02N0701 Q7 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 Q6 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 F3 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 0000000010101100 +word: SLICED.K0.INIT 1100000010100000 +word: SLICED.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C55:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 F7 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 V00B0000 +arc: A6 V00T0100 +arc: A7 F5 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: C5 H02W0601 +arc: C6 S1_V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: D5 V02N0401 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: V00B0000 F4 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +word: SLICEA.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1000000010001100 +word: SLICED.K0.INIT 0011010100111111 +word: SLICED.K1.INIT 1010111111001100 +word: SLICEA.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C56:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 E1_H02W0701 +arc: A4 F7 +arc: A6 V02N0301 +arc: A7 V02S0301 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B5 H01E0101 +arc: B6 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C2 N1_V02S0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 E1_H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 S1_V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D6 E1_H01W0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V02N0201 F2 +arc: V01S0100 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0101001111110011 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEA.K1.INIT 0011001011111110 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 0000010111010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C57:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0001 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V06S0203 +arc: A1 H02W0501 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 W1_H02E0101 +arc: B3 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: D1 V02S0201 +arc: D2 N1_V01S0000 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F6 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: S1_V02S0301 F1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101001010000 +word: SLICEC.K0.INIT 1010111110100011 +word: SLICEC.K1.INIT 1010110010100000 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C58:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V02S0701 +arc: A1 H00L0100 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A7 V02N0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 S1_V02N0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 S1_V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F6 +arc: S1_V02S0601 F4 +arc: V01S0000 F2 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101011110011 +word: SLICEC.K1.INIT 1010101011000000 +word: SLICED.K1.INIT 0000110101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C59:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 H02W0001 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 N1_V02S0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H01E0001 +arc: A4 E1_H01W0000 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 V02N0301 +arc: B5 S1_V02N0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 N1_V01N0001 +arc: C2 S1_V02N0401 +arc: C3 H02E0601 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 Q1 +arc: S3_V06S0203 F4 +arc: V00B0100 F5 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000111111101110 +word: SLICED.K0.INIT 1110111101000101 +word: SLICED.K1.INIT 1110101001000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0111011101000100 +word: SLICEA.K1.INIT 0011001111110000 +word: SLICEB.K0.INIT 0011111100001100 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C60:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A4 N1_V02S0301 +arc: B0 H02E0301 +arc: B4 W1_H02E0101 +arc: C0 F4 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +word: SLICEC.K0.INIT 0000101100110011 +word: SLICEA.K0.INIT 0011111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C61:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0701 S1_V02N0701 +arc: B0 H02E0101 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C62:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 E1_H01E0001 +arc: A4 H02W0501 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 S1_V02N0701 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: D4 N1_V02S0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0401 F4 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0003 Q0 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1101000000001101 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R81C63:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 N1_V02S0701 +arc: A1 H02W0501 +arc: A3 V00B0000 +arc: A4 E1_H01W0000 +arc: A5 N1_V02S0101 +arc: A7 N1_V02S0301 +arc: B0 S1_V02N0101 +arc: B2 V02N0101 +arc: B5 N1_V02S0501 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V02S0401 +arc: C4 E1_H02W0601 +arc: C5 V02N0201 +arc: C7 H02W0601 +arc: D0 V00B0100 +arc: D1 S1_V02N0201 +arc: D2 H02W0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 S1_V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEC.K1.INIT 1100010011110101 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEB.K1.INIT 0000000010100000 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C64:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 V00T0000 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 S1_V02N0101 +arc: B5 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 H02E0401 +arc: C4 N1_V02S0201 +arc: C5 F6 +arc: C6 N1_V02S0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 H02W0201 +arc: D6 S1_V02N0401 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: S1_V02S0101 F3 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 1011101100001011 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 0101000000000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICEA.K1.INIT 1111111111101010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C65:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A4 V00T0000 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 W1_H02E0101 +arc: B4 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 N1_V02S0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02S0201 +arc: D4 H02W0201 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V01S0000 F7 +arc: W1_H02W0201 F2 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 1011000000001011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111011111010 +word: SLICEA.K1.INIT 1111111111111000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 1000001011000011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R81C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06E0303 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 S3_V06N0203 +arc: A0 F7 +arc: A2 V02N0701 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 E1_H01W0000 +arc: A7 S1_V02N0101 +arc: B0 H02W0301 +arc: B1 V02S0301 +arc: B2 E1_H02W0301 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0301 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0601 +arc: D6 S1_V02N0601 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F3 +arc: V00B0000 F4 +arc: V00T0100 F1 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1111001101010001 +word: SLICEC.K0.INIT 1001000000001001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R81C67:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 H00L0100 +arc: A4 S1_V02N0101 +arc: A6 V00T0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B4 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: C0 N1_V02S0601 +arc: C1 F4 +arc: C2 V02S0401 +arc: C4 E1_H02W0401 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D4 V02N0401 +arc: D5 E1_H01W0100 +arc: D6 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: LSR1 V00B0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEA.K1.INIT 1111111011111010 +word: SLICED.K0.INIT 1001000000001001 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 1000010010100101 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C68:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICEB.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R81C69:PLC2 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 S1_V02N0601 + +.tile R81C70:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: S1_V02S0701 E3_H06W0203 + +.tile R81C71:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0100 E1_H02W0501 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0100 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 H00R0100 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: F0 F5A_SLICE +arc: M0 V00T0100 +arc: S3_V06S0003 F0 +word: SLICEA.K0.INIT 1010000010001000 +word: SLICEA.K1.INIT 1010000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R81C72:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02W0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0601 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: A7 E1_H01W0000 +arc: B5 H02E0101 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 1100001111110000 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 1100001110100101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C73:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A3 E1_H01E0001 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C7 V02S0201 +arc: D1 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D6 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E3_H06E0103 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: S1_V02S0601 F6 +arc: S3_V06S0103 F1 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F7 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0011001100110011 +word: SLICEB.K1.INIT 1100100100111001 +word: SLICEA.K0.INIT 0011001100110011 +word: SLICEA.K1.INIT 1100110000111100 +word: SLICED.K1.INIT 1100000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C74:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00B0000 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 V00B0100 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00T0000 +arc: M4 E1_H01E0101 +arc: M5 H02W0001 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F2 +arc: S3_V06S0303 F5 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010101011001010 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101000101010000 +word: SLICEC.K1.INIT 0101000101010000 +word: SLICED.K0.INIT 0101000101010101 +word: SLICED.K1.INIT 0101000101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R81C75:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V06S0003 +arc: A3 V02N0501 +arc: A5 V02N0301 +arc: A7 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011000000110011 +word: SLICEB.K1.INIT 0001000000110011 +word: SLICEC.K0.INIT 0011001100000011 +word: SLICEC.K1.INIT 0001001100000011 +word: SLICED.K1.INIT 0000000000000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R81C76:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 S1_V02N0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0103 H06E0103 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A1 V02N0501 +arc: A6 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: M0 H01E0001 +word: SLICED.K0.INIT 0101010100000000 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEA.K1.INIT 0001000100110001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R81C77:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0301 V06S0003 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 F7 +arc: A1 W1_H02E0701 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 S1_V02N0401 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 S1_V02N0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 1100000000110000 +word: SLICED.K0.INIT 0000100000000100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000111100000000 +word: SLICEC.K0.INIT 0000010101010101 +word: SLICEC.K1.INIT 0100010101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R81C78:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A2 S1_V02N0701 +arc: A4 W1_H02E0501 +arc: A6 N1_V02S0301 +arc: B3 V02S0101 +arc: B5 W1_H02E0301 +arc: B7 H02W0301 +arc: E1_H01E0101 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: S1_V02S0701 F7 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C79:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 E1_H01W0000 +arc: B0 V02S0101 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 H00R0000 +arc: B6 V02S0701 +arc: B7 H02E0301 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F4 +arc: S1_V02S0701 F7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C80:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 W3_H06E0003 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 H01E0101 +arc: A4 H02E0501 +arc: A5 E1_H01W0000 +arc: A6 H02W0501 +arc: A7 Q7 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 Q6 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0401 Q4 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q5 +arc: W1_H02W0001 F0 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICEC.K0.INIT 0101101001011010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C81:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N1_V01S0100 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 S1_V02N0701 +arc: A2 W1_H02E0501 +arc: A4 H02E0701 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B3 H02E0101 +arc: B5 H01E0101 +arc: E1_H01E0001 F7 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C82:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A2 V00B0000 +arc: A3 N1_V02S0501 +arc: A5 V02S0301 +arc: A6 N1_V01S0100 +arc: B4 H02E0101 +arc: B7 H02E0301 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F6 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R81C83:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0103 H06E0103 +arc: V00B0100 H02E0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D4 H01W0000 +arc: D5 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: V00B0000 Q4 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R81C86:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R81C89:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C91:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C92:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R81C94:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R81C95:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R81C98:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R83C100:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C101:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C102:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C103:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 + +.tile R83C104:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C105:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R83C106:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C107:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R83C108:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C109:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 + +.tile R83C110:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R83C111:PLC2 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 H06E0203 + +.tile R83C112:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C114:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C115:PLC2 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R83C117:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C118:PLC2 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C14:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R83C15:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R83C20:PLC2 +arc: N3_V06N0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R83C21:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R83C26:PLC2 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R83C32:PLC2 +arc: C5 V02N0001 +arc: D5 H02W0201 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +arc: S3_V06S0303 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1111000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R83C33:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: W1_H02W0201 V06S0103 + +.tile R83C34:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: A0 H00L0000 +arc: B0 E1_H02W0101 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0111010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C35:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0401 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A5 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B5 E1_H02W0301 +arc: C0 V02N0401 +arc: C1 W1_H02E0401 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D3 H00R0000 +arc: D5 E1_H02W0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C36:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 S3_V06N0203 +arc: A2 H00L0100 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A5 H02E0701 +arc: A6 V02S0301 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C37:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 E1_H02W0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 H01E0101 +arc: A0 N1_V02S0701 +arc: A1 H00L0100 +arc: A2 V02N0701 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 S1_V02N0101 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B2 S1_V02N0301 +arc: B3 W1_H02E0101 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 E1_H02W0301 +arc: B7 V00T0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0401 F4 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0201 F0 +arc: W1_H02W0301 F1 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C38:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0701 V01N0101 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B6 V02N0701 +arc: B7 H02W0301 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0701 Q7 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: V01S0000 F2 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R83C39:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 E1_H01W0000 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02W0101 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0101 Q1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F4 +arc: V01S0000 F4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +word: SLICED.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C3:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R83C40:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0701 +arc: A3 H02E0501 +arc: A4 V02N0101 +arc: A6 H02W0701 +arc: A7 N1_V01N0101 +arc: B0 H02W0101 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 E1_H02W0101 +arc: B6 V02N0701 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 H02W0401 +arc: C5 H01E0001 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 E1_H02W0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F2 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: S3_V06S0303 F5 +arc: V00B0100 F7 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 0001001100110011 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111011001100 +word: SLICED.K0.INIT 0000000000000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C41:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0001 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q6 +arc: V00B0100 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C42:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V06S0303 +arc: A0 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A7 H00R0000 +arc: B1 S1_V02N0301 +arc: B2 H02W0301 +arc: B5 H02E0301 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C3 E1_H02W0601 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 V02N0201 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q2 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: V00B0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000000000000100 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0101000011110000 +word: SLICEC.K1.INIT 0010001100110011 +word: SLICED.K0.INIT 0000000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R83C43:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0301 V02N0301 +arc: A1 S1_V02N0501 +arc: A3 V00T0000 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 V02N0101 +arc: B3 H01W0100 +arc: B5 H00R0000 +arc: C0 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0203 F4 +arc: V00T0000 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000010 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R83C44:PLC2 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 H01E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 W1_H02E0701 +arc: A3 N1_V02S0501 +arc: B3 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: C0 W1_H02E0401 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 W1_H02E0001 +arc: D6 V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 Q0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: N3_V06N0303 F6 +arc: V01S0000 F6 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R83C45:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 W1_H02E0201 + +.tile R83C46:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 H06W0203 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B6 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C6 V00T0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0000 +arc: V00B0000 F6 +word: SLICED.K0.INIT 0101111101001110 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R83C47:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 H02W0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0303 H06E0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 S1_V02N0501 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 E1_H01W0100 +arc: B3 V02N0101 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 E1_H02W0401 +arc: C3 H00L0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 F0 +arc: D3 V02N0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: M0 H01E0001 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F3 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEA.K1.INIT 0000000001000101 +word: SLICEB.K0.INIT 0000001110110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C48:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02E0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02W0301 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 N1_V02S0501 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A1 W1_H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02N0101 +arc: A5 N1_V02S0101 +arc: A6 V02N0301 +arc: A7 N1_V02S0301 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 S1_V02N0601 +arc: C1 H00L0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1101010110000000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1000000010001100 +word: SLICED.K1.INIT 0001001111011111 +word: SLICEB.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 0000010000000101 +word: SLICEC.K0.INIT 0000010111010101 +word: SLICED.K0.INIT 0011001111111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C49:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 H02W0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H00L0000 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A6 H02W0701 +arc: A7 S1_V02N0301 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 H02E0301 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C0 H02W0601 +arc: C2 V02S0401 +arc: C3 E1_H01W0000 +arc: C4 H02E0601 +arc: C5 S1_V02N0201 +arc: C6 V02S0201 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V01N0001 +arc: D6 H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 Q1 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M5 H02W0001 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0501 Q7 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q7 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1100111100000000 +word: SLICEA.K1.INIT 1100110010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000100000111111 +word: SLICEA.K0.INIT 0000101011111010 +word: SLICED.K0.INIT 0000001110110011 +word: SLICED.K1.INIT 1100111101000101 +word: SLICEB.K0.INIT 1100111101000101 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C50:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02E0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0501 +arc: A1 H00L0100 +arc: A2 H02E0701 +arc: A3 W1_H02E0701 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A7 V02N0101 +arc: B1 W1_H02E0101 +arc: B3 N1_V02S0101 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 N1_V02S0401 +arc: D7 H02W0001 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0303 F6 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 1100101000001010 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C51:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 S1_V02N0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 E1_H01W0000 +arc: B0 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 H02W0101 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0401 +arc: C4 V02N0001 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 H02W0201 +arc: D4 H02W0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 Q0 +arc: V01S0000 F7 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0401 F4 +arc: W1_H02W0601 F6 +word: SLICED.K1.INIT 1111010100000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEB.K1.INIT 1010001100000000 +word: SLICEB.K0.INIT 0101010111111100 +word: SLICED.K0.INIT 0010101001111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C52:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0100 E1_H02W0301 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 E1_H01W0100 +arc: A2 H02E0701 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: A6 H02W0701 +arc: A7 H02E0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V02N0301 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C1 W1_H02E0601 +arc: C2 H00L0100 +arc: C3 H02E0601 +arc: C4 F6 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 N1_V02S0001 +arc: D3 S1_V02N0201 +arc: D4 V02S0601 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H02E0501 F5 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1000010000100001 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEB.K0.INIT 1101000011011101 +word: SLICEC.K1.INIT 1100001100000000 +word: SLICEB.K1.INIT 0101111101011100 +word: SLICED.K1.INIT 0101001111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R83C53:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A2 N1_V02S0501 +arc: A4 V00T0100 +arc: A5 V02S0101 +arc: A6 W1_H02E0501 +arc: A7 V02N0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 N1_V02S0701 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0401 +arc: C3 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V00T0000 +arc: C6 V01N0101 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00T0100 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 N1_V02S0401 +arc: D6 N1_V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0501 F5 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F4 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0010011110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C54:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H01E0001 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A5 H02W0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 V02S0701 +arc: B6 H01E0101 +arc: B7 F1 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V02N0401 +arc: D5 F2 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1011001110000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICEA.K1.INIT 1000000001000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000000000100011 +word: SLICEC.K1.INIT 0000010110001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C55:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H02E0701 +arc: A4 V00T0100 +arc: A7 N1_V02S0301 +arc: B0 H01W0100 +arc: B1 W1_H02E0101 +arc: B2 H02E0101 +arc: B3 H02W0301 +arc: B5 H02W0101 +arc: B6 V01S0000 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 H00L0100 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00T0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0501 Q5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q6 +arc: V01S0100 Q4 +word: SLICED.K1.INIT 1010010100000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K0.INIT 0101010111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C56:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 H02W0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A2 H02W0701 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 H02E0701 +arc: A6 F5 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 H01E0001 +arc: C7 F4 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 W1_H02E0301 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 F6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICED.K1.INIT 1000000001000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K1.INIT 1011101100001011 +word: SLICED.K0.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R83C57:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0103 V06S0103 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02W0101 +arc: C0 H02E0601 +arc: C1 H02W0601 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 H02E0201 +arc: D3 H02E0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: V01S0000 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICED.K0.INIT 0101001111110011 +word: SLICEB.K0.INIT 1111101101010001 +word: SLICEB.K1.INIT 1110101001000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R83C58:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02N0601 +arc: A1 H02E0501 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 E1_H01W0000 +arc: A5 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 H02E0301 +arc: B5 V02S0701 +arc: B6 V01S0000 +arc: B7 V02S0701 +arc: C0 V02S0601 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 H02W0601 +arc: C5 H02E0401 +arc: C6 E1_H02W0601 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 E1_H02W0001 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F1 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010110000000000 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 0101111100110011 +word: SLICEC.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 0011111100111010 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000001000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C59:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0401 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0101 +arc: A6 F5 +arc: A7 F5 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0501 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 F6 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: V01S0100 F5 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000000000001011 +word: SLICEB.K1.INIT 0000110101010101 +word: SLICEC.K0.INIT 0010000000111111 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C60:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06S0303 +arc: A1 H00R0000 +arc: A3 W1_H02E0501 +arc: A6 S1_V02N0301 +arc: B0 F1 +arc: B1 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 H01E0101 +arc: C0 H00R0100 +arc: C1 V02N0401 +arc: C3 N1_V02S0601 +arc: C4 V02N0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D3 V00B0100 +arc: D4 V00B0000 +arc: D6 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +arc: W1_H02W0401 F4 +word: SLICED.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000101100110011 +word: SLICEA.K0.INIT 0011001111110000 +word: SLICEB.K1.INIT 0011000101010101 +word: SLICEC.K0.INIT 1100111111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R83C61:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 + +.tile R83C62:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02N0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0401 +arc: A0 H00L0000 +arc: A1 F7 +arc: A2 F5 +arc: A3 F5 +arc: A4 V00T0000 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 H02W0101 +arc: B7 H02E0301 +arc: C0 H00L0100 +arc: C1 F4 +arc: C2 H02W0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0201 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0001 +arc: D2 H00R0000 +arc: D3 N1_V02S0201 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0201 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +word: SLICED.K0.INIT 0011000000110000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000010001000 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICED.K1.INIT 0000110000000000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C63:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 E1_H01E0001 +arc: A2 H02W0501 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: A5 H02W0701 +arc: A6 F5 +arc: A7 N1_V02S0101 +arc: B0 F1 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 F3 +arc: B5 H02W0301 +arc: B7 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 N1_V02S0401 +arc: C4 H02E0601 +arc: C5 V02S0201 +arc: C6 F4 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 N1_V02S0001 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 V01N0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 1000100000100010 +word: SLICED.K1.INIT 1101110100001101 +word: SLICEC.K0.INIT 1000000000001000 +word: SLICEC.K1.INIT 1000000000100000 +word: SLICED.K0.INIT 1010000000000000 +word: SLICEB.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 1111111011101110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 V02N0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: A0 V02S0501 +arc: A1 E1_H02W0701 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 F3 +arc: B5 H00L0000 +arc: B6 S1_V02N0501 +arc: B7 H01E0101 +arc: C0 H02W0601 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 H02W0201 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 F4 +arc: V01S0100 F4 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1111010100110001 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111111101100 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R83C65:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02N0101 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 F7 +arc: A1 H01E0001 +arc: A2 F5 +arc: A4 V00T0000 +arc: A5 N1_V02S0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 F3 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B5 H02W0301 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 N1_V02S0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C6 H02W0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 H02E0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 F2 +arc: V00T0000 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000000011000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111111111101010 +word: SLICEC.K1.INIT 1000100001000100 +word: SLICEB.K0.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R83C66:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: A0 H02W0501 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 H00L0100 +arc: A4 V02N0301 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 W1_H02E0701 +arc: B0 V02S0301 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 H02E0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: C0 H02W0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 Q4 +arc: C5 V00T0100 +arc: C6 W1_H02E0601 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110101011000000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110101011000000 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C67:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 H02E0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 H02W0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0100 +arc: A5 Q5 +arc: A6 V02N0101 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02W0101 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0101 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 Q4 +arc: C5 H02E0601 +arc: C6 Q6 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V02N0001 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0101000011011100 +word: SLICEA.K1.INIT 1110101011000000 +word: SLICEB.K0.INIT 1111100010001000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110110010100000 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1110110010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C68:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A4 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 N1_V02S0301 +arc: B4 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02E0001 +arc: D4 H02E0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1110101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C69:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: B0 H01W0100 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: C0 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000110010101110 +word: SLICEB.K0.INIT 1100111000001010 +word: SLICEB.K1.INIT 0011101100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C70:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0401 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 S1_V02N0101 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 H01W0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 F5 +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M1 H00R0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 Q1 +arc: S3_V06S0103 F1 +arc: V01S0000 Q7 +arc: V01S0100 F1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEA.K1.INIT 0101000001010000 +word: SLICEA.K0.INIT 0000110001011100 +word: SLICEC.K0.INIT 1010000011101100 +word: SLICEC.K1.INIT 0101110100001100 +word: SLICED.K0.INIT 0101000011011100 +word: SLICED.K1.INIT 1010000011101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R83C71:PLC2 +arc: H00R0100 V02N0701 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H02E0701 +arc: A3 E1_H02W0501 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B3 V02N0301 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 V02S0001 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0501 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 1100110000111100 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 1001101010010101 +word: SLICEA.K0.INIT 1111110001011100 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111111000110010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C72:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02N0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A4 E1_H02W0701 +arc: A6 H00L0000 +arc: B0 H02W0301 +arc: B2 H02W0301 +arc: B4 H02W0301 +arc: B6 H02W0301 +arc: C0 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: D0 V00B0100 +arc: D1 V02N0201 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D6 V00B0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 E1_H02W0201 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0010110100111100 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0110010101010101 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K0.INIT 0110011001010110 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0110011001010110 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R83C73:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 V02S0501 +arc: B7 H02W0101 +arc: C0 E1_H02W0401 +arc: C1 N1_V01N0001 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F4 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: LSR0 V00T0100 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: S3_V06S0303 F5 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1000110011011100 +word: SLICEA.K1.INIT 1111010010110000 +word: SLICEB.K0.INIT 1101110010001100 +word: SLICEB.K1.INIT 1000110011011100 +word: SLICEC.K1.INIT 0011000000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1010111110101100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R83C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A2 V02N0501 +arc: A4 V00T0100 +arc: A6 H00L0000 +arc: B0 H02E0301 +arc: B2 H02E0301 +arc: B4 V02N0501 +arc: B6 V02N0501 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 S1_V02N0001 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 0101101000011110 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0101100101010101 +word: SLICED.K1.INIT 1111000011110000 +word: SLICEA.K0.INIT 0010001111011100 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 0011000111001110 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R83C75:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0203 H01E0001 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 S1_V02N0701 +arc: A3 H01E0001 +arc: A6 H02W0501 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: C1 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 H02E0001 +arc: D4 V00B0000 +arc: D6 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 F4 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F1 +arc: V01S0000 F3 +arc: V01S0100 F3 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 0101111100000000 +word: SLICED.K0.INIT 0111000000000000 +word: SLICEB.K1.INIT 0101010110101010 +word: SLICEA.K1.INIT 1111000011111111 +word: SLICEC.K1.INIT 1100000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R83C76:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 N1_V02S0601 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 V01N0101 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A6 V02N0301 +arc: B0 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0101 +arc: B6 H02W0101 +arc: C0 W1_H02E0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0001 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F6 +arc: H01W0100 F2 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: V00T0100 F1 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R83C77:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E3_H06W0203 +arc: A0 E1_H02W0701 +arc: A1 H00L0100 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0701 +arc: A7 H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0301 +arc: B3 H00L0000 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C0 V02N0401 +arc: C1 E1_H02W0401 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 Q1 +arc: N3_V06N0103 F2 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEA.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1100110001011100 +word: SLICEC.K1.INIT 1100110010101100 +word: SLICED.K0.INIT 1100110010101100 +word: SLICED.K1.INIT 1100110001011100 +word: SLICEB.K0.INIT 0000101000001111 +word: SLICEB.K1.INIT 0000001000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C78:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 H00L0100 +arc: A4 H02W0501 +arc: A6 H02E0501 +arc: B0 V02N0101 +arc: B1 S1_V02N0101 +arc: B2 V02N0301 +arc: B4 S1_V02N0701 +arc: B6 V02N0701 +arc: C0 H00R0100 +arc: C2 H00R0100 +arc: C4 V02S0201 +arc: C6 V02S0201 +arc: D0 N1_V01S0000 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D4 S1_V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: N1_V01N0001 F1 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011111100000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C79:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H02E0701 +arc: A3 V02N0501 +arc: A5 V00T0000 +arc: A6 V00T0100 +arc: B1 N1_V02S0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B5 V02S0501 +arc: B6 N1_V02S0501 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C5 H02E0401 +arc: C6 N1_V02S0001 +arc: D1 H00R0000 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D5 F0 +arc: D6 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: N3_V06N0103 F2 +arc: N3_V06N0303 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICEC.K1.INIT 1001000000000000 +word: SLICED.K0.INIT 0000100100000000 +word: SLICEB.K0.INIT 0000110011001100 +word: SLICEB.K1.INIT 0000010001000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R83C80:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 N1_V02S0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: A2 F7 +arc: A3 N1_V02S0701 +arc: A4 F7 +arc: B1 V01N0001 +arc: B2 H00R0000 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: C0 N1_V02S0401 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0001 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: D0 V00T0100 +arc: D1 F0 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 N1_V02S0601 +arc: D6 N1_V02S0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: S3_V06S0103 F2 +arc: V01S0000 F3 +arc: W1_H02W0301 F1 +arc: W3_H06W0103 F1 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000000001010000 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R83C81:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: B0 H02W0101 +arc: B5 N1_V02S0501 +arc: B6 H02W0301 +arc: B7 E1_H02W0301 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C82:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: A4 V02S0301 +arc: A6 H02E0701 +arc: A7 H02W0701 +arc: B0 H02W0101 +arc: B1 V02S0101 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: B5 N1_V02S0501 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0101010101010000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R83C83:PLC2 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 N1_V02S0701 +arc: A4 W1_H02E0501 +arc: B4 H00L0000 +arc: C4 W1_H02E0601 +arc: D4 N1_V02S0401 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H00L0000 F0 +arc: N3_V06N0203 F4 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000001001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R83C84:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 + +.tile R83C85:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: N3_V06N0303 H06E0303 + +.tile R83C86:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C87:PLC2 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0303 H06E0303 + +.tile R83C88:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C89:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C90:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R83C91:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 + +.tile R83C92:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R83C93:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R83C94:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 H06E0003 + +.tile R83C95:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R83C96:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 + +.tile R83C97:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C98:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R83C99:PLC2 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 + +.tile R84C100:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C103:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R84C105:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C106:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R84C108:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R84C109:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C111:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R84C112:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R84C115:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C32:PLC2 +arc: N1_V02N0001 S1_V02N0501 + +.tile R84C33:PLC2 +arc: E1_H02E0001 E3_H06W0003 + +.tile R84C34:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 + +.tile R84C35:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00T0000 V02N0601 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: A4 H02W0701 +arc: B3 H02E0101 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R84C36:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 V01N0101 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 H02W0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0701 V01N0101 +arc: A6 H02E0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H00R0000 +arc: B7 V00T0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0701 F5 +arc: V01S0100 F4 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R84C37:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: A0 H00R0000 +arc: A4 V02N0101 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 V02S0101 +arc: B1 H02W0301 +arc: B5 S1_V02N0701 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C4 H02E0401 +arc: C6 W1_H02E0401 +arc: C7 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q6 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q6 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q4 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICED.K0.INIT 1100000010101010 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R84C38:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 V02N0501 +arc: A3 H01E0001 +arc: A4 W1_H02E0701 +arc: A7 V02S0101 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0301 Q3 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1010000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C39:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 N1_V01S0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V00B0000 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 F7 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: B4 H02E0301 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 H02E0401 +arc: C3 F4 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 S1_V02N0001 +arc: D2 W1_H02E0001 +arc: D3 N1_V01S0000 +arc: D4 W1_H02E0001 +arc: D5 V02S0401 +arc: D6 V02S0601 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q1 +arc: V00B0000 F6 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0100000000000000 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEC.K1.INIT 1000000011110000 +word: SLICEB.K1.INIT 1000000011001100 +word: SLICEB.K0.INIT 1010000000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C40:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B7 H02W0301 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: D0 N1_V01S0000 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 F0 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: N3_V06N0203 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1100000011110000 +word: SLICEC.K1.INIT 0000000001010101 +word: SLICEC.K0.INIT 0100110000001000 +word: SLICED.K1.INIT 1100010010000000 +word: SLICEA.K1.INIT 1100000011110000 +word: SLICEB.K1.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R84C41:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 V02N0701 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 V00B0100 +arc: B7 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: C6 S1_V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 E1_H01W0100 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F3 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: S1_V02S0401 F4 +arc: W1_H02W0301 F3 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0101010011111100 +word: SLICED.K0.INIT 0001010000101000 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICED.K1.INIT 0010100000000000 +word: SLICEA.K0.INIT 0010111100100010 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C42:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 V02N0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V06N0003 +arc: A2 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0101 +arc: B1 Q1 +arc: B3 Q3 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 W1_H02E0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C43:PLC2 +arc: E1_H02E0201 V01N0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A3 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H02E0601 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 F4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0001010000101000 +word: SLICEC.K1.INIT 0010100000000000 +word: SLICED.K0.INIT 0010000010000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEC.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R84C44:PLC2 +arc: E1_H02E0601 H01E0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A5 V02S0101 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C1 V02S0401 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C4 Q4 +arc: C5 H02W0401 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1110001011100010 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C45:PLC2 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 H01E0001 +arc: A3 H02E0501 +arc: A4 F5 +arc: A5 V00T0100 +arc: B4 H01E0101 +arc: B5 H02E0301 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: D3 W1_H02E0201 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: N3_V06N0303 F6 +arc: V00T0100 F3 +arc: V01S0000 F6 +arc: W1_H02W0601 F4 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000000100000100 +word: SLICEC.K0.INIT 0010100000000000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R84C46:PLC2 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 + +.tile R84C47:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0103 V06S0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 V00T0100 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B4 H02W0301 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02W0601 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: V00B0000 F4 +arc: V00T0000 F0 +word: SLICEC.K0.INIT 0101111101011100 +word: SLICEA.K0.INIT 1010101011001111 +word: SLICEA.K1.INIT 1010101011000000 +word: SLICEB.K0.INIT 0000010000000000 +word: SLICEB.K1.INIT 0000010000000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0303 H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 F7 +arc: A1 F7 +arc: A3 E1_H02W0501 +arc: A5 S1_V02N0301 +arc: A7 E1_H02W0501 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B3 S1_V02N0301 +arc: B5 H00R0000 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0401 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 V02S0001 +arc: D5 H02W0201 +arc: D7 H02W0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: N1_V01N0001 F5 +arc: V00T0100 F3 +arc: V01S0000 F0 +arc: V01S0100 F7 +word: SLICEC.K1.INIT 0011001011111110 +word: SLICEB.K1.INIT 0101010111111100 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1100110010101111 +word: SLICEA.K1.INIT 1100110010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R84C49:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: A1 E1_H02W0501 +arc: A2 V00T0000 +arc: A3 E1_H02W0501 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B1 Q1 +arc: B3 H00R0000 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 H02E0401 +arc: C2 H00L0000 +arc: C3 N1_V02S0401 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 H02W0001 +arc: D4 V01N0001 +arc: D5 H02W0201 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q2 +arc: M4 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0601 F4 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000011011101 +word: SLICED.K1.INIT 1111000010001000 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C50:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0001 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 H01E0101 +arc: A2 E1_H02W0501 +arc: A5 V02S0101 +arc: A7 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 H02W0301 +arc: B3 H02E0301 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 1111000000110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1010101011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 + +.tile R84C51:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0000 +arc: A4 H02W0701 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 W1_H02E0401 +arc: C4 E1_H01E0101 +arc: C6 S1_V02N0201 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D6 H00R0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICED.K0.INIT 0100011111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C52:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0203 W3_H06E0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 F5 +arc: A7 V00T0100 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 H02W0101 +arc: B6 N1_V02S0701 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 V02S0601 +arc: C2 H00R0100 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 W1_H02E0201 +arc: D3 V02N0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: D6 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F4 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: V00T0000 Q0 +arc: V00T0100 F1 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000010101100 +word: SLICEA.K1.INIT 1111010100110001 +word: SLICED.K1.INIT 1000001000000000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K1.INIT 0001101110111011 +word: SLICED.K0.INIT 1011101100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C53:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V02S0601 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 V02S0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B3 W1_H02E0301 +arc: B4 S1_V02N0701 +arc: B5 E1_H02W0301 +arc: B6 H02E0301 +arc: B7 S1_V02N0501 +arc: C0 H02W0601 +arc: C1 V02N0601 +arc: C2 F4 +arc: C3 F6 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02W0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 F2 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 0000000011011000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICED.K0.INIT 1100010011110101 +word: SLICEB.K1.INIT 0101010111111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C54:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 S1_V02N0501 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0301 +arc: A7 V02N0101 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 N1_V02S0301 +arc: B3 V02N0301 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 S1_V02N0701 +arc: B7 V02S0501 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0601 F4 +arc: S1_V02S0301 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 0011111101010101 +word: SLICED.K0.INIT 0101111100110011 +word: SLICEC.K0.INIT 1100101011001111 +word: SLICEC.K1.INIT 1100101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R84C55:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A1 F7 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A6 V02S0301 +arc: A7 V00T0100 +arc: B0 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 H02E0101 +arc: B6 E1_H02W0301 +arc: B7 H02W0301 +arc: C0 H02E0601 +arc: C1 V02N0401 +arc: C2 E1_H02W0601 +arc: C3 W1_H02E0601 +arc: C4 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 H00R0000 +arc: D3 N1_V01S0000 +arc: D4 S1_V02N0401 +arc: D6 V01N0001 +arc: D7 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: V00T0000 Q0 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1000100011000000 +word: SLICEA.K1.INIT 1111000010100000 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1111001101010001 +word: SLICEB.K0.INIT 1011000010111011 +word: SLICEC.K0.INIT 0111011101110100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R84C56:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A6 F7 +arc: A7 N1_V01N0101 +arc: B1 E1_H02W0101 +arc: B3 H00L0000 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: B7 V00B0100 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C3 E1_H01W0000 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02S0001 +arc: D2 E1_H02W0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 V02S0401 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEA.K1.INIT 0101010111111100 +word: SLICED.K1.INIT 0101111100110011 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R84C57:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 F7 +arc: A2 V01N0101 +arc: A3 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: B2 S1_V02N0301 +arc: B3 V02N0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 F4 +arc: C3 S1_V02N0601 +arc: C4 E1_H01E0101 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 V00T0100 +arc: D2 S1_V02N0001 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 F3 +arc: V01S0100 Q0 +arc: W1_H02W0301 F1 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1000001001000001 +word: SLICED.K1.INIT 1111001101010001 +word: SLICEA.K1.INIT 1000001000000000 +word: SLICED.K0.INIT 0001101110111011 +word: SLICEC.K1.INIT 0010101001111111 +word: SLICEC.K0.INIT 1111010100110001 +word: SLICEB.K0.INIT 0101010111111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R84C58:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0303 W3_H06E0303 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 E1_H01W0100 +arc: B3 V01N0001 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C3 V02S0401 +arc: C5 H01E0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H01W0100 +arc: D5 V02S0401 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1010101011110011 +word: SLICED.K1.INIT 1010101011000000 +word: SLICEA.K1.INIT 0010101001111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R84C59:PLC2 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: A0 V02S0701 +arc: A1 H01E0001 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: A6 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B1 S1_V02N0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: B6 H01E0101 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0201 +arc: C7 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0201 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 W1_H02E0001 +arc: M2 H02E0601 +arc: M3 W1_H02E0201 +arc: M4 V00T0100 +arc: M6 N1_V01N0101 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 Q7 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 Q7 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000001000000011 +word: SLICEC.K0.INIT 1100110010101111 +word: SLICEC.K1.INIT 1111100000001000 +word: SLICEA.K1.INIT 0101111101011100 +word: SLICED.K0.INIT 1100110010101111 +word: SLICED.K1.INIT 1111000010001000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R84C60:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F7 +arc: A1 F7 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B7 H02W0301 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C7 W1_H02E0401 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D7 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: N1_V01N0001 F0 +arc: N1_V02N0201 F2 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000001000000000 +word: SLICEA.K1.INIT 0000001000000011 +word: SLICEB.K0.INIT 0000001000000000 +word: SLICEB.K1.INIT 0000001000000011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R84C61:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E3_H06E0203 W3_H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0401 E1_H02W0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 + +.tile R84C62:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: A0 H00L0100 +arc: A3 V01N0101 +arc: A4 V00B0000 +arc: B0 F1 +arc: B1 V00B0000 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B6 V02N0501 +arc: C0 F4 +arc: C1 S1_V02N0401 +arc: C3 V02S0601 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H01W0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0501 F5 +arc: V00B0000 F6 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEA.K1.INIT 0000110000000000 +word: SLICEA.K0.INIT 1111111011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C63:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N3_V06N0003 W3_H06E0003 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 V06S0203 +arc: A0 F5 +arc: A1 F7 +arc: A2 H01E0001 +arc: A3 E1_H01E0001 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 F3 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: C4 V02N0001 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H02W0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEB.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111011101110 +word: SLICED.K0.INIT 0000000000001000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C64:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0101 N3_V06S0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A4 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 F3 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 V00B0100 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V00B0100 +arc: C6 S1_V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 H02W0001 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +word: SLICED.K1.INIT 1000010000100001 +word: SLICED.K0.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111111111000 +word: SLICEB.K1.INIT 0000000011000000 +word: SLICEA.K1.INIT 1111111011111100 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C65:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0501 +arc: A1 F5 +arc: A2 F7 +arc: A4 H02E0701 +arc: A5 E1_H02W0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 H01E0101 +arc: B7 V00T0000 +arc: C0 H02E0401 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 V02N0601 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0100 F7 +arc: H01W0000 F4 +arc: H01W0100 F6 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000000011111111 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEC.K0.INIT 0000000000001000 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C66:PLC2 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06E0003 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 V06S0203 +arc: A0 F7 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B2 W1_H02E0301 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: B6 F3 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V02N0201 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D5 H02E0001 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 F2 +arc: V00T0000 Q0 +arc: V01S0100 F1 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000000000001000 +word: SLICED.K1.INIT 0000101000000000 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000011000000 +word: SLICEB.K0.INIT 1000001001000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R84C67:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0303 H06E0303 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 V02S0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 H01W0100 +arc: B3 V02S0101 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: C0 V02S0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 V02S0201 +arc: D3 H00R0000 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000010100000 +word: SLICEC.K0.INIT 0000101011001110 +word: SLICEC.K1.INIT 1100111000001010 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C68:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H02W0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 S1_V02N0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D3 V02S0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q6 +arc: H01W0100 F0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 E1_H02W0601 +arc: M1 V01S0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 F6 +arc: V00B0000 Q6 +arc: V01S0100 F4 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011101000110000 +word: SLICEA.K1.INIT 0011000010111010 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1010101001010101 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEC.K0.INIT 1010111011101010 +word: SLICEC.K1.INIT 1110101010101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C69:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H02W0701 +arc: A2 W1_H02E0501 +arc: A3 W1_H02E0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B1 H01W0100 +arc: B2 F1 +arc: B3 F1 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 H02E0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 F0 +arc: D6 F0 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +arc: V01S0100 F5 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 1111111110010000 +word: SLICEC.K1.INIT 1111111101100000 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 1111111101100000 +word: SLICED.K1.INIT 1111111110010000 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 1100111011101100 +word: SLICEB.K1.INIT 1110110011001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C70:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0501 W3_H06E0303 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 H02E0701 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B2 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C2 V02S0401 +arc: C4 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 H00R0100 +arc: D5 S1_V02N0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q1 +arc: V01S0000 F2 +arc: V01S0100 F4 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 0010111011100010 +word: SLICEC.K1.INIT 1011100001110100 +word: SLICED.K0.INIT 1011100001110100 +word: SLICED.K1.INIT 0111010010111000 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEB.K0.INIT 0000110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R84C71:PLC2 +arc: H00R0000 V02N0401 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A4 V02N0301 +arc: B3 H01W0100 +arc: B4 F3 +arc: C4 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: LSR1 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0601 F4 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 F4 +arc: V01S0000 F4 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 1010010110010101 +word: SLICEB.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R84C72:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 V06S0303 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06W0003 +arc: N3_V06N0103 H06E0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0103 H01E0101 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A2 V01N0101 +arc: A4 E1_H02W0501 +arc: A5 V02N0101 +arc: B0 H02W0301 +arc: B2 H02E0101 +arc: B3 V01N0001 +arc: B5 H02E0101 +arc: C0 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 V00T0000 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02S0401 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 F5 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR0 V00T0100 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1110000000011111 +word: SLICEB.K0.INIT 1010101011000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000010100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R84C73:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 V06S0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 E1_H01W0100 +arc: B6 V02N0701 +arc: C0 V02S0401 +arc: D0 V02S0201 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: N1_V01N0101 F6 +arc: V01S0000 F0 +arc: W1_H02W0401 F6 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R84C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 N1_V01S0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 V06S0303 + +.tile R84C75:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 F1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 V02S0601 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q3 +arc: V01S0000 F1 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +arc: W3_H06W0003 Q3 +word: SLICEA.K1.INIT 1010010110100101 +word: SLICEA.K0.INIT 0011111100110000 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1001100111110000 +word: SLICEC.K1.INIT 0110011011110000 +word: SLICED.K0.INIT 0110011011110000 +word: SLICED.K1.INIT 1001100111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 V01N0001 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 H01E0001 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 Q5 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H01W0000 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0501 +arc: M0 V00T0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 F0 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0100111011100100 +word: SLICEA.K1.INIT 1110010001001110 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0010111011100010 +word: SLICED.K0.INIT 1100101000111010 +word: SLICED.K1.INIT 0011101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C77:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0601 V02S0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 Q5 +arc: A7 V02N0101 +arc: B0 E1_H02W0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 V02S0601 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 W1_H02E0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0601 F6 +arc: V01S0000 F4 +arc: V01S0100 F6 +arc: W1_H02W0101 Q1 +word: SLICED.K0.INIT 1111000000001111 +word: SLICEB.K0.INIT 0101110010101100 +word: SLICEB.K1.INIT 1010110001011100 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICEA.K0.INIT 0110111101100000 +word: SLICEA.K1.INIT 1010110001011100 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R84C78:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H02W0201 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 F5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 F0 +arc: V01S0000 Q3 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 0101101011001100 +word: SLICEC.K1.INIT 1010010111001100 +word: SLICED.K0.INIT 1010110001011100 +word: SLICED.K1.INIT 0101101011001100 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R84C79:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 W1_H02E0501 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 V02S0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 W1_H02E0201 +arc: D3 S1_V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 H00L0100 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0100 F5 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR1 H02E0501 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q7 +arc: W1_H02W0001 Q0 +word: SLICEB.K0.INIT 1110010001001110 +word: SLICEB.K1.INIT 0100111011100100 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICED.K0.INIT 0110111101100000 +word: SLICED.K1.INIT 1100101000111010 +word: SLICEA.K0.INIT 1001111110010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R84C80:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N3_V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 S1_V02N0701 +arc: A6 F5 +arc: B5 N1_V01S0000 +arc: C0 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C7 V02N0001 +arc: D0 V01S0100 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: N1_V01N0001 F0 +arc: N1_V02N0701 F5 +arc: N3_V06N0303 F6 +arc: V01S0100 F7 +arc: W1_H02W0201 F0 +arc: W3_H06W0303 F6 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R84C81:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: W1_H02W0701 V02N0701 + +.tile R84C82:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C84:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R84C85:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R84C87:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 + +.tile R84C88:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C90:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R84C91:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R84C93:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R84C94:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile R84C96:PLC2 +arc: N3_V06N0303 H06E0303 + +.tile R84C99:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 + +.tile R85C34:PLC2 +arc: E1_H02E0201 V02S0201 + +.tile R85C35:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 V02S0001 +arc: N1_V02N0501 E1_H01W0100 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 V02S0501 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q4 +word: SLICEA.K0.INIT 1101010110000000 +word: SLICEA.K1.INIT 1100000010101010 +word: SLICEB.K0.INIT 1101010110000000 +word: SLICEB.K1.INIT 1010000011001100 +word: SLICEC.K0.INIT 1100000010101010 +word: SLICEC.K1.INIT 1100000010101010 +word: SLICED.K0.INIT 1100000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C36:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 V02S0301 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H02E0601 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0000 +arc: A2 H00L0100 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B2 V02S0101 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 W1_H02E0201 +arc: D2 Q2 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +word: SLICEA.K0.INIT 1110001000100010 +word: SLICEA.K1.INIT 0011000011001100 +word: SLICEB.K0.INIT 1101010110000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C37:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 W1_H02E0601 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0301 +arc: A2 V00B0000 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 W1_H02E0701 +arc: A6 H00R0000 +arc: A7 V00T0100 +arc: B0 V02S0101 +arc: B2 H00R0100 +arc: B3 N1_V02S0301 +arc: B4 N1_V02S0701 +arc: B5 S1_V02N0501 +arc: B6 E1_H02W0301 +arc: B7 N1_V02S0501 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C38:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: A1 H02W0501 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 W1_H02E0701 +arc: A6 N1_V02S0301 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 W1_H02E0101 +arc: B2 V02S0101 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 V02N0701 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C39:PLC2 +arc: E3_H06E0103 N1_V01S0100 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H02W0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: A0 S1_V02N0701 +arc: A1 H00R0000 +arc: B0 N1_V02S0101 +arc: B1 H02E0301 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R85C40:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H06W0103 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 F5 +arc: A1 E1_H01E0001 +arc: A2 H00L0100 +arc: A4 V02S0301 +arc: A5 S1_V02N0101 +arc: A6 E1_H02W0501 +arc: A7 N1_V01N0101 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B4 E1_H02W0301 +arc: B5 V02S0701 +arc: B6 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0601 +arc: C2 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D2 V00T0100 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D6 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F1 +arc: V00B0000 F4 +arc: V01S0000 Q0 +word: SLICEC.K0.INIT 0000011001100000 +word: SLICEA.K1.INIT 0001001001001000 +word: SLICEB.K0.INIT 0001001001001000 +word: SLICED.K0.INIT 0001001001001000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1010100110011010 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A4 E1_H02W0501 +arc: A5 E1_H01W0000 +arc: A6 E1_H02W0701 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00R0100 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 H01W0000 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0101 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0110100110010110 +word: SLICEB.K1.INIT 1100110000110011 +word: SLICEB.K0.INIT 1100100111000110 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1111000010010110 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C42:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0301 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: A0 H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: A4 E1_H01W0000 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 E1_H02W0401 +arc: C1 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 S1_V02N0401 +arc: C4 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 V02S0401 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0601 F6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEC.K0.INIT 0001010100101010 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +word: SLICEA.K1.INIT 0101000011001100 +word: SLICEB.K0.INIT 0111001101000000 +word: SLICEB.K1.INIT 0011111100101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C43:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 H01E0101 +arc: A2 F5 +arc: A3 V02N0701 +arc: A5 H02W0701 +arc: A6 H02E0701 +arc: A7 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 F6 +arc: C5 E1_H02W0601 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F7 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICED.K1.INIT 0010000010000000 +word: SLICEC.K1.INIT 0000000010010110 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000110010101100 +word: SLICED.K0.INIT 1110101100010100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V01N0101 +arc: A0 V02S0701 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 S1_V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: B1 Q1 +arc: B3 V01N0001 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: C0 N1_V02S0401 +arc: C1 V02S0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 V02N0201 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 W1_H02E0201 +arc: D4 V02N0601 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR1 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q4 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 0000111011100000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000101011001010 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C45:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H02E0201 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A2 H01E0001 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B3 H00L0000 +arc: B4 W1_H02E0301 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: B7 F3 +arc: C0 H02E0601 +arc: C1 H02E0401 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 S1_V02N0201 +arc: D1 V00B0100 +arc: D2 N1_V02S0201 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: N1_V01N0001 F7 +arc: V01S0000 F5 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 1111101011001000 +word: SLICEB.K0.INIT 0000000001010101 +word: SLICEB.K1.INIT 0011111100101010 +word: SLICED.K0.INIT 0111011101110000 +word: SLICEA.K1.INIT 0011001011111010 +word: SLICEC.K0.INIT 0101111101001100 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0101111101001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C46:PLC2 +arc: W1_H02W0401 H01E0001 + +.tile R85C47:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0203 H06W0203 + +.tile R85C48:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 + +.tile R85C49:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: A0 N1_V02S0701 +arc: A4 N1_V02S0101 +arc: A5 V02S0101 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R85C50:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A2 H02W0501 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: B3 E1_H01W0100 +arc: B4 H02W0301 +arc: B6 E1_H02W0301 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 V02N0601 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V00T0000 F0 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEB.K1.INIT 1100111101000101 +word: SLICEC.K0.INIT 0101010111111100 +word: SLICED.K0.INIT 1010111100100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R85C51:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A5 V00T0100 +arc: A6 V02N0101 +arc: B1 Q1 +arc: B3 E1_H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C0 E1_H02W0601 +arc: C1 V02N0401 +arc: C3 W1_H02E0601 +arc: C5 H02E0601 +arc: C6 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: D5 V02S0601 +arc: D6 V02S0601 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 F6 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 0001110111011101 +word: SLICEC.K1.INIT 0001110111011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C52:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 H00L0100 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B4 H02W0101 +arc: B6 H02E0101 +arc: B7 V02S0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00L0000 +arc: C4 H02E0401 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 E1_H02W0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q2 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q1 +arc: W3_H06W0003 Q3 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICED.K0.INIT 0011001100000000 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 1010001011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C53:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02N0201 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 W1_H02E0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A4 S1_V02N0101 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 V02N0301 +arc: B0 W1_H02E0301 +arc: B1 Q1 +arc: B3 N1_V02S0301 +arc: B4 V02N0701 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C0 N1_V02S0601 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: C6 W1_H02E0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V01S0000 F3 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1011100000000000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEC.K0.INIT 1011000010111011 +word: SLICEC.K1.INIT 1010000001010000 +word: SLICED.K1.INIT 0001110111011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C54:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0701 +arc: A1 V02N0501 +arc: A2 H02W0701 +arc: A3 N1_V02S0501 +arc: A5 V00B0000 +arc: A6 V02N0301 +arc: A7 F5 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C6 N1_V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 F2 +arc: D6 W1_H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0401 F4 +arc: V00B0000 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICEB.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 1100000000001100 +word: SLICEB.K0.INIT 1010000000001010 +word: SLICED.K0.INIT 1101110100001101 +word: SLICEC.K1.INIT 1000001000000000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C55:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 H02W0701 +arc: V00T0000 W1_H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 V01N0001 +arc: A1 N1_V02S0701 +arc: A3 V00B0000 +arc: A5 V00T0100 +arc: A6 E1_H02W0701 +arc: A7 H00R0000 +arc: B0 H02W0301 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C3 V02S0401 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D6 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: V00B0000 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1000101011001111 +word: SLICED.K0.INIT 0010101001111111 +word: SLICEB.K1.INIT 1000110010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R85C56:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 W1_H02E0501 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V02S0201 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 E1_H02W0701 +arc: A4 V02N0101 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: C0 E1_H02W0401 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C4 V02N0201 +arc: C5 H02E0401 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02E0001 +arc: D4 V02S0601 +arc: D5 N1_V02S0601 +arc: D6 W1_H02E0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0303 F5 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000010111000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 1000110000100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010001011110011 +word: SLICED.K1.INIT 1101000011011101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C57:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V02S0701 +arc: A1 H02E0701 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V00T0000 +arc: B1 V02N0101 +arc: B4 H01E0101 +arc: B5 F1 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C3 N1_V02S0401 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H00R0000 +arc: D2 V00B0100 +arc: D3 H02E0001 +arc: D4 V01N0001 +arc: D5 W1_H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0203 F7 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICED.K0.INIT 0000000011011000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1000010000000000 +word: SLICED.K1.INIT 0000000011011000 +word: SLICEA.K1.INIT 0001110111011101 +word: SLICEC.K1.INIT 1000101011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C58:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A2 V00T0000 +arc: A3 H02E0501 +arc: B0 H02E0301 +arc: B1 W1_H02E0101 +arc: B3 V02S0301 +arc: B5 W1_H02E0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 H02E0601 +arc: C2 H00L0000 +arc: C3 V02N0601 +arc: C5 H02E0601 +arc: C6 V01N0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 F6 +arc: N3_V06N0103 Q1 +arc: V00T0000 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K1.INIT 1100111101000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R85C59:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: A0 N1_V02S0501 +arc: A1 W1_H02E0701 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B1 V02N0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 V02N0701 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 W1_H02E0601 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D2 V02N0201 +arc: D3 H00R0000 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 V02N0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 Q6 +arc: V00T0100 F1 +arc: V01S0100 F6 +arc: W1_H02W0401 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 1100100001000000 +word: SLICED.K0.INIT 0011001111111010 +word: SLICEA.K1.INIT 0000111011111110 +word: SLICEB.K0.INIT 1111000010111011 +word: SLICEB.K1.INIT 1110101001000000 +word: SLICED.K1.INIT 0000111011111110 +word: SLICEC.K0.INIT 0000010000000000 +word: SLICEC.K1.INIT 0000010100000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R85C60:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H06E0003 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V02N0201 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B6 H01E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C6 E1_H02W0401 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0001 F0 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: M0 V00B0100 +arc: N3_V06N0303 F6 +word: SLICED.K0.INIT 1111110000000000 +word: SLICEA.K0.INIT 1110111101000101 +word: SLICEA.K1.INIT 1110101001000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C61:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0401 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0401 H01E0001 +arc: A3 V00B0000 +arc: B2 H01W0100 +arc: B3 N1_V02S0101 +arc: C2 E1_H01W0000 +arc: C3 H02E0401 +arc: D2 V00B0100 +arc: D3 H00R0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000000000001000 +word: SLICEB.K0.INIT 0000000011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R85C62:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02S0501 +arc: H00L0100 V02N0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 V01N0101 +arc: A0 H01E0001 +arc: A1 F5 +arc: A2 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 F7 +arc: A6 F7 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 E1_H02W0301 +arc: B4 V02N0701 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C1 F6 +arc: C2 H02E0601 +arc: C3 E1_H01W0000 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 V02N0001 +arc: D2 H02W0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: V00T0100 Q1 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111111111101010 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000000000001000 +word: SLICED.K0.INIT 0000000010100000 +word: SLICEA.K1.INIT 1111111011111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C63:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H01E0001 +arc: A1 F7 +arc: A2 V02N0701 +arc: A4 F7 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H00R0000 +arc: B4 H02E0101 +arc: C0 F6 +arc: C1 F4 +arc: C2 W1_H02E0601 +arc: C3 H02W0401 +arc: C4 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101010101010101 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C64:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V01N0001 +arc: A0 F7 +arc: A1 E1_H02W0501 +arc: A2 F7 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0701 +arc: B0 N1_V02S0101 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B5 S1_V02N0501 +arc: B6 F1 +arc: C0 N1_V01N0001 +arc: C1 H00L0000 +arc: C2 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: D6 S1_V02N0401 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0301 F1 +arc: S1_V02S0701 F5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 0000000000001000 +word: SLICEB.K1.INIT 0011001111111111 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R85C65:PLC2 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H02W0501 +arc: A1 H00L0100 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 S1_V02N0101 +arc: A5 Q5 +arc: A7 V00T0100 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B2 H00R0000 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 E1_H02W0601 +arc: C2 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V00B0100 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0501 Q5 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q4 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 1111100010001000 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1110101011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C66:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0601 E3_H06W0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0701 + +.tile R85C67:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H06W0203 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 S1_V02N0701 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 V01N0001 +arc: C0 N1_V02S0601 +arc: C1 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q7 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q2 +arc: S1_V02S0101 F1 +arc: S1_V02S0501 F7 +arc: V00T0000 Q2 +arc: V01S0000 F1 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q4 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEB.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111100010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C68:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0303 V01N0101 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 H01E0001 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0201 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F4 +arc: H01W0100 Q5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: V01S0000 F6 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1110110011001110 +word: SLICEA.K1.INIT 1100111011101100 +word: SLICEB.K0.INIT 1111111100101000 +word: SLICEB.K1.INIT 1111111110000010 +word: SLICEC.K0.INIT 1111010011111000 +word: SLICEC.K1.INIT 1111100011110100 +word: SLICED.K0.INIT 0011101100001010 +word: SLICED.K1.INIT 1100111000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C69:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E3_H06W0203 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 H01E0001 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 E1_H02W0101 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 N1_V02S0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q5 +arc: H01W0000 Q5 +arc: H01W0100 F1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 F0 +arc: N1_V02N0601 F6 +arc: S1_V02S0001 F0 +arc: V01S0000 F2 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1011100001110100 +word: SLICEB.K1.INIT 0111010010111000 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111101101001000 +word: SLICEA.K0.INIT 1100110000110011 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1010000011101100 +word: SLICED.K1.INIT 0000101011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C70:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 N1_V02S0401 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 E1_H02W0701 +arc: A1 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0401 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q1 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0100 F2 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0101 Q3 +arc: N1_V02N0401 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1011011110000100 +word: SLICEB.K1.INIT 0101101011001100 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICEA.K1.INIT 0111010010111000 +word: SLICED.K0.INIT 1100111011101100 +word: SLICED.K1.INIT 1110110011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R85C71:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 V02S0701 +arc: A2 N1_V02S0701 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: C0 E1_H02W0601 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C3 H00R0100 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 F6 +arc: LSR1 H02W0501 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 F4 +arc: S1_V02S0401 F6 +arc: V01S0000 Q1 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +word: SLICEA.K0.INIT 1001111110010000 +word: SLICEB.K0.INIT 1001100111110000 +word: SLICEB.K1.INIT 0011110010101010 +word: SLICED.K1.INIT 0011001111001100 +word: SLICEA.K1.INIT 0000101000001010 +word: SLICEC.K0.INIT 1111001011111000 +word: SLICEC.K1.INIT 1111100011110010 +word: SLICED.K0.INIT 1100110011000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R85C72:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 W3_H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H02E0501 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 E1_H02W0501 +arc: A6 N1_V01S0100 +arc: B0 H02E0101 +arc: B1 V02S0301 +arc: B3 N1_V02S0301 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: B7 W1_H02E0101 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 F5 +arc: V01S0000 F1 +arc: V01S0100 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F5 +word: SLICEC.K0.INIT 0001111011100001 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1110000100011110 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEA.K1.INIT 0101100101011010 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010101011110011 +word: SLICEA.K0.INIT 1010101011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C73:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02W0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 H02E0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 F1 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: N1_V01N0001 F5 +arc: N1_V02N0301 F1 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F1 +word: SLICEC.K1.INIT 0011001111001100 +word: SLICEB.K0.INIT 1110101000010101 +word: SLICEB.K1.INIT 0001010111101010 +word: SLICEA.K0.INIT 0001010111101010 +word: SLICEA.K1.INIT 1110101000010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C74:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A4 H02W0701 +arc: A6 H00R0000 +arc: B0 S1_V02N0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: B6 H02W0301 +arc: B7 H02W0301 +arc: C0 H02W0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V00B0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 V02S0401 +arc: D5 E1_H01W0100 +arc: D6 V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: LSR0 W1_H02E0501 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F5 +arc: S3_V06S0303 F5 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1001100110010110 +word: SLICEC.K0.INIT 0011110001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R85C75:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V01N0101 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0601 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 H02W0501 +arc: A6 F7 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: C1 N1_V02S0401 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 E1_H02W0601 +arc: C5 F6 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D6 V00B0000 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: LSR1 V00T0000 +arc: M2 W1_H02E0601 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 F6 +arc: S3_V06S0203 F7 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: V01S0100 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICED.K0.INIT 0101101000011110 +word: SLICEA.K0.INIT 0111011100100010 +word: SLICEC.K1.INIT 0011110000111100 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0111110100101000 +word: SLICEB.K1.INIT 1101011110000010 +word: SLICEA.K1.INIT 1111110000001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: H01W0100 Q3 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0101 F1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 0001010111101010 +word: SLICEA.K1.INIT 1110101000010101 +word: SLICEB.K0.INIT 1110101000010101 +word: SLICEB.K1.INIT 0001010111101010 +word: SLICEC.K0.INIT 0111101101001000 +word: SLICEC.K1.INIT 1011011110000100 +word: SLICED.K0.INIT 1100001110101010 +word: SLICED.K1.INIT 0011110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C77:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 V01N0001 +arc: A0 V02S0701 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 V02S0701 +arc: A4 N1_V01N0101 +arc: A5 E1_H02W0701 +arc: A6 V00T0100 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q5 +arc: N1_V02N0301 Q3 +arc: V00T0100 Q3 +arc: V01S0000 F4 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 0011101011001010 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 0101110010101100 +word: SLICED.K1.INIT 1110010001001110 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEA.K1.INIT 1100101000111010 +word: SLICEB.K0.INIT 0110111101100000 +word: SLICEB.K1.INIT 0110111101100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C78:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 H02W0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: A0 H02W0701 +arc: A1 H02E0701 +arc: A2 H00L0100 +arc: A3 H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H02W0501 +arc: A7 H02W0501 +arc: B0 E1_H02W0301 +arc: B1 E1_H01W0100 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: B6 S1_V02N0701 +arc: B7 V02N0701 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H00L0100 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 Q1 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 0111110100101000 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0111001011011000 +word: SLICEC.K0.INIT 1110010001001110 +word: SLICEC.K1.INIT 0100111011100100 +word: SLICED.K0.INIT 0111101101001000 +word: SLICED.K1.INIT 1011011110000100 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R85C79:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 E1_H02W0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 V01S0000 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0501 Q5 +arc: V01S0000 F0 +arc: V01S0100 F4 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1101011110000010 +word: SLICEA.K1.INIT 0011101011001010 +word: SLICEB.K0.INIT 0111101101001000 +word: SLICEB.K1.INIT 1011011110000100 +word: SLICEC.K0.INIT 1011100001110100 +word: SLICEC.K1.INIT 0111010010111000 +word: SLICED.K0.INIT 0101110010101100 +word: SLICED.K1.INIT 1010110001011100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C80:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 S1_V02N0301 +arc: A5 Q5 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 H02E0401 +arc: C5 E1_H02W0401 +arc: C6 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H02E0201 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: H01W0000 F7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00T0100 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 F1 +arc: S1_V02S0401 Q6 +arc: S1_V02S0701 F7 +arc: V00B0000 Q6 +arc: V01S0100 F7 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1111000000001111 +word: SLICED.K1.INIT 0000111111110000 +word: SLICEA.K0.INIT 0111001011011000 +word: SLICEA.K1.INIT 1101100001110010 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0010111011100010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R85C81:PLC2 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0701 H06E0203 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 N1_V02S0301 + +.tile R85C82:PLC2 +arc: W1_H02W0401 S1_V02N0401 + +.tile R85C83:PLC2 +arc: W3_H06W0003 N3_V06S0003 + +.tile R86C17:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R86C23:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R86C29:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R86C32:PLC2 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0501 H06W0303 + +.tile R86C35:PLC2 +arc: N1_V02N0501 H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R86C37:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 H06W0203 + +.tile R86C38:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 H02E0701 + +.tile R86C39:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 + +.tile R86C40:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 F5 +arc: A3 F5 +arc: B0 V02S0101 +arc: B2 E1_H01W0100 +arc: B3 V01N0001 +arc: B7 N1_V01S0000 +arc: C0 H02W0401 +arc: C3 H02W0401 +arc: C5 E1_H02W0601 +arc: C7 H02W0401 +arc: D2 V02S0201 +arc: D3 V00B0100 +arc: D5 E1_H02W0001 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1111000000001111 +word: SLICEB.K0.INIT 1100110000110011 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEA.K0.INIT 0110100101101001 +word: SLICEB.K1.INIT 1001011001101001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R86C41:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 H01E0001 +arc: H00L0100 V02N0301 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V01N0101 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A3 F5 +arc: A4 F5 +arc: A5 Q5 +arc: A6 V02S0101 +arc: A7 E1_H02W0501 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: B6 V02N0501 +arc: B7 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C4 Q4 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 0100000100010100 +word: SLICED.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICEA.K1.INIT 1110010011100100 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0000000001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C42:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: A1 H00L0100 +arc: A2 W1_H02E0501 +arc: A3 E1_H01E0001 +arc: A4 W1_H02E0501 +arc: A5 Q5 +arc: A6 W1_H02E0501 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V02N0601 +arc: D6 H02W0201 +arc: D7 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q6 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: S1_V02S0001 Q2 +arc: V00B0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0011111100101010 +word: SLICEB.K0.INIT 0011111100101010 +word: SLICEB.K1.INIT 0011111100101010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0011001011111010 +word: SLICED.K0.INIT 0100010011100100 +word: SLICED.K1.INIT 0011001011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C43:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06E0303 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A4 H02E0501 +arc: A5 H02W0701 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR1 H02W0501 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F5 +arc: S1_V02S0301 Q1 +arc: V00B0000 F6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1110111111100000 +word: SLICED.K0.INIT 0110100110010110 +word: SLICED.K1.INIT 1001011001101001 +word: SLICEA.K1.INIT 0000101011001010 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICEB.K1.INIT 0000000011111100 +word: SLICEC.K0.INIT 0111001001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C44:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0501 W3_H06E0303 +arc: A3 V02N0501 +arc: A4 E1_H02W0501 +arc: A5 W1_H02E0701 +arc: A7 H00R0000 +arc: B0 V01N0001 +arc: B1 Q1 +arc: B3 V02N0101 +arc: B6 V02N0701 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C4 V01N0101 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0701 F5 +arc: V00T0000 F2 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEC.K0.INIT 0000010101010000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1010010101011010 +word: SLICEA.K1.INIT 0000110011111100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000000010011001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C45:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0601 N3_V06S0303 + +.tile R86C46:PLC2 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 + +.tile R86C47:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 + +.tile R86C48:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W3_H06E0003 + +.tile R86C49:PLC2 +arc: N1_V02N0001 E1_H02W0001 + +.tile R86C50:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0601 H02W0601 + +.tile R86C51:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 H02W0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 N1_V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H02W0401 +arc: C4 Q4 +arc: C5 V00T0000 +arc: C6 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0303 Q6 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V01S0000 Q6 +word: SLICED.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111000011001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C52:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 N1_V01S0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 V02N0401 +arc: A6 F7 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 W1_H02E0201 +arc: D5 H00R0100 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q5 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q5 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1000000000100000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 1100111111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C53:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06S0003 +arc: A5 V02S0101 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: B5 V02S0701 +arc: C0 V02N0601 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 Q1 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q0 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0011001100100011 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C54:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0701 V06S0203 +arc: A1 W1_H02E0701 +arc: A2 V00T0000 +arc: A4 V00T0000 +arc: A5 E1_H01W0000 +arc: B0 H02E0301 +arc: B1 Q1 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B5 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C3 V02S0401 +arc: C4 V02N0201 +arc: C5 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 H00R0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 1000110010101111 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1010111110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C55:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0003 N1_V01S0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V02N0201 +arc: A4 V00T0000 +arc: A5 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C4 V02S0201 +arc: C5 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D4 H00L0100 +arc: D5 W1_H02E0001 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 1010001011110011 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1100111111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C56:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 V02N0101 +arc: A3 H02W0501 +arc: A6 H02W0701 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H02E0301 +arc: B3 Q3 +arc: B6 V00B0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 W1_H02E0601 +arc: C5 V00T0100 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D5 W1_H02E0001 +arc: D6 H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: V00T0100 Q3 +arc: V01S0100 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 F6 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1000010010100101 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110111001000100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C57:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0501 V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0100 +arc: A5 Q5 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B7 H02W0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 V02N0601 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 Q6 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H02E0001 +arc: D2 W1_H02E0001 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 Q3 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +arc: W1_H02W0301 Q3 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1010101011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C58:PLC2 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 V02N0601 +arc: A2 H00L0100 +arc: A3 H01E0001 +arc: A4 F7 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B7 V01S0000 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 N1_V02S0401 +arc: C4 W1_H02E0401 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: N3_V06N0003 Q3 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 0100011111001111 +word: SLICEC.K0.INIT 1011101100001011 +word: SLICEB.K1.INIT 0011111101010101 +word: SLICEB.K0.INIT 1010001011110011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R86C59:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02S0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C60:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 N3_V06S0303 + +.tile R86C61:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V06S0203 + +.tile R86C62:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 W3_H06E0103 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: A0 F5 +arc: A2 F5 +arc: B0 H00R0100 +arc: B2 H00L0000 +arc: B5 H02E0101 +arc: C0 H02E0401 +arc: C2 H02W0601 +arc: C3 H00L0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H00R0000 +arc: D3 H02W0001 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEA.K0.INIT 1000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C63:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A2 V02S0501 +arc: A4 V02N0301 +arc: B0 V02S0101 +arc: B1 H02W0101 +arc: B2 E1_H02W0301 +arc: B4 H00L0000 +arc: B7 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 F4 +arc: C3 H00L0000 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 E1_H02W0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0701 F7 +arc: V01S0100 Q0 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K1.INIT 0000111111111111 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R86C64:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 H06W0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A6 N1_V01N0101 +arc: B0 H00R0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B4 H02W0301 +arc: B5 V01S0000 +arc: B6 H02W0301 +arc: C0 F4 +arc: C1 F6 +arc: C2 H02E0401 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q1 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0011001111111111 +word: SLICEA.K0.INIT 1000111100001111 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K1.INIT 0000111111111111 +word: SLICED.K0.INIT 0000011101110111 +word: SLICEA.K1.INIT 1000111100001111 +word: SLICEB.K0.INIT 1000111100001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C65:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0203 E1_H01W0000 + +.tile R86C66:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0401 N3_V06S0203 +arc: A0 F5 +arc: A1 H02W0701 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 H02W0501 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B5 E1_H02W0301 +arc: C0 H00R0100 +arc: C1 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0100 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00R0100 +arc: D5 V02S0601 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0701 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1100111011101100 +word: SLICEB.K1.INIT 1110110011001110 +word: SLICEC.K1.INIT 1000001000101000 +word: SLICEA.K0.INIT 1010111110101010 +word: SLICEA.K1.INIT 0101000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C67:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0101 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H06W0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 V06S0203 +arc: A0 H00L0000 +arc: A1 E1_H01E0001 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 E1_H02W0301 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: B7 F1 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0501 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: V01S0000 F6 +arc: V01S0100 F2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1010111011101010 +word: SLICEB.K1.INIT 1110101010101110 +word: SLICEC.K0.INIT 1110101110101010 +word: SLICEC.K1.INIT 1101111011001100 +word: SLICEA.K0.INIT 0100111101000100 +word: SLICEA.K1.INIT 0000101000001010 +word: SLICED.K0.INIT 1100111011101100 +word: SLICED.K1.INIT 1110110011001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C68:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: A6 E1_H02W0701 +arc: A7 E1_H02W0501 +arc: B0 V02N0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 W1_H02E0301 +arc: B5 W1_H02E0301 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR1 H02W0501 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 F6 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 0010111011100010 +word: SLICEA.K1.INIT 1110001000101110 +word: SLICEB.K0.INIT 1000111110001000 +word: SLICEB.K1.INIT 0000110010101110 +word: SLICEC.K0.INIT 1110110011011100 +word: SLICEC.K1.INIT 1101110011101100 +word: SLICED.K0.INIT 1111111110010000 +word: SLICED.K1.INIT 1111111101100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C69:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 N1_V02S0701 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02N0301 +arc: A5 V02N0301 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 V02N0301 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V02S0701 +arc: B7 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0100 F5 +arc: H01W0000 Q3 +arc: H01W0100 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q1 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q1 +word: SLICEC.K0.INIT 0111110100101000 +word: SLICEC.K1.INIT 1101011110000010 +word: SLICED.K0.INIT 1101011110000010 +word: SLICED.K1.INIT 0111110100101000 +word: SLICEB.K0.INIT 0010111011100010 +word: SLICEB.K1.INIT 1110001000101110 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0100111011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C70:PLC2 +arc: H00R0000 V02S0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 V06S0103 +arc: A0 E1_H02W0501 +arc: A2 V00T0000 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: A7 N1_V02S0301 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0701 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V00T0100 +arc: D2 N1_V01S0000 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: LSR1 V00B0100 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1011100001110100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0111110100101000 +word: SLICEC.K1.INIT 1101011110000010 +word: SLICED.K0.INIT 1101011110000010 +word: SLICED.K1.INIT 0111110100101000 +word: SLICEB.K0.INIT 0101101010100101 +word: SLICEB.K1.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R86C71:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 N1_V01S0000 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A0 H00L0100 +arc: A1 H00L0100 +arc: A4 V02S0301 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B4 V02S0701 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C4 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D4 H00R0100 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F4 +arc: H01W0100 F0 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 1100101000111010 +word: SLICEA.K1.INIT 0011101011001010 +word: SLICEC.K0.INIT 0001111011100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R86C72:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: W3_H06W0303 V01N0101 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: C0 V02N0601 +arc: C2 V02S0401 +arc: C3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100110000000101 +word: SLICEB.K1.INIT 1111000001010101 +word: SLICEA.K0.INIT 1100111100000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C73:PLC2 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0303 V06S0303 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 E1_H02W0301 +arc: B1 W1_H02E0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0301 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 N1_V02S0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D0 H00R0000 +arc: D1 S1_V02N0001 +arc: D2 H00R0000 +arc: D3 V02S0201 +arc: D4 N1_V02S0601 +arc: D5 N1_V02S0401 +arc: D6 H02E0201 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 0011110011000011 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C74:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 V06S0003 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 V06S0203 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 V00T0000 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: B6 V00T0000 +arc: B7 V02S0701 +arc: C0 H00R0100 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 0011110000110011 +word: SLICEA.K1.INIT 1010010111110000 +word: SLICEB.K0.INIT 1010010111110000 +word: SLICEB.K1.INIT 0101101000001111 +word: SLICEC.K0.INIT 0011000111001110 +word: SLICEC.K1.INIT 1100111000110001 +word: SLICED.K0.INIT 1100110000111001 +word: SLICED.K1.INIT 0011000111001110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C75:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0100 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 E1_H02W0101 +arc: B1 V02S0301 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: LSR0 E1_H02W0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0110011001101001 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEB.K0.INIT 1101011110000010 +word: SLICEB.K1.INIT 0111110100101000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C76:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V01N0101 +arc: H00L0100 V02N0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0301 V02N0301 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 H02W0001 +arc: D6 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 W1_H02E0001 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 W1_H02E0001 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 1001011001101001 +word: SLICED.K1.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R86C77:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V01N0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02E0501 +arc: A2 N1_V02S0701 +arc: A4 N1_V01N0101 +arc: A5 W1_H02E0501 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B4 W1_H02E0101 +arc: B5 V00B0100 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 N1_V02S0601 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 H00R0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q0 +arc: V00B0100 Q5 +arc: V01S0000 F4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0110111101100000 +word: SLICEB.K1.INIT 0011110011000011 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0101110010101100 +word: SLICED.K0.INIT 1001111110010000 +word: SLICED.K1.INIT 0110111101100000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0111101101001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 V02N0601 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B2 V02S0101 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 V00B0100 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V00T0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 W1_H02E0401 +arc: M5 H00R0100 +arc: M6 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1111000000001111 +word: SLICEA.K0.INIT 0011110011000011 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 0100111011100100 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 1110010001001110 +word: SLICED.K1.INIT 0100111011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C79:PLC2 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02N0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 V00T0100 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 H01E0101 +arc: B5 H01E0101 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 V02S0401 +arc: C1 H02E0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H00R0000 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H00R0100 F5 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR1 H02E0501 +arc: M0 W1_H02E0601 +arc: M1 H02E0001 +arc: M2 W1_H02E0601 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V02N0101 Q3 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 1110010001001110 +word: SLICEA.K1.INIT 0111001011011000 +word: SLICEB.K0.INIT 0100111011100100 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 1100101000111010 +word: SLICEC.K1.INIT 0011101011001010 +word: SLICED.K0.INIT 0011101011001010 +word: SLICED.K1.INIT 1100101000111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C80:PLC2 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0701 W1_H02E0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V06S0003 +arc: A0 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: B0 H02W0301 +arc: B2 H00R0100 +arc: B3 Q3 +arc: C0 V02S0601 +arc: C2 V02S0601 +arc: C3 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F2 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1101011110000010 +word: SLICEB.K1.INIT 0100111011100100 +word: SLICEA.K0.INIT 0111110100101000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R86C81:PLC2 +arc: W1_H02W0301 V06S0003 + +.tile R87C11:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R87C17:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R87C23:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R87C29:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R87C2:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R87C35:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R87C37:PLC2 +arc: N1_V02N0501 E1_H02W0501 + +.tile R87C38:PLC2 +arc: E1_H02E0701 V06S0203 + +.tile R87C39:PLC2 +arc: N1_V02N0701 H02E0701 +arc: W1_H02W0501 N3_V06S0303 + +.tile R87C40:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 E1_H01W0000 +arc: V00B0000 E1_H02W0601 +arc: A0 H00L0000 +arc: B0 V00B0000 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000101011001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C41:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 V02S0501 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 H00L0100 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: A6 N1_V02S0101 +arc: A7 H00L0000 +arc: B1 V02N0101 +arc: B4 H02W0101 +arc: B5 V01S0000 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C0 H02W0401 +arc: C2 V02N0401 +arc: C3 F6 +arc: C5 V00T0000 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: D3 H02W0001 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +arc: W3_H06W0103 Q2 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICED.K1.INIT 0110100110010110 +word: SLICEC.K1.INIT 0110100110010110 +word: SLICEC.K0.INIT 0110011010011001 +word: SLICED.K0.INIT 0110011010011001 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1101110110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R87C42:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 H00R0000 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B1 W1_H02E0301 +arc: B3 H02W0301 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V02S0701 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 E1_H02W0601 +arc: C6 H02E0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q3 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0000110000000011 +word: SLICEC.K1.INIT 0000100100000110 +word: SLICED.K0.INIT 1001011010010110 +word: SLICEA.K1.INIT 0110100110010110 +word: SLICED.K1.INIT 0101101010100101 +word: SLICEC.K0.INIT 1001011001101001 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C43:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 H02W0601 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 F5 +arc: A1 H00R0000 +arc: A3 H02W0501 +arc: A7 W1_H02E0701 +arc: B2 H00L0000 +arc: B4 V02N0701 +arc: B7 H01E0101 +arc: C0 S1_V02N0601 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H02W0601 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0601 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V02N0201 Q0 +arc: V01S0000 F7 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 F1 +word: SLICEB.K0.INIT 0011110011000011 +word: SLICEA.K1.INIT 0101101010100101 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0011001111001100 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 0000101000000101 +word: SLICED.K1.INIT 1001000010010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R87C44:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02S0701 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: A3 V02S0701 +arc: A5 W1_H02E0701 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B7 V02S0701 +arc: C0 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: D0 F2 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F7 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0701 F5 +arc: W1_H02W0501 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 0011001111001100 +word: SLICEC.K1.INIT 0101010110101010 +word: SLICEA.K1.INIT 1001100101100110 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000100100000110 +word: SLICEB.K0.INIT 0110011010011001 +word: SLICEA.K0.INIT 0000100100000110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R87C45:PLC2 +arc: N1_V02N0201 W1_H02E0201 + +.tile R87C46:PLC2 +arc: E3_H06E0103 V01N0101 +arc: N1_V02N0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 + +.tile R87C47:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R87C48:PLC2 +arc: A0 V02N0701 +arc: B0 V02N0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110101011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C49:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 V02N0401 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A5 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 V01N0001 +arc: B5 V01S0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C5 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D5 V02N0401 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0110011011000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 1000110010101111 +word: SLICEC.K1.INIT 0000001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R87C50:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 E1_H01W0100 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0501 N3_V06S0303 +arc: A0 H00L0000 +arc: A4 E1_H01W0000 +arc: A6 H02E0701 +arc: B0 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B6 V02N0701 +arc: C0 H00L0100 +arc: C4 S1_V02N0001 +arc: C6 F4 +arc: D0 H02W0201 +arc: D4 W1_H02E0201 +arc: D6 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R87C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0000 V02N0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: V00T0000 H02W0201 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 H02E0701 +arc: A3 H00L0100 +arc: A4 N1_V02S0101 +arc: B0 V02N0101 +arc: B1 H02E0301 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B4 V02S0501 +arc: C0 N1_V01N0001 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D2 V02N0001 +arc: D3 W1_H02E0201 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111100010001000 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R87C52:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02S0401 +arc: A3 N1_V02S0501 +arc: A4 N1_V02S0301 +arc: A5 V00B0000 +arc: B0 E1_H02W0101 +arc: B2 V02S0301 +arc: B6 V00T0000 +arc: B7 V02S0501 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R87C53:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0001 N1_V01S0000 +arc: W3_H06W0003 E3_H06W0003 +arc: F0 F0_SLICE +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R87C54:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 N1_V01S0100 +arc: A4 V00B0000 +arc: A5 N1_V02S0301 +arc: B0 N1_V02S0101 +arc: B2 V02S0301 +arc: B3 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 V00T0000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0101010101010000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R87C55:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N1_V01S0000 +arc: F0 F0_SLICE +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R87C56:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: W1_H02W0001 N1_V02S0001 + +.tile R87C57:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 N1_V01S0100 + +.tile R87C58:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0601 N3_V06S0303 + +.tile R87C59:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N3_V06S0203 +arc: W3_H06W0003 E3_H06W0003 + +.tile R87C5:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R87C61:PLC2 +arc: E1_H02E0001 E3_H06W0003 + +.tile R87C62:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 + +.tile R87C63:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 E3_H06W0303 + +.tile R87C64:PLC2 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 + +.tile R87C65:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02N0301 +arc: C0 S1_V02N0601 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 H00R0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0100 F3 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R87C66:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A6 E1_H01W0000 +arc: B0 H02W0301 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H00R0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 F2 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N3_V06N0203 Q4 +arc: V01S0100 F0 +word: SLICED.K0.INIT 0000000010101010 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 1111111100101000 +word: SLICEA.K1.INIT 1111111110000010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C67:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V06S0003 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0301 H06W0003 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 V02N0301 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0101 +arc: A5 V02S0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 S1_V02N0701 +arc: B5 S1_V02N0501 +arc: C0 N1_V02S0401 +arc: C1 N1_V02S0401 +arc: C2 F6 +arc: C3 F6 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: H00R0100 F7 +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02W0601 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M7 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0701 Q5 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: W1_H02W0101 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 1010111011101010 +word: SLICEA.K1.INIT 1110101010101110 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEB.K0.INIT 1111100111110000 +word: SLICEB.K1.INIT 1111011011110000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111111100101000 +word: SLICEC.K1.INIT 1111111110000010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C68:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q3 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 F2 +arc: H01W0100 F4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H01W0100 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 W1_H02E0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q7 +arc: V01S0100 Q1 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1110001000101110 +word: SLICEA.K1.INIT 0010111011100010 +word: SLICEB.K0.INIT 0010111011100010 +word: SLICEB.K1.INIT 1110001000101110 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111101101001000 +word: SLICED.K0.INIT 1110001000101110 +word: SLICED.K1.INIT 0010111011100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C69:PLC2 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02N0301 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 N1_V01N0101 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 H02W0301 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C1 H00R0100 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00L0100 +arc: D5 H00L0100 +arc: D6 W1_H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H00R0100 Q5 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEB.K0.INIT 1110001000101110 +word: SLICEB.K1.INIT 0010111011100010 +word: SLICEC.K0.INIT 1011011110000100 +word: SLICEC.K1.INIT 0111110100101000 +word: SLICED.K0.INIT 1100001110101010 +word: SLICED.K1.INIT 0011101011001010 +word: SLICEA.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R87C70:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 H01E0101 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 S1_V02N0301 +arc: B1 H02E0301 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V02S0501 +arc: C0 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: C6 E1_H01E0101 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 N1_V02S0401 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: V01S0100 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0011101011001010 +word: SLICEB.K1.INIT 1100101000111010 +word: SLICEC.K0.INIT 1110101010101110 +word: SLICEC.K1.INIT 1010111011101010 +word: SLICED.K0.INIT 1011111010101010 +word: SLICED.K1.INIT 1110101110101010 +word: SLICEA.K0.INIT 0011000011111111 +word: SLICEA.K1.INIT 1100110000110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R87C71:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A5 N1_V02S0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B3 E1_H02W0301 +arc: B7 S1_V02N0701 +arc: C0 N1_V01N0001 +arc: C3 H00L0100 +arc: C5 V01N0101 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 H02E0201 +arc: D3 E1_H02W0001 +arc: D4 H00L0100 +arc: D5 E1_H02W0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M3 H00R0000 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0101010100000001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C72:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0303 N1_V01S0100 +arc: A0 H01E0001 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F5 +arc: LSR0 V00T0100 +arc: M4 H02E0401 +arc: M5 H02E0001 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V01S0000 Q0 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 1010010111110000 +word: SLICEC.K1.INIT 0101101000001111 +word: SLICED.K0.INIT 1001100111001001 +word: SLICED.K1.INIT 0011001111000110 +word: SLICEA.K0.INIT 1111010100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C73:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0601 H02E0601 +arc: V00B0000 H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A5 V02S0101 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C6 V02S0201 +arc: C7 V00T0100 +arc: D0 V02S0201 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: D6 H00L0100 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 H02W0401 +arc: M5 H00R0000 +arc: M6 H02W0401 +arc: N3_V06N0003 F3 +word: SLICEA.K0.INIT 1011010001001011 +word: SLICEA.K1.INIT 1001011011000011 +word: SLICEB.K0.INIT 0110100100111100 +word: SLICEB.K1.INIT 0110100100111100 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 1001101001100101 +word: SLICED.K0.INIT 0011110011000011 +word: SLICED.K1.INIT 0110010110011010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R87C74:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H06W0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 N3_V06S0303 + +.tile R87C75:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 S1_V02N0401 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 H00L0100 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A6 N1_V02S0101 +arc: A7 N1_V02S0101 +arc: B0 N1_V02S0101 +arc: B1 N1_V02S0101 +arc: B2 H00R0100 +arc: B3 N1_V02S0101 +arc: B5 V00B0100 +arc: B7 V00T0000 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H00L0100 +arc: D5 S1_V02N0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1001100101101001 +word: SLICEA.K1.INIT 1001100101101001 +word: SLICEB.K0.INIT 0110011010010110 +word: SLICEB.K1.INIT 0110011010010110 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 1001011010011001 +word: SLICED.K0.INIT 0101101010100101 +word: SLICED.K1.INIT 0101100110100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R87C76:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H01W0000 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: M0 E1_H02W0601 +arc: M1 H02W0001 +arc: M2 E1_H02W0601 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F4 +word: SLICEC.K0.INIT 1010101010100101 +word: SLICEA.K0.INIT 1010111101010000 +word: SLICEA.K1.INIT 0101000010101111 +word: SLICEB.K0.INIT 1011101001000101 +word: SLICEB.K1.INIT 0100010110111010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R87C77:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0103 H01E0101 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 V02S0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 V01N0101 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0301 +arc: B0 H00R0100 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 N1_V02S0701 +arc: B5 N1_V02S0701 +arc: B6 V02N0701 +arc: C0 V02N0601 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q3 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICED.K1.INIT 0000111111110000 +word: SLICED.K0.INIT 0001111011100001 +word: SLICEB.K0.INIT 1100101000111010 +word: SLICEB.K1.INIT 0011101011001010 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEC.K0.INIT 0010111011100010 +word: SLICEC.K1.INIT 1110001000101110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C78:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H02E0701 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00L0100 +arc: A1 H02E0701 +arc: B0 E1_H01W0100 +arc: B1 E1_H01W0100 +arc: B4 N1_V02S0501 +arc: C0 N1_V02S0601 +arc: C1 H00L0100 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: M0 W1_H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F4 +arc: V01S0100 F0 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 0011110011000011 +word: SLICEA.K0.INIT 0011110010101010 +word: SLICEA.K1.INIT 1101100001110010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C79:PLC2 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: A0 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: A6 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 V02S0301 +arc: B3 Q3 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C1 N1_V02S0601 +arc: C2 H02W0401 +arc: C3 H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0401 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 E1_H02W0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M3 H00L0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F1 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 F1 +arc: V01S0100 F5 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 0111110100101000 +word: SLICEB.K1.INIT 1110010001001110 +word: SLICEC.K0.INIT 0100111011100100 +word: SLICEC.K1.INIT 1110010001001110 +word: SLICED.K0.INIT 1110010001001110 +word: SLICED.K1.INIT 0100111011100100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R87C80:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06S0303 + +.tile R87C81:PLC2 +arc: W1_H02W0001 S1_V02N0001 + +.tile R87C82:PLC2 +arc: N1_V02N0401 W3_H06E0203 + +.tile R88C41:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: V00T0100 N1_V02S0501 +arc: A0 V02S0501 +arc: C0 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0101111101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C42:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0001 +arc: A0 E1_H02W0501 +arc: A1 H02W0501 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B1 Q1 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 H02W0301 +arc: C0 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C6 H02W0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: V01S0000 Q4 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +word: SLICED.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R88C43:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A0 F5 +arc: A1 H00L0100 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A5 V02N0301 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 V02N0301 +arc: B6 S1_V02N0501 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K1.INIT 0000000000001010 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEB.K1.INIT 1100101010101010 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1100000000000000 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 1111011111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C44:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H01E0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0501 +arc: A2 E1_H01E0001 +arc: B0 F1 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: C0 E1_H02W0401 +arc: C2 H02W0601 +arc: C4 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D4 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111101101000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEB.K0.INIT 0111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R88C45:PLC2 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H01E0001 +arc: A1 F7 +arc: A6 E1_H01W0000 +arc: B5 H00R0000 +arc: B6 H01E0101 +arc: B7 H02W0301 +arc: C0 H00R0100 +arc: C2 H02E0601 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: D0 E1_H02W0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D5 E1_H02W0201 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: S1_V02S0701 F5 +arc: W1_H02W0001 F2 +word: SLICED.K1.INIT 1100000011000000 +word: SLICED.K0.INIT 0000000001110101 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEC.K1.INIT 0000110011001100 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1010000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R88C46:PLC2 +arc: H00R0000 V02N0401 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0401 V02N0401 +arc: A0 H00L0100 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V02N0101 +arc: B3 H00R0000 +arc: B5 V01S0000 +arc: C0 N1_V01N0001 +arc: C2 H00L0100 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D5 V02N0401 +arc: D7 V02N0601 +arc: E1_H02E0101 Q1 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 Q1 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 F5 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F5 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 F2 +arc: W1_H02W0301 Q1 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1011101100000010 +word: SLICEB.K1.INIT 0011000000010001 +word: SLICEB.K0.INIT 1111000011110101 +word: SLICEC.K1.INIT 0011001100110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R88C47:PLC2 +arc: W1_H02W0201 V02N0201 + +.tile R88C48:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 W1_H02E0701 +arc: A0 W1_H02E0701 +arc: B0 W1_H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011001101010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C49:PLC2 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0001 +arc: A2 H01E0001 +arc: A3 V00B0000 +arc: A5 V02N0101 +arc: B0 E1_H02W0101 +arc: B4 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 H02E0301 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: N1_V01N0001 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R88C50:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A3 V02S0701 +arc: A5 V02N0101 +arc: A7 E1_H01W0000 +arc: B2 V02S0101 +arc: B4 S1_V02N0701 +arc: B6 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F1 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R88C51:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H00R0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: A6 E1_H01W0000 +arc: A7 N1_V01N0101 +arc: B1 V00B0000 +arc: B4 F1 +arc: B5 V01S0000 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 E1_H01W0100 +arc: D6 F0 +arc: D7 V00B0000 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q5 +arc: H01W0100 F7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: V00B0000 Q4 +arc: V01S0000 Q5 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1110110010100000 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R88C52:PLC2 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 + +.tile R88C53:PLC2 +arc: N1_V02N0401 N1_V01S0000 + +.tile R88C58:PLC2 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 + +.tile R88C63:PLC2 +arc: E1_H02E0501 V02S0501 + +.tile R88C64:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00L0000 H02W0201 +arc: H00L0100 V02S0301 +arc: N1_V02N0301 H02W0301 +arc: A0 H00L0100 +arc: B0 V01N0001 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0101110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C65:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0201 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A3 F5 +arc: A5 H02W0501 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 V00B0000 +arc: B3 H00R0000 +arc: B4 F3 +arc: B5 V02N0701 +arc: B6 V02N0501 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C3 E1_H01W0000 +arc: C5 V00T0000 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D3 S1_V02N0001 +arc: D4 E1_H02W0201 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0601 F4 +arc: V01S0000 F3 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0000000000110011 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 0100010011110000 +word: SLICEA.K1.INIT 0000001111000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C66:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: V00T0000 H02W0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: A1 H01E0001 +arc: B1 E1_H01W0100 +arc: C0 F6 +arc: C1 H02W0601 +arc: C6 V00T0000 +arc: D0 H01E0101 +arc: D1 V02N0201 +arc: D6 V02S0601 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: V01S0000 F0 +word: SLICED.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R88C67:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0000 H02W0401 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 V01N0001 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: C0 V02N0601 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0111001001010000 +word: SLICEA.K1.INIT 0101110100001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C68:PLC2 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 V02S0401 +arc: A0 H02E0701 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0100111101000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C69:PLC2 +arc: N1_V02N0101 H06W0103 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: A0 F7 +arc: A7 H02W0701 +arc: B0 V02S0301 +arc: B1 V02N0301 +arc: B3 V02N0301 +arc: B4 V02S0701 +arc: B7 N1_V02S0501 +arc: C0 V02N0601 +arc: C1 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D3 V02S0001 +arc: D4 E1_H02W0201 +arc: D7 V00B0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 F3 +arc: N3_V06N0203 F7 +arc: V01S0000 F7 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 1011011110000100 +word: SLICEA.K1.INIT 0011110011000011 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 0011110011000011 +word: SLICED.K1.INIT 1001011001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C70:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02S0501 +arc: B0 V02N0301 +arc: B3 V02N0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D3 V00B0100 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR1 V00B0000 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 F2 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1011101111110000 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C71:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: A0 E1_H02W0701 +arc: A7 E1_H01W0000 +arc: B0 V02S0101 +arc: B3 H00R0100 +arc: B5 H02E0301 +arc: C0 V02N0401 +arc: C3 H02W0401 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D7 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 E1_H02W0601 +arc: M3 H00L0000 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q3 +arc: V00B0100 Q7 +arc: V01S0000 F4 +arc: V01S0100 Q3 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111111000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: B1 W1_H02E0301 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V02S0001 +arc: F0 F5A_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: M0 H02W0601 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00T0000 F0 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R88C73:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H01E0001 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00L0000 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V02S0301 +arc: A5 N1_V02S0301 +arc: A6 H00L0000 +arc: A7 H00L0000 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B5 H00L0000 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 N1_V02S0201 +arc: C5 V00B0100 +arc: C6 N1_V02S0001 +arc: C7 N1_V02S0001 +arc: D0 V00B0100 +arc: D1 N1_V02S0201 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02W0401 +arc: M5 H02W0001 +arc: M6 H02W0401 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0011100111000110 +word: SLICEB.K0.INIT 0011011011001001 +word: SLICEB.K1.INIT 0011011011001001 +word: SLICEC.K0.INIT 0101101010100101 +word: SLICEC.K1.INIT 0110011010010110 +word: SLICED.K0.INIT 0101101001011010 +word: SLICED.K1.INIT 0101101001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C74:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0303 V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 V01N0101 + +.tile R88C75:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 W3_H06E0003 +arc: V00B0000 E1_H02W0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 E1_H02W0401 +arc: M5 H02E0001 +arc: M6 E1_H02W0401 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 0110011010010110 +word: SLICEA.K1.INIT 0110011010010110 +word: SLICEB.K0.INIT 0110011001101001 +word: SLICEB.K1.INIT 0110011001101001 +word: SLICEC.K0.INIT 0110100101101001 +word: SLICEC.K1.INIT 0110100101100110 +word: SLICED.K0.INIT 0011110000111100 +word: SLICED.K1.INIT 0110011001101001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C76:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 H02E0701 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0701 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 H02W0401 +arc: C5 H02W0401 +arc: C6 H02W0401 +arc: C7 H02W0401 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0401 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00R0000 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1010101001011010 +word: SLICEA.K1.INIT 0101010110100101 +word: SLICEB.K0.INIT 0101010110100101 +word: SLICEB.K1.INIT 1010101001011010 +word: SLICEC.K0.INIT 1001100111001001 +word: SLICEC.K1.INIT 0110011000110110 +word: SLICED.K0.INIT 0110011000110110 +word: SLICED.K1.INIT 1001100111001001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C77:PLC2 +arc: H00L0100 V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A5 V02S0301 +arc: A7 V02S0301 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0501 +arc: B5 V02S0501 +arc: B6 V02S0501 +arc: B7 V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V00B0100 +arc: C5 W1_H02E0401 +arc: C6 V00B0100 +arc: C7 W1_H02E0401 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0110100101100110 +word: SLICEB.K0.INIT 1001011010011001 +word: SLICEB.K1.INIT 1001011010011001 +word: SLICEC.K0.INIT 0011110011000011 +word: SLICEC.K1.INIT 0110100101100110 +word: SLICED.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1001011010011001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R88C78:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0601 S1_V02N0601 + +.tile R88C79:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H02W0601 + +.tile R88C80:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R88C81:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R89C12:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C15:PLC2 +arc: N3_V06N0203 H06W0203 + +.tile R89C18:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R89C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C21:PLC2 +arc: N3_V06N0103 H06W0103 + +.tile R89C24:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R89C25:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R89C30:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R89C31:PLC2 +arc: E1_H02E0001 W3_H06E0003 + +.tile R89C33:PLC2 +arc: V00T0000 W1_H02E0001 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0203 Q4 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C36:PLC2 +arc: N3_V06N0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C39:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R89C3:PLC2 +arc: N3_V06N0303 H06W0303 + +.tile R89C40:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 + +.tile R89C41:PLC2 +arc: V00B0100 W1_H02E0701 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C42:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: W3_H06W0203 E3_H06W0103 + +.tile R89C43:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0401 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 V02S0701 +arc: A3 E1_H01E0001 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 Q3 +arc: B6 V02N0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 F6 +arc: C4 V02N0001 +arc: C6 H02E0601 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 N1_V01S0000 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D4 E1_H02W0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: W1_H02W0001 Q2 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1111110001001100 +word: SLICEA.K1.INIT 1111101000101010 +word: SLICEB.K0.INIT 1011111110100000 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICED.K0.INIT 0011000000000000 +word: SLICEB.K1.INIT 1111010011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C44:PLC2 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 H02W0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 H02W0701 +arc: A3 H00L0100 +arc: A7 H02W0501 +arc: B0 V02S0301 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V01S0000 +arc: C0 V02S0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0401 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: C6 V02N0201 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V02S0001 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 F6 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 0110000010100000 +word: SLICEA.K0.INIT 0101110110000000 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEC.K1.INIT 0000110000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R89C45:PLC2 +arc: N1_V02N0301 H01E0101 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0701 +arc: B2 E1_H01W0100 +arc: B3 V02N0301 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F5 +arc: N1_V01N0101 F6 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0011001100110000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICED.K1.INIT 0011001100110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C46:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 E1_H01W0000 +arc: D2 V02N0201 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R89C47:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: W1_H02W0101 W3_H06E0103 + +.tile R89C48:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C49:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00R0100 V02S0501 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: B0 V02S0101 +arc: B1 Q1 +arc: C0 H02W0401 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V02S0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C50:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H00R0000 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: B0 H00R0100 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D2 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C51:PLC2 +arc: N1_V02N0101 H06W0103 +arc: N3_V06N0103 H06W0103 + +.tile R89C52:PLC2 +arc: W1_H02W0401 W3_H06E0203 + +.tile R89C54:PLC2 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C57:PLC2 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 H06W0103 + +.tile R89C60:PLC2 +arc: N3_V06N0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R89C64:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 E1_H02W0201 +arc: V00T0000 E1_H02W0201 +arc: B0 V00T0000 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 H02W0301 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C65:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0301 V01N0101 +arc: A0 H00R0000 +arc: A2 V02S0701 +arc: A3 H02W0701 +arc: A6 N1_V01S0100 +arc: B1 E1_H01W0100 +arc: B4 E1_H02W0301 +arc: B5 V02N0701 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R89C66:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 +arc: A4 W1_H02E0701 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: B4 H00R0000 +arc: B5 H02E0301 +arc: B6 V01S0000 +arc: B7 H01E0101 +arc: C4 Q4 +arc: C5 V00T0100 +arc: C6 V00T0000 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 H02W0201 +arc: D5 H02W0201 +arc: D6 H02W0201 +arc: D7 H02W0001 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: LSR1 H02E0501 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V00B0100 Q7 +arc: V01S0000 Q6 +arc: W1_H02W0401 Q4 +arc: W1_H02W0701 Q7 +word: SLICED.K0.INIT 0100010011110000 +word: SLICED.K1.INIT 0101000011001100 +word: SLICEC.K1.INIT 0000101011001100 +word: SLICEC.K0.INIT 0011000010101010 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R89C67:PLC2 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 H02W0401 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: A0 H00R0000 +arc: A1 H00L0100 +arc: A2 V00T0000 +arc: B0 H02W0301 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K1.INIT 0011101100001000 +word: SLICEB.K0.INIT 0101110100001000 +word: SLICEA.K0.INIT 0000111110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C68:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 F7 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A5 N1_V01N0101 +arc: A7 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 H01W0100 +arc: B5 H00L0000 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H01W0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M3 H00R0000 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q3 +arc: V00T0100 Q1 +arc: V01S0100 F6 +arc: W1_H02W0301 F3 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICED.K1.INIT 1010000000000000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEA.K0.INIT 0110110000001100 +word: SLICEA.K1.INIT 0000110000111100 +word: SLICEB.K0.INIT 0110110000001100 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 0000000001101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R89C69:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 + +.tile R89C6:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R89C70:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 + +.tile R89C71:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02W0701 +arc: V00B0100 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 V02S0101 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B0 V02S0101 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B5 S1_V02N0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0001 +arc: C7 H02E0401 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 E1_H02W0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0110100101100110 +word: SLICEA.K1.INIT 0110100101100110 +word: SLICEB.K0.INIT 1001011010011001 +word: SLICEB.K1.INIT 1001011010011001 +word: SLICEC.K0.INIT 0101101010100101 +word: SLICEC.K1.INIT 0110100101011010 +word: SLICED.K0.INIT 1010010101011010 +word: SLICED.K1.INIT 1001011010100101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R89C72:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 E1_H02W0401 +arc: C5 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02S0401 +arc: D5 V02S0401 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H02E0201 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 1010111101010000 +word: SLICEA.K1.INIT 0101000010101111 +word: SLICEB.K0.INIT 0101000010101111 +word: SLICEB.K1.INIT 1010111101010000 +word: SLICEC.K0.INIT 1001110010011001 +word: SLICEC.K1.INIT 0110001101100110 +word: SLICED.K0.INIT 0110001101100110 +word: SLICED.K1.INIT 1001110010011001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R89C73:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0101 + +.tile R89C74:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E3_H06W0103 +arc: W1_H02W0401 N3_V06S0203 + +.tile R89C75:PLC2 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0103 N3_V06S0103 + +.tile R89C76:PLC2 +arc: N1_V02N0401 W1_H02E0401 + +.tile R89C77:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 + +.tile R89C78:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R89C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R89C80:PLC2 +arc: W3_H06W0103 N3_V06S0103 + +.tile R89C81:PLC2 +arc: N1_V02N0001 W3_H06E0003 + +.tile R89C84:PLC2 +arc: N3_V06N0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R89C90:PLC2 +arc: F7 F7_SLICE +arc: N3_V06N0203 F7 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C15:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R8C18:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R8C21:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R8C27:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R8C33:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 + +.tile R8C39:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 + +.tile R8C40:PLC2 +arc: H00L0000 V02S0201 +arc: H00R0000 N1_V02S0601 +arc: A0 S1_V02N0501 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02S0101 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 H01W0100 +arc: B4 V02N0701 +arc: B6 N1_V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0401 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0101 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q7 +arc: H01W0000 F6 +arc: H01W0100 Q1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 E1_H02W0601 +arc: M1 H02E0001 +arc: M2 E1_H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEC.K0.INIT 1010101011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C41:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V02N0301 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02S0101 +arc: B1 Q1 +arc: B2 H02W0301 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 H00R0100 +arc: C1 F4 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 N1_V01S0000 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0401 +arc: D5 N1_V02S0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q1 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V01S0000 F6 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100111000000010 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C42:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 V02S0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 E1_H01E0001 +arc: A6 H02E0501 +arc: B0 V00B0000 +arc: B1 V02N0101 +arc: B3 H01W0100 +arc: B4 E1_H02W0101 +arc: B6 V02S0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H00R0100 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 V01S0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W1_H02W0301 Q1 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEA.K1.INIT 1000110111011000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1100110010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C43:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H02E0301 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 V02S0701 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: A6 V02S0101 +arc: B0 H01W0100 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 V01S0000 +arc: B5 V01S0000 +arc: C0 F4 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02W0401 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q5 +arc: S3_V06S0103 F2 +arc: V01S0000 Q0 +arc: V01S0100 Q5 +word: SLICEB.K0.INIT 1100010111001010 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C44:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00R0100 V02S0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V02S0701 +arc: A2 E1_H01E0001 +arc: B0 V02S0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 V02S0501 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H01E0001 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q7 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C45:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: V00B0000 N1_V02S0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: B0 V00T0000 +arc: B2 E1_H01W0100 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: LSR0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F2 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C46:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: V00B0000 S1_V02N0201 +arc: A0 H00L0000 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: B0 H02W0301 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C0 V02S0401 +arc: C2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 H02W0501 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEA.K0.INIT 1000101110001000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C47:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02N0201 +arc: N1_V02N0201 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: B0 V02N0301 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B4 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V02S0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0100 Q0 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q5 +arc: V00B0000 F4 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1010101000001100 +word: SLICED.K0.INIT 1111110000001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C48:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 E1_H01W0000 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 H02E0701 +arc: A2 V01N0101 +arc: B0 H02E0101 +arc: B2 H02W0101 +arc: B3 V01N0001 +arc: B4 V01S0000 +arc: B6 V02S0501 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 V02S0001 +arc: C6 H01E0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q3 +arc: V01S0100 F4 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C49:PLC2 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 V02S0701 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 S1_V02N0301 +arc: A0 H00L0000 +arc: A2 E1_H01E0001 +arc: A6 E1_H01W0000 +arc: B0 V02N0301 +arc: B2 V01N0001 +arc: B3 H00L0000 +arc: B4 V02N0701 +arc: C0 N1_V01N0001 +arc: C2 H02E0601 +arc: C3 V02N0601 +arc: C4 H01E0001 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D2 H02E0001 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: H01W0000 Q7 +arc: H01W0100 F6 +arc: LSR0 V00B0000 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 1010101000110000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C50:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 V02N0601 +arc: A0 W1_H02E0701 +arc: A2 V02S0701 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B4 H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 W1_H02E0601 +arc: C4 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D3 V01S0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E1_H01E0001 Q6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q5 +arc: LSR0 E1_H02W0501 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 Q5 +arc: V00B0100 Q5 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1000110111011000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C51:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0100 V02S0301 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 E1_H02W0701 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: B0 V01N0001 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 E1_H02W0001 +arc: D3 V01S0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111010000000100 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C52:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H00L0000 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A6 V02N0301 +arc: B0 V00T0000 +arc: B2 V02N0301 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C0 V02S0601 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 N1_V02S0001 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q5 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C53:PLC2 +arc: V00B0100 V02N0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0701 V02S0701 +arc: A0 H02E0501 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: F0 F5A_SLICE +arc: H01W0000 Q6 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0601 Q6 +arc: V00T0000 F0 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C57:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R8C63:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R8C66:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R8C7:PLC2 +arc: E1_H02E0201 S1_V02N0201 + +.tile R8C8:PLC2 +arc: V00T0000 H02E0201 +arc: CLK0 G_HPBX0000 +arc: D3 H02E0201 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 Q6 +arc: F3 F3_SLICE +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R8C9:PLC2 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q7 +arc: E3_H06E0203 Q4 +arc: H00R0000 Q6 +arc: LSR0 H02E0301 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 H02E0601 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C43:PLC2 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 + +.tile R90C44:PLC2 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: A0 H02W0701 +arc: B0 N1_V02S0301 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0101010110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C45:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 N1_V02S0701 +arc: B0 E1_H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0111001001010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C46:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: V00T0000 W1_H02E0201 +arc: A0 V02S0701 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 W1_H02E0701 +arc: A5 V02S0101 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0601 F6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R90C47:PLC2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R90C50:PLC2 +arc: N1_V02N0701 N1_V01S0100 + +.tile R90C64:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B7 H02W0101 +arc: C7 N1_V02S0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F7 +arc: F7 F7_SLICE +word: SLICED.K1.INIT 0000000000001000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R90C65:PLC2 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 N1_V02S0501 +arc: A1 H02E0701 +arc: A2 H02W0501 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 E1_H02W0101 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +word: SLICEA.K0.INIT 0011101011000000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 0111010000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C66:PLC2 +arc: H00R0000 V02S0601 +arc: W1_H02W0501 V06S0303 +arc: A0 H02E0701 +arc: A1 H00L0100 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +word: SLICEA.K0.INIT 0010001011100010 +word: SLICEA.K1.INIT 0011000010111000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R90C67:PLC2 +arc: W1_H02W0101 N1_V01S0100 + +.tile R90C68:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile R90C70:PLC2 +arc: N1_V02N0301 N3_V06S0003 + +.tile R90C71:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N3_V06S0203 + +.tile R90C72:PLC2 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 + +.tile R90C78:PLC2 +arc: N1_V02N0601 W3_H06E0303 + +.tile R91C71:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 N3_V06S0203 + +.tile R91C75:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R9C39:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: H00L0100 H02W0301 +arc: V00B0000 V02N0001 +arc: A0 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: S1_V02S0201 F0 +word: SLICEA.K0.INIT 1111000001100110 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R9C40:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0701 H06W0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V02S0501 +arc: A4 V02S0301 +arc: B0 H02W0101 +arc: B1 Q1 +arc: B2 S1_V02N0301 +arc: C0 H00L0000 +arc: C1 N1_V01S0100 +arc: C4 E1_H01E0101 +arc: C5 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: V00B0100 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C41:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0701 +arc: A3 V00T0000 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 N1_V02S0101 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B4 V01S0000 +arc: B6 H02W0101 +arc: C0 H00L0000 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: D6 S1_V02N0601 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q1 +arc: LSR1 V00B0000 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0301 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1101000111000000 +word: SLICEC.K0.INIT 1010001110101100 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100010111001010 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C42:PLC2 +arc: E1_H02E0601 V06N0303 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0101 H01E0101 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0201 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B6 V02S0701 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 E1_H02W0601 +arc: C3 H02W0601 +arc: C4 V02S0201 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H01W0000 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 E1_H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: S1_V02S0201 Q0 +arc: S3_V06S0203 Q7 +arc: V00T0100 Q1 +arc: W1_H02W0101 Q1 +word: SLICEB.K0.INIT 1100110001011010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C43:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A4 V02S0301 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B2 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: C0 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0201 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 H01E0101 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 Q1 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: H00R0100 Q7 +arc: H01W0000 Q1 +arc: H01W0100 Q7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M5 V01S0000 +arc: M6 H02W0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 F2 +arc: V01S0100 F6 +arc: W1_H02W0701 Q7 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 1010101000111100 +word: SLICEA.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C44:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0100 +arc: A5 V00T0100 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H01W0100 +arc: B4 H02E0301 +arc: B6 V01S0000 +arc: C0 N1_V01N0001 +arc: C1 F6 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1010101000111100 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICED.K0.INIT 1010101000111100 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEA.K1.INIT 1100110001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C45:PLC2 +arc: E3_H06E0303 W1_H02E0501 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A2 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 V00T0100 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 H00L0000 +arc: B4 V01S0000 +arc: B6 H02E0101 +arc: C0 N1_V01N0001 +arc: C1 F4 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F6 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0000 +arc: M4 W1_H02E0401 +arc: M6 H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q0 +arc: S1_V02S0501 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1101110000010000 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C46:PLC2 +arc: E1_H02E0101 V06N0103 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0201 S1_V02N0201 +arc: B0 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: E1_H02E0601 Q6 +arc: F0 F5A_SLICE +arc: LSR0 V00B0100 +arc: M0 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F0 +arc: S1_V02S0401 Q6 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C47:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0701 +arc: A2 V02S0701 +arc: A4 V00B0000 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B0 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: C0 H00L0000 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0601 F6 +word: SLICEB.K0.INIT 1111000001100110 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEC.K0.INIT 1100110001011010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C48:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H01E0101 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V02N0701 +arc: A4 S1_V02N0301 +arc: A5 V00T0000 +arc: A6 V02N0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B4 V01S0000 +arc: B6 N1_V01S0000 +arc: C0 F4 +arc: C1 E1_H01W0000 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q3 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00T0100 +arc: M3 H00R0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0701 Q7 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q7 +word: SLICEB.K0.INIT 1011000111100100 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111011000000110 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1100110001010000 +word: SLICEA.K1.INIT 1100110001010000 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C49:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 H00L0000 +arc: A1 H01E0001 +arc: A2 H00L0100 +arc: A4 V00T0100 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 H02E0301 +arc: B3 H01W0100 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: C0 H00R0100 +arc: C1 H00L0100 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0401 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F4 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: M2 V00B0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 F6 +word: SLICEB.K0.INIT 1010101000111100 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1000101110001000 +word: SLICEA.K1.INIT 1111000000100010 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1100110001011010 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R9C50:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02E0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 E1_H01E0001 +arc: A2 V02N0501 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 V02N0101 +arc: B4 V02S0501 +arc: B6 W1_H02E0301 +arc: C0 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C7 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0001 +arc: D5 H02W0001 +arc: D6 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00B0000 F4 +arc: V01S0000 Q7 +word: SLICEB.K0.INIT 1010001110101100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111000001100110 +word: SLICEC.K1.INIT 1111000010101010 +word: SLICEA.K0.INIT 1010101000001100 +word: SLICED.K0.INIT 1010101011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C51:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0501 W3_H06E0303 +arc: V00B0000 V02S0201 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 V02N0401 +arc: A0 V02N0501 +arc: A2 E1_H02W0501 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: B0 W1_H02E0101 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: B4 H02E0301 +arc: B6 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V00T0100 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0201 +arc: D3 S1_V02N0201 +arc: D4 H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F6 +arc: LSR1 H02E0501 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V02N0301 Q1 +word: SLICEA.K0.INIT 1011000111100100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 1111011000000110 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEC.K0.INIT 1100010111001010 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C52:PLC2 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: A0 H01E0001 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: A4 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B4 S1_V02N0701 +arc: B5 V01S0000 +arc: B6 V02N0701 +arc: C0 S1_V02N0401 +arc: C1 F4 +arc: C2 H02E0401 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 Q2 +arc: D4 H00L0100 +arc: D5 V02N0601 +arc: D6 N1_V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H00R0000 F6 +arc: H00R0100 Q5 +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M3 H00L0000 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: S1_V02S0101 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0701 Q5 +word: SLICEA.K0.INIT 1111001000000010 +word: SLICEC.K0.INIT 1011000111100100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEA.K1.INIT 1010101000110000 +word: SLICEB.K0.INIT 1011101000010000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C53:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 N1_V02S0701 + +.tile TAP_R11C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R11C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R12C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R12C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R13C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R13C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R14C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R14C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R16C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R16C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R16C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R17C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R17C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R17C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R17C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R18C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R19C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R23C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R24C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R25C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R27C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + 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G_VPTX0000 + +.tile TAP_R29C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R30C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R31C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R31C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R32C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R32C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R33C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R33C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R35C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R36C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R36C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + 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TAP_R39C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R39C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R3C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R3C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R40C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R41C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + 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G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R43C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R43C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R44C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R44C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R44C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R45C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R45C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R45C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R47C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R47C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R48C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R49C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R49C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R49C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R4C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R4C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R50C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R50C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R50C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R51C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R51C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C114:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R52C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R52C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R53C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R54C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C78:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R55C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R56C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R57C96:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R59C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R5C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R5C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R60C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R60C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R61C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R62C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R63C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R64C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R65C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R66C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R67C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R67C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R68C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R68C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R69C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R69C96:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R6C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R6C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R71C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R71C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R71C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R72C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R73C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R73C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R74C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R74C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R75C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R76C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R77C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R77C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R77C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R78C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R78C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R79C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R79C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R79C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R7C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R7C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R80C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R80C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R80C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R81C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R83C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R84C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R84C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R84C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R85C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R86C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R87C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R88C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R89C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R89C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R89C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R8C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R8C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R8C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R90C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R9C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R9C58:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile_group MIB_R58C73:MIB_DSP4 MIB_R58C73:MIB2_DSP4 MIB_R58C74:MIB_DSP5 MIB_R58C74:MIB2_DSP5 MIB_R58C75:MIB_DSP6 MIB_R58C75:MIB2_DSP6 MIB_R58C76:MIB_DSP7 MIB_R58C76:MIB2_DSP7 MIB_R58C77:MIB_DSP8 MIB_R58C77:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R4C0:PLL0_UL MIB_R5C0:PLL1_UL +word: CLKI_DIV 0000100 +word: CLKFB_DIV 0000001 +word: CLKOP_DIV 0111011 +word: CLKOP_CPHASE 0011110 +word: CLKOP_FPHASE 000 +word: CLKOS_DIV 0000111 +word: CLKOS_CPHASE 0000000 +word: CLKOS_FPHASE 000 +word: CLKOS2_DIV 0000111 +word: CLKOS2_CPHASE 0000000 +word: CLKOS2_FPHASE 000 +word: CLKOS3_DIV 0000111 +word: CLKOS3_CPHASE 0000000 +word: CLKOS3_FPHASE 000 +word: PLL_LOCK_MODE 000 +word: KVCO 000 +word: LPF_CAPACITOR 00 +word: LPF_RESISTOR 0001000 +word: ICP_CURRENT 01100 +word: FREQ_LOCK_ACCURACY 00 +word: MFG_GMC_GAIN 000 +word: MFG_GMC_TEST 1110 +word: MFG1_TEST 000 +word: MFG2_TEST 000 +word: MFG_FORCE_VFILTER 0 +word: MFG_ICP_TEST 0 +word: MFG_EN_UP 0 +word: MFG_FLOAT_ICP 0 +word: MFG_GMC_PRESET 0 +word: MFG_LF_PRESET 0 +word: MFG_GMC_RESET 0 +word: MFG_LF_RESET 0 +word: MFG_LF_RESGRND 0 +word: MFG_GMCREF_SEL 10 +word: MFG_ENABLE_FILTEROPAMP 1 +enum: MODE EHXPLLL +enum: CLKOP_ENABLE ENABLED +enum: CLKOS_ENABLE ENABLED +enum: CLKOS2_ENABLE ENABLED +enum: CLKOS3_ENABLE ENABLED +enum: FEEDBK_PATH INT_OP +enum: CLKOP_TRIM_POL RISING +enum: CLKOP_TRIM_DELAY 0 +enum: CLKOS_TRIM_POL RISING +enum: CLKOS_TRIM_DELAY 0 +enum: OUTDIVIDER_MUXA DIVA +enum: OUTDIVIDER_MUXB DIVB +enum: OUTDIVIDER_MUXC DIVC +enum: OUTDIVIDER_MUXD DIVD +enum: STDBY_ENABLE DISABLED +enum: REFIN_RESET DISABLED +enum: SYNC_ENABLE DISABLED +enum: INT_LOCK_STICKY ENABLED +enum: DPHASE_SOURCE DISABLED +enum: PLLRST_ENA DISABLED +enum: INTFB_WAKE DISABLED + diff --git a/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.svf b/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.svf new file mode 100644 index 00000000..9c34af1a --- /dev/null +++ b/evidence/lsc1-09-cleanroom/clean-build-2/ulx3s_lsc1_packet.svf @@ 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@@ -0,0 +1,32855 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command ` +read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v; +read_verilog -sv ulx3s_packet_top.sv ulx3s_core_pll.sv uart_bridge.sv uart_rx.sv uart_tx.sv ../../asic_core/rtl/lean_silicon_lsc1.sv ../../asic_core/rtl/lean_silicon_lsc1_mincore.sv ../../asic_core/rtl/lsc1_packet_frontend.sv ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_blake3_lifecycle.sv ../../asic_core/rtl/lsc1_response_payload_mux.sv ../../asic_core/rtl/lsc1_blake3_alias_check.sv ../../asic_core/rtl/lsc1_request_validator.sv ../../asic_core/rtl/lsc1_cell_alias_check.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv; +hierarchy -check -top ulx3s_packet_top; +proc; check; +synth_ecp5 -abc9 -nodffe -top ulx3s_packet_top; +write_json ulx3s_packet_top.json +' -- + +1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\DP16KD'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCUA'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: ulx3s_packet_top.sv +Parsing SystemVerilog input from `ulx3s_packet_top.sv' to AST representation. +Generating RTLIL representation for module `\ulx3s_packet_top'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: ulx3s_core_pll.sv +Parsing SystemVerilog input from `ulx3s_core_pll.sv' to AST representation. +Generating RTLIL representation for module `\ulx3s_core_pll'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: uart_bridge.sv +Parsing SystemVerilog input from `uart_bridge.sv' to AST representation. +Generating RTLIL representation for module `\uart_bridge'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: uart_rx.sv +Parsing SystemVerilog input from `uart_rx.sv' to AST representation. +Generating RTLIL representation for module `\uart_rx'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: uart_tx.sv +Parsing SystemVerilog input from `uart_tx.sv' to AST representation. +Generating RTLIL representation for module `\uart_tx'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: ../../asic_core/rtl/lean_silicon_lsc1.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lean_silicon_lsc1.sv' to AST representation. +Generating RTLIL representation for module `\lean_silicon_lsc1'. +Successfully finished Verilog frontend. + +9. Executing Verilog-2005 frontend: ../../asic_core/rtl/lean_silicon_lsc1_mincore.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lean_silicon_lsc1_mincore.sv' to AST representation. +Generating RTLIL representation for module `\lean_silicon_lsc1_mincore'. +Successfully finished Verilog frontend. + +10. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Warning: Replacing memory \staged_out_value with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:839 +Warning: Replacing memory \staged_out_present with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:838 +Warning: Replacing memory \staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:814, ../../asic_core/rtl/lsc1_packet_frontend.sv:556 +Warning: Replacing memory \scalar_staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:505 +Successfully finished Verilog frontend. + +11. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +12. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +13. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +14. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +15. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_blake3_lifecycle.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_blake3_lifecycle.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_blake3_lifecycle'. +Successfully finished Verilog frontend. + +16. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_response_payload_mux.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_response_payload_mux.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_response_payload_mux'. +Successfully finished Verilog frontend. + +17. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_blake3_alias_check.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_blake3_alias_check.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_blake3_alias_check'. +Successfully finished Verilog frontend. + +18. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_request_validator.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_request_validator.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_request_validator'. +Successfully finished Verilog frontend. + +19. Executing Verilog-2005 frontend: ../../asic_core/rtl/lsc1_cell_alias_check.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lsc1_cell_alias_check.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_cell_alias_check'. +Successfully finished Verilog frontend. + +20. Executing Verilog-2005 frontend: ../../asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `../../asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +21. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +22. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +23. Executing HIERARCHY pass (managing design hierarchy). + +23.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1_mincore +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \uart_tx +Used module: \uart_rx +Used module: \ulx3s_core_pll +Parameter \PACKET_MODE = 1'1 +Parameter \CLK_HZ = 10000000 + +23.2. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_bridge'. +Parameter \PACKET_MODE = 1'1 +Parameter \CLK_HZ = 10000000 +Generating RTLIL representation for module `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +23.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +23.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +23.5. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +23.6. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: \uart_tx +Used module: \uart_rx +Used module: \ulx3s_core_pll +Reprocessing module lsc1_packet_frontend because instantiated module lsc1_response_payload_mux has become available. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Warning: Replacing memory \staged_out_value with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:839 +Warning: Replacing memory \staged_out_present with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:838 +Warning: Replacing memory \staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:814, ../../asic_core/rtl/lsc1_packet_frontend.sv:556 +Warning: Replacing memory \scalar_staged_access with list of registers. See ../../asic_core/rtl/lsc1_packet_frontend.sv:505 +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 + +23.7. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 + +23.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. +Parameter \CLK_HZ = 10000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx'. + +23.9. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll + +23.10. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll +Removing unused module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx'. +Removing unused module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx'. +Removing unused module `\gf2n_mul_bitstream'. +Removing unused module `\lean_silicon_lsc1_mincore'. +Removing unused module `\uart_tx'. +Removing unused module `\uart_rx'. +Removing unused module `\uart_bridge'. +Removed 7 unused modules. + +24. Executing PROC pass (convert processes to netlists). + +24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. +Cleaned up 11 empty switches. + +24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 12 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866 in module leanvm_b_stream_alu. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575 in module lsc1_request_validator. +Marked 1 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547 in module lsc1_request_validator. +Removed 5 dead cases from process $proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155 in module lsc1_response_payload_mux. +Marked 36 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155 in module lsc1_response_payload_mux. +Marked 2 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143 in module lsc1_blake3_lifecycle. +Marked 5 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008 in module lsc1_stream_adapter. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721 in module lsc1_packet_tx. +Marked 10 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525 in module lsc1_packet_rx. +Marked 5 switch rules as full_case in process $proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 4 switch rules as full_case in process $proc$uart_tx.sv:22$4375 in module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Marked 112 switch rules as full_case in process $proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203 in module lsc1_packet_frontend. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:149$2991 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:131$2983 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:113$2981 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:96$2975 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:28$2969 in module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Marked 8 switch rules as full_case in process $proc$uart_rx.sv:33$4386 in module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114 in module DPR16X4C. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56 in module TRELLIS_DPR16X4. +Removed a total of 5 dead cases. + +24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 16 redundant assignments. +Promoted 374 assignments to connections. + +24.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. + Set init value: \por_shift = 8'00000000 +Found init rule in `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. + Set init value: \heartbeat = 24'000000000000000000000000 +Found init rule in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. + Set init value: \Q = 1'0 + +24.5. Executing PROC_ARST pass (detect async resets in processes). + +24.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +24.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + 1/5: $0\scratch_byte[7:0] [7:1] + 2/5: $0\scratch_byte[7:0] [0] + 3/5: $0\byte_index[3:0] + 4/5: $0\state[3:0] + 5/5: $0\fault[0:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. + 1/13: $2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875 + 2/13: $2\rx_ready[0:0] + 3/13: $2\tx_data[7:0] + 4/13: $2\tx_valid[0:0] + 5/13: $1\rx_ready[0:0] + 6/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.index[3:0]$2870 + 7/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2869 + 8/13: $1\mul_result_shift[0:0] + 9/13: $1\mul_bit_value[0:0] + 10/13: $1\mul_bit_valid[0:0] + 11/13: $1\mul_a_valid[0:0] + 12/13: $1\tx_valid[0:0] + 13/13: $1\tx_data[7:0] +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +Creating decoders for process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. + 1/37: $7\fault_detail[7:0] + 2/37: $7\fault_txn[31:0] + 3/37: $7\fault_status[7:0] + 4/37: $7\reject[0:0] + 5/37: $7\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2586 + 6/37: $6\fault_detail[7:0] + 7/37: $6\fault_txn[31:0] + 8/37: $6\fault_status[7:0] + 9/37: $6\reject[0:0] + 10/37: $6\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2585 + 11/37: $5\fault_detail[7:0] + 12/37: $5\fault_txn[31:0] + 13/37: $5\fault_status[7:0] + 14/37: $5\reject[0:0] + 15/37: $5\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2584 + 16/37: $4\fault_detail[7:0] + 17/37: $4\fault_txn[31:0] + 18/37: $4\fault_status[7:0] + 19/37: $4\reject[0:0] + 20/37: $4\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2583 + 21/37: $3\fault_detail[7:0] + 22/37: $3\fault_txn[31:0] + 23/37: $3\fault_status[7:0] + 24/37: $3\reject[0:0] + 25/37: $3\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2582 + 26/37: $2\fault_detail[7:0] + 27/37: $2\fault_txn[31:0] + 28/37: $2\fault_status[7:0] + 29/37: $2\reject[0:0] + 30/37: $2\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn[31:0]$2580 + 31/37: $2\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2581 + 32/37: $1\fault_detail[7:0] + 33/37: $1\fault_txn[31:0] + 34/37: $1\fault_status[7:0] + 35/37: $1\reject[0:0] + 36/37: $1\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn[31:0]$2579 + 37/37: $1\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn[31:0]$2578 +Creating decoders for process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. + 1/1: $1\expected_length[15:0] +Creating decoders for process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +Creating decoders for process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +Creating decoders for process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. + 1/127: $31\payload_data[7:0] + 2/127: $30\payload_data[7:0] + 3/127: $29\payload_data[7:0] + 4/127: $28\payload_data[7:0] + 5/127: $27\payload_data[7:0] + 6/127: $26\payload_data[7:0] + 7/127: $25\payload_data[7:0] + 8/127: $24\payload_data[7:0] + 9/127: $23\payload_data[7:0] + 10/127: $22\payload_data[7:0] + 11/127: $21\payload_data[7:0] + 12/127: $20\payload_data[7:0] + 13/127: $19\payload_data[7:0] + 14/127: $18\payload_data[7:0] + 15/127: $17\payload_data[7:0] + 16/127: $10$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2323 + 17/127: $16\payload_data[7:0] + 18/127: $9$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2318 + 19/127: $9$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2317 + 20/127: $15\ext_word[31:0] + 21/127: $15\payload_data[7:0] + 22/127: $8$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2313 + 23/127: $8$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2312 + 24/127: $14\ext_word[31:0] + 25/127: $9$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2302 + 26/127: $9$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2296 + 27/127: $14\payload_data[7:0] + 28/127: $8$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2293 + 29/127: $8$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2292 + 30/127: $8$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2295 + 31/127: $8$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2294 + 32/127: $7$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2284 + 33/127: $7$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2283 + 34/127: $7$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2282 + 35/127: $7$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2281 + 36/127: $13\payload_data[7:0] + 37/127: $13\ext_word[31:0] + 38/127: $7$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2286 + 39/127: $7$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2285 + 40/127: $12\payload_data[7:0] + 41/127: $6$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2277 + 42/127: $6$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2276 + 43/127: $6$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2275 + 44/127: $6$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2274 + 45/127: $6$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2273 + 46/127: $6$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2272 + 47/127: $12\ext_word[31:0] + 48/127: $11\payload_data[7:0] + 49/127: $5$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2266 + 50/127: $5$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2265 + 51/127: $5$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2264 + 52/127: $5$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2263 + 53/127: $5$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2262 + 54/127: $5$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2261 + 55/127: $11\ext_word[31:0] + 56/127: $10\payload_data[7:0] + 57/127: $4$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2255 + 58/127: $4$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2254 + 59/127: $4$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2253 + 60/127: $4$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2252 + 61/127: $4$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2251 + 62/127: $4$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2250 + 63/127: $10\ext_word[31:0] + 64/127: $9\payload_data[7:0] + 65/127: $3$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2245 + 66/127: $3$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2244 + 67/127: $3$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2243 + 68/127: $3$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2242 + 69/127: $3$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2241 + 70/127: $3$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2240 + 71/127: $9\ext_word[31:0] + 72/127: $2$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2238 + 73/127: $2$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2237 + 74/127: $2$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2236 + 75/127: $2$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2235 + 76/127: $2$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2234 + 77/127: $2$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2233 + 78/127: $8\ext_word[31:0] + 79/127: $8\payload_data[7:0] + 80/127: $8$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2222 + 81/127: $7\payload_data[7:0] + 82/127: $7$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2219 + 83/127: $7$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2218 + 84/127: $7\ext_word[31:0] + 85/127: $7$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2211 + 86/127: $6\payload_data[7:0] + 87/127: $6$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2206 + 88/127: $6$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2205 + 89/127: $6\ext_word[31:0] + 90/127: $6$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2208 + 91/127: $6$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2207 + 92/127: $5\payload_data[7:0] + 93/127: $5$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2203 + 94/127: $5$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2202 + 95/127: $5$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2201 + 96/127: $5$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2200 + 97/127: $5\ext_word[31:0] + 98/127: $4\payload_data[7:0] + 99/127: $4$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2198 + 100/127: $4$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2197 + 101/127: $4$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2196 + 102/127: $4$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2195 + 103/127: $4\ext_word[31:0] + 104/127: $3\payload_data[7:0] + 105/127: $3$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2189 + 106/127: $3$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2188 + 107/127: $3$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2187 + 108/127: $3$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2186 + 109/127: $3\ext_word[31:0] + 110/127: $2\payload_data[7:0] + 111/127: $2$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2181 + 112/127: $2$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2180 + 113/127: $2$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2179 + 114/127: $2$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2178 + 115/127: $2\ext_word[31:0] + 116/127: $1$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA[127:0]$2170 + 117/127: $1$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR[0:0]$2169 + 118/127: $1$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA[127:0]$2168 + 119/127: $1$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR[1:0]$2167 + 120/127: $1\ext_word[31:0] + 121/127: $1\payload_data[7:0] + 122/127: $1$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA[31:0]$2176 + 123/127: $1$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR[2:0]$2175 + 124/127: $1$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA[127:0]$2174 + 125/127: $1$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR[0:0]$2173 + 126/127: $1$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA[31:0]$2172 + 127/127: $1$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR[0:0]$2171 +Creating decoders for process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + 1/10: $0\done_pulse[0:0] + 2/10: $0\service_seq[31:0] + 3/10: $0\staged_service_id[31:0] + 4/10: $0\service_pending[0:0] + 5/10: $0\retire_seq[31:0] + 6/10: $0\staged_result_crc[31:0] + 7/10: $0\staged_next_fp[31:0] + 8/10: $0\staged_next_pc[31:0] + 9/10: $0\staged_txn_id[31:0] + 10/10: $0\result_pending[0:0] +Creating decoders for process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + 1/19: $3\next_accumulator[127:0] + 2/19: $3\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2129 + 3/19: $3\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2130 + 4/19: $2\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2127 + 5/19: $2\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2126 + 6/19: $2\next_accumulator[127:0] + 7/19: $0\multiply_start[0:0] + 8/19: $0\done_pulse[0:0] + 9/19: $1\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value[127:0]$2123 + 10/19: $1\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result[127:0]$2122 + 11/19: $1\next_accumulator[127:0] + 12/19: $0\accumulator[127:0] + 13/19: $0\saved_index[15:0] + 14/19: $0\bit_index[4:0] + 15/19: $0\result[127:0] + 16/19: $0\operand_b[127:0] + 17/19: $0\operand_a[127:0] + 18/19: $0\fault[0:0] + 19/19: $0\busy[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + 1/38: $6$lookahead\result$2032[127:0]$2100 + 2/38: $4$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2098 + 3/38: $4$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2097 + 4/38: $4$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2099 + 5/38: $5$lookahead\result$2032[127:0]$2074 + 6/38: $4$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2072 + 7/38: $4$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2071 + 8/38: $4$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2073 + 9/38: $4$lookahead\result$2032[127:0]$2065 + 10/38: $3$lookahead\result$2032[127:0]$2064 + 11/38: $3$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2063 + 12/38: $3$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2062 + 13/38: $3$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2061 + 14/38: $3$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2060 + 15/38: $3$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2059 + 16/38: $3$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2058 + 17/38: $2$lookahead\result$2032[127:0]$2055 + 18/38: $2$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2054 + 19/38: $2$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2053 + 20/38: $2$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2052 + 21/38: $2$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2051 + 22/38: $2$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2050 + 23/38: $2$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2049 + 24/38: $0\done_pulse[0:0] + 25/38: $1$lookahead\result$2032[127:0]$2048 + 26/38: $1$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001[31:0]$2047 + 27/38: $1$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000[127:0]$2046 + 28/38: $1$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999[127:0]$2045 + 29/38: $1$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998[31:0]$2044 + 30/38: $1$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997[127:0]$2043 + 31/38: $1$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996[127:0]$2042 + 32/38: $0\result_index[4:0] + 33/38: $0\saved_b[127:0] + 34/38: $0\saved_a[127:0] + 35/38: $0\saved_operation[7:0] + 36/38: $0\state[2:0] + 37/38: $0\payload_index[5:0] + 38/38: $0\fault[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. + 1/9: $6\core_rx_data[7:0] + 2/9: $5\core_rx_data[7:0] + 3/9: $4\core_rx_data[7:0] + 4/9: $3\core_rx_data[7:0] + 5/9: $3\core_rx_valid[0:0] + 6/9: $2\core_rx_data[7:0] + 7/9: $2\core_rx_valid[0:0] + 8/9: $1\core_rx_data[7:0] + 9/9: $1\core_rx_valid[0:0] +Creating decoders for process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + 1/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1918 + 2/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1921 + 3/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1922 + 4/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1920 + 5/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1919 + 6/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1913 + 7/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1916 + 8/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1917 + 9/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1915 + 10/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1914 + 11/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1873 + 12/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1876 + 13/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1877 + 14/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1875 + 15/104: $5\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1874 + 16/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1838 + 17/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1837 + 18/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1836 + 19/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1835 + 20/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1834 + 21/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1833 + 22/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1832 + 23/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1831 + 24/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1830 + 25/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1829 + 26/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1828 + 27/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1827 + 28/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1826 + 29/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1825 + 30/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1824 + 31/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1819 + 32/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1822 + 33/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1823 + 34/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1821 + 35/104: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1820 + 36/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1816 + 37/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1815 + 38/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1814 + 39/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1813 + 40/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1812 + 41/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1811 + 42/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1810 + 43/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1809 + 44/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1808 + 45/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1807 + 46/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1806 + 47/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1805 + 48/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1804 + 49/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1803 + 50/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1802 + 51/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1801 + 52/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1800 + 53/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1799 + 54/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1798 + 55/104: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1797 + 56/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1795 + 57/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1794 + 58/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1793 + 59/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1792 + 60/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1791 + 61/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1790 + 62/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1789 + 63/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1788 + 64/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1787 + 65/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1786 + 66/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1785 + 67/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1784 + 68/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1783 + 69/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1782 + 70/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1781 + 71/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1780 + 72/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1779 + 73/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1778 + 74/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1777 + 75/104: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1776 + 76/104: $0\done_pulse[0:0] + 77/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work[31:0]$1773 + 78/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index[31:0]$1772 + 79/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data[7:0]$1771 + 80/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in[31:0]$1770 + 81/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result[31:0]$1769 + 82/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work[31:0]$1768 + 83/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index[31:0]$1767 + 84/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data[7:0]$1766 + 85/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in[31:0]$1765 + 86/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result[31:0]$1764 + 87/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work[31:0]$1763 + 88/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index[31:0]$1762 + 89/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data[7:0]$1761 + 90/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in[31:0]$1760 + 91/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result[31:0]$1759 + 92/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work[31:0]$1758 + 93/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index[31:0]$1757 + 94/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data[7:0]$1756 + 95/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in[31:0]$1755 + 96/104: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result[31:0]$1754 + 97/104: $0\payload_crc_work[31:0] + 98/104: $0\envelope_crc_work[31:0] + 99/104: $0\saved_crc[31:0] + 100/104: $0\saved_status[7:0] + 101/104: $0\saved_length[15:0] + 102/104: $0\active[0:0] + 103/104: $0\index[15:0] + 104/104: $0\payload_crc[31:0] +Creating decoders for process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. + 1/7: $7\tx_data[7:0] + 2/7: $6\tx_data[7:0] + 3/7: $5\tx_data[7:0] + 4/7: $4\tx_data[7:0] + 5/7: $3\tx_data[7:0] + 6/7: $2\tx_data[7:0] + 7/7: $1\tx_data[7:0] +Creating decoders for process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + 1/264: $0\received_crc[31:0] [31:24] + 2/264: $0\received_crc[31:0] [23:16] + 3/264: $0\received_crc[31:0] [15:8] + 4/264: $0\received_crc[31:0] [7:0] + 5/264: $0\frame_payload_prefix[1519:0] [1511:1504] + 6/264: $0\frame_payload_prefix[1519:0] [1503:1496] + 7/264: $0\frame_payload_prefix[1519:0] [1495:1488] + 8/264: $0\frame_payload_prefix[1519:0] [1487:1480] + 9/264: $0\frame_payload_prefix[1519:0] [1479:1472] + 10/264: $0\frame_payload_prefix[1519:0] [1471:1464] + 11/264: $0\frame_payload_prefix[1519:0] [1463:1456] + 12/264: $0\frame_payload_prefix[1519:0] [1455:1448] + 13/264: $0\frame_payload_prefix[1519:0] [1447:1440] + 14/264: $0\frame_payload_prefix[1519:0] [1439:1432] + 15/264: $0\frame_payload_prefix[1519:0] [1431:1424] + 16/264: $0\frame_payload_prefix[1519:0] [1423:1416] + 17/264: $0\frame_payload_prefix[1519:0] [1415:1408] + 18/264: $0\frame_payload_prefix[1519:0] [1407:1400] + 19/264: $0\frame_payload_prefix[1519:0] [1399:1392] + 20/264: $0\frame_payload_prefix[1519:0] [1391:1384] + 21/264: $0\frame_payload_prefix[1519:0] [1383:1376] + 22/264: $0\frame_payload_prefix[1519:0] [1375:1368] + 23/264: $0\frame_payload_prefix[1519:0] [1367:1360] + 24/264: $0\frame_payload_prefix[1519:0] [1359:1352] + 25/264: $0\frame_payload_prefix[1519:0] [1351:1344] + 26/264: $0\frame_payload_prefix[1519:0] [1343:1336] + 27/264: $0\frame_payload_prefix[1519:0] [1335:1328] + 28/264: $0\frame_payload_prefix[1519:0] [1327:1320] + 29/264: $0\frame_payload_prefix[1519:0] [1319:1312] + 30/264: $0\frame_payload_prefix[1519:0] [1311:1304] + 31/264: $0\frame_payload_prefix[1519:0] [1303:1296] + 32/264: $0\frame_payload_prefix[1519:0] [1295:1288] + 33/264: $0\frame_payload_prefix[1519:0] [1287:1280] + 34/264: $0\frame_payload_prefix[1519:0] [1279:1272] + 35/264: $0\frame_payload_prefix[1519:0] [1271:1264] + 36/264: $0\frame_payload_prefix[1519:0] [1263:1256] + 37/264: $0\frame_payload_prefix[1519:0] [1255:1248] + 38/264: $0\frame_payload_prefix[1519:0] [1247:1240] + 39/264: $0\frame_payload_prefix[1519:0] [1239:1232] + 40/264: $0\frame_payload_prefix[1519:0] [1231:1224] + 41/264: $0\frame_payload_prefix[1519:0] [1223:1216] + 42/264: $0\frame_payload_prefix[1519:0] [1215:1208] + 43/264: $0\frame_payload_prefix[1519:0] [1207:1200] + 44/264: $0\frame_payload_prefix[1519:0] [1199:1192] + 45/264: $0\frame_payload_prefix[1519:0] [1191:1184] + 46/264: $0\frame_payload_prefix[1519:0] [1183:1176] + 47/264: $0\frame_payload_prefix[1519:0] [1175:1168] + 48/264: $0\frame_payload_prefix[1519:0] [1167:1160] + 49/264: $0\frame_payload_prefix[1519:0] [1159:1152] + 50/264: $0\frame_payload_prefix[1519:0] [1151:1144] + 51/264: $0\frame_payload_prefix[1519:0] [1143:1136] + 52/264: $0\frame_payload_prefix[1519:0] [1135:1128] + 53/264: $0\frame_payload_prefix[1519:0] [1127:1120] + 54/264: $0\frame_payload_prefix[1519:0] [1119:1112] + 55/264: $0\frame_payload_prefix[1519:0] [1111:1104] + 56/264: $0\frame_payload_prefix[1519:0] [1103:1096] + 57/264: $0\frame_payload_prefix[1519:0] [1095:1088] + 58/264: $0\frame_payload_prefix[1519:0] [1087:1080] + 59/264: $0\frame_payload_prefix[1519:0] [1079:1072] + 60/264: $0\frame_payload_prefix[1519:0] [1071:1064] + 61/264: $0\frame_payload_prefix[1519:0] [1063:1056] + 62/264: $0\frame_payload_prefix[1519:0] [1055:1048] + 63/264: $0\frame_payload_prefix[1519:0] [1047:1040] + 64/264: $0\frame_payload_prefix[1519:0] [1039:1032] + 65/264: $0\frame_payload_prefix[1519:0] [1031:1024] + 66/264: $0\frame_payload_prefix[1519:0] [1023:1016] + 67/264: $0\frame_payload_prefix[1519:0] [1015:1008] + 68/264: $0\frame_payload_prefix[1519:0] [1007:1000] + 69/264: $0\frame_payload_prefix[1519:0] [999:992] + 70/264: $0\frame_payload_prefix[1519:0] [991:984] + 71/264: $0\frame_payload_prefix[1519:0] [983:976] + 72/264: $0\frame_payload_prefix[1519:0] [975:968] + 73/264: $0\frame_payload_prefix[1519:0] [967:960] + 74/264: $0\frame_payload_prefix[1519:0] [959:952] + 75/264: $0\frame_payload_prefix[1519:0] [951:944] + 76/264: $0\frame_payload_prefix[1519:0] [943:936] + 77/264: $0\frame_payload_prefix[1519:0] [935:928] + 78/264: $0\frame_payload_prefix[1519:0] [927:920] + 79/264: $0\frame_payload_prefix[1519:0] [919:912] + 80/264: $0\frame_payload_prefix[1519:0] [911:904] + 81/264: $0\frame_payload_prefix[1519:0] [903:896] + 82/264: $0\frame_payload_prefix[1519:0] [895:888] + 83/264: $0\frame_payload_prefix[1519:0] [887:880] + 84/264: $0\frame_payload_prefix[1519:0] [879:872] + 85/264: $0\frame_payload_prefix[1519:0] [871:864] + 86/264: $0\frame_payload_prefix[1519:0] [863:856] + 87/264: $0\frame_payload_prefix[1519:0] [855:848] + 88/264: $0\frame_payload_prefix[1519:0] [847:840] + 89/264: $0\frame_payload_prefix[1519:0] [839:832] + 90/264: $0\frame_payload_prefix[1519:0] [831:824] + 91/264: $0\frame_payload_prefix[1519:0] [823:816] + 92/264: $0\frame_payload_prefix[1519:0] [815:808] + 93/264: $0\frame_payload_prefix[1519:0] [807:800] + 94/264: $0\frame_payload_prefix[1519:0] [799:792] + 95/264: $0\frame_payload_prefix[1519:0] [791:784] + 96/264: $0\frame_payload_prefix[1519:0] [783:776] + 97/264: $0\frame_payload_prefix[1519:0] [775:768] + 98/264: $0\frame_payload_prefix[1519:0] [767:760] + 99/264: $0\frame_payload_prefix[1519:0] [759:752] + 100/264: $0\frame_payload_prefix[1519:0] [751:744] + 101/264: $0\frame_payload_prefix[1519:0] [743:736] + 102/264: $0\frame_payload_prefix[1519:0] [735:728] + 103/264: $0\frame_payload_prefix[1519:0] [727:720] + 104/264: $0\frame_payload_prefix[1519:0] [719:712] + 105/264: $0\frame_payload_prefix[1519:0] [711:704] + 106/264: $0\frame_payload_prefix[1519:0] [703:696] + 107/264: $0\frame_payload_prefix[1519:0] [695:688] + 108/264: $0\frame_payload_prefix[1519:0] [687:680] + 109/264: $0\frame_payload_prefix[1519:0] [679:672] + 110/264: $0\frame_payload_prefix[1519:0] [671:664] + 111/264: $0\frame_payload_prefix[1519:0] [663:656] + 112/264: $0\frame_payload_prefix[1519:0] [655:648] + 113/264: $0\frame_payload_prefix[1519:0] [647:640] + 114/264: $0\frame_payload_prefix[1519:0] [639:632] + 115/264: $0\frame_payload_prefix[1519:0] [631:624] + 116/264: $0\frame_payload_prefix[1519:0] [623:616] + 117/264: $0\frame_payload_prefix[1519:0] [615:608] + 118/264: $0\frame_payload_prefix[1519:0] [607:600] + 119/264: $0\frame_payload_prefix[1519:0] [599:592] + 120/264: $0\frame_payload_prefix[1519:0] [591:584] + 121/264: $0\frame_payload_prefix[1519:0] [583:576] + 122/264: $0\frame_payload_prefix[1519:0] [575:568] + 123/264: $0\frame_payload_prefix[1519:0] [567:560] + 124/264: $0\frame_payload_prefix[1519:0] [559:552] + 125/264: $0\frame_payload_prefix[1519:0] [551:544] + 126/264: $0\frame_payload_prefix[1519:0] [543:536] + 127/264: $0\frame_payload_prefix[1519:0] [535:528] + 128/264: $0\frame_payload_prefix[1519:0] [527:520] + 129/264: $0\frame_payload_prefix[1519:0] [519:512] + 130/264: $0\frame_payload_prefix[1519:0] [511:504] + 131/264: $0\frame_payload_prefix[1519:0] [503:496] + 132/264: $0\frame_payload_prefix[1519:0] [495:488] + 133/264: $0\frame_payload_prefix[1519:0] [487:480] + 134/264: $0\frame_payload_prefix[1519:0] [479:472] + 135/264: $0\frame_payload_prefix[1519:0] [471:464] + 136/264: $0\frame_payload_prefix[1519:0] [463:456] + 137/264: $0\frame_payload_prefix[1519:0] [455:448] + 138/264: $0\frame_payload_prefix[1519:0] [447:440] + 139/264: $0\frame_payload_prefix[1519:0] [439:432] + 140/264: $0\frame_payload_prefix[1519:0] [431:424] + 141/264: $0\frame_payload_prefix[1519:0] [423:416] + 142/264: $0\frame_payload_prefix[1519:0] [415:408] + 143/264: $0\frame_payload_prefix[1519:0] [407:400] + 144/264: $0\frame_payload_prefix[1519:0] [399:392] + 145/264: $0\frame_payload_prefix[1519:0] [391:384] + 146/264: $0\frame_payload_prefix[1519:0] [383:376] + 147/264: $0\frame_payload_prefix[1519:0] [375:368] + 148/264: $0\frame_payload_prefix[1519:0] [367:360] + 149/264: $0\frame_payload_prefix[1519:0] [359:352] + 150/264: $0\frame_payload_prefix[1519:0] [351:344] + 151/264: $0\frame_payload_prefix[1519:0] [343:336] + 152/264: $0\frame_payload_prefix[1519:0] [335:328] + 153/264: $0\frame_payload_prefix[1519:0] [327:320] + 154/264: $0\frame_payload_prefix[1519:0] [319:312] + 155/264: $0\frame_payload_prefix[1519:0] [311:304] + 156/264: $0\frame_payload_prefix[1519:0] [303:296] + 157/264: $0\frame_payload_prefix[1519:0] [295:288] + 158/264: $0\frame_payload_prefix[1519:0] [287:280] + 159/264: $0\frame_payload_prefix[1519:0] [279:272] + 160/264: $0\frame_payload_prefix[1519:0] [271:264] + 161/264: $0\frame_payload_prefix[1519:0] [263:256] + 162/264: $0\frame_payload_prefix[1519:0] [255:248] + 163/264: $0\frame_payload_prefix[1519:0] [247:240] + 164/264: $0\frame_payload_prefix[1519:0] [239:232] + 165/264: $0\frame_payload_prefix[1519:0] [231:224] + 166/264: $0\frame_payload_prefix[1519:0] [223:216] + 167/264: $0\frame_payload_prefix[1519:0] [215:208] + 168/264: $0\frame_payload_prefix[1519:0] [207:200] + 169/264: $0\frame_payload_prefix[1519:0] [199:192] + 170/264: $0\frame_payload_prefix[1519:0] [191:184] + 171/264: $0\frame_payload_prefix[1519:0] [183:176] + 172/264: $0\frame_payload_prefix[1519:0] [175:168] + 173/264: $0\frame_payload_prefix[1519:0] [167:160] + 174/264: $0\frame_payload_prefix[1519:0] [159:152] + 175/264: $0\frame_payload_prefix[1519:0] [151:144] + 176/264: $0\frame_payload_prefix[1519:0] [143:136] + 177/264: $0\frame_payload_prefix[1519:0] [135:128] + 178/264: $0\frame_payload_prefix[1519:0] [127:120] + 179/264: $0\frame_payload_prefix[1519:0] [119:112] + 180/264: $0\frame_payload_prefix[1519:0] [111:104] + 181/264: $0\frame_payload_prefix[1519:0] [103:96] + 182/264: $0\frame_payload_prefix[1519:0] [95:88] + 183/264: $0\frame_payload_prefix[1519:0] [87:80] + 184/264: $0\frame_payload_prefix[1519:0] [79:72] + 185/264: $0\frame_payload_prefix[1519:0] [71:64] + 186/264: $0\frame_payload_prefix[1519:0] [63:56] + 187/264: $0\frame_payload_prefix[1519:0] [55:48] + 188/264: $0\frame_payload_prefix[1519:0] [47:40] + 189/264: $0\frame_payload_prefix[1519:0] [39:32] + 190/264: $0\frame_payload_prefix[1519:0] [31:24] + 191/264: $0\frame_payload_prefix[1519:0] [23:16] + 192/264: $0\frame_payload_prefix[1519:0] [15:8] + 193/264: $0\frame_payload_prefix[1519:0] [7:0] + 194/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1665 + 195/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1666 + 196/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1664 + 197/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1663 + 198/264: $4\payload_byte[31:0] + 199/264: $0\declared_length[15:0] [15:8] + 200/264: $0\declared_length[15:0] [7:0] + 201/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1589 + 202/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1588 + 203/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1587 + 204/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1575 + 205/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1574 + 206/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1573 + 207/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1572 + 208/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1585 + 209/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1584 + 210/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1583 + 211/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1582 + 212/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1581 + 213/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1580 + 214/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1579 + 215/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1578 + 216/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1577 + 217/264: $3\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1576 + 218/264: $3\payload_byte[31:0] + 219/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1571 + 220/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1570 + 221/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1569 + 222/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1568 + 223/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1567 + 224/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1566 + 225/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1565 + 226/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1564 + 227/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1563 + 228/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1562 + 229/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1561 + 230/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1560 + 231/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1559 + 232/264: $2\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1558 + 233/264: $2\payload_byte[31:0] + 234/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work[31:0]$1555 + 235/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index[31:0]$1554 + 236/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data[7:0]$1553 + 237/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in[31:0]$1552 + 238/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1551 + 239/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work[31:0]$1550 + 240/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index[31:0]$1549 + 241/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data[7:0]$1548 + 242/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in[31:0]$1547 + 243/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result[31:0]$1546 + 244/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1545 + 245/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index[31:0]$1544 + 246/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data[7:0]$1543 + 247/264: $1\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result[31:0]$1542 + 248/264: $1\payload_byte[31:0] + 249/264: $0\payload_write_enable[189:0] + 250/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result[31:0]$1662 + 251/264: $0\frame_payload_prefix[1519:0] [1519:1512] + 252/264: $0\crc[31:0] + 253/264: $0\flags[7:0] + 254/264: $0\opcode[7:0] + 255/264: $0\version[7:0] + 256/264: $4\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work[31:0]$1590 + 257/264: $0\body_index[15:0] + 258/264: $0\header_index[2:0] + 259/264: $0\state[2:0] + 260/264: $0\fault_valid[0:0] + 261/264: $0\fault_status[7:0] + 262/264: $0\frame_length[15:0] + 263/264: $0\frame_opcode[7:0] + 264/264: $0\frame_valid[0:0] +Creating decoders for process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + 1/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3093 + 2/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3095 + 3/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3094 + 4/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3091 + 5/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3090 + 6/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3089 + 7/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3084 [127:120] + 8/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3084 [119:0] + 9/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3081 + 10/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3083 + 11/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3082 + 12/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3087 + 13/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3086 + 14/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3085 + 15/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3080 + 16/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3079 + 17/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3078 + 18/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3077 + 19/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3076 + 20/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3075 + 21/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3074 + 22/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry[0:0]$3073 + 23/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value[127:0]$3072 + 24/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result[127:0]$3071 + 25/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value[127:0]$3070 + 26/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value[7:0]$3069 + 27/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value[127:0]$3068 + 28/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result[127:0]$3067 + 29/30: $0\a_shift[127:0] + 30/30: $0\accumulator[127:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + 1/5: $0\shift[8:0] + 2/5: $0\bit_cnt[3:0] + 3/5: $0\div_cnt[15:0] + 4/5: $0\tx_serial[0:0] + 5/5: $0\tx_ready[0:0] +Creating decoders for process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + 1/2051: $56\result_length[31:0] + 2/2051: $55\result_length[31:0] + 3/2051: $54\result_length[31:0] + 4/2051: $53\result_length[31:0] + 5/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4362 + 6/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4361 + 7/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4360 + 8/2051: $21\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4363 + 9/2051: $52\result_length[31:0] + 10/2051: $20\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4358 + 11/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4357 + 12/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4356 + 13/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4355 + 14/2051: $51\result_length[31:0] + 15/2051: $41\decision_deferred[0:0] + 16/2051: $40\decision_deferred[0:0] + 17/2051: $39\decision_deferred[0:0] + 18/2051: $51\decision_fault[7:0] + 19/2051: $51\decision_ok[0:0] + 20/2051: $38\decision_deferred[0:0] + 21/2051: $50\decision_fault[7:0] + 22/2051: $50\decision_ok[0:0] + 23/2051: $37\decision_deferred[0:0] + 24/2051: $36\decision_deferred[0:0] + 25/2051: $49\decision_ok[0:0] + 26/2051: $49\decision_fault[7:0] + 27/2051: $35\decision_deferred[0:0] + 28/2051: $48\decision_ok[0:0] + 29/2051: $48\decision_fault[7:0] + 30/2051: $47\decision_fault[7:0] + 31/2051: $47\decision_ok[0:0] + 32/2051: $46\decision_fault[7:0] + 33/2051: $46\decision_ok[0:0] + 34/2051: $28\addr_c[31:0] + 35/2051: $28\addr_b[31:0] + 36/2051: $31\addr_a[31:0] + 37/2051: $34\decision_deferred[0:0] + 38/2051: $45\decision_ok[0:0] + 39/2051: $45\decision_fault[7:0] + 40/2051: $26\solved_b[127:0] + 41/2051: $26\solved_a[127:0] + 42/2051: $27\addr_c[31:0] + 43/2051: $27\addr_b[31:0] + 44/2051: $30\addr_a[31:0] + 45/2051: $24\inv_value[127:0] + 46/2051: $24\inv_present[7:0] + 47/2051: $24\val_c[127:0] + 48/2051: $24\pres_c[7:0] + 49/2051: $24\val_b[127:0] + 50/2051: $24\pres_b[7:0] + 51/2051: $24\val_a[127:0] + 52/2051: $24\pres_a[7:0] + 53/2051: $24\off_c[31:0] + 54/2051: $24\off_b[31:0] + 55/2051: $24\off_a[31:0] + 56/2051: $29\decision_detail[7:0] + 57/2051: $44\decision_fault[7:0] + 58/2051: $44\decision_ok[0:0] + 59/2051: $28\decision_detail[7:0] + 60/2051: $43\decision_fault[7:0] + 61/2051: $43\decision_ok[0:0] + 62/2051: $42\decision_fault[7:0] + 63/2051: $42\decision_ok[0:0] + 64/2051: $33\decision_deferred[0:0] + 65/2051: $41\decision_fault[7:0] + 66/2051: $41\decision_ok[0:0] + 67/2051: $32\decision_deferred[0:0] + 68/2051: $31\decision_deferred[0:0] + 69/2051: $40\decision_ok[0:0] + 70/2051: $40\decision_fault[7:0] + 71/2051: $27\decision_detail[7:0] + 72/2051: $26\decision_detail[7:0] + 73/2051: $39\decision_fault[7:0] + 74/2051: $39\decision_ok[0:0] + 75/2051: $30\decision_deferred[0:0] + 76/2051: $38\decision_fault[7:0] + 77/2051: $38\decision_ok[0:0] + 78/2051: $29\decision_deferred[0:0] + 79/2051: $25\decision_detail[7:0] + 80/2051: $37\decision_fault[7:0] + 81/2051: $37\decision_ok[0:0] + 82/2051: $28\decision_deferred[0:0] + 83/2051: $24\decision_detail[7:0] + 84/2051: $26\addr_c[31:0] + 85/2051: $26\addr_b[31:0] + 86/2051: $29\addr_a[31:0] + 87/2051: $27\decision_deferred[0:0] + 88/2051: $36\decision_ok[0:0] + 89/2051: $23\decision_detail[7:0] + 90/2051: $36\decision_fault[7:0] + 91/2051: $25\addr_c[31:0] + 92/2051: $25\addr_b[31:0] + 93/2051: $28\addr_a[31:0] + 94/2051: $23\inv_value[127:0] + 95/2051: $23\inv_present[7:0] + 96/2051: $23\proposed_fp[31:0] + 97/2051: $23\proposed_pc[31:0] + 98/2051: $23\val_c[127:0] + 99/2051: $23\val_b[127:0] + 100/2051: $23\val_a[127:0] + 101/2051: $23\off_c[31:0] + 102/2051: $23\off_b[31:0] + 103/2051: $23\off_a[31:0] + 104/2051: $25\solved_b[127:0] + 105/2051: $25\solved_a[127:0] + 106/2051: $23\pres_c[7:0] + 107/2051: $23\pres_b[7:0] + 108/2051: $23\pres_a[7:0] + 109/2051: $35\decision_fault[7:0] + 110/2051: $35\decision_ok[0:0] + 111/2051: $26\decision_deferred[0:0] + 112/2051: $34\decision_fault[7:0] + 113/2051: $34\decision_ok[0:0] + 114/2051: $25\decision_deferred[0:0] + 115/2051: $24\addr_c[31:0] + 116/2051: $24\addr_b[31:0] + 117/2051: $27\addr_a[31:0] + 118/2051: $33\decision_fault[7:0] + 119/2051: $33\decision_ok[0:0] + 120/2051: $24\decision_deferred[0:0] + 121/2051: $23\addr_c[31:0] + 122/2051: $23\addr_b[31:0] + 123/2051: $26\addr_a[31:0] + 124/2051: $23\decision_deferred[0:0] + 125/2051: $32\decision_ok[0:0] + 126/2051: $32\decision_fault[7:0] + 127/2051: $22\addr_c[31:0] + 128/2051: $22\addr_b[31:0] + 129/2051: $25\addr_a[31:0] + 130/2051: $22\val_c[127:0] + 131/2051: $22\pres_c[7:0] + 132/2051: $22\val_b[127:0] + 133/2051: $22\pres_b[7:0] + 134/2051: $22\base_index[31:0] + 135/2051: $22\val_a[127:0] + 136/2051: $22\off_c[31:0] + 137/2051: $22\off_b[31:0] + 138/2051: $22\off_a[31:0] + 139/2051: $22\decision_detail[7:0] + 140/2051: $24\solved_b[127:0] + 141/2051: $24\solved_a[127:0] + 142/2051: $22\inv_value[127:0] + 143/2051: $22\inv_present[7:0] + 144/2051: $22\pres_a[7:0] + 145/2051: $22\proposed_fp[31:0] + 146/2051: $22\proposed_pc[31:0] + 147/2051: $36\n_writes[31:0] + 148/2051: $36\write_value[127:0] + 149/2051: $36\write_address[31:0] + 150/2051: $24\addr_a[31:0] + 151/2051: $31\decision_fault[7:0] + 152/2051: $31\decision_ok[0:0] + 153/2051: $35\write_address[31:0] + 154/2051: $23\addr_a[31:0] + 155/2051: $35\n_writes[31:0] + 156/2051: $35\write_value[127:0] + 157/2051: $30\decision_fault[7:0] + 158/2051: $30\decision_ok[0:0] + 159/2051: $34\write_address[31:0] + 160/2051: $22\addr_a[31:0] + 161/2051: $34\n_writes[31:0] + 162/2051: $34\write_value[127:0] + 163/2051: $21\addr_c[31:0] + 164/2051: $21\addr_b[31:0] + 165/2051: $21\addr_a[31:0] + 166/2051: $29\decision_ok[0:0] + 167/2051: $29\decision_fault[7:0] + 168/2051: $33\write_address[31:0] + 169/2051: $33\n_writes[31:0] + 170/2051: $33\write_value[127:0] + 171/2051: $21\val_a[127:0] + 172/2051: $21\pres_a[7:0] + 173/2051: $21\result_value[127:0] + 174/2051: $21\off_a[31:0] + 175/2051: $22\decision_deferred[0:0] + 176/2051: $21\decision_detail[7:0] + 177/2051: $23\solved_b[127:0] + 178/2051: $23\solved_a[127:0] + 179/2051: $21\inv_value[127:0] + 180/2051: $21\val_c[127:0] + 181/2051: $21\val_b[127:0] + 182/2051: $21\inv_present[7:0] + 183/2051: $21\pres_c[7:0] + 184/2051: $21\pres_b[7:0] + 185/2051: $21\proposed_fp[31:0] + 186/2051: $21\proposed_pc[31:0] + 187/2051: $21\base_index[31:0] + 188/2051: $21\off_c[31:0] + 189/2051: $21\off_b[31:0] + 190/2051: $21\decision_deferred[0:0] + 191/2051: $28\decision_fault[7:0] + 192/2051: $28\decision_ok[0:0] + 193/2051: $27\decision_fault[7:0] + 194/2051: $27\decision_ok[0:0] + 195/2051: $26\decision_fault[7:0] + 196/2051: $26\decision_ok[0:0] + 197/2051: $25\decision_fault[7:0] + 198/2051: $25\decision_ok[0:0] + 199/2051: $24\decision_fault[7:0] + 200/2051: $24\decision_ok[0:0] + 201/2051: $20\decision_deferred[0:0] + 202/2051: $23\decision_ok[0:0] + 203/2051: $23\decision_fault[7:0] + 204/2051: $20\staged_access[6][31:0] + 205/2051: $20\staged_access[4][31:0] + 206/2051: $20\staged_access[3][31:0] + 207/2051: $20\staged_access[2][31:0] + 208/2051: $20\staged_access[1][31:0] + 209/2051: $20\staged_access[0][31:0] + 210/2051: $20\decision_detail[7:0] + 211/2051: $32\write_address[31:0] + 212/2051: $22\solved_b[127:0] + 213/2051: $22\solved_a[127:0] + 214/2051: $20\result_value[127:0] + 215/2051: $20\inv_value[127:0] + 216/2051: $20\val_c[127:0] + 217/2051: $20\val_b[127:0] + 218/2051: $20\val_a[127:0] + 219/2051: $20\inv_present[7:0] + 220/2051: $20\pres_c[7:0] + 221/2051: $20\pres_b[7:0] + 222/2051: $20\pres_a[7:0] + 223/2051: $20\proposed_fp[31:0] + 224/2051: $20\proposed_pc[31:0] + 225/2051: $20\base_index[31:0] + 226/2051: $20\addr_c[31:0] + 227/2051: $20\addr_b[31:0] + 228/2051: $20\addr_a[31:0] + 229/2051: $20\off_c[31:0] + 230/2051: $20\off_b[31:0] + 231/2051: $20\off_a[31:0] + 232/2051: $32\n_writes[31:0] + 233/2051: $32\write_value[127:0] + 234/2051: $22\decision_fault[7:0] + 235/2051: $22\decision_ok[0:0] + 236/2051: $21\decision_fault[7:0] + 237/2051: $21\decision_ok[0:0] + 238/2051: $20\decision_fault[7:0] + 239/2051: $20\decision_ok[0:0] + 240/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4210 + 241/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4209 + 242/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4208 + 243/2051: $19\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4214 + 244/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4213 + 245/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4212 + 246/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4211 + 247/2051: $19\staged_access[6][31:0] + 248/2051: $19\staged_access[4][31:0] + 249/2051: $19\staged_access[3][31:0] + 250/2051: $19\staged_access[2][31:0] + 251/2051: $19\staged_access[1][31:0] + 252/2051: $19\staged_access[0][31:0] + 253/2051: $19\decision_deferred[0:0] + 254/2051: $19\decision_ok[0:0] + 255/2051: $19\decision_detail[7:0] + 256/2051: $19\decision_fault[7:0] + 257/2051: $31\write_address[31:0] + 258/2051: $21\solved_b[127:0] + 259/2051: $21\solved_a[127:0] + 260/2051: $19\result_value[127:0] + 261/2051: $19\inv_value[127:0] + 262/2051: $19\val_c[127:0] + 263/2051: $19\val_b[127:0] + 264/2051: $19\val_a[127:0] + 265/2051: $19\inv_present[7:0] + 266/2051: $19\pres_c[7:0] + 267/2051: $19\pres_b[7:0] + 268/2051: $19\pres_a[7:0] + 269/2051: $19\profile[7:0] + 270/2051: $26\deferred_local[31:0] + 271/2051: $26\deferred_target[31:0] + 272/2051: $21\next_fp_value[31:0] + 273/2051: $21\next_pc_value[31:0] + 274/2051: $19\proposed_fp[31:0] + 275/2051: $19\proposed_pc[31:0] + 276/2051: $19\base_index[31:0] + 277/2051: $19\addr_c[31:0] + 278/2051: $19\addr_b[31:0] + 279/2051: $19\addr_a[31:0] + 280/2051: $19\off_c[31:0] + 281/2051: $19\off_b[31:0] + 282/2051: $19\off_a[31:0] + 283/2051: $19\fp[31:0] + 284/2051: $19\pc[31:0] + 285/2051: $19\txn_id[31:0] + 286/2051: $50\result_length[31:0] + 287/2051: $26\n_deferred[31:0] + 288/2051: $31\n_writes[31:0] + 289/2051: $31\write_value[127:0] + 290/2051: $25\staged_write_count[1:0] + 291/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4203 + 292/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4202 + 293/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4201 + 294/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4200 + 295/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4199 + 296/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4198 + 297/2051: $24\staged_write_count[1:0] + 298/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4193 + 299/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4192 + 300/2051: $24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4191 + 301/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4190 + 302/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4189 + 303/2051: $24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4188 + 304/2051: $23\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4173 + 305/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4186 + 306/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4185 + 307/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4184 + 308/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4183 + 309/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4182 + 310/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4181 + 311/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4180 + 312/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4179 + 313/2051: $23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4178 + 314/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4177 + 315/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4176 + 316/2051: $23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4175 + 317/2051: $23\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4174 + 318/2051: $23\staged_write_count[1:0] + 319/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4145 + 320/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4144 + 321/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4159 + 322/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4158 + 323/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4157 + 324/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4156 + 325/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4155 + 326/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4154 + 327/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4153 + 328/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4152 + 329/2051: $22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4151 + 330/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4150 + 331/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4149 + 332/2051: $22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4148 + 333/2051: $22\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4147 + 334/2051: $22\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4146 + 335/2051: $22\staged_write_count[1:0] + 336/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4122 + 337/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4138 + 338/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4137 + 339/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4136 + 340/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4135 + 341/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4134 + 342/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4133 + 343/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4132 + 344/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4131 + 345/2051: $21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4130 + 346/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4129 + 347/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4128 + 348/2051: $21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4127 + 349/2051: $21\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4126 + 350/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4125 + 351/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4124 + 352/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4123 + 353/2051: $21\staged_write_count[1:0] + 354/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4120 + 355/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4119 + 356/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4118 + 357/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4117 + 358/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4116 + 359/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4115 + 360/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4114 + 361/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4113 + 362/2051: $20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4112 + 363/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4111 + 364/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4110 + 365/2051: $20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4109 + 366/2051: $20\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4108 + 367/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4107 + 368/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4106 + 369/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4105 + 370/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4104 + 371/2051: $20\staged_write_count[1:0] + 372/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4085 + 373/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4102 + 374/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4101 + 375/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4100 + 376/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4099 + 377/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4098 + 378/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4097 + 379/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4096 + 380/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4095 + 381/2051: $19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4094 + 382/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4093 + 383/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4092 + 384/2051: $19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4091 + 385/2051: $19\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4090 + 386/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4089 + 387/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4088 + 388/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4087 + 389/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4086 + 390/2051: $19\staged_write_count[1:0] + 391/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4083 + 392/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4082 + 393/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4081 + 394/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4080 + 395/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4079 + 396/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4078 + 397/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4077 + 398/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4076 + 399/2051: $18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4075 + 400/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4074 + 401/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4073 + 402/2051: $18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4072 + 403/2051: $18\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4064 + 404/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4063 + 405/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4062 + 406/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4061 + 407/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4060 + 408/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4059 + 409/2051: $18\staged_write_count[1:0] + 410/2051: $18\txn_id[31:0] + 411/2051: $18\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4071 + 412/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4070 + 413/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4069 + 414/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4068 + 415/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4067 + 416/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4066 + 417/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4065 + 418/2051: $18\staged_access[6][31:0] + 419/2051: $18\staged_access[4][31:0] + 420/2051: $18\staged_access[3][31:0] + 421/2051: $18\staged_access[2][31:0] + 422/2051: $18\staged_access[1][31:0] + 423/2051: $18\staged_access[0][31:0] + 424/2051: $18\decision_deferred[0:0] + 425/2051: $18\decision_ok[0:0] + 426/2051: $18\decision_detail[7:0] + 427/2051: $18\decision_fault[7:0] + 428/2051: $30\write_address[31:0] + 429/2051: $20\solved_b[127:0] + 430/2051: $20\solved_a[127:0] + 431/2051: $18\result_value[127:0] + 432/2051: $18\inv_value[127:0] + 433/2051: $18\val_c[127:0] + 434/2051: $18\val_b[127:0] + 435/2051: $18\val_a[127:0] + 436/2051: $18\inv_present[7:0] + 437/2051: $18\pres_c[7:0] + 438/2051: $18\pres_b[7:0] + 439/2051: $18\pres_a[7:0] + 440/2051: $18\profile[7:0] + 441/2051: $25\deferred_local[31:0] + 442/2051: $25\deferred_target[31:0] + 443/2051: $20\next_fp_value[31:0] + 444/2051: $20\next_pc_value[31:0] + 445/2051: $18\proposed_fp[31:0] + 446/2051: $18\proposed_pc[31:0] + 447/2051: $18\base_index[31:0] + 448/2051: $18\addr_c[31:0] + 449/2051: $18\addr_b[31:0] + 450/2051: $18\addr_a[31:0] + 451/2051: $18\off_c[31:0] + 452/2051: $18\off_b[31:0] + 453/2051: $18\off_a[31:0] + 454/2051: $18\fp[31:0] + 455/2051: $18\pc[31:0] + 456/2051: $49\result_length[31:0] + 457/2051: $25\n_deferred[31:0] + 458/2051: $30\n_writes[31:0] + 459/2051: $30\write_value[127:0] + 460/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4054 + 461/2051: $21\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4053 + 462/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4047 + 463/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4049 + 464/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4048 + 465/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4044 + 466/2051: $20\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4043 + 467/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4038 + 468/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4037 + 469/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4041 + 470/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4040 + 471/2051: $19\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4039 + 472/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$4031 + 473/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4036 + 474/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4035 + 475/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4034 + 476/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4033 + 477/2051: $18\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4032 + 478/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$4004 + 479/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$4003 + 480/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$4002 + 481/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$4001 + 482/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$4000 + 483/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3999 + 484/2051: $17\txn_id[31:0] + 485/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4029 + 486/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$4028 + 487/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$4027 + 488/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4026 + 489/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$4025 + 490/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4024 + 491/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4023 + 492/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$4022 + 493/2051: $17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$4021 + 494/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4020 + 495/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$4019 + 496/2051: $17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4018 + 497/2051: $17\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$4017 + 498/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$4016 + 499/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$4015 + 500/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$4014 + 501/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$4013 + 502/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$4012 + 503/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$4011 + 504/2051: $17\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$4010 + 505/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$4009 + 506/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$4008 + 507/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$4007 + 508/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$4006 + 509/2051: $17\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$4005 + 510/2051: $17\staged_access[6][31:0] + 511/2051: $17\staged_access[4][31:0] + 512/2051: $17\staged_access[3][31:0] + 513/2051: $17\staged_access[2][31:0] + 514/2051: $17\staged_access[1][31:0] + 515/2051: $17\staged_access[0][31:0] + 516/2051: $17\decision_deferred[0:0] + 517/2051: $17\decision_ok[0:0] + 518/2051: $17\decision_detail[7:0] + 519/2051: $17\decision_fault[7:0] + 520/2051: $29\write_address[31:0] + 521/2051: $19\solved_b[127:0] + 522/2051: $19\solved_a[127:0] + 523/2051: $17\result_value[127:0] + 524/2051: $17\inv_value[127:0] + 525/2051: $17\val_c[127:0] + 526/2051: $17\val_b[127:0] + 527/2051: $17\val_a[127:0] + 528/2051: $17\inv_present[7:0] + 529/2051: $17\pres_c[7:0] + 530/2051: $17\pres_b[7:0] + 531/2051: $17\pres_a[7:0] + 532/2051: $17\profile[7:0] + 533/2051: $24\deferred_local[31:0] + 534/2051: $24\deferred_target[31:0] + 535/2051: $19\next_fp_value[31:0] + 536/2051: $19\next_pc_value[31:0] + 537/2051: $17\proposed_fp[31:0] + 538/2051: $17\proposed_pc[31:0] + 539/2051: $17\base_index[31:0] + 540/2051: $17\addr_c[31:0] + 541/2051: $17\addr_b[31:0] + 542/2051: $17\addr_a[31:0] + 543/2051: $17\off_c[31:0] + 544/2051: $17\off_b[31:0] + 545/2051: $17\off_a[31:0] + 546/2051: $17\fp[31:0] + 547/2051: $17\pc[31:0] + 548/2051: $48\result_length[31:0] + 549/2051: $24\n_deferred[31:0] + 550/2051: $29\n_writes[31:0] + 551/2051: $17\staged_write_count[1:0] + 552/2051: $29\write_value[127:0] + 553/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3988 + 554/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3987 + 555/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3986 + 556/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3985 + 557/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3984 + 558/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3983 + 559/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3982 + 560/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3981 + 561/2051: $16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3980 + 562/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3979 + 563/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3978 + 564/2051: $16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3977 + 565/2051: $16\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3976 + 566/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3975 + 567/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3974 + 568/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3973 + 569/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3972 + 570/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3971 + 571/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3970 + 572/2051: $16\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3969 + 573/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3968 + 574/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3967 + 575/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3966 + 576/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3965 + 577/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3964 + 578/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3963 + 579/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3962 + 580/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3961 + 581/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3960 + 582/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3959 + 583/2051: $16\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3958 + 584/2051: $16\staged_access[6][31:0] + 585/2051: $16\staged_access[4][31:0] + 586/2051: $16\staged_access[3][31:0] + 587/2051: $16\staged_access[2][31:0] + 588/2051: $16\staged_access[1][31:0] + 589/2051: $16\staged_access[0][31:0] + 590/2051: $16\decision_deferred[0:0] + 591/2051: $16\decision_ok[0:0] + 592/2051: $16\decision_detail[7:0] + 593/2051: $16\decision_fault[7:0] + 594/2051: $28\write_address[31:0] + 595/2051: $18\solved_b[127:0] + 596/2051: $18\solved_a[127:0] + 597/2051: $16\result_value[127:0] + 598/2051: $16\inv_value[127:0] + 599/2051: $16\val_c[127:0] + 600/2051: $16\val_b[127:0] + 601/2051: $16\val_a[127:0] + 602/2051: $16\inv_present[7:0] + 603/2051: $16\pres_c[7:0] + 604/2051: $16\pres_b[7:0] + 605/2051: $16\pres_a[7:0] + 606/2051: $16\profile[7:0] + 607/2051: $23\deferred_local[31:0] + 608/2051: $23\deferred_target[31:0] + 609/2051: $18\next_fp_value[31:0] + 610/2051: $18\next_pc_value[31:0] + 611/2051: $16\proposed_fp[31:0] + 612/2051: $16\proposed_pc[31:0] + 613/2051: $16\base_index[31:0] + 614/2051: $16\addr_c[31:0] + 615/2051: $16\addr_b[31:0] + 616/2051: $16\addr_a[31:0] + 617/2051: $16\off_c[31:0] + 618/2051: $16\off_b[31:0] + 619/2051: $16\off_a[31:0] + 620/2051: $16\fp[31:0] + 621/2051: $16\pc[31:0] + 622/2051: $16\txn_id[31:0] + 623/2051: $47\result_length[31:0] + 624/2051: $23\n_deferred[31:0] + 625/2051: $28\n_writes[31:0] + 626/2051: $16\staged_write_count[1:0] + 627/2051: $28\write_value[127:0] + 628/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3952 + 629/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3951 + 630/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3950 + 631/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3949 + 632/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3948 + 633/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3947 + 634/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3946 + 635/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3945 + 636/2051: $15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3944 + 637/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3943 + 638/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3942 + 639/2051: $15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3941 + 640/2051: $15\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3940 + 641/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3939 + 642/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3938 + 643/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3937 + 644/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3936 + 645/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3935 + 646/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3934 + 647/2051: $15\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3933 + 648/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3932 + 649/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3931 + 650/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3930 + 651/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3929 + 652/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3928 + 653/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3927 + 654/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3926 + 655/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3925 + 656/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3924 + 657/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3923 + 658/2051: $15\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3922 + 659/2051: $15\staged_access[6][31:0] + 660/2051: $15\staged_access[4][31:0] + 661/2051: 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691/2051: $15\addr_a[31:0] + 692/2051: $15\off_c[31:0] + 693/2051: $15\off_b[31:0] + 694/2051: $15\off_a[31:0] + 695/2051: $15\fp[31:0] + 696/2051: $15\pc[31:0] + 697/2051: $15\txn_id[31:0] + 698/2051: $46\result_length[31:0] + 699/2051: $22\n_deferred[31:0] + 700/2051: $27\n_writes[31:0] + 701/2051: $15\staged_write_count[1:0] + 702/2051: $27\write_value[127:0] + 703/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3887 + 704/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3886 + 705/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3918 + 706/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3917 + 707/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3916 + 708/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3915 + 709/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3914 + 710/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3913 + 711/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3912 + 712/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3911 + 713/2051: $14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3910 + 714/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3909 + 715/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3908 + 716/2051: $14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3907 + 717/2051: $14\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3906 + 718/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3905 + 719/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3904 + 720/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3903 + 721/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3902 + 722/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3901 + 723/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3900 + 724/2051: $14\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3899 + 725/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3898 + 726/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3897 + 727/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3896 + 728/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3895 + 729/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3894 + 730/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3893 + 731/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3892 + 732/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3891 + 733/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3890 + 734/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3889 + 735/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3888 + 736/2051: $14\staged_access[6][31:0] + 737/2051: $14\staged_access[4][31:0] + 738/2051: $14\staged_access[3][31:0] + 739/2051: $14\staged_access[2][31:0] + 740/2051: $14\staged_access[1][31:0] + 741/2051: $14\staged_access[0][31:0] + 742/2051: $14\decision_deferred[0:0] + 743/2051: $14\decision_ok[0:0] + 744/2051: $14\decision_detail[7:0] + 745/2051: $14\decision_fault[7:0] + 746/2051: $26\write_address[31:0] + 747/2051: $16\solved_b[127:0] + 748/2051: $16\solved_a[127:0] + 749/2051: $14\result_value[127:0] + 750/2051: $14\inv_value[127:0] + 751/2051: $14\val_c[127:0] + 752/2051: $14\val_b[127:0] + 753/2051: $14\val_a[127:0] + 754/2051: $14\inv_present[7:0] + 755/2051: $14\pres_c[7:0] + 756/2051: $14\pres_b[7:0] + 757/2051: $14\pres_a[7:0] + 758/2051: $14\profile[7:0] + 759/2051: $21\deferred_local[31:0] + 760/2051: $21\deferred_target[31:0] + 761/2051: $16\next_fp_value[31:0] + 762/2051: $16\next_pc_value[31:0] + 763/2051: $14\proposed_fp[31:0] + 764/2051: $14\proposed_pc[31:0] + 765/2051: $14\base_index[31:0] + 766/2051: $14\addr_c[31:0] + 767/2051: $14\addr_b[31:0] + 768/2051: $14\addr_a[31:0] + 769/2051: $14\off_c[31:0] + 770/2051: $14\off_b[31:0] + 771/2051: $14\off_a[31:0] + 772/2051: $14\fp[31:0] + 773/2051: $14\pc[31:0] + 774/2051: $14\txn_id[31:0] + 775/2051: $45\result_length[31:0] + 776/2051: $21\n_deferred[31:0] + 777/2051: $26\n_writes[31:0] + 778/2051: $14\staged_write_count[1:0] + 779/2051: $26\write_value[127:0] + 780/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3885 + 781/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3884 + 782/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3883 + 783/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3882 + 784/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3881 + 785/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3880 + 786/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3879 + 787/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3878 + 788/2051: $13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3877 + 789/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3876 + 790/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3875 + 791/2051: $13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3874 + 792/2051: $13\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3873 + 793/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3872 + 794/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3871 + 795/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3870 + 796/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3869 + 797/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3868 + 798/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3867 + 799/2051: $13\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3866 + 800/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3865 + 801/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3864 + 802/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3863 + 803/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3862 + 804/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3861 + 805/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3860 + 806/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3859 + 807/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3858 + 808/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3857 + 809/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3856 + 810/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3855 + 811/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3854 + 812/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3853 + 813/2051: $13\staged_access[6][31:0] + 814/2051: $13\staged_access[4][31:0] + 815/2051: $13\staged_access[3][31:0] + 816/2051: $13\staged_access[2][31:0] + 817/2051: $13\staged_access[1][31:0] + 818/2051: $13\staged_access[0][31:0] + 819/2051: $13\decision_deferred[0:0] + 820/2051: $13\decision_ok[0:0] + 821/2051: $13\decision_detail[7:0] + 822/2051: $13\decision_fault[7:0] + 823/2051: $25\write_address[31:0] + 824/2051: $15\solved_b[127:0] + 825/2051: $15\solved_a[127:0] + 826/2051: $13\result_value[127:0] + 827/2051: $13\inv_value[127:0] + 828/2051: $13\val_c[127:0] + 829/2051: $13\val_b[127:0] + 830/2051: $13\val_a[127:0] + 831/2051: $13\inv_present[7:0] + 832/2051: $13\pres_c[7:0] + 833/2051: $13\pres_b[7:0] + 834/2051: $13\pres_a[7:0] + 835/2051: $13\profile[7:0] + 836/2051: $20\deferred_local[31:0] + 837/2051: $20\deferred_target[31:0] + 838/2051: $15\next_fp_value[31:0] + 839/2051: $15\next_pc_value[31:0] + 840/2051: $13\proposed_fp[31:0] + 841/2051: $13\proposed_pc[31:0] + 842/2051: $13\base_index[31:0] + 843/2051: $13\addr_c[31:0] + 844/2051: $13\addr_b[31:0] + 845/2051: $13\addr_a[31:0] + 846/2051: $13\off_c[31:0] + 847/2051: $13\off_b[31:0] + 848/2051: $13\off_a[31:0] + 849/2051: $13\fp[31:0] + 850/2051: $13\pc[31:0] + 851/2051: $13\txn_id[31:0] + 852/2051: $44\result_length[31:0] + 853/2051: $20\n_deferred[31:0] + 854/2051: $25\n_writes[31:0] + 855/2051: $13\staged_write_count[1:0] + 856/2051: $25\write_value[127:0] + 857/2051: $43\result_length[31:0] + 858/2051: $42\result_length[31:0] + 859/2051: $41\result_length[31:0] + 860/2051: $40\result_length[31:0] + 861/2051: $24\n_writes[31:0] + 862/2051: $24\write_value[127:0] + 863/2051: $24\write_address[31:0] + 864/2051: $14\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3847 + 865/2051: $23\write_address[31:0] + 866/2051: $39\result_length[31:0] + 867/2051: $23\n_writes[31:0] + 868/2051: $23\write_value[127:0] + 869/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3842 + 870/2051: $13\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3844 + 871/2051: $13\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3843 + 872/2051: $22\write_address[31:0] + 873/2051: $38\result_length[31:0] + 874/2051: $22\n_writes[31:0] + 875/2051: $22\write_value[127:0] + 876/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3808 + 877/2051: $12\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3807 + 878/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3806 + 879/2051: $21\write_address[31:0] + 880/2051: $37\result_length[31:0] + 881/2051: $21\n_writes[31:0] + 882/2051: $21\write_value[127:0] + 883/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3841 + 884/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3840 + 885/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3839 + 886/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3838 + 887/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3837 + 888/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3836 + 889/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3835 + 890/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3834 + 891/2051: $12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3833 + 892/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3832 + 893/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3831 + 894/2051: $12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3830 + 895/2051: $12\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3829 + 896/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3828 + 897/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3827 + 898/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3826 + 899/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3825 + 900/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3824 + 901/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3823 + 902/2051: $12\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3822 + 903/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3821 + 904/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3820 + 905/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3819 + 906/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3818 + 907/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3817 + 908/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3816 + 909/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3815 + 910/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3814 + 911/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3813 + 912/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3812 + 913/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3811 + 914/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3810 + 915/2051: $12\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3809 + 916/2051: $12\staged_access[6][31:0] + 917/2051: $12\staged_access[4][31:0] + 918/2051: $12\staged_access[3][31:0] + 919/2051: $12\staged_access[2][31:0] + 920/2051: $12\staged_access[1][31:0] + 921/2051: $12\staged_access[0][31:0] + 922/2051: $12\decision_deferred[0:0] + 923/2051: $12\decision_ok[0:0] + 924/2051: $12\decision_detail[7:0] + 925/2051: $12\decision_fault[7:0] + 926/2051: $14\solved_b[127:0] + 927/2051: $14\solved_a[127:0] + 928/2051: $12\result_value[127:0] + 929/2051: $12\inv_value[127:0] + 930/2051: $12\val_c[127:0] + 931/2051: $12\val_b[127:0] + 932/2051: $12\val_a[127:0] + 933/2051: $12\inv_present[7:0] + 934/2051: $12\pres_c[7:0] + 935/2051: $12\pres_b[7:0] + 936/2051: $12\pres_a[7:0] + 937/2051: $12\profile[7:0] + 938/2051: $19\deferred_local[31:0] + 939/2051: $19\deferred_target[31:0] + 940/2051: $14\next_fp_value[31:0] + 941/2051: $14\next_pc_value[31:0] + 942/2051: $12\proposed_fp[31:0] + 943/2051: $12\proposed_pc[31:0] + 944/2051: $12\base_index[31:0] + 945/2051: $12\addr_c[31:0] + 946/2051: $12\addr_b[31:0] + 947/2051: $12\addr_a[31:0] + 948/2051: $12\off_c[31:0] + 949/2051: $12\off_b[31:0] + 950/2051: $12\off_a[31:0] + 951/2051: $12\fp[31:0] + 952/2051: $12\pc[31:0] + 953/2051: $12\txn_id[31:0] + 954/2051: $19\n_deferred[31:0] + 955/2051: $12\staged_write_count[1:0] + 956/2051: $13\solved_a[127:0] + 957/2051: $13\solved_b[127:0] + 958/2051: $20\n_writes[31:0] + 959/2051: $20\write_value[127:0] + 960/2051: $20\write_address[31:0] + 961/2051: $12\solved_b[127:0] + 962/2051: $12\solved_a[127:0] + 963/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3798 + 964/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3797 + 965/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3796 + 966/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3795 + 967/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3794 + 968/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3793 + 969/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3792 + 970/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3791 + 971/2051: $11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3790 + 972/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3789 + 973/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3788 + 974/2051: $11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3787 + 975/2051: $11\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3786 + 976/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3785 + 977/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3784 + 978/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3783 + 979/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3782 + 980/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3781 + 981/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3780 + 982/2051: $11\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3779 + 983/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3778 + 984/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3777 + 985/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3776 + 986/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3775 + 987/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3774 + 988/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3773 + 989/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3772 + 990/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3771 + 991/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3770 + 992/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3769 + 993/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3768 + 994/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3767 + 995/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3766 + 996/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3765 + 997/2051: $11\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3764 + 998/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3763 + 999/2051: $11\staged_access[6][31:0] + 1000/2051: $11\staged_access[4][31:0] + 1001/2051: $11\staged_access[3][31:0] + 1002/2051: $11\staged_access[2][31:0] + 1003/2051: $11\staged_access[1][31:0] + 1004/2051: $11\staged_access[0][31:0] + 1005/2051: $11\decision_deferred[0:0] + 1006/2051: $11\decision_ok[0:0] + 1007/2051: $11\decision_detail[7:0] + 1008/2051: $11\decision_fault[7:0] + 1009/2051: $11\result_value[127:0] + 1010/2051: $11\inv_value[127:0] + 1011/2051: $11\val_c[127:0] + 1012/2051: $11\val_b[127:0] + 1013/2051: $11\val_a[127:0] + 1014/2051: $11\inv_present[7:0] + 1015/2051: $11\pres_c[7:0] + 1016/2051: $11\pres_b[7:0] + 1017/2051: $11\pres_a[7:0] + 1018/2051: $11\profile[7:0] + 1019/2051: $18\deferred_local[31:0] + 1020/2051: $18\deferred_target[31:0] + 1021/2051: $13\next_fp_value[31:0] + 1022/2051: $13\next_pc_value[31:0] + 1023/2051: $11\proposed_fp[31:0] + 1024/2051: $11\proposed_pc[31:0] + 1025/2051: $11\base_index[31:0] + 1026/2051: $11\addr_c[31:0] + 1027/2051: $11\addr_b[31:0] + 1028/2051: $11\addr_a[31:0] + 1029/2051: $11\off_c[31:0] + 1030/2051: $11\off_b[31:0] + 1031/2051: $11\off_a[31:0] + 1032/2051: $11\fp[31:0] + 1033/2051: $11\pc[31:0] + 1034/2051: $11\txn_id[31:0] + 1035/2051: $36\result_length[31:0] + 1036/2051: $18\n_deferred[31:0] + 1037/2051: $11\staged_write_count[1:0] + 1038/2051: $11\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3760 + 1039/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3721 + 1040/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3757 + 1041/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3756 + 1042/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3755 + 1043/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3754 + 1044/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3753 + 1045/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3752 + 1046/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3751 + 1047/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3750 + 1048/2051: $10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3749 + 1049/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3748 + 1050/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3747 + 1051/2051: $10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3746 + 1052/2051: $10\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3745 + 1053/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3744 + 1054/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3743 + 1055/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3742 + 1056/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3741 + 1057/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3740 + 1058/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3739 + 1059/2051: $10\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3738 + 1060/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3737 + 1061/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3736 + 1062/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3735 + 1063/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3734 + 1064/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3733 + 1065/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3732 + 1066/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3731 + 1067/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3730 + 1068/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3729 + 1069/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3728 + 1070/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3727 + 1071/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3726 + 1072/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3725 + 1073/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3724 + 1074/2051: $10\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3723 + 1075/2051: $10\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3722 + 1076/2051: $10\staged_access[6][31:0] + 1077/2051: $10\staged_access[4][31:0] + 1078/2051: $10\staged_access[3][31:0] + 1079/2051: $10\staged_access[2][31:0] + 1080/2051: $10\staged_access[1][31:0] + 1081/2051: $10\staged_access[0][31:0] + 1082/2051: $10\decision_deferred[0:0] + 1083/2051: $10\decision_ok[0:0] + 1084/2051: $10\decision_detail[7:0] + 1085/2051: $10\decision_fault[7:0] + 1086/2051: $19\write_address[31:0] + 1087/2051: $11\solved_b[127:0] + 1088/2051: $11\solved_a[127:0] + 1089/2051: $10\result_value[127:0] + 1090/2051: $10\inv_value[127:0] + 1091/2051: $10\val_c[127:0] + 1092/2051: $10\val_b[127:0] + 1093/2051: $10\val_a[127:0] + 1094/2051: $10\inv_present[7:0] + 1095/2051: $10\pres_c[7:0] + 1096/2051: $10\pres_b[7:0] + 1097/2051: $10\pres_a[7:0] + 1098/2051: $10\profile[7:0] + 1099/2051: $17\deferred_local[31:0] + 1100/2051: $17\deferred_target[31:0] + 1101/2051: $12\next_fp_value[31:0] + 1102/2051: $12\next_pc_value[31:0] + 1103/2051: $10\proposed_fp[31:0] + 1104/2051: $10\proposed_pc[31:0] + 1105/2051: $10\base_index[31:0] + 1106/2051: $10\addr_c[31:0] + 1107/2051: $10\addr_b[31:0] + 1108/2051: $10\addr_a[31:0] + 1109/2051: $10\off_c[31:0] + 1110/2051: $10\off_b[31:0] + 1111/2051: $10\off_a[31:0] + 1112/2051: $10\fp[31:0] + 1113/2051: $10\pc[31:0] + 1114/2051: $10\txn_id[31:0] + 1115/2051: $35\result_length[31:0] + 1116/2051: $17\n_deferred[31:0] + 1117/2051: $19\n_writes[31:0] + 1118/2051: $10\staged_write_count[1:0] + 1119/2051: $19\write_value[127:0] + 1120/2051: $10\solved_a[127:0] + 1121/2051: $10\solved_b[127:0] + 1122/2051: $18\n_writes[31:0] + 1123/2051: $18\write_value[127:0] + 1124/2051: $18\write_address[31:0] + 1125/2051: $9\solved_b[127:0] + 1126/2051: $9\solved_a[127:0] + 1127/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3715 + 1128/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3714 + 1129/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3713 + 1130/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3712 + 1131/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3711 + 1132/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3710 + 1133/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3709 + 1134/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3708 + 1135/2051: $9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3707 + 1136/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3706 + 1137/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3705 + 1138/2051: $9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3704 + 1139/2051: $9\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3703 + 1140/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3702 + 1141/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3701 + 1142/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3700 + 1143/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3699 + 1144/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3698 + 1145/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3697 + 1146/2051: $9\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3696 + 1147/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3695 + 1148/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3694 + 1149/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3693 + 1150/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3692 + 1151/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3691 + 1152/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3690 + 1153/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3689 + 1154/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3688 + 1155/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3687 + 1156/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3686 + 1157/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3685 + 1158/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3684 + 1159/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3683 + 1160/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3682 + 1161/2051: $9\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3681 + 1162/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3680 + 1163/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3679 + 1164/2051: $9\staged_access[6][31:0] + 1165/2051: $9\staged_access[4][31:0] + 1166/2051: $9\staged_access[3][31:0] + 1167/2051: $9\staged_access[2][31:0] + 1168/2051: $9\staged_access[1][31:0] + 1169/2051: $9\staged_access[0][31:0] + 1170/2051: $9\decision_deferred[0:0] + 1171/2051: $9\decision_ok[0:0] + 1172/2051: $9\decision_detail[7:0] + 1173/2051: $9\decision_fault[7:0] + 1174/2051: $9\result_value[127:0] + 1175/2051: $9\inv_value[127:0] + 1176/2051: $9\val_c[127:0] + 1177/2051: $9\val_b[127:0] + 1178/2051: $9\val_a[127:0] + 1179/2051: $9\inv_present[7:0] + 1180/2051: $9\pres_c[7:0] + 1181/2051: $9\pres_b[7:0] + 1182/2051: $9\pres_a[7:0] + 1183/2051: $9\profile[7:0] + 1184/2051: $16\deferred_local[31:0] + 1185/2051: $16\deferred_target[31:0] + 1186/2051: $11\next_fp_value[31:0] + 1187/2051: $11\next_pc_value[31:0] + 1188/2051: $9\proposed_fp[31:0] + 1189/2051: $9\proposed_pc[31:0] + 1190/2051: $9\base_index[31:0] + 1191/2051: $9\addr_c[31:0] + 1192/2051: $9\addr_b[31:0] + 1193/2051: $9\addr_a[31:0] + 1194/2051: $9\off_c[31:0] + 1195/2051: $9\off_b[31:0] + 1196/2051: $9\off_a[31:0] + 1197/2051: $9\fp[31:0] + 1198/2051: $9\pc[31:0] + 1199/2051: $9\txn_id[31:0] + 1200/2051: $34\result_length[31:0] + 1201/2051: $16\n_deferred[31:0] + 1202/2051: $9\staged_write_count[1:0] + 1203/2051: $33\result_length[31:0] + 1204/2051: $32\result_length[31:0] + 1205/2051: $31\result_length[31:0] + 1206/2051: $30\result_length[31:0] + 1207/2051: $9\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3673 + 1208/2051: $29\result_length[31:0] + 1209/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3633 + 1210/2051: $28\result_length[31:0] + 1211/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3670 + 1212/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3669 + 1213/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3668 + 1214/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3667 + 1215/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3666 + 1216/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3665 + 1217/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3664 + 1218/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3663 + 1219/2051: $8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3662 + 1220/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3661 + 1221/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3660 + 1222/2051: $8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3659 + 1223/2051: $8\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3658 + 1224/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3657 + 1225/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3656 + 1226/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3655 + 1227/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3654 + 1228/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3653 + 1229/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3652 + 1230/2051: $8\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3651 + 1231/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3650 + 1232/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3649 + 1233/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3648 + 1234/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3647 + 1235/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3646 + 1236/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3645 + 1237/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3644 + 1238/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3643 + 1239/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3642 + 1240/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3641 + 1241/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3640 + 1242/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3639 + 1243/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3638 + 1244/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3637 + 1245/2051: $8\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3636 + 1246/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3635 + 1247/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3634 + 1248/2051: $8\staged_access[6][31:0] + 1249/2051: $8\staged_access[4][31:0] + 1250/2051: $8\staged_access[3][31:0] + 1251/2051: $8\staged_access[2][31:0] + 1252/2051: $8\staged_access[1][31:0] + 1253/2051: $8\staged_access[0][31:0] + 1254/2051: $8\decision_deferred[0:0] + 1255/2051: $8\decision_ok[0:0] + 1256/2051: $8\decision_detail[7:0] + 1257/2051: $8\decision_fault[7:0] + 1258/2051: $17\write_address[31:0] + 1259/2051: $8\solved_b[127:0] + 1260/2051: $8\solved_a[127:0] + 1261/2051: $8\result_value[127:0] + 1262/2051: $8\inv_value[127:0] + 1263/2051: $8\val_c[127:0] + 1264/2051: $8\val_b[127:0] + 1265/2051: $8\val_a[127:0] + 1266/2051: $8\inv_present[7:0] + 1267/2051: $8\pres_c[7:0] + 1268/2051: $8\pres_b[7:0] + 1269/2051: $8\pres_a[7:0] + 1270/2051: $8\profile[7:0] + 1271/2051: $15\deferred_local[31:0] + 1272/2051: $15\deferred_target[31:0] + 1273/2051: $10\next_fp_value[31:0] + 1274/2051: $10\next_pc_value[31:0] + 1275/2051: $8\proposed_fp[31:0] + 1276/2051: $8\proposed_pc[31:0] + 1277/2051: $8\base_index[31:0] + 1278/2051: $8\addr_c[31:0] + 1279/2051: $8\addr_b[31:0] + 1280/2051: $8\addr_a[31:0] + 1281/2051: $8\off_c[31:0] + 1282/2051: $8\off_b[31:0] + 1283/2051: $8\off_a[31:0] + 1284/2051: $8\fp[31:0] + 1285/2051: $8\pc[31:0] + 1286/2051: $8\txn_id[31:0] + 1287/2051: $15\n_deferred[31:0] + 1288/2051: $17\n_writes[31:0] + 1289/2051: $8\staged_write_count[1:0] + 1290/2051: $17\write_value[127:0] + 1291/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3630 + 1292/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3589 + 1293/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3627 + 1294/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3626 + 1295/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3625 + 1296/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3624 + 1297/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3623 + 1298/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3622 + 1299/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3621 + 1300/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3620 + 1301/2051: $7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3619 + 1302/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3618 + 1303/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3617 + 1304/2051: $7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3616 + 1305/2051: $7\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3615 + 1306/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3614 + 1307/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3613 + 1308/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3612 + 1309/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3611 + 1310/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3610 + 1311/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3609 + 1312/2051: $7\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3608 + 1313/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3607 + 1314/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3606 + 1315/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3605 + 1316/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3604 + 1317/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3603 + 1318/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3602 + 1319/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3601 + 1320/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3600 + 1321/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3599 + 1322/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3598 + 1323/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3597 + 1324/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3596 + 1325/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3595 + 1326/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3594 + 1327/2051: $7\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3593 + 1328/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3592 + 1329/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3591 + 1330/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3590 + 1331/2051: $7\staged_access[6][31:0] + 1332/2051: $7\staged_access[4][31:0] + 1333/2051: $7\staged_access[3][31:0] + 1334/2051: $7\staged_access[2][31:0] + 1335/2051: $7\staged_access[1][31:0] + 1336/2051: $7\staged_access[0][31:0] + 1337/2051: $7\decision_deferred[0:0] + 1338/2051: $7\decision_ok[0:0] + 1339/2051: $7\decision_detail[7:0] + 1340/2051: $7\decision_fault[7:0] + 1341/2051: $16\write_address[31:0] + 1342/2051: $7\solved_b[127:0] + 1343/2051: $7\solved_a[127:0] + 1344/2051: $7\result_value[127:0] + 1345/2051: $7\inv_value[127:0] + 1346/2051: $7\val_c[127:0] + 1347/2051: $7\val_b[127:0] + 1348/2051: $7\val_a[127:0] + 1349/2051: $7\inv_present[7:0] + 1350/2051: $7\pres_c[7:0] + 1351/2051: $7\pres_b[7:0] + 1352/2051: $7\pres_a[7:0] + 1353/2051: $7\profile[7:0] + 1354/2051: $14\deferred_local[31:0] + 1355/2051: $14\deferred_target[31:0] + 1356/2051: $9\next_fp_value[31:0] + 1357/2051: $9\next_pc_value[31:0] + 1358/2051: $7\proposed_fp[31:0] + 1359/2051: $7\proposed_pc[31:0] + 1360/2051: $7\base_index[31:0] + 1361/2051: $7\addr_c[31:0] + 1362/2051: $7\addr_b[31:0] + 1363/2051: $7\addr_a[31:0] + 1364/2051: $7\off_c[31:0] + 1365/2051: $7\off_b[31:0] + 1366/2051: $7\off_a[31:0] + 1367/2051: $7\fp[31:0] + 1368/2051: $7\pc[31:0] + 1369/2051: $7\txn_id[31:0] + 1370/2051: $27\result_length[31:0] + 1371/2051: $14\n_deferred[31:0] + 1372/2051: $16\n_writes[31:0] + 1373/2051: $7\staged_write_count[1:0] + 1374/2051: $16\write_value[127:0] + 1375/2051: $26\result_length[31:0] + 1376/2051: $25\result_length[31:0] + 1377/2051: $24\result_length[31:0] + 1378/2051: $23\result_length[31:0] + 1379/2051: $8\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3583 + 1380/2051: $8\next_fp_value[31:0] + 1381/2051: $8\next_pc_value[31:0] + 1382/2051: $22\result_length[31:0] + 1383/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3580 + 1384/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3581 + 1385/2051: $7\next_fp_value[31:0] + 1386/2051: $7\next_pc_value[31:0] + 1387/2051: $21\result_length[31:0] + 1388/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3540 + 1389/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3539 + 1390/2051: $6\next_fp_value[31:0] + 1391/2051: $6\next_pc_value[31:0] + 1392/2051: $20\result_length[31:0] + 1393/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3579 + 1394/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3578 + 1395/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3577 + 1396/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3576 + 1397/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3575 + 1398/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3574 + 1399/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3573 + 1400/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3572 + 1401/2051: $6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3571 + 1402/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3570 + 1403/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3569 + 1404/2051: $6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3568 + 1405/2051: $6\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3567 + 1406/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3566 + 1407/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3565 + 1408/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3564 + 1409/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3563 + 1410/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3562 + 1411/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3561 + 1412/2051: $6\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3560 + 1413/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3559 + 1414/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3558 + 1415/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3557 + 1416/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3556 + 1417/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3555 + 1418/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3554 + 1419/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3553 + 1420/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3552 + 1421/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3551 + 1422/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3550 + 1423/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3549 + 1424/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3548 + 1425/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3547 + 1426/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3546 + 1427/2051: $6\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3545 + 1428/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3544 + 1429/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3543 + 1430/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3542 + 1431/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3541 + 1432/2051: $6\staged_access[6][31:0] + 1433/2051: $6\staged_access[4][31:0] + 1434/2051: $6\staged_access[3][31:0] + 1435/2051: $6\staged_access[2][31:0] + 1436/2051: $6\staged_access[1][31:0] + 1437/2051: $6\staged_access[0][31:0] + 1438/2051: $6\decision_deferred[0:0] + 1439/2051: $6\decision_ok[0:0] + 1440/2051: $6\decision_detail[7:0] + 1441/2051: $6\decision_fault[7:0] + 1442/2051: $15\write_address[31:0] + 1443/2051: $6\solved_b[127:0] + 1444/2051: $6\solved_a[127:0] + 1445/2051: $6\result_value[127:0] + 1446/2051: $6\inv_value[127:0] + 1447/2051: $6\val_c[127:0] + 1448/2051: $6\val_b[127:0] + 1449/2051: $6\val_a[127:0] + 1450/2051: $6\inv_present[7:0] + 1451/2051: $6\pres_c[7:0] + 1452/2051: $6\pres_b[7:0] + 1453/2051: $6\pres_a[7:0] + 1454/2051: $6\profile[7:0] + 1455/2051: $13\deferred_local[31:0] + 1456/2051: $13\deferred_target[31:0] + 1457/2051: $6\proposed_fp[31:0] + 1458/2051: $6\proposed_pc[31:0] + 1459/2051: $6\base_index[31:0] + 1460/2051: $6\addr_c[31:0] + 1461/2051: $6\addr_b[31:0] + 1462/2051: $6\addr_a[31:0] + 1463/2051: $6\off_c[31:0] + 1464/2051: $6\off_b[31:0] + 1465/2051: $6\off_a[31:0] + 1466/2051: $6\fp[31:0] + 1467/2051: $6\pc[31:0] + 1468/2051: $6\txn_id[31:0] + 1469/2051: $13\n_deferred[31:0] + 1470/2051: $15\n_writes[31:0] + 1471/2051: $6\staged_write_count[1:0] + 1472/2051: $15\write_value[127:0] + 1473/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3536 + 1474/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3533 + 1475/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3534 + 1476/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3491 + 1477/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3490 + 1478/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3532 + 1479/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3531 + 1480/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3530 + 1481/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3529 + 1482/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3528 + 1483/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3527 + 1484/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3526 + 1485/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3525 + 1486/2051: $5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3524 + 1487/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3523 + 1488/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3522 + 1489/2051: $5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3521 + 1490/2051: $5\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3520 + 1491/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3519 + 1492/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3518 + 1493/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3517 + 1494/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3516 + 1495/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3515 + 1496/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3514 + 1497/2051: $5\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3513 + 1498/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3512 + 1499/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3511 + 1500/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3510 + 1501/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3509 + 1502/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3508 + 1503/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3507 + 1504/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3506 + 1505/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3505 + 1506/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3504 + 1507/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3503 + 1508/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3502 + 1509/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3501 + 1510/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3500 + 1511/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3499 + 1512/2051: $5\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3498 + 1513/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3497 + 1514/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3496 + 1515/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3495 + 1516/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3494 + 1517/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3493 + 1518/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3492 + 1519/2051: $5\staged_access[6][31:0] + 1520/2051: $5\staged_access[4][31:0] + 1521/2051: $5\staged_access[3][31:0] + 1522/2051: $5\staged_access[2][31:0] + 1523/2051: $5\staged_access[1][31:0] + 1524/2051: $5\staged_access[0][31:0] + 1525/2051: $5\decision_deferred[0:0] + 1526/2051: $5\decision_ok[0:0] + 1527/2051: $5\decision_detail[7:0] + 1528/2051: $5\decision_fault[7:0] + 1529/2051: $14\write_address[31:0] + 1530/2051: $5\solved_b[127:0] + 1531/2051: $5\solved_a[127:0] + 1532/2051: $5\result_value[127:0] + 1533/2051: $5\inv_value[127:0] + 1534/2051: $5\val_c[127:0] + 1535/2051: $5\val_b[127:0] + 1536/2051: $5\val_a[127:0] + 1537/2051: $5\inv_present[7:0] + 1538/2051: $5\pres_c[7:0] + 1539/2051: $5\pres_b[7:0] + 1540/2051: $5\pres_a[7:0] + 1541/2051: $5\profile[7:0] + 1542/2051: $12\deferred_local[31:0] + 1543/2051: $12\deferred_target[31:0] + 1544/2051: $5\next_fp_value[31:0] + 1545/2051: $5\next_pc_value[31:0] + 1546/2051: $5\proposed_fp[31:0] + 1547/2051: $5\proposed_pc[31:0] + 1548/2051: $5\base_index[31:0] + 1549/2051: $5\addr_c[31:0] + 1550/2051: $5\addr_b[31:0] + 1551/2051: $5\addr_a[31:0] + 1552/2051: $5\off_c[31:0] + 1553/2051: $5\off_b[31:0] + 1554/2051: $5\off_a[31:0] + 1555/2051: $5\fp[31:0] + 1556/2051: $5\pc[31:0] + 1557/2051: $5\txn_id[31:0] + 1558/2051: $19\result_length[31:0] + 1559/2051: $12\n_deferred[31:0] + 1560/2051: $14\n_writes[31:0] + 1561/2051: $5\staged_write_count[1:0] + 1562/2051: $14\write_value[127:0] + 1563/2051: $18\result_length[31:0] + 1564/2051: $17\result_length[31:0] + 1565/2051: $16\result_length[31:0] + 1566/2051: $15\result_length[31:0] + 1567/2051: $13\write_value[127:0] + 1568/2051: $13\write_address[31:0] + 1569/2051: $13\n_writes[31:0] + 1570/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3483 + 1571/2051: $12\write_address[31:0] + 1572/2051: $14\result_length[31:0] + 1573/2051: $12\n_writes[31:0] + 1574/2051: $12\write_value[127:0] + 1575/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3479 + 1576/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3480 + 1577/2051: $11\write_address[31:0] + 1578/2051: $13\result_length[31:0] + 1579/2051: $11\n_writes[31:0] + 1580/2051: $11\write_value[127:0] + 1581/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3435 + 1582/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3434 + 1583/2051: $10\write_address[31:0] + 1584/2051: $12\result_length[31:0] + 1585/2051: $10\n_writes[31:0] + 1586/2051: $10\write_value[127:0] + 1587/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3478 + 1588/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3477 + 1589/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3476 + 1590/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3475 + 1591/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3474 + 1592/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3473 + 1593/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3472 + 1594/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3471 + 1595/2051: $4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3470 + 1596/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3469 + 1597/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3468 + 1598/2051: $4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3467 + 1599/2051: $4\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3466 + 1600/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3465 + 1601/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3464 + 1602/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3463 + 1603/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3462 + 1604/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3461 + 1605/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3460 + 1606/2051: $4\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3459 + 1607/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3458 + 1608/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3457 + 1609/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3456 + 1610/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3455 + 1611/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3454 + 1612/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3453 + 1613/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3452 + 1614/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3451 + 1615/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3450 + 1616/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3449 + 1617/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3448 + 1618/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3447 + 1619/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3446 + 1620/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3445 + 1621/2051: $4\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3444 + 1622/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3443 + 1623/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3442 + 1624/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3441 + 1625/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3440 + 1626/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3439 + 1627/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3438 + 1628/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3437 + 1629/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3436 + 1630/2051: $4\staged_access[6][31:0] + 1631/2051: $4\staged_access[4][31:0] + 1632/2051: $4\staged_access[3][31:0] + 1633/2051: $4\staged_access[2][31:0] + 1634/2051: $4\staged_access[1][31:0] + 1635/2051: $4\staged_access[0][31:0] + 1636/2051: $4\decision_deferred[0:0] + 1637/2051: $4\decision_ok[0:0] + 1638/2051: $4\decision_detail[7:0] + 1639/2051: $4\decision_fault[7:0] + 1640/2051: $4\solved_b[127:0] + 1641/2051: $4\solved_a[127:0] + 1642/2051: $4\result_value[127:0] + 1643/2051: $4\inv_value[127:0] + 1644/2051: $4\val_c[127:0] + 1645/2051: $4\val_b[127:0] + 1646/2051: $4\val_a[127:0] + 1647/2051: $4\inv_present[7:0] + 1648/2051: $4\pres_c[7:0] + 1649/2051: $4\pres_b[7:0] + 1650/2051: $4\pres_a[7:0] + 1651/2051: $4\profile[7:0] + 1652/2051: $11\deferred_local[31:0] + 1653/2051: $11\deferred_target[31:0] + 1654/2051: $4\next_fp_value[31:0] + 1655/2051: $4\next_pc_value[31:0] + 1656/2051: $4\proposed_fp[31:0] + 1657/2051: $4\proposed_pc[31:0] + 1658/2051: $4\base_index[31:0] + 1659/2051: $4\addr_c[31:0] + 1660/2051: $4\addr_b[31:0] + 1661/2051: $4\addr_a[31:0] + 1662/2051: $4\off_c[31:0] + 1663/2051: $4\off_b[31:0] + 1664/2051: $4\off_a[31:0] + 1665/2051: $4\fp[31:0] + 1666/2051: $4\pc[31:0] + 1667/2051: $4\txn_id[31:0] + 1668/2051: $11\n_deferred[31:0] + 1669/2051: $4\staged_write_count[1:0] + 1670/2051: $11\result_length[31:0] + 1671/2051: $10\result_length[31:0] + 1672/2051: $9\result_length[31:0] + 1673/2051: $8\result_length[31:0] + 1674/2051: $10\deferred_local[31:0] + 1675/2051: $10\deferred_target[31:0] + 1676/2051: $10\n_deferred[31:0] + 1677/2051: $9\write_value[127:0] + 1678/2051: $9\write_address[31:0] + 1679/2051: $9\n_writes[31:0] + 1680/2051: $9\deferred_local[31:0] + 1681/2051: $9\deferred_target[31:0] + 1682/2051: $9\n_deferred[31:0] + 1683/2051: $8\write_value[127:0] + 1684/2051: $8\write_address[31:0] + 1685/2051: $8\n_writes[31:0] + 1686/2051: $8\deferred_local[31:0] + 1687/2051: $8\deferred_target[31:0] + 1688/2051: $8\n_deferred[31:0] + 1689/2051: $7\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3418 + 1690/2051: $7\write_address[31:0] + 1691/2051: $7\deferred_local[31:0] + 1692/2051: $7\deferred_target[31:0] + 1693/2051: $7\result_length[31:0] + 1694/2051: $7\n_deferred[31:0] + 1695/2051: $7\n_writes[31:0] + 1696/2051: $7\write_value[127:0] + 1697/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3413 + 1698/2051: $6\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3414 + 1699/2051: $6\write_address[31:0] + 1700/2051: $6\deferred_local[31:0] + 1701/2051: $6\deferred_target[31:0] + 1702/2051: $6\result_length[31:0] + 1703/2051: $6\n_deferred[31:0] + 1704/2051: $6\n_writes[31:0] + 1705/2051: $6\write_value[127:0] + 1706/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3409 + 1707/2051: $5\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3408 + 1708/2051: $5\write_address[31:0] + 1709/2051: $5\deferred_local[31:0] + 1710/2051: $5\deferred_target[31:0] + 1711/2051: $5\result_length[31:0] + 1712/2051: $5\n_deferred[31:0] + 1713/2051: $5\n_writes[31:0] + 1714/2051: $5\write_value[127:0] + 1715/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3404 + 1716/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3406 + 1717/2051: $4\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3405 + 1718/2051: $4\write_address[31:0] + 1719/2051: $4\deferred_local[31:0] + 1720/2051: $4\deferred_target[31:0] + 1721/2051: $4\result_length[31:0] + 1722/2051: $4\n_deferred[31:0] + 1723/2051: $4\n_writes[31:0] + 1724/2051: $4\write_value[127:0] + 1725/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3356 + 1726/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3355 + 1727/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3354 + 1728/2051: $3\write_address[31:0] + 1729/2051: $3\deferred_local[31:0] + 1730/2051: $3\deferred_target[31:0] + 1731/2051: $3\result_length[31:0] + 1732/2051: $3\n_deferred[31:0] + 1733/2051: $3\n_writes[31:0] + 1734/2051: $3\write_value[127:0] + 1735/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3401 + 1736/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3400 + 1737/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3399 + 1738/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3398 + 1739/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3397 + 1740/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3396 + 1741/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3395 + 1742/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3394 + 1743/2051: $3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3393 + 1744/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3392 + 1745/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3391 + 1746/2051: $3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3390 + 1747/2051: $3\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3389 + 1748/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3388 + 1749/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3387 + 1750/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3386 + 1751/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3385 + 1752/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3384 + 1753/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3383 + 1754/2051: $3\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3382 + 1755/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3381 + 1756/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3380 + 1757/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3379 + 1758/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3378 + 1759/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3377 + 1760/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3376 + 1761/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3375 + 1762/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3374 + 1763/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3373 + 1764/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3372 + 1765/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3371 + 1766/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3370 + 1767/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3369 + 1768/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3368 + 1769/2051: $3\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3367 + 1770/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3366 + 1771/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3365 + 1772/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3364 + 1773/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3363 + 1774/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3362 + 1775/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3361 + 1776/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3360 + 1777/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3359 + 1778/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3358 + 1779/2051: $3\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3357 + 1780/2051: $3\staged_access[6][31:0] + 1781/2051: $3\staged_access[4][31:0] + 1782/2051: $3\staged_access[3][31:0] + 1783/2051: $3\staged_access[2][31:0] + 1784/2051: $3\staged_access[1][31:0] + 1785/2051: $3\staged_access[0][31:0] + 1786/2051: $3\decision_deferred[0:0] + 1787/2051: $3\decision_ok[0:0] + 1788/2051: $3\decision_detail[7:0] + 1789/2051: $3\decision_fault[7:0] + 1790/2051: $3\solved_b[127:0] + 1791/2051: $3\solved_a[127:0] + 1792/2051: $3\result_value[127:0] + 1793/2051: $3\inv_value[127:0] + 1794/2051: $3\val_c[127:0] + 1795/2051: $3\val_b[127:0] + 1796/2051: $3\val_a[127:0] + 1797/2051: $3\inv_present[7:0] + 1798/2051: $3\pres_c[7:0] + 1799/2051: $3\pres_b[7:0] + 1800/2051: $3\pres_a[7:0] + 1801/2051: $3\profile[7:0] + 1802/2051: $3\next_fp_value[31:0] + 1803/2051: $3\next_pc_value[31:0] + 1804/2051: $3\proposed_fp[31:0] + 1805/2051: $3\proposed_pc[31:0] + 1806/2051: $3\base_index[31:0] + 1807/2051: $3\addr_c[31:0] + 1808/2051: $3\addr_b[31:0] + 1809/2051: $3\addr_a[31:0] + 1810/2051: $3\off_c[31:0] + 1811/2051: $3\off_b[31:0] + 1812/2051: $3\off_a[31:0] + 1813/2051: $3\fp[31:0] + 1814/2051: $3\pc[31:0] + 1815/2051: $3\txn_id[31:0] + 1816/2051: $3\staged_write_count[1:0] + 1817/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3348 + 1818/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3347 + 1819/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3346 + 1820/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3345 + 1821/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3344 + 1822/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3343 + 1823/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3342 + 1824/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3341 + 1825/2051: $2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3340 + 1826/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3339 + 1827/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3338 + 1828/2051: $2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3337 + 1829/2051: $2\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3336 + 1830/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3335 + 1831/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3334 + 1832/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3333 + 1833/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3332 + 1834/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3331 + 1835/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3330 + 1836/2051: $2\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3329 + 1837/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3328 + 1838/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3327 + 1839/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3326 + 1840/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3325 + 1841/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3324 + 1842/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3323 + 1843/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3322 + 1844/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3321 + 1845/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3320 + 1846/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3319 + 1847/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3318 + 1848/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3317 + 1849/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3316 + 1850/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3315 + 1851/2051: $2\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3314 + 1852/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3313 + 1853/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3312 + 1854/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3311 + 1855/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3310 + 1856/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3309 + 1857/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3308 + 1858/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3307 + 1859/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3306 + 1860/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3305 + 1861/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3304 + 1862/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3303 + 1863/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3302 + 1864/2051: $2\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3301 + 1865/2051: $2\staged_access[6][31:0] + 1866/2051: $2\staged_access[4][31:0] + 1867/2051: $2\staged_access[3][31:0] + 1868/2051: $2\staged_access[2][31:0] + 1869/2051: $2\staged_access[1][31:0] + 1870/2051: $2\staged_access[0][31:0] + 1871/2051: $2\decision_deferred[0:0] + 1872/2051: $2\decision_ok[0:0] + 1873/2051: $2\decision_detail[7:0] + 1874/2051: $2\decision_fault[7:0] + 1875/2051: $2\write_address[31:0] + 1876/2051: $2\solved_b[127:0] + 1877/2051: $2\solved_a[127:0] + 1878/2051: $2\result_value[127:0] + 1879/2051: $2\inv_value[127:0] + 1880/2051: $2\val_c[127:0] + 1881/2051: $2\val_b[127:0] + 1882/2051: $2\val_a[127:0] + 1883/2051: $2\inv_present[7:0] + 1884/2051: $2\pres_c[7:0] + 1885/2051: $2\pres_b[7:0] + 1886/2051: $2\pres_a[7:0] + 1887/2051: $2\profile[7:0] + 1888/2051: $2\deferred_local[31:0] + 1889/2051: $2\deferred_target[31:0] + 1890/2051: $2\next_fp_value[31:0] + 1891/2051: $2\next_pc_value[31:0] + 1892/2051: $2\proposed_fp[31:0] + 1893/2051: $2\proposed_pc[31:0] + 1894/2051: $2\base_index[31:0] + 1895/2051: $2\addr_c[31:0] + 1896/2051: $2\addr_b[31:0] + 1897/2051: $2\addr_a[31:0] + 1898/2051: $2\off_c[31:0] + 1899/2051: $2\off_b[31:0] + 1900/2051: $2\off_a[31:0] + 1901/2051: $2\fp[31:0] + 1902/2051: $2\pc[31:0] + 1903/2051: $2\txn_id[31:0] + 1904/2051: $2\result_length[31:0] + 1905/2051: $2\n_deferred[31:0] + 1906/2051: $2\n_writes[31:0] + 1907/2051: $2\staged_write_count[1:0] + 1908/2051: $2\write_value[127:0] + 1909/2051: $0\core_done_pulse[0:0] + 1910/2051: $0\blake_service_discard[0:0] + 1911/2051: $0\blake_service_accept[0:0] + 1912/2051: $0\blake_service_start[0:0] + 1913/2051: $1\staged_write_count[1:0] + 1914/2051: $0\encoder_start[0:0] + 1915/2051: $0\alu_start[0:0] + 1916/2051: $0\tx_start[0:0] + 1917/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3300 + 1918/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA[127:0]$3299 + 1919/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR[1:0]$3298 + 1920/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3297 + 1921/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA[31:0]$3296 + 1922/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3295 + 1923/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3294 + 1924/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3293 + 1925/2051: $1$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR[1:0]$3292 + 1926/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3291 + 1927/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3290 + 1928/2051: $1$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3289 + 1929/2051: $1\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count[7:0]$3288 + 1930/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail[7:0]$3287 + 1931/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn[31:0]$3286 + 1932/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status[7:0]$3285 + 1933/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail[7:0]$3284 + 1934/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn[31:0]$3283 + 1935/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status[7:0]$3282 + 1936/2051: $1\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length[31:0]$3281 + 1937/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn[31:0]$3280 + 1938/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail[7:0]$3279 + 1939/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn[31:0]$3278 + 1940/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn[31:0]$3277 + 1941/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn[31:0]$3276 + 1942/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail[7:0]$3275 + 1943/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn[31:0]$3274 + 1944/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn[31:0]$3273 + 1945/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail[7:0]$3272 + 1946/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn[31:0]$3271 + 1947/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn[31:0]$3270 + 1948/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail[7:0]$3269 + 1949/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status[7:0]$3268 + 1950/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn[31:0]$3267 + 1951/2051: $1\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product[127:0]$3266 + 1952/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn[31:0]$3265 + 1953/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn[31:0]$3264 + 1954/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn[31:0]$3263 + 1955/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn[31:0]$3262 + 1956/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn[31:0]$3261 + 1957/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn[31:0]$3260 + 1958/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn[31:0]$3259 + 1959/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn[31:0]$3258 + 1960/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn[31:0]$3257 + 1961/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn[31:0]$3256 + 1962/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn[31:0]$3255 + 1963/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn[31:0]$3254 + 1964/2051: $1\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn[31:0]$3253 + 1965/2051: $1\staged_access[6][31:0] + 1966/2051: $1\staged_access[4][31:0] + 1967/2051: $1\staged_access[3][31:0] + 1968/2051: $1\staged_access[2][31:0] + 1969/2051: $1\staged_access[1][31:0] + 1970/2051: $1\staged_access[0][31:0] + 1971/2051: $1\decision_deferred[0:0] + 1972/2051: $1\decision_ok[0:0] + 1973/2051: $1\decision_detail[7:0] + 1974/2051: $1\decision_fault[7:0] + 1975/2051: $1\write_address[31:0] + 1976/2051: $1\solved_b[127:0] + 1977/2051: $1\solved_a[127:0] + 1978/2051: $1\result_value[127:0] + 1979/2051: $1\inv_value[127:0] + 1980/2051: $1\val_c[127:0] + 1981/2051: $1\val_b[127:0] + 1982/2051: $1\val_a[127:0] + 1983/2051: $1\inv_present[7:0] + 1984/2051: $1\pres_c[7:0] + 1985/2051: $1\pres_b[7:0] + 1986/2051: $1\pres_a[7:0] + 1987/2051: $1\profile[7:0] + 1988/2051: $1\deferred_local[31:0] + 1989/2051: $1\deferred_target[31:0] + 1990/2051: $1\next_fp_value[31:0] + 1991/2051: $1\next_pc_value[31:0] + 1992/2051: $1\proposed_fp[31:0] + 1993/2051: $1\proposed_pc[31:0] + 1994/2051: $1\base_index[31:0] + 1995/2051: $1\addr_c[31:0] + 1996/2051: $1\addr_b[31:0] + 1997/2051: $1\addr_a[31:0] + 1998/2051: $1\off_c[31:0] + 1999/2051: $1\off_b[31:0] + 2000/2051: $1\off_a[31:0] + 2001/2051: $1\fp[31:0] + 2002/2051: $1\pc[31:0] + 2003/2051: $1\txn_id[31:0] + 2004/2051: $1\result_length[31:0] + 2005/2051: $1\n_deferred[31:0] + 2006/2051: $1\n_writes[31:0] + 2007/2051: $1\write_value[127:0] + 2008/2051: $0\staged_out_value[1][127:0] + 2009/2051: $0\staged_out_value[0][127:0] + 2010/2051: $0\staged_out_present[1][7:0] + 2011/2051: $0\staged_out_present[0][7:0] + 2012/2051: $0\staged_access[7][31:0] + 2013/2051: $0\staged_access[5][31:0] + 2014/2051: $0\scalar_staged_access[2][31:0] + 2015/2051: $0\scalar_staged_access[1][31:0] + 2016/2051: $0\scalar_staged_access[0][31:0] + 2017/2051: $0\last_fault[7:0] + 2018/2051: $0\last_status[7:0] + 2019/2051: $0\active_profile[7:0] + 2020/2051: $0\retire_seq[31:0] + 2021/2051: $0\committed_fp[31:0] + 2022/2051: $0\committed_pc[31:0] + 2023/2051: $0\state_valid[0:0] + 2024/2051: $0\scalar_staged_deferred_local[31:0] + 2025/2051: $0\scalar_staged_deferred_target[31:0] + 2026/2051: $0\scalar_staged_write_value[127:0] + 2027/2051: $0\scalar_staged_write_address[31:0] + 2028/2051: $0\scalar_staged_access_count[7:0] + 2029/2051: $0\scalar_staged_deferred[0:0] + 2030/2051: $0\scalar_staged_write_count[1:0] + 2031/2051: $0\staged_result_crc[31:0] + 2032/2051: $0\staged_next_fp[31:0] + 2033/2051: $0\staged_next_pc[31:0] + 2034/2051: $0\staged_txn_id[31:0] + 2035/2051: $0\staged_operation[7:0] + 2036/2051: $0\blake_start_next_fp[31:0] + 2037/2051: $0\blake_start_next_pc[31:0] + 2038/2051: $0\blake_start_txn_id[31:0] + 2039/2051: $0\result_pending[0:0] + 2040/2051: $0\encoder_index[15:0] + 2041/2051: $0\alu_operand_b[127:0] + 2042/2051: $0\alu_operand_a[127:0] + 2043/2051: $0\alu_operation[7:0] + 2044/2051: $0\compute_state[3:0] + 2045/2051: $0\capture_result_crc[0:0] + 2046/2051: $0\short_detail[7:0] + 2047/2051: $0\short_txn_id[31:0] + 2048/2051: $0\tx_external_kind[2:0] + 2049/2051: $0\tx_length[15:0] + 2050/2051: $0\tx_status[7:0] + 2051/2051: $0\fault[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + 1/2: $0\tx_data_q[7:0] + 2/2: $0\tx_full[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. + 1/1: $0\rx_overrun[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + 1/2: $0\rx_data_q[7:0] + 2/2: $0\rx_full[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. + 1/1: $0\abort_q[0:0] +Creating decoders for process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. + 1/1: $0\por_shift[7:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + 1/27: $5$lookahead\shift$4385[7:0]$4419 + 2/27: $5$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4417 + 3/27: $5$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4416 + 4/27: $5$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4418 + 5/27: $4$lookahead\shift$4385[7:0]$4412 + 6/27: $4$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4411 + 7/27: $4$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4410 + 8/27: $4$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4409 + 9/27: $3$lookahead\shift$4385[7:0]$4407 + 10/27: $3$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4406 + 11/27: $3$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4405 + 12/27: $3$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4404 + 13/27: $2$lookahead\shift$4385[7:0]$4400 + 14/27: $2$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4399 + 15/27: $2$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4398 + 16/27: $2$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4397 + 17/27: $0\framing_err[0:0] + 18/27: $0\rx_valid[0:0] + 19/27: $1$lookahead\shift$4385[7:0]$4395 + 20/27: $1$bitselwrite$sel$uart_rx.sv:72$4383[31:0]$4394 + 21/27: $1$bitselwrite$data$uart_rx.sv:72$4382[7:0]$4393 + 22/27: $1$bitselwrite$mask$uart_rx.sv:72$4381[7:0]$4392 + 23/27: $0\wait_idle[0:0] + 24/27: $0\receiving[0:0] + 25/27: $0\bit_cnt[3:0] + 26/27: $0\div_cnt[15:0] + 27/27: $0\rx_data[7:0] +Creating decoders for process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. +Creating decoders for process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. +Creating decoders for process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + 1/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_EN[3:0]$120 + 2/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_DATA[3:0]$119 + 3/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_ADDR[3:0]$118 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + 1/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_EN[3:0]$62 + 2/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_DATA[3:0]$61 + 3/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_ADDR[3:0]$60 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. + +24.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\leanvm_b_stream_alu.\tx_data' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\rx_ready' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_a_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_value' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_result_shift' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.index' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2789.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:96$2792.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2788.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:94$2791.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2787.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.$result' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.address_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.address_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.present_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.present_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.value_x' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_cell_alias_check.\pair_inconsistent$func$../../asic_core/rtl/lsc1_cell_alias_check.sv:92$2790.value_y' from process `\lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2504.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:138$2531.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2503.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:136$2530.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2502.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:134$2529.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2501.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:132$2528.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2500.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:129$2527.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2499.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:127$2526.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2498.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:125$2525.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2497.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:123$2524.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2496.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:120$2523.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2495.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:118$2522.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2494.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:116$2521.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2493.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:113$2520.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2492.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2519.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2491.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2518.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2490.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2517.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2489.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2516.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2488.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2515.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2487.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2514.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2486.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2513.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2485.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.$result' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.cell_present' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\cell_malformed$func$../../asic_core/rtl/lsc1_request_validator.sv:107$2512.cell_value' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +No latch inferred for signal `\lsc1_request_validator.\reject' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_status' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault_detail' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:175$2506.txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\fault$func$../../asic_core/rtl/lsc1_request_validator.sv:185$2511.txn' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +No latch inferred for signal `\lsc1_request_validator.\expected_length' from process `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\address[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\present[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[0]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[1]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[2]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[3]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[4]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[5]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[6]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_blake3_alias_check.\value[7]' from process `\lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[2]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[3]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[4]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[5]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[6]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_access[7]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[2]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_message[3]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_cv[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_cv[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_address[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_address[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_value[0]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\staged_write_value[1]' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +No latch inferred for signal `\lsc1_response_payload_mux.\payload_data' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_message$../../asic_core/rtl/lsc1_response_payload_mux.sv:59$2150_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_cv$../../asic_core/rtl/lsc1_response_payload_mux.sv:62$2151_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_address$../../asic_core/rtl/lsc1_response_payload_mux.sv:76$2152_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_write_value$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2153_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_ADDR' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +No latch inferred for signal `\lsc1_response_payload_mux.$mem2reg_rd$\staged_access$../../asic_core/rtl/lsc1_response_payload_mux.sv:85$2154_DATA' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Latch inferred for signal `\lsc1_response_payload_mux.\ext_word' from process `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155': $auto$proc_dlatch.cc:427:proc_dlatch$88733 +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_data' from process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_valid' from process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +No latch inferred for signal `\lsc1_packet_tx.\tx_data' from process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. + +24.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\leanvm_b_stream_alu.\fault' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88734' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\state' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88735' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\byte_index' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88736' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\scratch_byte' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. + created $dff cell `$procdff$88737' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\done_pulse' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88738' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\result_pending' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88739' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_txn_id' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88740' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_next_pc' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88741' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_next_fp' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88742' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_result_crc' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88743' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\retire_seq' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88744' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\service_pending' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88745' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\staged_service_id' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88746' with positive edge clock. +Creating register for signal `\lsc1_blake3_lifecycle.\service_seq' using process `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. + created $dff cell `$procdff$88747' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\busy' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88748' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\fault' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88749' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\done_pulse' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88750' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_a' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88751' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_b' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88752' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\result' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88753' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\multiply_start' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88754' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\bit_index' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88755' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\saved_index' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88756' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\accumulator' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88757' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\next_accumulator' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88758' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.$result' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88759' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$../../asic_core/rtl/lsc1_field_encoder.sv:64$2116.value' using process `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. + created $dff cell `$procdff$88760' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\fault' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88761' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\done_pulse' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88762' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\payload_index' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88763' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88764' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\state' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88765' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_operation' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88766' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_a' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88767' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_b' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88768' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result_index' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88769' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1996' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88770' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1997' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88771' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:138$1998' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88772' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$../../asic_core/rtl/lsc1_stream_adapter.sv:160$1999' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88773' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2000' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88774' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$../../asic_core/rtl/lsc1_stream_adapter.sv:160$2001' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88775' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$lookahead\result$2032' using process `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. + created $dff cell `$procdff$88776' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\done_pulse' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88777' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88778' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88779' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\active' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88780' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_length' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88781' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_status' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88782' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_crc' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88783' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\envelope_crc_work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88784' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc_work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88785' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88786' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88787' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88788' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88789' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:95$1707.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88790' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88791' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88792' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88793' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88794' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:97$1708.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88795' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88796' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88797' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88798' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88799' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:99$1709.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88800' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.$result' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88801' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.crc_in' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88802' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.data' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88803' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.bit_index' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88804' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_tx.sv:101$1710.work' using process `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. + created $dff cell `$procdff$88805' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88806' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88807' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88808' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88809' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88810' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88811' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88812' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88813' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88814' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88815' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88816' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88817' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88818' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88819' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload_prefix' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88820' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\payload_write_enable' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88821' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\payload_byte' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88822' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88823' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88824' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88825' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:105$1509.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88826' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88827' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.crc_in' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88828' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88829' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88830' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:111$1510.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88831' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.$result' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88832' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.crc_in' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88833' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.data' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88834' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.bit_index' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88835' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$../../asic_core/rtl/lsc1_packet_rx.sv:143$1512.work' using process `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. + created $dff cell `$procdff$88836' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\accumulator' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88837' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\a_shift' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88838' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88839' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88840' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.byte_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88841' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$3054.next_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88842' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88843' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88844' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$3055.carry' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. + created $dff cell `$procdff$88845' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\tx_ready' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88846' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\tx_serial' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88847' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\div_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88848' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\bit_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88849' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.\shift' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. + created $dff cell `$procdff$88850' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88851' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88852' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88853' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88854' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_external_kind' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88855' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\short_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88856' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\short_detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88857' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\capture_result_crc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88858' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\compute_state' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88859' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88860' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operation' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88861' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88862' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88863' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88864' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_index' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88865' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_pending' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88866' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_start' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88867' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_accept' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88868' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_service_discard' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88869' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88870' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_next_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88871' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\blake_start_next_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88872' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\core_done_pulse' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88873' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_operation' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88874' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88875' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88876' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88877' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_result_crc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88878' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88879' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88880' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88881' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_address' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88882' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_write_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88883' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88884' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred_target' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88885' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_deferred_local' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88886' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\state_valid' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88887' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88888' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88889' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\retire_seq' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88890' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\active_profile' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88891' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88892' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88893' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_write_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88894' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_writes' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88895' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88896' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88897' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\txn_id' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88898' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88899' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88900' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88901' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88902' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88903' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88904' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88905' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88906' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\base_index' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88907' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_pc' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88908' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_fp' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88909' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_pc_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88910' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_fp_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88911' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_target' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88912' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_local' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88913' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\profile' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88914' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88915' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88916' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88917' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_present' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88918' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88919' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88920' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_c' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88921' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88922' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_value' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88923' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_a' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88924' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_b' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88925' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_address' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88926' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_fault' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88927' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88928' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_ok' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88929' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_deferred' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88930' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88931' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88932' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\scalar_staged_access[2]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88933' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88934' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88935' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[2]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88936' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[3]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88937' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[4]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88938' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[5]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88939' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[6]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88940' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_access[7]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88941' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_present[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88942' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_present[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88943' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_value[0]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88944' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_out_value[1]' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88945' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:444$3119.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88946' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:448$3120.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88947' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:450$3121.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88948' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:565$3123.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88949' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:567$3124.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88950' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:579$3126.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88951' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:582$3127.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88952' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:591$3128.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88953' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:593$3129.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88954' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:602$3131.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88955' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:611$3132.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88956' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:630$3134.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88957' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:652$3135.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88958' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\finish_binary$func$../../asic_core/rtl/lsc1_packet_frontend.sv:654$3136.product' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88959' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:413$3137.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88960' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88961' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:658$3139.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88962' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:703$3146.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88963' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88964' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:706$3147.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88965' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:722$3148.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88966' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88967' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:726$3149.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88968' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:746$3150.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88969' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:750$3152.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88970' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88971' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:754$3153.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88972' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:763$3154.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88973' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_blake_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:776$3155.blake_result_length' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88974' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88975' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88976' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:779$3156.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88977' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.status' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88978' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.txn' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88979' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1018$3157.detail' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88980' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_result$func$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$3158.access_count' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88981' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88982' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88983' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88984' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88985' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88986' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88987' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88988' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88989' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88990' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_ADDR' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88991' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_DATA' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88992' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN' using process `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. + created $dff cell `$procdff$88993' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\tx_full' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + created $dff cell `$procdff$88994' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\tx_data_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. + created $dff cell `$procdff$88995' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_overrun' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. + created $dff cell `$procdff$88996' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_full' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + created $dff cell `$procdff$88997' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\rx_data_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. + created $dff cell `$procdff$88998' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\abort_q' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. + created $dff cell `$procdff$88999' with positive edge clock. +Creating register for signal `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.\por_shift' using process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. + created $dff cell `$procdff$89000' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_data' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89001' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_valid' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89002' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\framing_err' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89003' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\div_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89004' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\bit_cnt' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89005' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\shift' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89006' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\receiving' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89007' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\wait_idle' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89008' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$mask$uart_rx.sv:72$4381' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89009' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$data$uart_rx.sv:72$4382' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89010' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$bitselwrite$sel$uart_rx.sv:72$4383' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89011' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$lookahead\shift$4385' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. + created $dff cell `$procdff$89012' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_m' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. + created $dff cell `$procdff$89013' with positive edge clock. +Creating register for signal `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.\rx_s' using process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. + created $dff cell `$procdff$89014' with positive edge clock. +Creating register for signal `\ulx3s_packet_top.\heartbeat' using process `\ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. + created $dff cell `$procdff$89015' with positive edge clock. +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. + created $dff cell `$procdff$89016' with positive edge clock. +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$98_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$99_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$100_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$101_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$102_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$103_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$104_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$105_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$106_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$107_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$108_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$109_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$110_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$111_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$112_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_ADDR' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89017' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_DATA' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89018' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$113_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. + created $dff cell `$procdff$89019' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$38_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$39_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$40_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$41_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$42_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$43_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$44_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$45_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$46_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$47_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$48_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$49_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$50_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$51_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$52_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$53_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89020' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89021' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$54_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. + created $dff cell `$procdff$89022' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. + created direct connection (no actual register cell created). + +24.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 23 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$2905'. +Found and cleaned up 3 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$2866'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2844'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2830'. +Removing empty process `lsc1_cell_alias_check.$proc$../../asic_core/rtl/lsc1_cell_alias_check.sv:0$2816'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2777'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2767'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2757'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2747'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2737'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2727'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2717'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2707'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2697'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2687'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2677'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2667'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2657'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2647'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2637'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2627'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2617'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2607'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2597'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:0$2587'. +Found and cleaned up 7 empty switches in `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:167$2575'. +Found and cleaned up 1 empty switch in `\lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +Removing empty process `lsc1_request_validator.$proc$../../asic_core/rtl/lsc1_request_validator.sv:72$2547'. +Removing empty process `lsc1_blake3_alias_check.$proc$../../asic_core/rtl/lsc1_blake3_alias_check.sv:0$2482'. +Removing empty process `lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2340'. +Found and cleaned up 36 empty switches in `\lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Removing empty process `lsc1_response_payload_mux.$proc$../../asic_core/rtl/lsc1_response_payload_mux.sv:48$2155'. +Found and cleaned up 8 empty switches in `\lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. +Removing empty process `lsc1_blake3_lifecycle.$proc$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:39$2143'. +Found and cleaned up 5 empty switches in `\lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. +Removing empty process `lsc1_field_encoder.$proc$../../asic_core/rtl/lsc1_field_encoder.sv:38$2117'. +Found and cleaned up 14 empty switches in `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. +Removing empty process `lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:83$2033'. +Found and cleaned up 6 empty switches in `\lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +Removing empty process `lsc1_stream_adapter.$proc$../../asic_core/rtl/lsc1_stream_adapter.sv:54$2008'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. +Removing empty process `lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:72$1731'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. +Removing empty process `lsc1_packet_tx.$proc$../../asic_core/rtl/lsc1_packet_tx.sv:54$1721'. +Found and cleaned up 203 empty switches in `\lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. +Removing empty process `lsc1_packet_rx.$proc$../../asic_core/rtl/lsc1_packet_rx.sv:69$1525'. +Found and cleaned up 7 empty switches in `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. +Removing empty process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$3058'. +Found and cleaned up 5 empty switches in `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx.$proc$uart_tx.sv:22$4375'. +Found and cleaned up 114 empty switches in `\lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Removing empty process `lsc1_packet_frontend.$proc$../../asic_core/rtl/lsc1_packet_frontend.sv:476$3203'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:27$2994'. +Found and cleaned up 4 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:149$2991'. +Found and cleaned up 2 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:131$2983'. +Found and cleaned up 4 empty switches in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:113$2981'. +Found and cleaned up 1 empty switch in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:96$2975'. +Found and cleaned up 1 empty switch in `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. +Removing empty process `$paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000.$proc$uart_bridge.sv:28$2969'. +Found and cleaned up 10 empty switches in `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:33$4386'. +Removing empty process `$paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx.$proc$uart_rx.sv:22$4384'. +Removing empty process `ulx3s_packet_top.$proc$ulx3s_packet_top.sv:19$161'. +Removing empty process `ulx3s_packet_top.$proc$ulx3s_packet_top.sv:20$158'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$156'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$155'. +Removing empty process `DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$137'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$114'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$80'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$56'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$55'. +Cleaned up 472 empty switches. + +24.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module gf128_mul_bitstream. +Optimizing module leanvm_b_stream_alu. + +Optimizing module lsc1_cell_alias_check. +Optimizing module lsc1_request_validator. + +Optimizing module lsc1_blake3_alias_check. +Optimizing module lsc1_response_payload_mux. + +Optimizing module lsc1_blake3_lifecycle. + +Optimizing module lsc1_field_encoder. + +Optimizing module lsc1_stream_adapter. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_packet_rx. + +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. + +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. + +Optimizing module lean_silicon_lsc1. + +Optimizing module lsc1_packet_frontend. + +Optimizing module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. + +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. + +Optimizing module ulx3s_core_pll. +Optimizing module ulx3s_packet_top. + +25. Executing CHECK pass (checking for obvious problems). +Checking module gf128_mul_bitstream... +Checking module leanvm_b_stream_alu... +Checking module lsc1_cell_alias_check... +Checking module lsc1_request_validator... +Checking module lsc1_blake3_alias_check... +Checking module lsc1_response_payload_mux... +Checking module lsc1_blake3_lifecycle... +Checking module lsc1_field_encoder... +Checking module lsc1_stream_adapter... +Checking module lsc1_packet_tx... +Checking module lsc1_packet_rx... +Checking module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream... +Checking module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx... +Checking module lean_silicon_lsc1... +Checking module lsc1_packet_frontend... +Checking module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000... +Checking module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx... +Checking module ulx3s_core_pll... +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +26. Executing SYNTH_ECP5 pass. + +26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Replacing existing module `\LUT4' at /usr/bin/../share/yosys/ecp5/cells_sim.v:4.1-16.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\$__ABC9_LUT5' at /usr/bin/../share/yosys/ecp5/cells_sim.v:22.1-30.10. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Replacing existing blackbox module `\$__ABC9_LUT6' at /usr/bin/../share/yosys/ecp5/cells_sim.v:36.1-45.10. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Replacing existing blackbox module `\$__ABC9_LUT7' at /usr/bin/../share/yosys/ecp5/cells_sim.v:51.1-61.10. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Replacing existing module `\L6MUX21' at /usr/bin/../share/yosys/ecp5/cells_sim.v:65.1-72.10. +Generating RTLIL representation for module `\L6MUX21'. +Replacing existing module `\CCU2C' at /usr/bin/../share/yosys/ecp5/cells_sim.v:76.1-134.10. +Generating RTLIL representation for module `\CCU2C'. +Replacing existing blackbox module `\TRELLIS_RAM16X2' at /usr/bin/../share/yosys/ecp5/cells_sim.v:138.1-175.10. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Replacing existing module `\PFUMX' at /usr/bin/../share/yosys/ecp5/cells_sim.v:179.1-186.10. +Generating RTLIL representation for module `\PFUMX'. +Replacing existing module `\TRELLIS_DPR16X4' at /usr/bin/../share/yosys/ecp5/cells_sim.v:190.1-231.10. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Replacing existing module `\DPR16X4C' at /usr/bin/../share/yosys/ecp5/cells_sim.v:236.1-295.10. +Generating RTLIL representation for module `\DPR16X4C'. +Replacing existing module `\LUT2' at /usr/bin/../share/yosys/ecp5/cells_sim.v:300.1-304.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing module `\TRELLIS_FF' at /usr/bin/../share/yosys/ecp5/cells_sim.v:311.1-376.10. +Generating RTLIL representation for module `\TRELLIS_FF'. +Replacing existing blackbox module `\TRELLIS_IO' at /usr/bin/../share/yosys/ecp5/cells_sim.v:380.1-406.10. +Generating RTLIL representation for module `\TRELLIS_IO'. +Replacing existing blackbox module `\INV' at /usr/bin/../share/yosys/ecp5/cells_sim.v:410.1-412.10. +Generating RTLIL representation for module `\INV'. +Replacing existing blackbox module `\TRELLIS_COMB' at /usr/bin/../share/yosys/ecp5/cells_sim.v:416.1-457.10. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Replacing existing blackbox module `\DP16KD' at /usr/bin/../share/yosys/ecp5/cells_sim.v:460.1-674.10. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /usr/bin/../share/yosys/ecp5/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /usr/bin/../share/yosys/ecp5/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /usr/bin/../share/yosys/ecp5/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /usr/bin/../share/yosys/ecp5/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /usr/bin/../share/yosys/ecp5/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /usr/bin/../share/yosys/ecp5/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /usr/bin/../share/yosys/ecp5/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /usr/bin/../share/yosys/ecp5/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Replacing existing blackbox module `\MULT18X18D' at /usr/bin/../share/yosys/ecp5/cells_bb.v:5.1-48.10. +Generating RTLIL representation for module `\MULT18X18D'. +Replacing existing blackbox module `\ALU54B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:51.1-117.10. +Generating RTLIL representation for module `\ALU54B'. +Replacing existing blackbox module `\EHXPLLL' at /usr/bin/../share/yosys/ecp5/cells_bb.v:120.1-165.10. +Generating RTLIL representation for module `\EHXPLLL'. +Replacing existing blackbox module `\DTR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:168.1-172.10. +Generating RTLIL representation for module `\DTR'. +Replacing existing blackbox module `\OSCG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:175.1-179.10. +Generating RTLIL representation for module `\OSCG'. +Replacing existing blackbox module `\USRMCLK' at /usr/bin/../share/yosys/ecp5/cells_bb.v:182.1-186.10. +Generating RTLIL representation for module `\USRMCLK'. +Replacing existing blackbox module `\JTAGG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:189.1-204.10. +Generating RTLIL representation for module `\JTAGG'. +Replacing existing blackbox module `\DELAYF' at /usr/bin/../share/yosys/ecp5/cells_bb.v:207.1-213.10. +Generating RTLIL representation for module `\DELAYF'. +Replacing existing blackbox module `\DELAYG' at /usr/bin/../share/yosys/ecp5/cells_bb.v:216.1-222.10. +Generating RTLIL representation for module `\DELAYG'. +Replacing existing blackbox module `\IDDRX1F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:225.1-230.10. +Generating RTLIL representation for module `\IDDRX1F'. +Replacing existing blackbox module `\IDDRX2F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:233.1-238.10. +Generating RTLIL representation for module `\IDDRX2F'. +Replacing existing blackbox module `\IDDR71B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:241.1-246.10. +Generating RTLIL representation for module `\IDDR71B'. +Replacing existing blackbox module `\IDDRX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:249.1-255.10. +Generating RTLIL representation for module `\IDDRX2DQA'. +Replacing existing blackbox module `\ODDRX1F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:258.1-263.10. +Generating RTLIL representation for module `\ODDRX1F'. +Replacing existing blackbox module `\ODDRX2F' at /usr/bin/../share/yosys/ecp5/cells_bb.v:266.1-271.10. +Generating RTLIL representation for module `\ODDRX2F'. +Replacing existing blackbox module `\ODDR71B' at /usr/bin/../share/yosys/ecp5/cells_bb.v:274.1-279.10. +Generating RTLIL representation for module `\ODDR71B'. +Replacing existing blackbox module `\OSHX2A' at /usr/bin/../share/yosys/ecp5/cells_bb.v:282.1-287.10. +Generating RTLIL representation for module `\OSHX2A'. +Replacing existing blackbox module `\ODDRX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:290.1-295.10. +Generating RTLIL representation for module `\ODDRX2DQA'. +Replacing existing blackbox module `\ODDRX2DQSB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:298.1-303.10. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Replacing existing blackbox module `\TSHX2DQA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:306.1-312.10. +Generating RTLIL representation for module `\TSHX2DQA'. +Replacing existing blackbox module `\TSHX2DQSA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:315.1-321.10. +Generating RTLIL representation for module `\TSHX2DQSA'. +Replacing existing blackbox module `\DQSBUFM' at /usr/bin/../share/yosys/ecp5/cells_bb.v:324.1-339.10. +Generating RTLIL representation for module `\DQSBUFM'. +Replacing existing blackbox module `\DDRDLLA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:342.1-348.10. +Generating RTLIL representation for module `\DDRDLLA'. +Replacing existing blackbox module `\DLLDELD' at /usr/bin/../share/yosys/ecp5/cells_bb.v:351.1-357.10. +Generating RTLIL representation for module `\DLLDELD'. +Replacing existing blackbox module `\CLKDIVF' at /usr/bin/../share/yosys/ecp5/cells_bb.v:360.1-366.10. +Generating RTLIL representation for module `\CLKDIVF'. +Replacing existing blackbox module `\ECLKSYNCB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:369.1-373.10. +Generating RTLIL representation for module `\ECLKSYNCB'. +Replacing existing blackbox module `\ECLKBRIDGECS' at /usr/bin/../share/yosys/ecp5/cells_bb.v:376.1-380.10. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Replacing existing blackbox module `\DCCA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:383.1-387.10. +Generating RTLIL representation for module `\DCCA'. +Replacing existing blackbox module `\DCSC' at /usr/bin/../share/yosys/ecp5/cells_bb.v:390.1-397.10. +Generating RTLIL representation for module `\DCSC'. +Replacing existing blackbox module `\DCUA' at /usr/bin/../share/yosys/ecp5/cells_bb.v:400.1-715.10. +Generating RTLIL representation for module `\DCUA'. +Replacing existing blackbox module `\EXTREFB' at /usr/bin/../share/yosys/ecp5/cells_bb.v:718.1-728.10. +Generating RTLIL representation for module `\EXTREFB'. +Replacing existing blackbox module `\PCSCLKDIV' at /usr/bin/../share/yosys/ecp5/cells_bb.v:731.1-736.10. +Generating RTLIL representation for module `\PCSCLKDIV'. +Replacing existing blackbox module `\PUR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:740.1-744.10. +Generating RTLIL representation for module `\PUR'. +Replacing existing blackbox module `\GSR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:747.1-750.10. +Generating RTLIL representation for module `\GSR'. +Replacing existing blackbox module `\SGSR' at /usr/bin/../share/yosys/ecp5/cells_bb.v:753.1-756.10. +Generating RTLIL representation for module `\SGSR'. +Replacing existing blackbox module `\PDPW16KD' at /usr/bin/../share/yosys/ecp5/cells_bb.v:760.1-850.10. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +26.3. Executing HIERARCHY pass (managing design hierarchy). + +26.3.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll + +26.3.2. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Used module: $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000 +Used module: \lean_silicon_lsc1 +Used module: \lsc1_packet_frontend +Used module: \lsc1_response_payload_mux +Used module: \lsc1_blake3_lifecycle +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Used module: \lsc1_cell_alias_check +Used module: \lsc1_request_validator +Used module: \lsc1_blake3_alias_check +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx +Used module: $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx +Used module: \ulx3s_core_pll +Removed 0 unused modules. + +26.4. Executing PROC pass (convert processes to netlists). + +26.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. +Cleaned up 1 empty switch. + +26.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316 in module DPR16X4C. +Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258 in module TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +26.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 42 assignments to connections. + +26.4.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. + Set init value: \Q = 1'0 + +26.4.5. Executing PROC_ARST pass (detect async resets in processes). + +26.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +26.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. +Creating decoders for process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + 1/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_EN[3:0]$89320 + 2/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_DATA[3:0]$89321 + 3/3: $1$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_ADDR[3:0]$89322 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + 1/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_EN[3:0]$89262 + 2/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_DATA[3:0]$89263 + 3/3: $1$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_ADDR[3:0]$89264 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. + +26.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +26.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. + created $dff cell `$procdff$89389' with positive edge clock. +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89314_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89313_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89312_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89311_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89310_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89309_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89308_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89307_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89306_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89305_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89304_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89303_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89302_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89301_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:281$89300_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_EN' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89390' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_DATA' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89391' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/bin/../share/yosys/ecp5/cells_sim.v:287$89315_ADDR' using process `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. + created $dff cell `$procdff$89392' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89255_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89254_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89253_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89252_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89251_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89250_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89249_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89248_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89247_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89246_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89245_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89244_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89243_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89242_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89241_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:207$89240_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89393' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89394' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/bin/../share/yosys/ecp5/cells_sim.v:223$89256_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. + created $dff cell `$procdff$89395' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. + created direct connection (no actual register cell created). + +26.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +26.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89365'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. +Removing empty process `TRELLIS_FF.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:350$89364'. +Removing empty process `DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89339'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:285$89316'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:0$89282'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:221$89258'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/bin/../share/yosys/ecp5/cells_sim.v:213$89257'. +Cleaned up 4 empty switches. + +26.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_cell_alias_check. +Optimizing module lsc1_request_validator. +Optimizing module lsc1_blake3_alias_check. +Optimizing module lsc1_response_payload_mux. +Optimizing module lsc1_blake3_lifecycle. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_stream_adapter. +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_rx. +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Optimizing module lean_silicon_lsc1. +Optimizing module lsc1_packet_frontend. +Optimizing module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Optimizing module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Optimizing module ulx3s_core_pll. +Optimizing module ulx3s_packet_top. +Optimizing module gf128_mul_bitstream. + +26.5. Executing FLATTEN pass (flatten design). +Deleting now unused module leanvm_b_stream_alu. +Deleting now unused module lsc1_cell_alias_check. +Deleting now unused module lsc1_request_validator. +Deleting now unused module lsc1_blake3_alias_check. +Deleting now unused module lsc1_response_payload_mux. +Deleting now unused module lsc1_blake3_lifecycle. +Deleting now unused module lsc1_field_encoder. +Deleting now unused module lsc1_stream_adapter. +Deleting now unused module lsc1_packet_tx. +Deleting now unused module lsc1_packet_rx. +Deleting now unused module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Deleting now unused module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_tx. +Deleting now unused module lean_silicon_lsc1. +Deleting now unused module lsc1_packet_frontend. +Deleting now unused module $paramod\uart_bridge\PACKET_MODE=1'1\CLK_HZ=s32'00000000100110001001011010000000. +Deleting now unused module $paramod$2f51e420815dfbb27ed99b63ff892b80f8d2ef5b\uart_rx. +Deleting now unused module ulx3s_core_pll. +Deleting now unused module gf128_mul_bitstream. + + +26.6. Executing TRIBUF pass. + +26.7. Executing DEMINOUT pass (demote inout ports to input or output). + +26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 9329 unused cells and 40894 unused wires. + + +26.10. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +26.11. Executing OPT pass (performing simple optimizations). + +26.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1008 cells. + +26.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15648: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86029: \bridge.g_packet.asic.packet_core.result_pending -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15124: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88031: \bridge.urx.wait_idle -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88029: \bridge.urx.wait_idle -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88048: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\urx.$procmux$88044: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88040: \bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88054: \bridge.urx.receiving -> 1'0 + Replacing known input bits on port B of cell $flatten\bridge.\urx.$procmux$88051: \bridge.urx.receiving -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12978: \bridge.utx.tx_ready -> 1'1 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12975: \bridge.utx.tx_ready -> 1'0 + Replacing known input bits on port A of cell $flatten\bridge.\utx.$procmux$12973: \bridge.utx.tx_ready -> 1'0 + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15464. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15467. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15470. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15473. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15476. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15479. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15482. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15485. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15488. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15491. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15494. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15497. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15504. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15507. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15510. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15513. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15516. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15519. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15522. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15525. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15528. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15531. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15534. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15536. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15539. 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$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6936. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6938. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7020. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7023. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7025. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7092. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7094. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$7145. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15438. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15441. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15444. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8953. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8956. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8959. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8962. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8965. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8968. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8974. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8977. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8980. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8983. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8986. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8992. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8995. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8998. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9001. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9007. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9010. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9013. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9019. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9022. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$9028. + dead port 1/2 on $mux $flatten\bridge.\urx.$procmux$87804. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87806. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87809. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87812. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87863. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87866. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87869. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87911. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87914. + dead port 2/2 on $mux $flatten\bridge.\urx.$procmux$87947. +Removed 14532 multiplexer ports. + + +26.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New input vector for $reduce_or cell $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$reduce_or$../../asic_core/rtl/lsc1_blake3_alias_check.sv:63$2341: { \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [55] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [47:46] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [39:37] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [31:28] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [23:19] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [15:10] \bridge.g_packet.asic.packet_core.blake3_alias_check.alias_pair [7:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=128'11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4609: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $auto$opt_reduce.cc:134:opt_pmux$89397 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4621: { $auto$opt_reduce.cc:134:opt_pmux$89399 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640: { $auto$opt_reduce.cc:134:opt_pmux$89401 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4642_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4688: { $auto$opt_reduce.cc:134:opt_pmux$89405 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89403 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4732: { $auto$opt_reduce.cc:134:opt_pmux$89409 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89407 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7733: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4609: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $auto$opt_reduce.cc:134:opt_pmux$89411 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4621: { $auto$opt_reduce.cc:134:opt_pmux$89413 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640: { $auto$opt_reduce.cc:134:opt_pmux$89415 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4642_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4688: { $auto$opt_reduce.cc:134:opt_pmux$89419 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89417 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4732: { $auto$opt_reduce.cc:134:opt_pmux$89423 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $auto$opt_reduce.cc:134:opt_pmux$89421 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12522: { $auto$opt_reduce.cc:134:opt_pmux$89425 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=128'11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5245: { $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5200_CMP $auto$opt_reduce.cc:134:opt_pmux$89427 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5195_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5191_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5190_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5188_CMP } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4193, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32854_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4190, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33070_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4203, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32350_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4200, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32566_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4186, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33355_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4183, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33562_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4180, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33769_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4177, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33976_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4159, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34453_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4156, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34651_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4153, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34849_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4150, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35047_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4135, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35695_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4132, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35884_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4129, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36073_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4138, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35506_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4120, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36577_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4117, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36757_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4114, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36937_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4111, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37117_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4102, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37714_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4099, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37885_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4096, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38056_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4093, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38227_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4083, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38739_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4080, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38901_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4077, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39063_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4074, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39225_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$4029, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43857_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$4026, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44010_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$4023, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44163_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$4020, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44316_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3982, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47613_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3979, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47757_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3988, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47325_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3985, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47469_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3952, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$50925_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3949, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51060_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3946, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51195_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3943, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51330_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3918, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54384_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3915, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54510_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3912, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54636_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3909, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54762_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3885, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57533_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3882, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57650_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3879, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57767_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3876, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57884_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3841, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61592_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3838, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61700_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3835, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61808_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3832, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61916_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3798, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64457_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3795, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64556_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3792, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64655_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3789, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64754_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3757, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$66995_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3754, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67085_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3751, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67175_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3748, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67265_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3715, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69590_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3712, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69671_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3709, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69752_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3706, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69833_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3661, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72086_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3670, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71870_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3667, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71942_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3664, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72014_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3627, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73835_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3624, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73898_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3621, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73961_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3618, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74024_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3579, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75962_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3576, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76016_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3573, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76070_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3570, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76124_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3532, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77489_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3529, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77534_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3526, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77579_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3523, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77624_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3478, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79169_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3475, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79205_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3472, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79241_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3469, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79277_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3401, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81338_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3398, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81365_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3395, B=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81392_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3392, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81419_Y [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83235: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3348, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82076_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:773$3162_EN[127:0]$3251 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83244: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3345, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82094_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_EN[31:0]$3248 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83253: + Old ports: A=128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3342, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82112_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [127:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_EN[127:0]$3245 [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83262: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3339, Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82130_Y [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [31:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] $flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_EN[31:0]$3242 [0] } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 111 changes. + +26.11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 226 cells. + +26.11.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 15739 unused wires. + + +26.11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7617: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7609_CMP $auto$opt_reduce.cc:134:opt_pmux$89429 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89431 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4540: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89433 $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7617: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP $auto$opt_reduce.cc:134:opt_pmux$89435 } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89437 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4540: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $auto$opt_reduce.cc:134:opt_pmux$89439 $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 6 changes. + +26.11.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.11.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.11.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.11.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.11.20. Executing OPT_DFF pass (perform DFF optimizations). + +26.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.11.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.11.23. Finished OPT passes. (There is nothing left to do.) + +26.12. Executing FSM pass (extract and optimize FSM). + +26.12.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.adapter.datapath.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.adapter.state as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.alu_operation as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.compute_state. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.field_encoder.multiplier.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.n_deferred as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.n_writes as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.receiver.fault_status as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.receiver.state. +Not marking ulx3s_packet_top.bridge.g_packet.asic.packet_core.scalar_staged_access_count as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register ulx3s_packet_top.bridge.g_packet.asic.packet_core.tx_external_kind. + +26.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\bridge.g_packet.asic.packet_core.adapter.datapath.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88735 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89433 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + found state code: 4'1010 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last + found state code: 4'0110 + found state code: 4'1000 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.core_rx_fire + found state code: 4'0111 + found state code: 4'0001 + found state code: 4'0010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP + found state code: 4'1001 + found state code: 4'0100 + found state code: 4'0011 + found state code: 4'0101 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last \bridge.g_packet.asic.packet_core.adapter.core_tx_fire \bridge.g_packet.asic.packet_core.adapter.core_rx_fire $auto$opt_reduce.cc:134:opt_pmux$89433 } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP } + transition: 4'0000 14'0------------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10----------0- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10--000000--1- -> 4'1010 15'010100010000000 + transition: 4'0000 14'10-------1--1- -> 4'0001 15'000010010000000 + transition: 4'0000 14'10------1---1- -> 4'0101 15'001010010000000 + transition: 4'0000 14'10-----1----1- -> 4'0011 15'000110010000000 + transition: 4'0000 14'10----1-----1- -> 4'0100 15'001000010000000 + transition: 4'0000 14'10---1------1- -> 4'1001 15'010010010000000 + transition: 4'0000 14'10--1-------1- -> 4'0000 15'000000010000000 + transition: 4'0000 14'11------------ -> 4'0000 15'000000010000000 + transition: 4'1000 14'0------------- -> 4'0000 15'000000000010000 + transition: 4'1000 14'10---------0-- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--------01-- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--------11-- -> 4'0000 15'000000000010000 + transition: 4'1000 14'11------------ -> 4'0000 15'000000000010000 + transition: 4'0100 14'0------------- -> 4'0000 15'000000001000000 + transition: 4'0100 14'10--------0--- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--------10-- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--------11-- -> 4'0000 15'000000001000000 + transition: 4'0100 14'11------------ -> 4'0000 15'000000001000000 + transition: 4'0010 14'0------------- -> 4'0000 15'000000000000010 + transition: 4'0010 14'10---------0-- -> 4'0010 15'000100000000010 + transition: 4'0010 14'10--------01-- -> 4'0001 15'000010000000010 + transition: 4'0010 14'10--------11-- -> 4'0000 15'000000000000010 + transition: 4'0010 14'11------------ -> 4'0000 15'000000000000010 + transition: 4'1010 14'0------------- -> 4'0000 15'000000000000001 + transition: 4'1010 14'10---------0-- -> 4'1010 15'010100000000001 + transition: 4'1010 14'10---------1-- -> 4'0000 15'000000000000001 + transition: 4'1010 14'11------------ -> 4'0000 15'000000000000001 + transition: 4'0110 14'0------------- -> 4'0000 15'000001000000000 + transition: 4'0110 14'10----------0- -> 4'0110 15'001101000000000 + transition: 4'0110 14'10----------1- -> 4'0111 15'001111000000000 + transition: 4'0110 14'11------------ -> 4'0000 15'000001000000000 + transition: 4'0001 14'0------------- -> 4'0000 15'000000100000000 + transition: 4'0001 14'10----------0- -> 4'0001 15'000010100000000 + transition: 4'0001 14'10----------1- -> 4'0010 15'000100100000000 + transition: 4'0001 14'11------------ -> 4'0000 15'000000100000000 + transition: 4'1001 14'0------------- -> 4'0000 15'000000000100000 + transition: 4'1001 14'10---------0-- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10-0-------1-- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10-1-------1-- -> 4'0000 15'000000000100000 + transition: 4'1001 14'11------------ -> 4'0000 15'000000000100000 + transition: 4'0101 14'0------------- -> 4'0000 15'000000000001000 + transition: 4'0101 14'10----------0- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10--------0-1- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10--------1-1- -> 4'0110 15'001100000001000 + transition: 4'0101 14'11------------ -> 4'0000 15'000000000001000 + transition: 4'0011 14'0------------- -> 4'0000 15'000000000000100 + transition: 4'0011 14'10---------0-- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--------01-- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--------11-- -> 4'0000 15'000000000000100 + transition: 4'0011 14'11------------ -> 4'0000 15'000000000000100 + transition: 4'0111 14'0------------- -> 4'0000 15'100000000000000 + transition: 4'0111 14'100----------- -> 4'0111 15'101110000000000 + transition: 4'0111 14'101-------0--- -> 4'0110 15'101100000000000 + transition: 4'0111 14'101-------1--- -> 4'1000 15'110000000000000 + transition: 4'0111 14'11------------ -> 4'0000 15'100000000000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.compute_state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88859 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.fault_valid + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_reject + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_validator.is_xor + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y + found state code: 4'0001 + found state code: 4'0101 + found state code: 4'0011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y + found ctrl input: \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y + found state code: 4'1000 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y + found state code: 4'0110 + found state code: 4'0100 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + found state code: 4'0010 + found state code: 4'1001 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + found state code: 4'1010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + found state code: 4'0111 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.request_reject $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP \bridge.g_packet.asic.packet_core.request_validator.is_xor \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.field_encoder.fault } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y } + transition: 4'0000 44'0------------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-000000------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'100010000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'101010000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'110000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--101------01-00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'101100000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-011----------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-0-1------------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000-1--------------0---0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'101000000000000 + transition: 4'0000 44'10100--00-00-000001000--------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10-00--00-00-000001001--------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10-10--00-00-00000100---------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-00000101---------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-0000011----------------------0- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-000001-----------------------1- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-00001-------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-0001--------------------------- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10--0--00-000001---------------------------- -> 4'0010 15'100100000000000 + transition: 4'0000 44'10--0--00-001001---------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-00-01----------------------------- -> 4'0011 15'100110000000000 + transition: 4'0000 44'10--0--00-00-1------------------------------ -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-010------------------------------- -> 4'1001 15'110010000000000 + transition: 4'0000 44'10--0--00-011------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--00-1--------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--010---------------------------------0 -> 4'1010 15'110100000000000 + transition: 4'0000 44'10--0--011---------------------------------0 -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--01----------------------------------1 -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--0--1------------------------------------ -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--100------------------------------------- -> 4'0111 15'101110000000000 + transition: 4'0000 44'10--101------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'10--11-------------------------------------- -> 4'0000 15'100000000000000 + transition: 4'0000 44'11------------------------------------------ -> 4'0000 15'100000000000000 + transition: 4'1000 44'0------------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-000000------------------------- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--101------01-00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-011----------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-0-1------------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000-1--------------0---0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000100000 + transition: 4'1000 44'10100--00-00-000001000--------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10-00--00-00-000001001--------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10-10--00-00-00000100---------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-00000101---------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-0000011----------------------0- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-000001-----------------------1- -> 4'1000 15'010000000100000 + transition: 4'1000 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000100000 + transition: 4'1000 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000100000 + transition: 4'1000 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-010------------------------------- -> 4'1001 15'010010000100000 + transition: 4'1000 44'10--0--00-011------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--010---------------------------------0 -> 4'1010 15'010100000100000 + transition: 4'1000 44'10--0--011---------------------------------0 -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--01----------------------------------1 -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--0--1------------------------------------ -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--100------------------------------------- -> 4'0111 15'001110000100000 + transition: 4'1000 44'10--101------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'10--11-------------------------------------- -> 4'0000 15'000000000100000 + transition: 4'1000 44'11------------------------------------------ -> 4'0000 15'000000000100000 + transition: 4'0100 44'0------------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-000000------------------------- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--101------01-00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-011----------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-0-1------------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000-1--------------0---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10100--00-00-000001000--------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10-00--00-00-000001001--------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10-10--00-00-00000100---------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-00000101---------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-0000011----------------------0- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-000001-----------------------1- -> 4'0100 15'001000000010000 + transition: 4'0100 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000010000 + transition: 4'0100 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000010000 + transition: 4'0100 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-010------------------------------- -> 4'1001 15'010010000010000 + transition: 4'0100 44'10--0--00-011------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--010---------------------------------0 -> 4'1010 15'010100000010000 + transition: 4'0100 44'10--0--011---------------------------------0 -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--01----------------------------------1 -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--0--1------------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--100------------------------------------- -> 4'0111 15'001110000010000 + transition: 4'0100 44'10--101------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'10--11-------------------------------------- -> 4'0000 15'000000000010000 + transition: 4'0100 44'11------------------------------------------ -> 4'0000 15'000000000010000 + transition: 4'0010 44'0------------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-000000------------------------- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--101------01-00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-011----------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-0-1------------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000-1--------------0---0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000010 + transition: 4'0010 44'10100--00-00-000001000--------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10-00--00-00-000001001--------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10-10--00-00-00000100---------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-00000101---------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-0000011----------------------0- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-000001-----------------------1- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000010 + transition: 4'0010 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000010 + transition: 4'0010 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000010 + transition: 4'0010 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000010 + transition: 4'0010 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--0--1------------------------------------ -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--100------------------------------------- -> 4'0111 15'001110000000010 + transition: 4'0010 44'10--101------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'10--11-------------------------------------- -> 4'0000 15'000000000000010 + transition: 4'0010 44'11------------------------------------------ -> 4'0000 15'000000000000010 + transition: 4'1010 44'0------------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-000000------------------------- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--101------01-00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-011----------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-0-1------------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000-1--------------0---0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000001000000 + transition: 4'1010 44'10100--00-00-000001000--------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10-00--00-00-000001001--------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10-10--00-00-00000100---------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-00000101---------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-0000011----------------------0- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-000001-----------------------1- -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10--0--00-000001---------------------------- -> 4'0010 15'000100001000000 + transition: 4'1010 44'10--0--00-001001---------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110001000000 + transition: 4'1010 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-010------------------------------- -> 4'1001 15'010010001000000 + transition: 4'1010 44'10--0--00-011------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--00-1--------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--010---------------------------------0 -> 4'1010 15'010100001000000 + transition: 4'1010 44'10--0--011---------------------------------0 -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--01----------------------------------1 -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--0--1------------------------------------ -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--100------------------------------------- -> 4'0111 15'001110001000000 + transition: 4'1010 44'10--101------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'10--11-------------------------------------- -> 4'0000 15'000000001000000 + transition: 4'1010 44'11------------------------------------------ -> 4'0000 15'000000001000000 + transition: 4'0110 44'0------------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-000000------------------------- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000011000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001011000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010001000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--101------01-00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-011----------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-0-1------------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000-1--------------0---0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001001000000000 + transition: 4'0110 44'10100--00-00-000001000--------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10-00--00-00-000001001--------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10-10--00-00-00000100---------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-00000101---------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-0000011----------------------0- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-000001-----------------------1- -> 4'0110 15'001101000000000 + transition: 4'0110 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10--0--00-000001---------------------------- -> 4'0010 15'000101000000000 + transition: 4'0110 44'10--0--00-001001---------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-00-01----------------------------- -> 4'0011 15'000111000000000 + transition: 4'0110 44'10--0--00-00-1------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-010------------------------------- -> 4'1001 15'010011000000000 + transition: 4'0110 44'10--0--00-011------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--00-1--------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--010---------------------------------0 -> 4'1010 15'010101000000000 + transition: 4'0110 44'10--0--011---------------------------------0 -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--01----------------------------------1 -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--0--1------------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--100------------------------------------- -> 4'0111 15'001111000000000 + transition: 4'0110 44'10--101------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'10--11-------------------------------------- -> 4'0000 15'000001000000000 + transition: 4'0110 44'11------------------------------------------ -> 4'0000 15'000001000000000 + transition: 4'0001 44'0------------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-000000------------------------- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--101------01-00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-011----------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-0-1------------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000-1--------------0---0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000100 + transition: 4'0001 44'10100--00-00-000001000--------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10-00--00-00-000001001--------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10-10--00-00-00000100---------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-00000101---------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-0000011----------------------0- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-000001-----------------------1- -> 4'0001 15'000010000000100 + transition: 4'0001 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000100 + transition: 4'0001 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000100 + transition: 4'0001 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000100 + transition: 4'0001 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000100 + transition: 4'0001 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--0--1------------------------------------ -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--100------------------------------------- -> 4'0111 15'001110000000100 + transition: 4'0001 44'10--101------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'10--11-------------------------------------- -> 4'0000 15'000000000000100 + transition: 4'0001 44'11------------------------------------------ -> 4'0000 15'000000000000100 + transition: 4'1001 44'0------------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-000000------------------------- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100000-00--0--------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--10-------00-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--101------01-00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--11-------0--00- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0000--1--------0--10- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0100--1--------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0100---------0--10- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-0101---------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-011----------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-0-1------------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000-1--------------0---0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000010000000 + transition: 4'1001 44'10100--00-00-000001000--------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10-00--00-00-000001001--------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10-10--00-00-00000100---------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-00000101---------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-0000011----------------------0- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-000001-----------------------1- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10--0--00-000001---------------------------- -> 4'0010 15'000100010000000 + transition: 4'1001 44'10--0--00-001001---------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110010000000 + transition: 4'1001 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-010------------------------------- -> 4'1001 15'010010010000000 + transition: 4'1001 44'10--0--00-011------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--00-1--------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--010---------------------------------0 -> 4'1010 15'010100010000000 + transition: 4'1001 44'10--0--011---------------------------------0 -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--01----------------------------------1 -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--0--1------------------------------------ -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--100------------------------------------- -> 4'0111 15'001110010000000 + transition: 4'1001 44'10--101------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'10--11-------------------------------------- -> 4'0000 15'000000010000000 + transition: 4'1001 44'11------------------------------------------ -> 4'0000 15'000000010000000 + transition: 4'0101 44'0------------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-000000------------------------- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--101------01-00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-011----------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-0-1------------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000-1--------------0---0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000001000 + transition: 4'0101 44'10100--00-00-000001000--------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10-00--00-00-000001001--------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10-10--00-00-00000100---------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-00000101---------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-0000011----------------------0- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-000001-----------------------1- -> 4'0101 15'001010000001000 + transition: 4'0101 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000001000 + transition: 4'0101 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000001000 + transition: 4'0101 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-010------------------------------- -> 4'1001 15'010010000001000 + transition: 4'0101 44'10--0--00-011------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--010---------------------------------0 -> 4'1010 15'010100000001000 + transition: 4'0101 44'10--0--011---------------------------------0 -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--01----------------------------------1 -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--0--1------------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--100------------------------------------- -> 4'0111 15'001110000001000 + transition: 4'0101 44'10--101------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'10--11-------------------------------------- -> 4'0000 15'000000000001000 + transition: 4'0101 44'11------------------------------------------ -> 4'0000 15'000000000001000 + transition: 4'0011 44'0------------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-000000------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--101------01-00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-011----------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-0-1------------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000-1--------------0---0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000000000001 + transition: 4'0011 44'10100--00-00-000001000--------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10-00--00-00-000001001--------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10-10--00-00-00000100---------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-00000101---------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-0000011----------------------0- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-000001-----------------------1- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-000001---------------------------- -> 4'0010 15'000100000000001 + transition: 4'0011 44'10--0--00-001001---------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110000000001 + transition: 4'0011 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-010------------------------------- -> 4'1001 15'010010000000001 + transition: 4'0011 44'10--0--00-011------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--00-1--------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--010---------------------------------0 -> 4'1010 15'010100000000001 + transition: 4'0011 44'10--0--011---------------------------------0 -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--01----------------------------------1 -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--0--1------------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--100------------------------------------- -> 4'0111 15'001110000000001 + transition: 4'0011 44'10--101------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'10--11-------------------------------------- -> 4'0000 15'000000000000001 + transition: 4'0011 44'11------------------------------------------ -> 4'0000 15'000000000000001 + transition: 4'0111 44'0------------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-000000------------------------- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100000-00--0--------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---0--000---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---100000-0-0- -> 4'0001 15'000010100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 4'0101 15'001010100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0------010---0- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10000--00-00-00000100010-00--0------1-0---0- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--10-------00-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1000-----01-00- -> 4'1000 15'010000100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1001-----01-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--101------01-00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--11-------0--00- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0000--1--------0--10- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0100--1--------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0100---------0--00- -> 4'0110 15'001100100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0100---------0--10- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-0101---------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-011----------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-0-1------------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000-1--------------0---0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10000--00-00-000001000----------------1---0- -> 4'0100 15'001000100000000 + transition: 4'0111 44'10100--00-00-000001000--------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10-00--00-00-000001001--------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10-10--00-00-00000100---------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-00000101---------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-0000011----------------------0- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-000001-----------------------1- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--0--00-00-00001-------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-0001--------------------------- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10--0--00-000001---------------------------- -> 4'0010 15'000100100000000 + transition: 4'0111 44'10--0--00-001001---------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-00-01----------------------------- -> 4'0011 15'000110100000000 + transition: 4'0111 44'10--0--00-00-1------------------------------ -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-010------------------------------- -> 4'1001 15'010010100000000 + transition: 4'0111 44'10--0--00-011------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--00-1--------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--010---------------------------------0 -> 4'1010 15'010100100000000 + transition: 4'0111 44'10--0--011---------------------------------0 -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--01----------------------------------1 -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--0--1------------------------------------ -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--100------------------------------------- -> 4'0111 15'001110100000000 + transition: 4'0111 44'10--101------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'10--11-------------------------------------- -> 4'0000 15'000000100000000 + transition: 4'0111 44'11------------------------------------------ -> 4'0000 15'000000100000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88735 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89439 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + found state code: 4'1010 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last + found state code: 4'0110 + found state code: 4'1000 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + found state code: 4'0111 + found state code: 4'0001 + found state code: 4'0010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP + found state code: 4'1001 + found state code: 4'0100 + found state code: 4'0011 + found state code: 4'0101 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q $auto$opt_reduce.cc:134:opt_pmux$89439 \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y } + transition: 4'0000 14'0------------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-0---------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-1--000000-- -> 4'1010 15'000000010010100 + transition: 4'0000 14'10-1--1------- -> 4'0001 15'000000010000010 + transition: 4'0000 14'10-1---1------ -> 4'0101 15'000000010001010 + transition: 4'0000 14'10-1----1----- -> 4'0011 15'000000010000110 + transition: 4'0000 14'10-1-----1---- -> 4'0100 15'000000010001000 + transition: 4'0000 14'10-1------1--- -> 4'1001 15'000000010010010 + transition: 4'0000 14'10-1-------1-- -> 4'0000 15'000000010000000 + transition: 4'0000 14'11------------ -> 4'0000 15'000000010000000 + transition: 4'1000 14'0------------- -> 4'0000 15'000010000000000 + transition: 4'1000 14'10--0--------- -> 4'1000 15'000010000010000 + transition: 4'1000 14'10--10-------- -> 4'1000 15'000010000010000 + transition: 4'1000 14'10--11-------- -> 4'0000 15'000010000000000 + transition: 4'1000 14'11------------ -> 4'0000 15'000010000000000 + transition: 4'0100 14'0------------- -> 4'0000 15'000000100000000 + transition: 4'0100 14'10---0-------- -> 4'0100 15'000000100001000 + transition: 4'0100 14'10--01-------- -> 4'0100 15'000000100001000 + transition: 4'0100 14'10--11-------- -> 4'0000 15'000000100000000 + transition: 4'0100 14'11------------ -> 4'0000 15'000000100000000 + transition: 4'0010 14'0------------- -> 4'0000 15'010000000000000 + transition: 4'0010 14'10--0--------- -> 4'0010 15'010000000000100 + transition: 4'0010 14'10--10-------- -> 4'0001 15'010000000000010 + transition: 4'0010 14'10--11-------- -> 4'0000 15'010000000000000 + transition: 4'0010 14'11------------ -> 4'0000 15'010000000000000 + transition: 4'1010 14'0------------- -> 4'0000 15'100000000000000 + transition: 4'1010 14'10--0--------- -> 4'1010 15'100000000010100 + transition: 4'1010 14'10--1--------- -> 4'0000 15'100000000000000 + transition: 4'1010 14'11------------ -> 4'0000 15'100000000000000 + transition: 4'0110 14'0------------- -> 4'0000 15'000000000100000 + transition: 4'0110 14'10-0---------- -> 4'0110 15'000000000101100 + transition: 4'0110 14'10-1---------- -> 4'0111 15'000000000101110 + transition: 4'0110 14'11------------ -> 4'0000 15'000000000100000 + transition: 4'0001 14'0------------- -> 4'0000 15'000000001000000 + transition: 4'0001 14'10-0---------- -> 4'0001 15'000000001000010 + transition: 4'0001 14'10-1---------- -> 4'0010 15'000000001000100 + transition: 4'0001 14'11------------ -> 4'0000 15'000000001000000 + transition: 4'1001 14'0------------- -> 4'0000 15'000001000000000 + transition: 4'1001 14'10--0--------- -> 4'1001 15'000001000010010 + transition: 4'1001 14'10--1-------0- -> 4'1001 15'000001000010010 + transition: 4'1001 14'10--1-------1- -> 4'0000 15'000001000000000 + transition: 4'1001 14'11------------ -> 4'0000 15'000001000000000 + transition: 4'0101 14'0------------- -> 4'0000 15'000100000000000 + transition: 4'0101 14'10-0---------- -> 4'0101 15'000100000001010 + transition: 4'0101 14'10-1-0-------- -> 4'0101 15'000100000001010 + transition: 4'0101 14'10-1-1-------- -> 4'0110 15'000100000001100 + transition: 4'0101 14'11------------ -> 4'0000 15'000100000000000 + transition: 4'0011 14'0------------- -> 4'0000 15'001000000000000 + transition: 4'0011 14'10--0--------- -> 4'0011 15'001000000000110 + transition: 4'0011 14'10--10-------- -> 4'0011 15'001000000000110 + transition: 4'0011 14'10--11-------- -> 4'0000 15'001000000000000 + transition: 4'0011 14'11------------ -> 4'0000 15'001000000000000 + transition: 4'0111 14'0------------- -> 4'0000 15'000000000000001 + transition: 4'0111 14'10-----------0 -> 4'0111 15'000000000001111 + transition: 4'0111 14'10---0-------1 -> 4'0110 15'000000000001101 + transition: 4'0111 14'10---1-------1 -> 4'1000 15'000000000010001 + transition: 4'0111 14'11------------ -> 4'0000 15'000000000000001 +Extracting FSM `\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88765 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 3'000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y + found state code: 3'100 + found state code: 3'011 + found state code: 3'010 + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.multiply_start + found state code: 3'001 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y \bridge.g_packet.asic.packet_core.field_encoder.multiply_start } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP } + transition: 3'000 8'0------- -> 3'000 8'00000001 + transition: 3'000 8'10-----0 -> 3'000 8'00000001 + transition: 3'000 8'10-----1 -> 3'001 8'00000101 + transition: 3'000 8'11------ -> 3'000 8'00000001 + transition: 3'100 8'0------- -> 3'000 8'00000010 + transition: 3'100 8'10-0---- -> 3'100 8'00010010 + transition: 3'100 8'10-1--0- -> 3'100 8'00010010 + transition: 3'100 8'10-1--1- -> 3'000 8'00000010 + transition: 3'100 8'11------ -> 3'000 8'00000010 + transition: 3'010 8'0------- -> 3'000 8'00100000 + transition: 3'010 8'100----- -> 3'010 8'00101000 + transition: 3'010 8'101----- -> 3'011 8'00101100 + transition: 3'010 8'11------ -> 3'000 8'00100000 + transition: 3'001 8'0------- -> 3'000 8'01000000 + transition: 3'001 8'100----- -> 3'001 8'01000100 + transition: 3'001 8'101----- -> 3'010 8'01001000 + transition: 3'001 8'11------ -> 3'000 8'01000000 + transition: 3'011 8'0------- -> 3'000 8'10000000 + transition: 3'011 8'100----- -> 3'011 8'10001100 + transition: 3'011 8'101-0--- -> 3'011 8'10001100 + transition: 3'011 8'101-10-- -> 3'000 8'10000000 + transition: 3'011 8'101-11-- -> 3'100 8'10010000 + transition: 3'011 8'11------ -> 3'000 8'10000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.receiver.state' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88811 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.rx_fire + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y + found state code: 3'000 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP + found state code: 3'011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$89425 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y + found state code: 3'010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y + found state code: 3'001 + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$89425 $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y \bridge.g_packet.asic.packet_core.receiver.rx_fire $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y } + transition: 3'000 10'-0-----000 -> 3'000 7'0100001 + transition: 3'000 10'-1-----000 -> 3'000 7'0100001 + transition: 3'000 10'-------100 -> 3'000 7'0100001 + transition: 3'000 10'------0-10 -> 3'001 7'0100011 + transition: 3'000 10'------1-10 -> 3'011 7'0100111 + transition: 3'000 10'---------1 -> 3'000 7'0100001 + transition: 3'010 10'-0-----000 -> 3'010 7'0010101 + transition: 3'010 10'-1-----000 -> 3'000 7'0010001 + transition: 3'010 10'-------100 -> 3'000 7'0010001 + transition: 3'010 10'-00-0--010 -> 3'010 7'0010101 + transition: 3'010 10'-10-0--010 -> 3'000 7'0010001 + transition: 3'010 10'--0-0--110 -> 3'000 7'0010001 + transition: 3'010 10'--1-0---10 -> 3'011 7'0010111 + transition: 3'010 10'-0--1--010 -> 3'010 7'0010101 + transition: 3'010 10'-1--1--010 -> 3'000 7'0010001 + transition: 3'010 10'----1--110 -> 3'000 7'0010001 + transition: 3'010 10'---------1 -> 3'000 7'0010001 + transition: 3'001 10'-0-----000 -> 3'001 7'1000011 + transition: 3'001 10'-1-----000 -> 3'000 7'1000001 + transition: 3'001 10'-------100 -> 3'000 7'1000001 + transition: 3'001 10'0--0----10 -> 3'000 7'1000001 + transition: 3'001 10'10-----010 -> 3'001 7'1000011 + transition: 3'001 10'11-----010 -> 3'000 7'1000001 + transition: 3'001 10'1------110 -> 3'000 7'1000001 + transition: 3'001 10'---1-0--10 -> 3'010 7'1000101 + transition: 3'001 10'---1-1--10 -> 3'011 7'1000111 + transition: 3'001 10'---------1 -> 3'000 7'1000001 + transition: 3'011 10'-0-----000 -> 3'011 7'0000110 + transition: 3'011 10'-1-----000 -> 3'000 7'0000000 + transition: 3'011 10'-------100 -> 3'000 7'0000000 + transition: 3'011 10'--------10 -> 3'000 7'0000000 + transition: 3'011 10'---------1 -> 3'000 7'0000000 +Extracting FSM `\bridge.g_packet.asic.packet_core.tx_external_kind' from module `\ulx3s_packet_top'. + found $dff cell for state register: $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88855 + root of input selection tree: $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \bridge.por_shift [7] + found state code: 3'000 + found ctrl input: \bridge.abort_q + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + found ctrl input: \bridge.g_packet.asic.packet_core.receiver.fault_valid + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_reject + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] + found state code: 3'100 + found state code: 3'011 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] + found state code: 3'001 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y + found ctrl input: \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y + found state code: 3'010 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y + found ctrl input: \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending + found ctrl input: \bridge.g_packet.asic.packet_core.result_pending + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y + found state code: 3'111 + found ctrl input: \bridge.g_packet.asic.packet_core.blake_retire_match + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y + found ctrl input: \bridge.g_packet.asic.packet_core.request_validator.bad_state + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y + found state code: 3'110 + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y + found state code: 3'101 + found ctrl input: \bridge.g_packet.asic.packet_core.adapter.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y + found ctrl input: \bridge.g_packet.asic.packet_core.field_encoder.fault + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y + found ctrl input: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y + found ctrl output: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y + ctrl inputs: { \bridge.por_shift [7] \bridge.abort_q \bridge.g_packet.asic.packet_core.result_pending \bridge.g_packet.asic.packet_core.blake_retire_match \bridge.g_packet.asic.packet_core.request_reject $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] \bridge.g_packet.asic.packet_core.request_validator.bad_state \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.adapter.fault \bridge.g_packet.asic.packet_core.field_encoder.fault \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending } + ctrl outputs: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y } + transition: 3'000 51'0-------------------------------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'000 10'0000000000 + transition: 3'000 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000000 + transition: 3'000 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000000 + transition: 3'000 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000000 + transition: 3'000 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000000 + transition: 3'000 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000000 + transition: 3'000 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000000 + transition: 3'000 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000000 + transition: 3'000 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-001--------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-000-01---------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-0-0-1----------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-0-10-------------------------------- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-10---------------------------------0-- -> 3'000 10'0000000000 + transition: 3'000 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000000 + transition: 3'000 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000000 + transition: 3'000 51'10----0----1------------------------------------1-- -> 3'100 10'0100000000 + transition: 3'000 51'10----100------------------------------------------ -> 3'000 10'0000000000 + transition: 3'000 51'10----10100---------------------------------------- -> 3'011 10'0011000000 + transition: 3'000 51'10----10101---------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----1011----------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'10----11------------------------------------------- -> 3'100 10'0100000000 + transition: 3'000 51'11------------------------------------------------- -> 3'000 10'0000000000 + transition: 3'100 51'0-------------------------------------------------- -> 3'000 10'0000000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'100 10'0100000100 + transition: 3'100 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000100 + transition: 3'100 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000100 + transition: 3'100 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000100 + transition: 3'100 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000100 + transition: 3'100 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000100 + transition: 3'100 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000100 + transition: 3'100 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000100 + transition: 3'100 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-001--------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-000-01---------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-0-1----------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-10-------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-10---------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000100 + transition: 3'100 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000100 + transition: 3'100 51'10----0----1------------------------------------1-- -> 3'100 10'0100000100 + transition: 3'100 51'10----100------------------------------------------ -> 3'100 10'0100000100 + transition: 3'100 51'10----10100---------------------------------------- -> 3'011 10'0011000100 + transition: 3'100 51'10----10101---------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----1011----------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'10----11------------------------------------------- -> 3'100 10'0100000100 + transition: 3'100 51'11------------------------------------------------- -> 3'000 10'0000000100 + transition: 3'010 51'0-------------------------------------------------- -> 3'000 10'1000000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'1100000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'1011000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'010 10'1010000000 + transition: 3'010 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'1001000000 + transition: 3'010 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'1010000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'1100000000 + transition: 3'010 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'1100000000 + transition: 3'010 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'1111000000 + transition: 3'010 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'1100000000 + transition: 3'010 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'1100000000 + transition: 3'010 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'1111000000 + transition: 3'010 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'1110000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'1101000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-001--------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-000-01---------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-0-0-1----------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-0-10-------------------------------- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-10---------------------------------0-- -> 3'010 10'1010000000 + transition: 3'010 51'10----0----0-11---------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----0-1----------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----10-----------------------------------0-- -> 3'011 10'1011000000 + transition: 3'010 51'10----0----11-----------------------------------0-- -> 3'100 10'1100000000 + transition: 3'010 51'10----0----1------------------------------------1-- -> 3'100 10'1100000000 + transition: 3'010 51'10----100------------------------------------------ -> 3'010 10'1010000000 + transition: 3'010 51'10----10100---------------------------------------- -> 3'011 10'1011000000 + transition: 3'010 51'10----10101---------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----1011----------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'10----11------------------------------------------- -> 3'100 10'1100000000 + transition: 3'010 51'11------------------------------------------------- -> 3'000 10'1000000000 + transition: 3'110 51'0-------------------------------------------------- -> 3'000 10'0000010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'110 10'0110010000 + transition: 3'110 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001010000 + transition: 3'110 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100010000 + transition: 3'110 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100010000 + transition: 3'110 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111010000 + transition: 3'110 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100010000 + transition: 3'110 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100010000 + transition: 3'110 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111010000 + transition: 3'110 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-001--------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-000-01---------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-0-0-1----------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-0-10-------------------------------- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-10---------------------------------0-- -> 3'110 10'0110010000 + transition: 3'110 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----10-----------------------------------0-- -> 3'011 10'0011010000 + transition: 3'110 51'10----0----11-----------------------------------0-- -> 3'100 10'0100010000 + transition: 3'110 51'10----0----1------------------------------------1-- -> 3'100 10'0100010000 + transition: 3'110 51'10----100------------------------------------------ -> 3'110 10'0110010000 + transition: 3'110 51'10----10100---------------------------------------- -> 3'011 10'0011010000 + transition: 3'110 51'10----10101---------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----1011----------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'10----11------------------------------------------- -> 3'100 10'0100010000 + transition: 3'110 51'11------------------------------------------------- -> 3'000 10'0000010000 + transition: 3'001 51'0-------------------------------------------------- -> 3'000 10'0000000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000001 + transition: 3'001 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000001 + transition: 3'001 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000001 + transition: 3'001 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000001 + transition: 3'001 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000001 + transition: 3'001 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000001 + transition: 3'001 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000001 + transition: 3'001 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-001--------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-000-01---------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-0-0-1----------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-0-10-------------------------------- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-10---------------------------------0-- -> 3'001 10'0001000001 + transition: 3'001 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000001 + transition: 3'001 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000001 + transition: 3'001 51'10----0----1------------------------------------1-- -> 3'100 10'0100000001 + transition: 3'001 51'10----100------------------------------------------ -> 3'001 10'0001000001 + transition: 3'001 51'10----10100---------------------------------------- -> 3'011 10'0011000001 + transition: 3'001 51'10----10101---------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----1011----------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'10----11------------------------------------------- -> 3'100 10'0100000001 + transition: 3'001 51'11------------------------------------------------- -> 3'000 10'0000000001 + transition: 3'101 51'0-------------------------------------------------- -> 3'000 10'0000001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'101 10'0101001000 + transition: 3'101 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001001000 + transition: 3'101 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100001000 + transition: 3'101 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100001000 + transition: 3'101 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111001000 + transition: 3'101 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100001000 + transition: 3'101 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100001000 + transition: 3'101 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111001000 + transition: 3'101 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-001--------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-000-01---------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-0-0-1----------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-0-10-------------------------------- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-10---------------------------------0-- -> 3'101 10'0101001000 + transition: 3'101 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----10-----------------------------------0-- -> 3'011 10'0011001000 + transition: 3'101 51'10----0----11-----------------------------------0-- -> 3'100 10'0100001000 + transition: 3'101 51'10----0----1------------------------------------1-- -> 3'100 10'0100001000 + transition: 3'101 51'10----100------------------------------------------ -> 3'101 10'0101001000 + transition: 3'101 51'10----10100---------------------------------------- -> 3'011 10'0011001000 + transition: 3'101 51'10----10101---------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----1011----------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'10----11------------------------------------------- -> 3'100 10'0100001000 + transition: 3'101 51'11------------------------------------------------- -> 3'000 10'0000001000 + transition: 3'011 51'0-------------------------------------------------- -> 3'000 10'0000000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'011 10'0011000010 + transition: 3'011 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001000010 + transition: 3'011 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100000010 + transition: 3'011 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100000010 + transition: 3'011 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111000010 + transition: 3'011 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100000010 + transition: 3'011 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100000010 + transition: 3'011 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111000010 + transition: 3'011 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-001--------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-000-01---------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-0-0-1----------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-0-10-------------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-10---------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----10-----------------------------------0-- -> 3'011 10'0011000010 + transition: 3'011 51'10----0----11-----------------------------------0-- -> 3'100 10'0100000010 + transition: 3'011 51'10----0----1------------------------------------1-- -> 3'100 10'0100000010 + transition: 3'011 51'10----100------------------------------------------ -> 3'011 10'0011000010 + transition: 3'011 51'10----10100---------------------------------------- -> 3'011 10'0011000010 + transition: 3'011 51'10----10101---------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----1011----------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'10----11------------------------------------------- -> 3'100 10'0100000010 + transition: 3'011 51'11------------------------------------------------- -> 3'000 10'0000000010 + transition: 3'111 51'0-------------------------------------------------- -> 3'000 10'0000100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 3'100 10'0100100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 3'011 10'0011100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3'111 10'0111100000 + transition: 3'111 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 3'001 10'0001100000 + transition: 3'111 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 3'010 10'0010100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 3'100 10'0100100000 + transition: 3'111 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 3'100 10'0100100000 + transition: 3'111 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 3'111 10'0111100000 + transition: 3'111 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 3'100 10'0100100000 + transition: 3'111 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'100 10'0100100000 + transition: 3'111 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 3'111 10'0111100000 + transition: 3'111 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3'110 10'0110100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 3'101 10'0101100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-00010---------------------0--- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-0-0-0-00011---------------------0--- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-0001----------------------1--- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-001--------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-000-01---------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-010-01---------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-0-0-1----------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-0-10------------------------------ -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-0-0-11------------------------------ -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-0-10-------------------------------- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-0-0-11-------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-10-------------------------------0-- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----0-0-11-------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-0-1--------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-10---------------------------------0-- -> 3'111 10'0111100000 + transition: 3'111 51'10----0----0-11---------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----0-1----------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----10-----------------------------------0-- -> 3'011 10'0011100000 + transition: 3'111 51'10----0----11-----------------------------------0-- -> 3'100 10'0100100000 + transition: 3'111 51'10----0----1------------------------------------1-- -> 3'100 10'0100100000 + transition: 3'111 51'10----100------------------------------------------ -> 3'111 10'0111100000 + transition: 3'111 51'10----10100---------------------------------------- -> 3'011 10'0011100000 + transition: 3'111 51'10----10101---------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----1011----------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'10----11------------------------------------------- -> 3'100 10'0100100000 + transition: 3'111 51'11------------------------------------------------- -> 3'000 10'0000100000 + +26.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + Merging pattern 51'10----0----0-0-0-000-01---------------------------- and 51'10----0----0-0-0-010-01---------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-010-01---------------------------- and 51'10----0----0-0-0-000-01---------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-10-------------------------------- and 51'10----0----0-0-0-11-------------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-0-0-11-------------------------------- and 51'10----0----0-0-0-10-------------------------------- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-10---------------------------------0-- and 51'10----0----0-11---------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-11---------------------------------0-- and 51'10----0----0-10---------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-1----------------------------------0-- and 51'10----0----0-1----------------------------------1-- from group (1 1 10'0100000100). + Merging pattern 51'10----0----0-1----------------------------------1-- and 51'10----0----0-1----------------------------------0-- from group (1 1 10'0100000100). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----1--1-0---- from group (4 4 10'0001000001). + Merging pattern 51'10--000----0-0-0-0-0-0000-10-0------0----1--1-0---- and 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- from group (4 4 10'0001000001). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. + Merging pattern 10'-0-----000 and 10'-1-----000 from group (0 0 7'0100001). + Merging pattern 10'-1-----000 and 10'-0-----000 from group (0 0 7'0100001). + Merging pattern 10'-------000 and 10'-------100 from group (0 0 7'0100001). + Merging pattern 10'-------100 and 10'-------000 from group (0 0 7'0100001). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. + Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$89439. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. + Merging pattern 44'10000--00-00-000001000-0000--1000-----01-00- and 44'10000--00-00-000001000-0000--1001-----01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1001-----01-00- and 44'10000--00-00-000001000-0000--1000-----01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--100------01-00- and 44'10000--00-00-000001000-0000--101------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--101------01-00- and 44'10000--00-00-000001000-0000--100------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------00-00- and 44'10000--00-00-000001000-0000--10-------01-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------01-00- and 44'10000--00-00-000001000-0000--10-------00-00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--10-------0--00- and 44'10000--00-00-000001000-0000--11-------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--11-------0--00- and 44'10000--00-00-000001000-0000--10-------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0--00- and 44'10000--00-00-000001000-0000--1--------0--10- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0--10- and 44'10000--00-00-000001000-0000--1--------0--00- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0000--1--------0---0- and 44'10000--00-00-000001000-0100--1--------0---0- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0100--1--------0---0- and 44'10000--00-00-000001000-0000--1--------0---0- from group (1 1 15'010000000100000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0--00- and 44'10000--00-00-000001000-0-0100---------0--10- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0--10- and 44'10000--00-00-000001000-0-0100---------0--00- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0100---------0---0- and 44'10000--00-00-000001000-0-0101---------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-0101---------0---0- and 44'10000--00-00-000001000-0-0100---------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-010----------0---0- and 44'10000--00-00-000001000-0-011----------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-000001000-0-011----------0---0- and 44'10000--00-00-000001000-0-010----------0---0- from group (5 5 15'001101000000000). + Merging pattern 44'10000--00-00-00000100010-00--0---100000-0-0- and 44'10000--00-00-00000100010-00--0---101000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---101000-0-0- and 44'10000--00-00-00000100010-00--0---100000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---10-000-0-0- and 44'10000--00-00-00000100010-00--0---11-000-0-0- from group (6 6 15'000010000000100). + Merging pattern 44'10000--00-00-00000100010-00--0---11-000-0-0- and 44'10000--00-00-00000100010-00--0---10-000-0-0- from group (6 6 15'000010000000100). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. + Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$89433. + +26.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 215 unused cells and 216 unused wires. + + +26.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$0\state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\compute_state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [2]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$0\state[3:0] [3]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [0]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [1]. + Removing unused output signal $flatten\bridge.\g_packet.asic.\packet_core.$0\tx_external_kind[2:0] [2]. + +26.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ---1 + 010 -> --1- + 001 -> -1-- + 011 -> 1--- +Recoding FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> -------1 + 100 -> ------1- + 010 -> -----1-- + 110 -> ----1--- + 001 -> ---1---- + 101 -> --1----- + 011 -> -1------ + 111 -> 1------- + +26.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440 (\bridge.g_packet.asic.packet_core.adapter.datapath.state): + + Number of input signals: 13 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.adapter.core_rx_fire + 1: \bridge.g_packet.asic.packet_core.adapter.core_tx_fire + 2: \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.a_last + 3: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + 10: \bridge.g_packet.asic.packet_core.adapter.datapath.mul_tail_last + 11: \bridge.abort_q + 12: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4541_CMP + 1: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4529_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4523_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4511_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4498_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4492_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4473_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4449_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4448_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4445_CMP + 10: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 13'10----------0 -> 0 11'00010000000 + 1: 0 13'10--1-------1 -> 0 11'00010000000 + 2: 0 13'11----------- -> 0 11'00010000000 + 3: 0 13'0------------ -> 0 11'00010000000 + 4: 0 13'10----1-----1 -> 2 11'00010000000 + 5: 0 13'10--000000--1 -> 4 11'00010000000 + 6: 0 13'10-------1--1 -> 6 11'00010000000 + 7: 0 13'10---1------1 -> 7 11'00010000000 + 8: 0 13'10------1---1 -> 8 11'00010000000 + 9: 0 13'10-----1----1 -> 9 11'00010000000 + 10: 1 13'10--------11- -> 0 11'00000010000 + 11: 1 13'11----------- -> 0 11'00000010000 + 12: 1 13'0------------ -> 0 11'00000010000 + 13: 1 13'10---------0- -> 1 11'00000010000 + 14: 1 13'10--------01- -> 1 11'00000010000 + 15: 2 13'10--------11- -> 0 11'00001000000 + 16: 2 13'11----------- -> 0 11'00001000000 + 17: 2 13'0------------ -> 0 11'00001000000 + 18: 2 13'10--------10- -> 2 11'00001000000 + 19: 2 13'10--------0-- -> 2 11'00001000000 + 20: 3 13'10--------11- -> 0 11'00000000010 + 21: 3 13'11----------- -> 0 11'00000000010 + 22: 3 13'0------------ -> 0 11'00000000010 + 23: 3 13'10---------0- -> 3 11'00000000010 + 24: 3 13'10--------01- -> 6 11'00000000010 + 25: 4 13'10---------1- -> 0 11'00000000001 + 26: 4 13'11----------- -> 0 11'00000000001 + 27: 4 13'0------------ -> 0 11'00000000001 + 28: 4 13'10---------0- -> 4 11'00000000001 + 29: 5 13'11----------- -> 0 11'01000000000 + 30: 5 13'0------------ -> 0 11'01000000000 + 31: 5 13'10----------0 -> 5 11'01000000000 + 32: 5 13'10----------1 -> 10 11'01000000000 + 33: 6 13'11----------- -> 0 11'00100000000 + 34: 6 13'0------------ -> 0 11'00100000000 + 35: 6 13'10----------1 -> 3 11'00100000000 + 36: 6 13'10----------0 -> 6 11'00100000000 + 37: 7 13'10-1-------1- -> 0 11'00000100000 + 38: 7 13'11----------- -> 0 11'00000100000 + 39: 7 13'0------------ -> 0 11'00000100000 + 40: 7 13'10---------0- -> 7 11'00000100000 + 41: 7 13'10-0-------1- -> 7 11'00000100000 + 42: 8 13'11----------- -> 0 11'00000001000 + 43: 8 13'0------------ -> 0 11'00000001000 + 44: 8 13'10--------1-1 -> 5 11'00000001000 + 45: 8 13'10----------0 -> 8 11'00000001000 + 46: 8 13'10--------0-1 -> 8 11'00000001000 + 47: 9 13'10--------11- -> 0 11'00000000100 + 48: 9 13'11----------- -> 0 11'00000000100 + 49: 9 13'0------------ -> 0 11'00000000100 + 50: 9 13'10---------0- -> 9 11'00000000100 + 51: 9 13'10--------01- -> 9 11'00000000100 + 52: 10 13'11----------- -> 0 11'10000000000 + 53: 10 13'0------------ -> 0 11'10000000000 + 54: 10 13'101-------1-- -> 1 11'10000000000 + 55: 10 13'101-------0-- -> 5 11'10000000000 + 56: 10 13'100---------- -> 10 11'10000000000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.compute_state$89453 (\bridge.g_packet.asic.packet_core.compute_state): + + Number of input signals: 44 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.fault + 1: \bridge.g_packet.asic.packet_core.receiver.fault_valid + 2: \bridge.g_packet.asic.packet_core.cell_alias_check.alias_inconsistent + 3: \bridge.g_packet.asic.packet_core.request_validator.is_xor + 4: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16952_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4354_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:996$4352_Y + 7: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:989$4348_Y + 8: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:978$4342_Y + 9: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:976$4341_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:968$4331_Y + 11: $flatten\bridge.\g_packet.asic.\packet_core.$logic_not$../../asic_core/rtl/lsc1_packet_frontend.sv:928$4306_Y + 12: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4305_Y + 13: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301_Y + 14: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4288_Y + 15: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4283_Y + 16: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:884$4278_Y + 17: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:871$4270_Y + 18: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:854$4257_Y + 19: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4244_Y + 20: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + 21: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_ok[0:0] + 22: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + 23: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + 24: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + 25: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + 26: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + 27: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + 28: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + 29: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + 30: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + 31: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + 32: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + 33: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + 34: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + 35: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + 36: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + 37: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + 38: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + 39: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + 40: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + 41: \bridge.g_packet.asic.packet_core.request_reject + 42: \bridge.abort_q + 43: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3804_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3761_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3719_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3677_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3631_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3587_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3537_Y + 7: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3488_Y + 8: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3432_Y + 9: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3352_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:194$3176_Y + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 44'10--0--011---------------------------------0 -> 0 11'10000000000 + 1: 0 44'10--0--01----------------------------------1 -> 0 11'10000000000 + 2: 0 44'10000--00-00-000001000-0000--10-------00-00- -> 0 11'10000000000 + 3: 0 44'10000--00-00-000001000-0000--1001-----01-00- -> 0 11'10000000000 + 4: 0 44'10000--00-00-000001000-0000--101------01-00- -> 0 11'10000000000 + 5: 0 44'10000--00-00-000001000-0000--11-------0--00- -> 0 11'10000000000 + 6: 0 44'10000--00-00-000001000-0000--1--------0--10- -> 0 11'10000000000 + 7: 0 44'10000--00-00-000001000-0-0100---------0--10- -> 0 11'10000000000 + 8: 0 44'10000--00-00-00000100010-00--0---101000-0-0- -> 0 11'10000000000 + 9: 0 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 0 11'10000000000 + 10: 0 44'10000--00-00-00000100010-00--0---0--000---0- -> 0 11'10000000000 + 11: 0 44'10000--00-00-00000100000-00--0--------0---0- -> 0 11'10000000000 + 12: 0 44'10000--00-00-000001000-0100--1--------0---0- -> 0 11'10000000000 + 13: 0 44'10000--00-00-000001000-0-0101---------0---0- -> 0 11'10000000000 + 14: 0 44'10000--00-00-000001000-0-011----------0---0- -> 0 11'10000000000 + 15: 0 44'10000--00-00-000001000-0-1------------0---0- -> 0 11'10000000000 + 16: 0 44'10000--00-00-000001000-1--------------0---0- -> 0 11'10000000000 + 17: 0 44'10100--00-00-000001000--------------------0- -> 0 11'10000000000 + 18: 0 44'10-00--00-00-000001001--------------------0- -> 0 11'10000000000 + 19: 0 44'10-10--00-00-00000100---------------------0- -> 0 11'10000000000 + 20: 0 44'10--0--00-00-00000101---------------------0- -> 0 11'10000000000 + 21: 0 44'10--0--00-00-0000011----------------------0- -> 0 11'10000000000 + 22: 0 44'10--0--00-00-000001-----------------------1- -> 0 11'10000000000 + 23: 0 44'10--0--00-00-000000------------------------- -> 0 11'10000000000 + 24: 0 44'10--0--00-00-00001-------------------------- -> 0 11'10000000000 + 25: 0 44'10--0--00-001001---------------------------- -> 0 11'10000000000 + 26: 0 44'10--0--00-00-1------------------------------ -> 0 11'10000000000 + 27: 0 44'10--0--00-011------------------------------- -> 0 11'10000000000 + 28: 0 44'10--0--00-1--------------------------------- -> 0 11'10000000000 + 29: 0 44'10--0--1------------------------------------ -> 0 11'10000000000 + 30: 0 44'10--101------------------------------------- -> 0 11'10000000000 + 31: 0 44'10--11-------------------------------------- -> 0 11'10000000000 + 32: 0 44'11------------------------------------------ -> 0 11'10000000000 + 33: 0 44'0------------------------------------------- -> 0 11'10000000000 + 34: 0 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'10000000000 + 35: 0 44'10000--00-00-000001000----------------1---0- -> 2 11'10000000000 + 36: 0 44'10--0--00-000001---------------------------- -> 3 11'10000000000 + 37: 0 44'10--0--010---------------------------------0 -> 4 11'10000000000 + 38: 0 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'10000000000 + 39: 0 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'10000000000 + 40: 0 44'10--0--00-010------------------------------- -> 7 11'10000000000 + 41: 0 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'10000000000 + 42: 0 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'10000000000 + 43: 0 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'10000000000 + 44: 0 44'10--0--00-00-0001--------------------------- -> 9 11'10000000000 + 45: 0 44'10--0--00-00-01----------------------------- -> 9 11'10000000000 + 46: 0 44'10--100------------------------------------- -> 10 11'10000000000 + 47: 1 44'10--0--011---------------------------------0 -> 0 11'00000100000 + 48: 1 44'10--0--01----------------------------------1 -> 0 11'00000100000 + 49: 1 44'10--0--00-00-00001-------------------------- -> 0 11'00000100000 + 50: 1 44'10--0--00-001001---------------------------- -> 0 11'00000100000 + 51: 1 44'10--0--00-00-1------------------------------ -> 0 11'00000100000 + 52: 1 44'10--0--00-011------------------------------- -> 0 11'00000100000 + 53: 1 44'10--0--00-1--------------------------------- -> 0 11'00000100000 + 54: 1 44'10--0--1------------------------------------ -> 0 11'00000100000 + 55: 1 44'10--101------------------------------------- -> 0 11'00000100000 + 56: 1 44'10--11-------------------------------------- -> 0 11'00000100000 + 57: 1 44'11------------------------------------------ -> 0 11'00000100000 + 58: 1 44'0------------------------------------------- -> 0 11'00000100000 + 59: 1 44'10000--00-00-000001000-0-0100---------0--10- -> 1 11'00000100000 + 60: 1 44'10000--00-00-00000100010-00--0---101000-0-0- -> 1 11'00000100000 + 61: 1 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 1 11'00000100000 + 62: 1 44'10000--00-00-00000100010-00--0---0--000---0- -> 1 11'00000100000 + 63: 1 44'10000--00-00-00000100000-00--0--------0---0- -> 1 11'00000100000 + 64: 1 44'10000--00-00-000001000-0-00--1--------0---0- -> 1 11'00000100000 + 65: 1 44'10000--00-00-000001000-0-0101---------0---0- -> 1 11'00000100000 + 66: 1 44'10000--00-00-000001000-0-011----------0---0- -> 1 11'00000100000 + 67: 1 44'10000--00-00-000001000-0-1------------0---0- -> 1 11'00000100000 + 68: 1 44'10000--00-00-000001000-1--------------0---0- -> 1 11'00000100000 + 69: 1 44'10100--00-00-000001000--------------------0- -> 1 11'00000100000 + 70: 1 44'10-00--00-00-000001001--------------------0- -> 1 11'00000100000 + 71: 1 44'10-10--00-00-00000100---------------------0- -> 1 11'00000100000 + 72: 1 44'10--0--00-00-00000101---------------------0- -> 1 11'00000100000 + 73: 1 44'10--0--00-00-0000011----------------------0- -> 1 11'00000100000 + 74: 1 44'10--0--00-00-000001-----------------------1- -> 1 11'00000100000 + 75: 1 44'10--0--00-00-000000------------------------- -> 1 11'00000100000 + 76: 1 44'10000--00-00-000001000----------------1---0- -> 2 11'00000100000 + 77: 1 44'10--0--00-000001---------------------------- -> 3 11'00000100000 + 78: 1 44'10--0--010---------------------------------0 -> 4 11'00000100000 + 79: 1 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000100000 + 80: 1 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000100000 + 81: 1 44'10--0--00-010------------------------------- -> 7 11'00000100000 + 82: 1 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000100000 + 83: 1 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000100000 + 84: 1 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000100000 + 85: 1 44'10--0--00-00-0001--------------------------- -> 9 11'00000100000 + 86: 1 44'10--0--00-00-01----------------------------- -> 9 11'00000100000 + 87: 1 44'10--100------------------------------------- -> 10 11'00000100000 + 88: 2 44'10--0--011---------------------------------0 -> 0 11'00000010000 + 89: 2 44'10--0--01----------------------------------1 -> 0 11'00000010000 + 90: 2 44'10--0--00-00-00001-------------------------- -> 0 11'00000010000 + 91: 2 44'10--0--00-001001---------------------------- -> 0 11'00000010000 + 92: 2 44'10--0--00-00-1------------------------------ -> 0 11'00000010000 + 93: 2 44'10--0--00-011------------------------------- -> 0 11'00000010000 + 94: 2 44'10--0--00-1--------------------------------- -> 0 11'00000010000 + 95: 2 44'10--0--1------------------------------------ -> 0 11'00000010000 + 96: 2 44'10--101------------------------------------- -> 0 11'00000010000 + 97: 2 44'10--11-------------------------------------- -> 0 11'00000010000 + 98: 2 44'11------------------------------------------ -> 0 11'00000010000 + 99: 2 44'0------------------------------------------- -> 0 11'00000010000 + 100: 2 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000010000 + 101: 2 44'10000--00-00-000001000-0000--10-------00-00- -> 2 11'00000010000 + 102: 2 44'10000--00-00-000001000-0000--1001-----01-00- -> 2 11'00000010000 + 103: 2 44'10000--00-00-000001000-0000--101------01-00- -> 2 11'00000010000 + 104: 2 44'10000--00-00-000001000-0000--11-------0--00- -> 2 11'00000010000 + 105: 2 44'10000--00-00-000001000-0000--1--------0--10- -> 2 11'00000010000 + 106: 2 44'10000--00-00-000001000-0-0100---------0--10- -> 2 11'00000010000 + 107: 2 44'10000--00-00-00000100010-00--0---101000-0-0- -> 2 11'00000010000 + 108: 2 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 2 11'00000010000 + 109: 2 44'10000--00-00-00000100010-00--0---0--000---0- -> 2 11'00000010000 + 110: 2 44'10000--00-00-00000100000-00--0--------0---0- -> 2 11'00000010000 + 111: 2 44'10000--00-00-000001000-0100--1--------0---0- -> 2 11'00000010000 + 112: 2 44'10000--00-00-000001000-0-0101---------0---0- -> 2 11'00000010000 + 113: 2 44'10000--00-00-000001000-0-011----------0---0- -> 2 11'00000010000 + 114: 2 44'10000--00-00-000001000-0-1------------0---0- -> 2 11'00000010000 + 115: 2 44'10000--00-00-000001000-1--------------0---0- -> 2 11'00000010000 + 116: 2 44'10000--00-00-000001000----------------1---0- -> 2 11'00000010000 + 117: 2 44'10100--00-00-000001000--------------------0- -> 2 11'00000010000 + 118: 2 44'10-00--00-00-000001001--------------------0- -> 2 11'00000010000 + 119: 2 44'10-10--00-00-00000100---------------------0- -> 2 11'00000010000 + 120: 2 44'10--0--00-00-00000101---------------------0- -> 2 11'00000010000 + 121: 2 44'10--0--00-00-0000011----------------------0- -> 2 11'00000010000 + 122: 2 44'10--0--00-00-000001-----------------------1- -> 2 11'00000010000 + 123: 2 44'10--0--00-00-000000------------------------- -> 2 11'00000010000 + 124: 2 44'10--0--00-000001---------------------------- -> 3 11'00000010000 + 125: 2 44'10--0--010---------------------------------0 -> 4 11'00000010000 + 126: 2 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000010000 + 127: 2 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000010000 + 128: 2 44'10--0--00-010------------------------------- -> 7 11'00000010000 + 129: 2 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000010000 + 130: 2 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000010000 + 131: 2 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000010000 + 132: 2 44'10--0--00-00-0001--------------------------- -> 9 11'00000010000 + 133: 2 44'10--0--00-00-01----------------------------- -> 9 11'00000010000 + 134: 2 44'10--100------------------------------------- -> 10 11'00000010000 + 135: 3 44'10--0--011---------------------------------0 -> 0 11'00000000010 + 136: 3 44'10--0--01----------------------------------1 -> 0 11'00000000010 + 137: 3 44'10--0--00-00-00001-------------------------- -> 0 11'00000000010 + 138: 3 44'10--0--00-001001---------------------------- -> 0 11'00000000010 + 139: 3 44'10--0--00-00-1------------------------------ -> 0 11'00000000010 + 140: 3 44'10--0--00-011------------------------------- -> 0 11'00000000010 + 141: 3 44'10--0--00-1--------------------------------- -> 0 11'00000000010 + 142: 3 44'10--0--1------------------------------------ -> 0 11'00000000010 + 143: 3 44'10--101------------------------------------- -> 0 11'00000000010 + 144: 3 44'10--11-------------------------------------- -> 0 11'00000000010 + 145: 3 44'11------------------------------------------ -> 0 11'00000000010 + 146: 3 44'0------------------------------------------- -> 0 11'00000000010 + 147: 3 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000000010 + 148: 3 44'10000--00-00-000001000----------------1---0- -> 2 11'00000000010 + 149: 3 44'10000--00-00-000001000-0000--10-------00-00- -> 3 11'00000000010 + 150: 3 44'10000--00-00-000001000-0000--1001-----01-00- -> 3 11'00000000010 + 151: 3 44'10000--00-00-000001000-0000--101------01-00- -> 3 11'00000000010 + 152: 3 44'10000--00-00-000001000-0000--11-------0--00- -> 3 11'00000000010 + 153: 3 44'10000--00-00-000001000-0000--1--------0--10- -> 3 11'00000000010 + 154: 3 44'10000--00-00-000001000-0-0100---------0--10- -> 3 11'00000000010 + 155: 3 44'10000--00-00-00000100010-00--0---101000-0-0- -> 3 11'00000000010 + 156: 3 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 3 11'00000000010 + 157: 3 44'10000--00-00-00000100010-00--0---0--000---0- -> 3 11'00000000010 + 158: 3 44'10000--00-00-00000100000-00--0--------0---0- -> 3 11'00000000010 + 159: 3 44'10000--00-00-000001000-0100--1--------0---0- -> 3 11'00000000010 + 160: 3 44'10000--00-00-000001000-0-0101---------0---0- -> 3 11'00000000010 + 161: 3 44'10000--00-00-000001000-0-011----------0---0- -> 3 11'00000000010 + 162: 3 44'10000--00-00-000001000-0-1------------0---0- -> 3 11'00000000010 + 163: 3 44'10000--00-00-000001000-1--------------0---0- -> 3 11'00000000010 + 164: 3 44'10100--00-00-000001000--------------------0- -> 3 11'00000000010 + 165: 3 44'10-00--00-00-000001001--------------------0- -> 3 11'00000000010 + 166: 3 44'10-10--00-00-00000100---------------------0- -> 3 11'00000000010 + 167: 3 44'10--0--00-00-00000101---------------------0- -> 3 11'00000000010 + 168: 3 44'10--0--00-00-0000011----------------------0- -> 3 11'00000000010 + 169: 3 44'10--0--00-00-000001-----------------------1- -> 3 11'00000000010 + 170: 3 44'10--0--00-00-000000------------------------- -> 3 11'00000000010 + 171: 3 44'10--0--00-000001---------------------------- -> 3 11'00000000010 + 172: 3 44'10--0--010---------------------------------0 -> 4 11'00000000010 + 173: 3 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000000010 + 174: 3 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000000010 + 175: 3 44'10--0--00-010------------------------------- -> 7 11'00000000010 + 176: 3 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000010 + 177: 3 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000010 + 178: 3 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000010 + 179: 3 44'10--0--00-00-0001--------------------------- -> 9 11'00000000010 + 180: 3 44'10--0--00-00-01----------------------------- -> 9 11'00000000010 + 181: 3 44'10--100------------------------------------- -> 10 11'00000000010 + 182: 4 44'10--0--011---------------------------------0 -> 0 11'00001000000 + 183: 4 44'10--0--01----------------------------------1 -> 0 11'00001000000 + 184: 4 44'10--0--00-00-00001-------------------------- -> 0 11'00001000000 + 185: 4 44'10--0--00-001001---------------------------- -> 0 11'00001000000 + 186: 4 44'10--0--00-00-1------------------------------ -> 0 11'00001000000 + 187: 4 44'10--0--00-011------------------------------- -> 0 11'00001000000 + 188: 4 44'10--0--00-1--------------------------------- -> 0 11'00001000000 + 189: 4 44'10--0--1------------------------------------ -> 0 11'00001000000 + 190: 4 44'10--101------------------------------------- -> 0 11'00001000000 + 191: 4 44'10--11-------------------------------------- -> 0 11'00001000000 + 192: 4 44'11------------------------------------------ -> 0 11'00001000000 + 193: 4 44'0------------------------------------------- -> 0 11'00001000000 + 194: 4 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00001000000 + 195: 4 44'10000--00-00-000001000----------------1---0- -> 2 11'00001000000 + 196: 4 44'10--0--00-000001---------------------------- -> 3 11'00001000000 + 197: 4 44'10--0--010---------------------------------0 -> 4 11'00001000000 + 198: 4 44'10000--00-00-000001000-0000--10-------00-00- -> 4 11'00001000000 + 199: 4 44'10000--00-00-000001000-0000--1001-----01-00- -> 4 11'00001000000 + 200: 4 44'10000--00-00-000001000-0000--101------01-00- -> 4 11'00001000000 + 201: 4 44'10000--00-00-000001000-0000--11-------0--00- -> 4 11'00001000000 + 202: 4 44'10000--00-00-000001000-0000--1--------0--10- -> 4 11'00001000000 + 203: 4 44'10000--00-00-000001000-0-0100---------0--10- -> 4 11'00001000000 + 204: 4 44'10000--00-00-00000100010-00--0---101000-0-0- -> 4 11'00001000000 + 205: 4 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 4 11'00001000000 + 206: 4 44'10000--00-00-00000100010-00--0---0--000---0- -> 4 11'00001000000 + 207: 4 44'10000--00-00-00000100000-00--0--------0---0- -> 4 11'00001000000 + 208: 4 44'10000--00-00-000001000-0100--1--------0---0- -> 4 11'00001000000 + 209: 4 44'10000--00-00-000001000-0-0101---------0---0- -> 4 11'00001000000 + 210: 4 44'10000--00-00-000001000-0-011----------0---0- -> 4 11'00001000000 + 211: 4 44'10000--00-00-000001000-0-1------------0---0- -> 4 11'00001000000 + 212: 4 44'10000--00-00-000001000-1--------------0---0- -> 4 11'00001000000 + 213: 4 44'10100--00-00-000001000--------------------0- -> 4 11'00001000000 + 214: 4 44'10-00--00-00-000001001--------------------0- -> 4 11'00001000000 + 215: 4 44'10-10--00-00-00000100---------------------0- -> 4 11'00001000000 + 216: 4 44'10--0--00-00-00000101---------------------0- -> 4 11'00001000000 + 217: 4 44'10--0--00-00-0000011----------------------0- -> 4 11'00001000000 + 218: 4 44'10--0--00-00-000001-----------------------1- -> 4 11'00001000000 + 219: 4 44'10--0--00-00-000000------------------------- -> 4 11'00001000000 + 220: 4 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00001000000 + 221: 4 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00001000000 + 222: 4 44'10--0--00-010------------------------------- -> 7 11'00001000000 + 223: 4 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00001000000 + 224: 4 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00001000000 + 225: 4 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00001000000 + 226: 4 44'10--0--00-00-0001--------------------------- -> 9 11'00001000000 + 227: 4 44'10--0--00-00-01----------------------------- -> 9 11'00001000000 + 228: 4 44'10--100------------------------------------- -> 10 11'00001000000 + 229: 5 44'10--0--011---------------------------------0 -> 0 11'01000000000 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11'00000000100 + 295: 6 44'10000--00-00-000001000-0-0100---------0--10- -> 6 11'00000000100 + 296: 6 44'10000--00-00-00000100010-00--0---1--000-0-0- -> 6 11'00000000100 + 297: 6 44'10000--00-00-00000100010-00--0---0--000---0- -> 6 11'00000000100 + 298: 6 44'10000--00-00-00000100000-00--0--------0---0- -> 6 11'00000000100 + 299: 6 44'10000--00-00-000001000-0100--1--------0---0- -> 6 11'00000000100 + 300: 6 44'10000--00-00-000001000-0-0101---------0---0- -> 6 11'00000000100 + 301: 6 44'10000--00-00-000001000-0-011----------0---0- -> 6 11'00000000100 + 302: 6 44'10000--00-00-000001000-0-1------------0---0- -> 6 11'00000000100 + 303: 6 44'10000--00-00-000001000-1--------------0---0- -> 6 11'00000000100 + 304: 6 44'10100--00-00-000001000--------------------0- -> 6 11'00000000100 + 305: 6 44'10-00--00-00-000001001--------------------0- -> 6 11'00000000100 + 306: 6 44'10-10--00-00-00000100---------------------0- -> 6 11'00000000100 + 307: 6 44'10--0--00-00-00000101---------------------0- -> 6 11'00000000100 + 308: 6 44'10--0--00-00-0000011----------------------0- -> 6 11'00000000100 + 309: 6 44'10--0--00-00-000001-----------------------1- -> 6 11'00000000100 + 310: 6 44'10--0--00-00-000000------------------------- -> 6 11'00000000100 + 311: 6 44'10--0--00-010------------------------------- -> 7 11'00000000100 + 312: 6 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000100 + 313: 6 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000100 + 314: 6 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000100 + 315: 6 44'10--0--00-00-0001--------------------------- -> 9 11'00000000100 + 316: 6 44'10--0--00-00-01----------------------------- -> 9 11'00000000100 + 317: 6 44'10--100------------------------------------- -> 10 11'00000000100 + 318: 7 44'10--0--011---------------------------------0 -> 0 11'00010000000 + 319: 7 44'10--0--01----------------------------------1 -> 0 11'00010000000 + 320: 7 44'10--0--00-00-00001-------------------------- -> 0 11'00010000000 + 321: 7 44'10--0--00-001001---------------------------- -> 0 11'00010000000 + 322: 7 44'10--0--00-00-1------------------------------ -> 0 11'00010000000 + 323: 7 44'10--0--00-011------------------------------- -> 0 11'00010000000 + 324: 7 44'10--0--00-1--------------------------------- -> 0 11'00010000000 + 325: 7 44'10--0--1------------------------------------ -> 0 11'00010000000 + 326: 7 44'10--101------------------------------------- -> 0 11'00010000000 + 327: 7 44'10--11-------------------------------------- -> 0 11'00010000000 + 328: 7 44'11------------------------------------------ -> 0 11'00010000000 + 329: 7 44'0------------------------------------------- -> 0 11'00010000000 + 330: 7 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00010000000 + 331: 7 44'10000--00-00-000001000----------------1---0- -> 2 11'00010000000 + 332: 7 44'10--0--00-000001---------------------------- -> 3 11'00010000000 + 333: 7 44'10--0--010---------------------------------0 -> 4 11'00010000000 + 334: 7 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00010000000 + 335: 7 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00010000000 + 336: 7 44'10000--00-00-000001000-0000--10-------00-00- -> 7 11'00010000000 + 337: 7 44'10000--00-00-000001000-0000--1001-----01-00- -> 7 11'00010000000 + 338: 7 44'10000--00-00-000001000-0000--101------01-00- -> 7 11'00010000000 + 339: 7 44'10000--00-00-000001000-0000--11-------0--00- -> 7 11'00010000000 + 340: 7 44'10000--00-00-000001000-0000--1--------0--10- -> 7 11'00010000000 + 341: 7 44'10000--00-00-000001000-0-0100---------0--10- -> 7 11'00010000000 + 342: 7 44'10000--00-00-00000100010-00--0---101000-0-0- -> 7 11'00010000000 + 343: 7 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 7 11'00010000000 + 344: 7 44'10000--00-00-00000100010-00--0---0--000---0- -> 7 11'00010000000 + 345: 7 44'10000--00-00-00000100000-00--0--------0---0- -> 7 11'00010000000 + 346: 7 44'10000--00-00-000001000-0100--1--------0---0- -> 7 11'00010000000 + 347: 7 44'10000--00-00-000001000-0-0101---------0---0- -> 7 11'00010000000 + 348: 7 44'10000--00-00-000001000-0-011----------0---0- -> 7 11'00010000000 + 349: 7 44'10000--00-00-000001000-0-1------------0---0- -> 7 11'00010000000 + 350: 7 44'10000--00-00-000001000-1--------------0---0- -> 7 11'00010000000 + 351: 7 44'10100--00-00-000001000--------------------0- -> 7 11'00010000000 + 352: 7 44'10-00--00-00-000001001--------------------0- -> 7 11'00010000000 + 353: 7 44'10-10--00-00-00000100---------------------0- -> 7 11'00010000000 + 354: 7 44'10--0--00-00-00000101---------------------0- -> 7 11'00010000000 + 355: 7 44'10--0--00-00-0000011----------------------0- -> 7 11'00010000000 + 356: 7 44'10--0--00-00-000001-----------------------1- -> 7 11'00010000000 + 357: 7 44'10--0--00-00-000000------------------------- -> 7 11'00010000000 + 358: 7 44'10--0--00-010------------------------------- -> 7 11'00010000000 + 359: 7 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00010000000 + 360: 7 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00010000000 + 361: 7 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00010000000 + 362: 7 44'10--0--00-00-0001--------------------------- -> 9 11'00010000000 + 363: 7 44'10--0--00-00-01----------------------------- -> 9 11'00010000000 + 364: 7 44'10--100------------------------------------- -> 10 11'00010000000 + 365: 8 44'10--0--011---------------------------------0 -> 0 11'00000001000 + 366: 8 44'10--0--01----------------------------------1 -> 0 11'00000001000 + 367: 8 44'10--0--00-00-00001-------------------------- -> 0 11'00000001000 + 368: 8 44'10--0--00-001001---------------------------- -> 0 11'00000001000 + 369: 8 44'10--0--00-00-1------------------------------ -> 0 11'00000001000 + 370: 8 44'10--0--00-011------------------------------- -> 0 11'00000001000 + 371: 8 44'10--0--00-1--------------------------------- -> 0 11'00000001000 + 372: 8 44'10--0--1------------------------------------ -> 0 11'00000001000 + 373: 8 44'10--101------------------------------------- -> 0 11'00000001000 + 374: 8 44'10--11-------------------------------------- -> 0 11'00000001000 + 375: 8 44'11------------------------------------------ -> 0 11'00000001000 + 376: 8 44'0------------------------------------------- -> 0 11'00000001000 + 377: 8 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000001000 + 378: 8 44'10000--00-00-000001000----------------1---0- -> 2 11'00000001000 + 379: 8 44'10--0--00-000001---------------------------- -> 3 11'00000001000 + 380: 8 44'10--0--010---------------------------------0 -> 4 11'00000001000 + 381: 8 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000001000 + 382: 8 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000001000 + 383: 8 44'10--0--00-010------------------------------- -> 7 11'00000001000 + 384: 8 44'10000--00-00-000001000-0000--10-------00-00- -> 8 11'00000001000 + 385: 8 44'10000--00-00-000001000-0000--1001-----01-00- -> 8 11'00000001000 + 386: 8 44'10000--00-00-000001000-0000--101------01-00- -> 8 11'00000001000 + 387: 8 44'10000--00-00-000001000-0000--11-------0--00- -> 8 11'00000001000 + 388: 8 44'10000--00-00-000001000-0000--1--------0--10- -> 8 11'00000001000 + 389: 8 44'10000--00-00-000001000-0-0100---------0--10- -> 8 11'00000001000 + 390: 8 44'10000--00-00-00000100010-00--0---101000-0-0- -> 8 11'00000001000 + 391: 8 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 8 11'00000001000 + 392: 8 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000001000 + 393: 8 44'10000--00-00-00000100010-00--0---0--000---0- -> 8 11'00000001000 + 394: 8 44'10000--00-00-00000100000-00--0--------0---0- -> 8 11'00000001000 + 395: 8 44'10000--00-00-000001000-0100--1--------0---0- -> 8 11'00000001000 + 396: 8 44'10000--00-00-000001000-0-0101---------0---0- -> 8 11'00000001000 + 397: 8 44'10000--00-00-000001000-0-011----------0---0- -> 8 11'00000001000 + 398: 8 44'10000--00-00-000001000-0-1------------0---0- -> 8 11'00000001000 + 399: 8 44'10000--00-00-000001000-1--------------0---0- -> 8 11'00000001000 + 400: 8 44'10100--00-00-000001000--------------------0- -> 8 11'00000001000 + 401: 8 44'10-00--00-00-000001001--------------------0- -> 8 11'00000001000 + 402: 8 44'10-10--00-00-00000100---------------------0- -> 8 11'00000001000 + 403: 8 44'10--0--00-00-00000101---------------------0- -> 8 11'00000001000 + 404: 8 44'10--0--00-00-0000011----------------------0- -> 8 11'00000001000 + 405: 8 44'10--0--00-00-000001-----------------------1- -> 8 11'00000001000 + 406: 8 44'10--0--00-00-000000------------------------- -> 8 11'00000001000 + 407: 8 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000001000 + 408: 8 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000001000 + 409: 8 44'10--0--00-00-0001--------------------------- -> 9 11'00000001000 + 410: 8 44'10--0--00-00-01----------------------------- -> 9 11'00000001000 + 411: 8 44'10--100------------------------------------- -> 10 11'00000001000 + 412: 9 44'10--0--011---------------------------------0 -> 0 11'00000000001 + 413: 9 44'10--0--01----------------------------------1 -> 0 11'00000000001 + 414: 9 44'10--0--00-00-00001-------------------------- -> 0 11'00000000001 + 415: 9 44'10--0--00-001001---------------------------- -> 0 11'00000000001 + 416: 9 44'10--0--00-00-1------------------------------ -> 0 11'00000000001 + 417: 9 44'10--0--00-011------------------------------- -> 0 11'00000000001 + 418: 9 44'10--0--00-1--------------------------------- -> 0 11'00000000001 + 419: 9 44'10--0--1------------------------------------ -> 0 11'00000000001 + 420: 9 44'10--101------------------------------------- -> 0 11'00000000001 + 421: 9 44'10--11-------------------------------------- -> 0 11'00000000001 + 422: 9 44'11------------------------------------------ -> 0 11'00000000001 + 423: 9 44'0------------------------------------------- -> 0 11'00000000001 + 424: 9 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00000000001 + 425: 9 44'10000--00-00-000001000----------------1---0- -> 2 11'00000000001 + 426: 9 44'10--0--00-000001---------------------------- -> 3 11'00000000001 + 427: 9 44'10--0--010---------------------------------0 -> 4 11'00000000001 + 428: 9 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00000000001 + 429: 9 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00000000001 + 430: 9 44'10--0--00-010------------------------------- -> 7 11'00000000001 + 431: 9 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00000000001 + 432: 9 44'10000--00-00-000001000-0000--10-------00-00- -> 9 11'00000000001 + 433: 9 44'10000--00-00-000001000-0000--1001-----01-00- -> 9 11'00000000001 + 434: 9 44'10000--00-00-000001000-0000--101------01-00- -> 9 11'00000000001 + 435: 9 44'10000--00-00-000001000-0000--11-------0--00- -> 9 11'00000000001 + 436: 9 44'10000--00-00-000001000-0000--1--------0--10- -> 9 11'00000000001 + 437: 9 44'10000--00-00-000001000-0-0100---------0--10- -> 9 11'00000000001 + 438: 9 44'10000--00-00-00000100010-00--0---101000-0-0- -> 9 11'00000000001 + 439: 9 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 9 11'00000000001 + 440: 9 44'10000--00-00-00000100010-00--0---0--000---0- -> 9 11'00000000001 + 441: 9 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00000000001 + 442: 9 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00000000001 + 443: 9 44'10000--00-00-00000100000-00--0--------0---0- -> 9 11'00000000001 + 444: 9 44'10000--00-00-000001000-0100--1--------0---0- -> 9 11'00000000001 + 445: 9 44'10000--00-00-000001000-0-0101---------0---0- -> 9 11'00000000001 + 446: 9 44'10000--00-00-000001000-0-011----------0---0- -> 9 11'00000000001 + 447: 9 44'10000--00-00-000001000-0-1------------0---0- -> 9 11'00000000001 + 448: 9 44'10000--00-00-000001000-1--------------0---0- -> 9 11'00000000001 + 449: 9 44'10100--00-00-000001000--------------------0- -> 9 11'00000000001 + 450: 9 44'10-00--00-00-000001001--------------------0- -> 9 11'00000000001 + 451: 9 44'10-10--00-00-00000100---------------------0- -> 9 11'00000000001 + 452: 9 44'10--0--00-00-00000101---------------------0- -> 9 11'00000000001 + 453: 9 44'10--0--00-00-0000011----------------------0- -> 9 11'00000000001 + 454: 9 44'10--0--00-00-000001-----------------------1- -> 9 11'00000000001 + 455: 9 44'10--0--00-00-000000------------------------- -> 9 11'00000000001 + 456: 9 44'10--0--00-00-0001--------------------------- -> 9 11'00000000001 + 457: 9 44'10--0--00-00-01----------------------------- -> 9 11'00000000001 + 458: 9 44'10--100------------------------------------- -> 10 11'00000000001 + 459: 10 44'10--0--011---------------------------------0 -> 0 11'00100000000 + 460: 10 44'10--0--01----------------------------------1 -> 0 11'00100000000 + 461: 10 44'10--0--00-00-00001-------------------------- -> 0 11'00100000000 + 462: 10 44'10--0--00-001001---------------------------- -> 0 11'00100000000 + 463: 10 44'10--0--00-00-1------------------------------ -> 0 11'00100000000 + 464: 10 44'10--0--00-011------------------------------- -> 0 11'00100000000 + 465: 10 44'10--0--00-1--------------------------------- -> 0 11'00100000000 + 466: 10 44'10--0--1------------------------------------ -> 0 11'00100000000 + 467: 10 44'10--101------------------------------------- -> 0 11'00100000000 + 468: 10 44'10--11-------------------------------------- -> 0 11'00100000000 + 469: 10 44'11------------------------------------------ -> 0 11'00100000000 + 470: 10 44'0------------------------------------------- -> 0 11'00100000000 + 471: 10 44'10000--00-00-000001000-0000--1000-----01-00- -> 1 11'00100000000 + 472: 10 44'10000--00-00-000001000----------------1---0- -> 2 11'00100000000 + 473: 10 44'10--0--00-000001---------------------------- -> 3 11'00100000000 + 474: 10 44'10--0--010---------------------------------0 -> 4 11'00100000000 + 475: 10 44'10000--00-00-000001000-0-0100---------0--00- -> 5 11'00100000000 + 476: 10 44'10000--00-00-00000100010-00--0---100000-0-0- -> 6 11'00100000000 + 477: 10 44'10--0--00-010------------------------------- -> 7 11'00100000000 + 478: 10 44'10000--00-00-00000100010-00--0---1--000-1-0- -> 8 11'00100000000 + 479: 10 44'10000--00-00-00000100010-00--0------010---0- -> 9 11'00100000000 + 480: 10 44'10000--00-00-00000100010-00--0------1-0---0- -> 9 11'00100000000 + 481: 10 44'10--0--00-00-0001--------------------------- -> 9 11'00100000000 + 482: 10 44'10--0--00-00-01----------------------------- -> 9 11'00100000000 + 483: 10 44'10000--00-00-000001000-0000--10-------00-00- -> 10 11'00100000000 + 484: 10 44'10000--00-00-000001000-0000--1001-----01-00- -> 10 11'00100000000 + 485: 10 44'10000--00-00-000001000-0000--101------01-00- -> 10 11'00100000000 + 486: 10 44'10000--00-00-000001000-0000--11-------0--00- -> 10 11'00100000000 + 487: 10 44'10000--00-00-000001000-0000--1--------0--10- -> 10 11'00100000000 + 488: 10 44'10000--00-00-000001000-0-0100---------0--10- -> 10 11'00100000000 + 489: 10 44'10000--00-00-00000100010-00--0---101000-0-0- -> 10 11'00100000000 + 490: 10 44'10000--00-00-00000100010-00--0---11-000-0-0- -> 10 11'00100000000 + 491: 10 44'10000--00-00-00000100010-00--0---0--000---0- -> 10 11'00100000000 + 492: 10 44'10000--00-00-00000100000-00--0--------0---0- -> 10 11'00100000000 + 493: 10 44'10000--00-00-000001000-0100--1--------0---0- -> 10 11'00100000000 + 494: 10 44'10000--00-00-000001000-0-0101---------0---0- -> 10 11'00100000000 + 495: 10 44'10000--00-00-000001000-0-011----------0---0- -> 10 11'00100000000 + 496: 10 44'10000--00-00-000001000-0-1------------0---0- -> 10 11'00100000000 + 497: 10 44'10000--00-00-000001000-1--------------0---0- -> 10 11'00100000000 + 498: 10 44'10100--00-00-000001000--------------------0- -> 10 11'00100000000 + 499: 10 44'10-00--00-00-000001001--------------------0- -> 10 11'00100000000 + 500: 10 44'10-10--00-00-00000100---------------------0- -> 10 11'00100000000 + 501: 10 44'10--0--00-00-00000101---------------------0- -> 10 11'00100000000 + 502: 10 44'10--0--00-00-0000011----------------------0- -> 10 11'00100000000 + 503: 10 44'10--0--00-00-000001-----------------------1- -> 10 11'00100000000 + 504: 10 44'10--0--00-00-000000------------------------- -> 10 11'00100000000 + 505: 10 44'10--100------------------------------------- -> 10 11'00100000000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466 (\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state): + + Number of input signals: 13 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.mul_tail_last + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP + 8: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.a_last + 9: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + 10: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + 11: \bridge.abort_q + 12: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$2860_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4445_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4448_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4449_CMP + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4473_CMP + 5: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4492_CMP + 6: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4498_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4511_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4523_CMP + 9: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4529_CMP + 10: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4541_CMP + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 13'101-------1-- -> 0 11'00000001000 + 1: 0 13'100---------- -> 0 11'00000001000 + 2: 0 13'11----------- -> 0 11'00000001000 + 3: 0 13'0------------ -> 0 11'00000001000 + 4: 0 13'101-----1---- -> 2 11'00000001000 + 5: 0 13'101--000000-- -> 4 11'00000001000 + 6: 0 13'101--1------- -> 6 11'00000001000 + 7: 0 13'101------1--- -> 7 11'00000001000 + 8: 0 13'101---1------ -> 8 11'00000001000 + 9: 0 13'101----1----- -> 9 11'00000001000 + 10: 1 13'10-11-------- -> 0 11'00001000000 + 11: 1 13'11----------- -> 0 11'00001000000 + 12: 1 13'0------------ -> 0 11'00001000000 + 13: 1 13'10-10-------- -> 1 11'00001000000 + 14: 1 13'10-0--------- -> 1 11'00001000000 + 15: 2 13'10-11-------- -> 0 11'00000010000 + 16: 2 13'11----------- -> 0 11'00000010000 + 17: 2 13'0------------ -> 0 11'00000010000 + 18: 2 13'10--0-------- -> 2 11'00000010000 + 19: 2 13'10-01-------- -> 2 11'00000010000 + 20: 3 13'10-11-------- -> 0 11'01000000000 + 21: 3 13'11----------- -> 0 11'01000000000 + 22: 3 13'0------------ -> 0 11'01000000000 + 23: 3 13'10-0--------- -> 3 11'01000000000 + 24: 3 13'10-10-------- -> 6 11'01000000000 + 25: 4 13'10-1--------- -> 0 11'10000000000 + 26: 4 13'11----------- -> 0 11'10000000000 + 27: 4 13'0------------ -> 0 11'10000000000 + 28: 4 13'10-0--------- -> 4 11'10000000000 + 29: 5 13'11----------- -> 0 11'00000000010 + 30: 5 13'0------------ -> 0 11'00000000010 + 31: 5 13'100---------- -> 5 11'00000000010 + 32: 5 13'101---------- -> 10 11'00000000010 + 33: 6 13'11----------- -> 0 11'00000000100 + 34: 6 13'0------------ -> 0 11'00000000100 + 35: 6 13'101---------- -> 3 11'00000000100 + 36: 6 13'100---------- -> 6 11'00000000100 + 37: 7 13'10-1-------1- -> 0 11'00000100000 + 38: 7 13'11----------- -> 0 11'00000100000 + 39: 7 13'0------------ -> 0 11'00000100000 + 40: 7 13'10-1-------0- -> 7 11'00000100000 + 41: 7 13'10-0--------- -> 7 11'00000100000 + 42: 8 13'11----------- -> 0 11'00010000000 + 43: 8 13'0------------ -> 0 11'00010000000 + 44: 8 13'101-1-------- -> 5 11'00010000000 + 45: 8 13'101-0-------- -> 8 11'00010000000 + 46: 8 13'100---------- -> 8 11'00010000000 + 47: 9 13'10-11-------- -> 0 11'00100000000 + 48: 9 13'11----------- -> 0 11'00100000000 + 49: 9 13'0------------ -> 0 11'00100000000 + 50: 9 13'10-10-------- -> 9 11'00100000000 + 51: 9 13'10-0--------- -> 9 11'00100000000 + 52: 10 13'11----------- -> 0 11'00000000001 + 53: 10 13'0------------ -> 0 11'00000000001 + 54: 10 13'10--1-------1 -> 1 11'00000000001 + 55: 10 13'10--0-------1 -> 5 11'00000000001 + 56: 10 13'10----------0 -> 10 11'00000000001 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479 (\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state): + + Number of input signals: 8 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.field_encoder.multiply_start + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$logic_or$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2094_Y + 4: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_tx_fire + 5: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.core_rx_fire + 6: \bridge.abort_q + 7: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7609_CMP + 1: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:103$2056_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002_Y + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 8'10-----0 -> 0 5'00001 + 1: 0 8'11------ -> 0 5'00001 + 2: 0 8'0------- -> 0 5'00001 + 3: 0 8'10-----1 -> 3 5'00001 + 4: 1 8'10-1--1- -> 0 5'00010 + 5: 1 8'11------ -> 0 5'00010 + 6: 1 8'0------- -> 0 5'00010 + 7: 1 8'10-1--0- -> 1 5'00010 + 8: 1 8'10-0---- -> 1 5'00010 + 9: 2 8'11------ -> 0 5'00100 + 10: 2 8'0------- -> 0 5'00100 + 11: 2 8'100----- -> 2 5'00100 + 12: 2 8'101----- -> 4 5'00100 + 13: 3 8'11------ -> 0 5'01000 + 14: 3 8'0------- -> 0 5'01000 + 15: 3 8'101----- -> 2 5'01000 + 16: 3 8'100----- -> 3 5'01000 + 17: 4 8'101-10-- -> 0 5'10000 + 18: 4 8'11------ -> 0 5'10000 + 19: 4 8'0------- -> 0 5'10000 + 20: 4 8'101-11-- -> 1 5'10000 + 21: 4 8'101-0--- -> 4 5'10000 + 22: 4 8'100----- -> 4 5'10000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486 (\bridge.g_packet.asic.packet_core.receiver.state): + + Number of input signals: 10 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$logic_or$../../asic_core/rtl/lsc1_field_encoder.sv:39$2121_Y + 1: \bridge.g_packet.asic.packet_core.receiver.rx_fire + 2: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$logic_and$../../asic_core/rtl/lsc1_packet_rx.sv:91$1557_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:102$1586_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11999_CMP + 7: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP + 8: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:264$3197_Y + 9: $auto$opt_reduce.cc:134:opt_pmux$89425 + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:58$1519_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10007_CMP + 2: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10008_CMP + 3: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12001_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 10'--------00 -> 0 4'0101 + 1: 0 10'---------1 -> 0 4'0101 + 2: 0 10'------0-10 -> 2 4'0101 + 3: 0 10'------1-10 -> 3 4'0101 + 4: 1 10'-1-----000 -> 0 4'0011 + 5: 1 10'-------100 -> 0 4'0011 + 6: 1 10'-10-0--010 -> 0 4'0011 + 7: 1 10'-1--1--010 -> 0 4'0011 + 8: 1 10'--0-0--110 -> 0 4'0011 + 9: 1 10'----1--110 -> 0 4'0011 + 10: 1 10'---------1 -> 0 4'0011 + 11: 1 10'-0-----000 -> 1 4'0011 + 12: 1 10'-00-0--010 -> 1 4'0011 + 13: 1 10'-0--1--010 -> 1 4'0011 + 14: 1 10'--1-0---10 -> 3 4'0011 + 15: 2 10'-1-----000 -> 0 4'1001 + 16: 2 10'-------100 -> 0 4'1001 + 17: 2 10'11-----010 -> 0 4'1001 + 18: 2 10'1------110 -> 0 4'1001 + 19: 2 10'0--0----10 -> 0 4'1001 + 20: 2 10'---------1 -> 0 4'1001 + 21: 2 10'---1-0--10 -> 1 4'1001 + 22: 2 10'-0-----000 -> 2 4'1001 + 23: 2 10'10-----010 -> 2 4'1001 + 24: 2 10'---1-1--10 -> 3 4'1001 + 25: 3 10'-1-----000 -> 0 4'0000 + 26: 3 10'-------100 -> 0 4'0000 + 27: 3 10'--------10 -> 0 4'0000 + 28: 3 10'---------1 -> 0 4'0000 + 29: 3 10'-0-----000 -> 3 4'0000 + +------------------------------------- + +FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `ulx3s_packet_top': +------------------------------------- + + Information on FSM $fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492 (\bridge.g_packet.asic.packet_core.tx_external_kind): + + Number of input signals: 51 + Number of output signals: 7 + Number of state bits: 8 + + Input signals: + 0: \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending + 1: \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending + 2: \bridge.g_packet.asic.packet_core.field_encoder.fault + 3: \bridge.g_packet.asic.packet_core.adapter.fault + 4: \bridge.g_packet.asic.packet_core.receiver.fault_valid + 5: \bridge.g_packet.asic.packet_core.request_validator.bad_state + 6: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_deferred[0:0] + 7: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_ok[0:0] + 8: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_ok[0:0] + 9: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4225_Y + 10: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y + 11: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y + 12: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y + 13: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y + 14: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y + 15: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:723$4052_Y + 16: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030_Y + 17: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997_Y + 18: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y + 19: $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990_Y + 20: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989_Y + 21: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y + 22: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:661$3953_Y + 23: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y + 24: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y + 25: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:411$3846_Y + 26: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y + 27: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y + 28: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y + 29: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y + 30: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:609$3672_Y + 31: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y + 32: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3629_Y + 33: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y + 34: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:592$3582_Y + 35: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y + 36: $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:580$3535_Y + 37: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y + 38: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:566$3482_Y + 39: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y + 40: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:449$3417_Y + 41: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:447$3412_Y + 42: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407_Y + 43: $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:442$3403_Y + 44: $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y + 45: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y + 46: \bridge.g_packet.asic.packet_core.request_reject + 47: \bridge.g_packet.asic.packet_core.blake_retire_match + 48: \bridge.g_packet.asic.packet_core.result_pending + 49: \bridge.abort_q + 50: \bridge.por_shift [7] + + Output signals: + 0: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:50$2166_Y + 1: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:87$2331_Y + 2: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:188$2333_Y + 3: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:197$2334_Y + 4: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:222$2338_Y + 5: $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:240$2339_Y + 6: $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:236$3179_Y + + State encoding: + 0: 8'-------1 + 1: 8'------1- + 2: 8'-----1-- + 3: 8'----1--- + 4: 8'---1---- + 5: 8'--1----- + 6: 8'-1------ + 7: 8'1------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 51'10----0----0-10---------------------------------0-- -> 0 7'0000000 + 1: 0 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 0 7'0000000 + 2: 0 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 0 7'0000000 + 3: 0 51'10----0----0-0-0-0-0-0000-0------------------------ -> 0 7'0000000 + 4: 0 51'10----0----0-0-0-0-0-001--------------------------- -> 0 7'0000000 + 5: 0 51'10----0----0-0-0-000-01---------------------------- -> 0 7'0000000 + 6: 0 51'10----0----0-0-0-0-0-1----------------------------- -> 0 7'0000000 + 7: 0 51'10----0----0-0-0-10-------------------------------- -> 0 7'0000000 + 8: 0 51'10----100------------------------------------------ -> 0 7'0000000 + 9: 0 51'11------------------------------------------------- -> 0 7'0000000 + 10: 0 51'0-------------------------------------------------- -> 0 7'0000000 + 11: 0 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000000 + 12: 0 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000000 + 13: 0 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000000 + 14: 0 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000000 + 15: 0 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000000 + 16: 0 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000000 + 17: 0 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000000 + 18: 0 51'10----0----0-11---------------------------------0-- -> 1 7'0000000 + 19: 0 51'10----0----11-----------------------------------0-- -> 1 7'0000000 + 20: 0 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000000 + 21: 0 51'10----0----0-1----------------------------------1-- -> 1 7'0000000 + 22: 0 51'10----0----1------------------------------------1-- -> 1 7'0000000 + 23: 0 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000000 + 24: 0 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000000 + 25: 0 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000000 + 26: 0 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000000 + 27: 0 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000000 + 28: 0 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000000 + 29: 0 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000000 + 30: 0 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000000 + 31: 0 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000000 + 32: 0 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000000 + 33: 0 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000000 + 34: 0 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000000 + 35: 0 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000000 + 36: 0 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000000 + 37: 0 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000000 + 38: 0 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000000 + 39: 0 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000000 + 40: 0 51'10----10101---------------------------------------- -> 1 7'0000000 + 41: 0 51'10----1011----------------------------------------- -> 1 7'0000000 + 42: 0 51'10----11------------------------------------------- -> 1 7'0000000 + 43: 0 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000000 + 44: 0 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000000 + 45: 0 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000000 + 46: 0 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000000 + 47: 0 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000000 + 48: 0 51'10----0----10-----------------------------------0-- -> 6 7'0000000 + 49: 0 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000000 + 50: 0 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000000 + 51: 0 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000000 + 52: 0 51'10----10100---------------------------------------- -> 6 7'0000000 + 53: 0 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000000 + 54: 0 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000000 + 55: 1 51'11------------------------------------------------- -> 0 7'0000100 + 56: 1 51'0-------------------------------------------------- -> 0 7'0000100 + 57: 1 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000100 + 58: 1 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000100 + 59: 1 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000100 + 60: 1 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000100 + 61: 1 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000100 + 62: 1 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000100 + 63: 1 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000100 + 64: 1 51'10----0----11-----------------------------------0-- -> 1 7'0000100 + 65: 1 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000100 + 66: 1 51'10----0----1------------------------------------1-- -> 1 7'0000100 + 67: 1 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000100 + 68: 1 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000100 + 69: 1 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000100 + 70: 1 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000100 + 71: 1 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000100 + 72: 1 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000100 + 73: 1 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 1 7'0000100 + 74: 1 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 1 7'0000100 + 75: 1 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000100 + 76: 1 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000100 + 77: 1 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000100 + 78: 1 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000100 + 79: 1 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000100 + 80: 1 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000100 + 81: 1 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000100 + 82: 1 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000100 + 83: 1 51'10----0----0-0-0-0-0-0000-0------------------------ -> 1 7'0000100 + 84: 1 51'10----0----0-0-0-0-0-001--------------------------- -> 1 7'0000100 + 85: 1 51'10----0----0-0-0-0-0-01---------------------------- -> 1 7'0000100 + 86: 1 51'10----0----0-0-0-0-0-1----------------------------- -> 1 7'0000100 + 87: 1 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000100 + 88: 1 51'10----0----0-0-0-1--------------------------------- -> 1 7'0000100 + 89: 1 51'10----0----0-1------------------------------------- -> 1 7'0000100 + 90: 1 51'10----10101---------------------------------------- -> 1 7'0000100 + 91: 1 51'10----1011----------------------------------------- -> 1 7'0000100 + 92: 1 51'10----100------------------------------------------ -> 1 7'0000100 + 93: 1 51'10----11------------------------------------------- -> 1 7'0000100 + 94: 1 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000100 + 95: 1 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000100 + 96: 1 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000100 + 97: 1 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000100 + 98: 1 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000100 + 99: 1 51'10----0----10-----------------------------------0-- -> 6 7'0000100 + 100: 1 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000100 + 101: 1 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000100 + 102: 1 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000100 + 103: 1 51'10----10100---------------------------------------- -> 6 7'0000100 + 104: 1 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000100 + 105: 1 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000100 + 106: 2 51'11------------------------------------------------- -> 0 7'1000000 + 107: 2 51'0-------------------------------------------------- -> 0 7'1000000 + 108: 2 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'1000000 + 109: 2 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'1000000 + 110: 2 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'1000000 + 111: 2 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'1000000 + 112: 2 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'1000000 + 113: 2 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'1000000 + 114: 2 51'10----0----0-0-11-------------------------------0-- -> 1 7'1000000 + 115: 2 51'10----0----0-11---------------------------------0-- -> 1 7'1000000 + 116: 2 51'10----0----11-----------------------------------0-- -> 1 7'1000000 + 117: 2 51'10----0----0-0-1--------------------------------1-- -> 1 7'1000000 + 118: 2 51'10----0----0-1----------------------------------1-- -> 1 7'1000000 + 119: 2 51'10----0----1------------------------------------1-- -> 1 7'1000000 + 120: 2 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'1000000 + 121: 2 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'1000000 + 122: 2 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'1000000 + 123: 2 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'1000000 + 124: 2 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'1000000 + 125: 2 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'1000000 + 126: 2 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'1000000 + 127: 2 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'1000000 + 128: 2 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'1000000 + 129: 2 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'1000000 + 130: 2 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'1000000 + 131: 2 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'1000000 + 132: 2 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'1000000 + 133: 2 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'1000000 + 134: 2 51'10----0----0-0-0-010-01---------------------------- -> 1 7'1000000 + 135: 2 51'10----0----0-0-0-0-11------------------------------ -> 1 7'1000000 + 136: 2 51'10----0----0-0-0-11-------------------------------- -> 1 7'1000000 + 137: 2 51'10----10101---------------------------------------- -> 1 7'1000000 + 138: 2 51'10----1011----------------------------------------- -> 1 7'1000000 + 139: 2 51'10----11------------------------------------------- -> 1 7'1000000 + 140: 2 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'1000000 + 141: 2 51'10----0----0-10---------------------------------0-- -> 2 7'1000000 + 142: 2 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 2 7'1000000 + 143: 2 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 2 7'1000000 + 144: 2 51'10----0----0-0-0-0-0-0000-0------------------------ -> 2 7'1000000 + 145: 2 51'10----0----0-0-0-0-0-001--------------------------- -> 2 7'1000000 + 146: 2 51'10----0----0-0-0-000-01---------------------------- -> 2 7'1000000 + 147: 2 51'10----0----0-0-0-0-0-1----------------------------- -> 2 7'1000000 + 148: 2 51'10----0----0-0-0-10-------------------------------- -> 2 7'1000000 + 149: 2 51'10----100------------------------------------------ -> 2 7'1000000 + 150: 2 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'1000000 + 151: 2 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'1000000 + 152: 2 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'1000000 + 153: 2 51'10----0----0-0-10-------------------------------0-- -> 6 7'1000000 + 154: 2 51'10----0----10-----------------------------------0-- -> 6 7'1000000 + 155: 2 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'1000000 + 156: 2 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'1000000 + 157: 2 51'10----0----0-0-0-0-10------------------------------ -> 6 7'1000000 + 158: 2 51'10----10100---------------------------------------- -> 6 7'1000000 + 159: 2 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'1000000 + 160: 2 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'1000000 + 161: 3 51'11------------------------------------------------- -> 0 7'0010000 + 162: 3 51'0-------------------------------------------------- -> 0 7'0010000 + 163: 3 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0010000 + 164: 3 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0010000 + 165: 3 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0010000 + 166: 3 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0010000 + 167: 3 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0010000 + 168: 3 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0010000 + 169: 3 51'10----0----0-0-11-------------------------------0-- -> 1 7'0010000 + 170: 3 51'10----0----0-11---------------------------------0-- -> 1 7'0010000 + 171: 3 51'10----0----11-----------------------------------0-- -> 1 7'0010000 + 172: 3 51'10----0----0-0-1--------------------------------1-- -> 1 7'0010000 + 173: 3 51'10----0----0-1----------------------------------1-- -> 1 7'0010000 + 174: 3 51'10----0----1------------------------------------1-- -> 1 7'0010000 + 175: 3 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0010000 + 176: 3 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0010000 + 177: 3 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0010000 + 178: 3 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0010000 + 179: 3 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0010000 + 180: 3 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0010000 + 181: 3 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0010000 + 182: 3 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0010000 + 183: 3 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0010000 + 184: 3 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0010000 + 185: 3 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0010000 + 186: 3 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0010000 + 187: 3 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0010000 + 188: 3 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0010000 + 189: 3 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0010000 + 190: 3 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0010000 + 191: 3 51'10----0----0-0-0-11-------------------------------- -> 1 7'0010000 + 192: 3 51'10----10101---------------------------------------- -> 1 7'0010000 + 193: 3 51'10----1011----------------------------------------- -> 1 7'0010000 + 194: 3 51'10----11------------------------------------------- -> 1 7'0010000 + 195: 3 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0010000 + 196: 3 51'10----0----0-10---------------------------------0-- -> 3 7'0010000 + 197: 3 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0010000 + 198: 3 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 3 7'0010000 + 199: 3 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 3 7'0010000 + 200: 3 51'10----0----0-0-0-0-0-0000-0------------------------ -> 3 7'0010000 + 201: 3 51'10----0----0-0-0-0-0-001--------------------------- -> 3 7'0010000 + 202: 3 51'10----0----0-0-0-000-01---------------------------- -> 3 7'0010000 + 203: 3 51'10----0----0-0-0-0-0-1----------------------------- -> 3 7'0010000 + 204: 3 51'10----0----0-0-0-10-------------------------------- -> 3 7'0010000 + 205: 3 51'10----100------------------------------------------ -> 3 7'0010000 + 206: 3 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0010000 + 207: 3 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0010000 + 208: 3 51'10----0----0-0-10-------------------------------0-- -> 6 7'0010000 + 209: 3 51'10----0----10-----------------------------------0-- -> 6 7'0010000 + 210: 3 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0010000 + 211: 3 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0010000 + 212: 3 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0010000 + 213: 3 51'10----10100---------------------------------------- -> 6 7'0010000 + 214: 3 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0010000 + 215: 3 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0010000 + 216: 4 51'11------------------------------------------------- -> 0 7'0000001 + 217: 4 51'0-------------------------------------------------- -> 0 7'0000001 + 218: 4 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000001 + 219: 4 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000001 + 220: 4 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000001 + 221: 4 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000001 + 222: 4 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000001 + 223: 4 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000001 + 224: 4 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000001 + 225: 4 51'10----0----0-11---------------------------------0-- -> 1 7'0000001 + 226: 4 51'10----0----11-----------------------------------0-- -> 1 7'0000001 + 227: 4 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000001 + 228: 4 51'10----0----0-1----------------------------------1-- -> 1 7'0000001 + 229: 4 51'10----0----1------------------------------------1-- -> 1 7'0000001 + 230: 4 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000001 + 231: 4 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000001 + 232: 4 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000001 + 233: 4 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000001 + 234: 4 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000001 + 235: 4 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000001 + 236: 4 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000001 + 237: 4 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000001 + 238: 4 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000001 + 239: 4 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000001 + 240: 4 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000001 + 241: 4 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000001 + 242: 4 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000001 + 243: 4 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000001 + 244: 4 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000001 + 245: 4 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000001 + 246: 4 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000001 + 247: 4 51'10----10101---------------------------------------- -> 1 7'0000001 + 248: 4 51'10----1011----------------------------------------- -> 1 7'0000001 + 249: 4 51'10----11------------------------------------------- -> 1 7'0000001 + 250: 4 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000001 + 251: 4 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000001 + 252: 4 51'10----0----0-10---------------------------------0-- -> 4 7'0000001 + 253: 4 51'10--000----0-0-0-0-0-0000-10-0------0-------1-0---- -> 4 7'0000001 + 254: 4 51'10----0----0-0-0-0-0-0000-0------------------------ -> 4 7'0000001 + 255: 4 51'10----0----0-0-0-0-0-001--------------------------- -> 4 7'0000001 + 256: 4 51'10----0----0-0-0-000-01---------------------------- -> 4 7'0000001 + 257: 4 51'10----0----0-0-0-0-0-1----------------------------- -> 4 7'0000001 + 258: 4 51'10----0----0-0-0-10-------------------------------- -> 4 7'0000001 + 259: 4 51'10----100------------------------------------------ -> 4 7'0000001 + 260: 4 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000001 + 261: 4 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000001 + 262: 4 51'10----0----10-----------------------------------0-- -> 6 7'0000001 + 263: 4 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000001 + 264: 4 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000001 + 265: 4 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000001 + 266: 4 51'10----10100---------------------------------------- -> 6 7'0000001 + 267: 4 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000001 + 268: 4 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000001 + 269: 5 51'11------------------------------------------------- -> 0 7'0001000 + 270: 5 51'0-------------------------------------------------- -> 0 7'0001000 + 271: 5 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0001000 + 272: 5 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0001000 + 273: 5 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0001000 + 274: 5 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0001000 + 275: 5 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0001000 + 276: 5 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0001000 + 277: 5 51'10----0----0-0-11-------------------------------0-- -> 1 7'0001000 + 278: 5 51'10----0----0-11---------------------------------0-- -> 1 7'0001000 + 279: 5 51'10----0----11-----------------------------------0-- -> 1 7'0001000 + 280: 5 51'10----0----0-0-1--------------------------------1-- -> 1 7'0001000 + 281: 5 51'10----0----0-1----------------------------------1-- -> 1 7'0001000 + 282: 5 51'10----0----1------------------------------------1-- -> 1 7'0001000 + 283: 5 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0001000 + 284: 5 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0001000 + 285: 5 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0001000 + 286: 5 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0001000 + 287: 5 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0001000 + 288: 5 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0001000 + 289: 5 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0001000 + 290: 5 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0001000 + 291: 5 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0001000 + 292: 5 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0001000 + 293: 5 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0001000 + 294: 5 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0001000 + 295: 5 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0001000 + 296: 5 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0001000 + 297: 5 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0001000 + 298: 5 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0001000 + 299: 5 51'10----0----0-0-0-11-------------------------------- -> 1 7'0001000 + 300: 5 51'10----10101---------------------------------------- -> 1 7'0001000 + 301: 5 51'10----1011----------------------------------------- -> 1 7'0001000 + 302: 5 51'10----11------------------------------------------- -> 1 7'0001000 + 303: 5 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0001000 + 304: 5 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0001000 + 305: 5 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0001000 + 306: 5 51'10----0----0-10---------------------------------0-- -> 5 7'0001000 + 307: 5 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 5 7'0001000 + 308: 5 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 5 7'0001000 + 309: 5 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0001000 + 310: 5 51'10----0----0-0-0-0-0-0000-0------------------------ -> 5 7'0001000 + 311: 5 51'10----0----0-0-0-0-0-001--------------------------- -> 5 7'0001000 + 312: 5 51'10----0----0-0-0-000-01---------------------------- -> 5 7'0001000 + 313: 5 51'10----0----0-0-0-0-0-1----------------------------- -> 5 7'0001000 + 314: 5 51'10----0----0-0-0-10-------------------------------- -> 5 7'0001000 + 315: 5 51'10----100------------------------------------------ -> 5 7'0001000 + 316: 5 51'10----0----0-0-10-------------------------------0-- -> 6 7'0001000 + 317: 5 51'10----0----10-----------------------------------0-- -> 6 7'0001000 + 318: 5 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0001000 + 319: 5 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0001000 + 320: 5 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0001000 + 321: 5 51'10----10100---------------------------------------- -> 6 7'0001000 + 322: 5 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0001000 + 323: 5 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0001000 + 324: 6 51'11------------------------------------------------- -> 0 7'0000010 + 325: 6 51'0-------------------------------------------------- -> 0 7'0000010 + 326: 6 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0000010 + 327: 6 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0000010 + 328: 6 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0000010 + 329: 6 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0000010 + 330: 6 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0000010 + 331: 6 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0000010 + 332: 6 51'10----0----0-0-11-------------------------------0-- -> 1 7'0000010 + 333: 6 51'10----0----0-11---------------------------------0-- -> 1 7'0000010 + 334: 6 51'10----0----11-----------------------------------0-- -> 1 7'0000010 + 335: 6 51'10----0----0-0-1--------------------------------1-- -> 1 7'0000010 + 336: 6 51'10----0----0-1----------------------------------1-- -> 1 7'0000010 + 337: 6 51'10----0----1------------------------------------1-- -> 1 7'0000010 + 338: 6 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0000010 + 339: 6 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0000010 + 340: 6 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0000010 + 341: 6 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0000010 + 342: 6 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0000010 + 343: 6 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0000010 + 344: 6 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0000010 + 345: 6 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0000010 + 346: 6 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0000010 + 347: 6 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0000010 + 348: 6 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0000010 + 349: 6 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0000010 + 350: 6 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0000010 + 351: 6 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0000010 + 352: 6 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0000010 + 353: 6 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0000010 + 354: 6 51'10----0----0-0-0-11-------------------------------- -> 1 7'0000010 + 355: 6 51'10----10101---------------------------------------- -> 1 7'0000010 + 356: 6 51'10----1011----------------------------------------- -> 1 7'0000010 + 357: 6 51'10----11------------------------------------------- -> 1 7'0000010 + 358: 6 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0000010 + 359: 6 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0000010 + 360: 6 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0000010 + 361: 6 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0000010 + 362: 6 51'10----0----0-0-10-------------------------------0-- -> 6 7'0000010 + 363: 6 51'10----0----0-10---------------------------------0-- -> 6 7'0000010 + 364: 6 51'10----0----10-----------------------------------0-- -> 6 7'0000010 + 365: 6 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0000010 + 366: 6 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0000010 + 367: 6 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 6 7'0000010 + 368: 6 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 6 7'0000010 + 369: 6 51'10----0----0-0-0-0-0-0000-0------------------------ -> 6 7'0000010 + 370: 6 51'10----0----0-0-0-0-0-001--------------------------- -> 6 7'0000010 + 371: 6 51'10----0----0-0-0-000-01---------------------------- -> 6 7'0000010 + 372: 6 51'10----0----0-0-0-0-0-1----------------------------- -> 6 7'0000010 + 373: 6 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0000010 + 374: 6 51'10----0----0-0-0-10-------------------------------- -> 6 7'0000010 + 375: 6 51'10----10100---------------------------------------- -> 6 7'0000010 + 376: 6 51'10----100------------------------------------------ -> 6 7'0000010 + 377: 6 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0000010 + 378: 6 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0000010 + 379: 7 51'11------------------------------------------------- -> 0 7'0100000 + 380: 7 51'0-------------------------------------------------- -> 0 7'0100000 + 381: 7 51'10---00----0-0-0-0-0-0000-10-0------100-------0---0 -> 1 7'0100000 + 382: 7 51'10---00----0-0-0-0-0-0000-10-0------10001-----0---1 -> 1 7'0100000 + 383: 7 51'10---00----0-0-0-0-0-0000-10-0------1001------0---1 -> 1 7'0100000 + 384: 7 51'101--10----0-0-0-0-0-0000-10-0----01----------0--0- -> 1 7'0100000 + 385: 7 51'100--10----0-0-0-0-0-0000-10-0----0-----------0--0- -> 1 7'0100000 + 386: 7 51'10-0-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 1 7'0100000 + 387: 7 51'10----0----0-0-11-------------------------------0-- -> 1 7'0100000 + 388: 7 51'10----0----0-11---------------------------------0-- -> 1 7'0100000 + 389: 7 51'10----0----11-----------------------------------0-- -> 1 7'0100000 + 390: 7 51'10----0----0-0-1--------------------------------1-- -> 1 7'0100000 + 391: 7 51'10----0----0-1----------------------------------1-- -> 1 7'0100000 + 392: 7 51'10----0----1------------------------------------1-- -> 1 7'0100000 + 393: 7 51'10----0----0-0-0-0-0-00011---------------------0--- -> 1 7'0100000 + 394: 7 51'10----0----0-0-0-0-0-0001----------------------1--- -> 1 7'0100000 + 395: 7 51'10----0----0-0-0-0-0-0000-10-10011-----------00---- -> 1 7'0100000 + 396: 7 51'10----0----0-0-0-0-0-0000-10-1000------------00---- -> 1 7'0100000 + 397: 7 51'10----0----0-0-0-0-0-0000-10-100-------------10---- -> 1 7'0100000 + 398: 7 51'10--000----0-0-0-0-0-0000-10-0------0-----0-0-0---- -> 1 7'0100000 + 399: 7 51'10---00----0-0-0-0-0-0000-10-0------101-------0---- -> 1 7'0100000 + 400: 7 51'10---00----0-0-0-0-0-0000-10-0------11--------0---- -> 1 7'0100000 + 401: 7 51'10--100----0-0-0-0-0-0000-10-0------0---------0---- -> 1 7'0100000 + 402: 7 51'10---10----0-0-0-0-0-0000-10-0----1-----------0---- -> 1 7'0100000 + 403: 7 51'10----0----0-0-0-0-0-0000-10-101--------------0---- -> 1 7'0100000 + 404: 7 51'10----0----0-0-0-0-0-0000-10-11---------------0---- -> 1 7'0100000 + 405: 7 51'10----0----0-0-0-0-0-0000-111-----------------0---- -> 1 7'0100000 + 406: 7 51'10----0----0-0-0-0-0-0000-1-------------------1---- -> 1 7'0100000 + 407: 7 51'10----0----0-0-0-010-01---------------------------- -> 1 7'0100000 + 408: 7 51'10----0----0-0-0-0-11------------------------------ -> 1 7'0100000 + 409: 7 51'10----0----0-0-0-11-------------------------------- -> 1 7'0100000 + 410: 7 51'10----10101---------------------------------------- -> 1 7'0100000 + 411: 7 51'10----1011----------------------------------------- -> 1 7'0100000 + 412: 7 51'10----11------------------------------------------- -> 1 7'0100000 + 413: 7 51'10---00----0-0-0-0-0-0000-10-0------10000-----0---1 -> 2 7'0100000 + 414: 7 51'10----0----0-0-0-0-0-0000-10-10010-----------00---- -> 3 7'0100000 + 415: 7 51'10--000----0-0-0-0-0-0000-10-0------0----1-11-0---- -> 4 7'0100000 + 416: 7 51'10----0----0-0-0-0-0-0000-110-----------------0---- -> 5 7'0100000 + 417: 7 51'10----0----0-0-10-------------------------------0-- -> 6 7'0100000 + 418: 7 51'10----0----10-----------------------------------0-- -> 6 7'0100000 + 419: 7 51'10----0----0-0-0-0-0-00010---------------------0--- -> 6 7'0100000 + 420: 7 51'10--000----0-0-0-0-0-0000-10-0------0-----1-0-0---- -> 6 7'0100000 + 421: 7 51'10----0----0-0-0-0-10------------------------------ -> 6 7'0100000 + 422: 7 51'10----10100---------------------------------------- -> 6 7'0100000 + 423: 7 51'101--10----0-0-0-0-0-0000-10-0----00----------0--0- -> 7 7'0100000 + 424: 7 51'10-1-10----0-0-0-0-0-0000-10-0----0-----------0--1- -> 7 7'0100000 + 425: 7 51'10----0----0-10---------------------------------0-- -> 7 7'0100000 + 426: 7 51'10--000----0-0-0-0-0-0000-10-0------0----1-01-0---- -> 7 7'0100000 + 427: 7 51'10--000----0-0-0-0-0-0000-10-0------0----0--1-0---- -> 7 7'0100000 + 428: 7 51'10----0----0-0-0-0-0-0000-0------------------------ -> 7 7'0100000 + 429: 7 51'10----0----0-0-0-0-0-001--------------------------- -> 7 7'0100000 + 430: 7 51'10----0----0-0-0-000-01---------------------------- -> 7 7'0100000 + 431: 7 51'10----0----0-0-0-0-0-1----------------------------- -> 7 7'0100000 + 432: 7 51'10----0----0-0-0-10-------------------------------- -> 7 7'0100000 + 433: 7 51'10----100------------------------------------------ -> 7 7'0100000 + +------------------------------------- + +26.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.adapter.datapath.state$89440' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.compute_state$89453' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state$89466' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.field_encoder.multiplier.state$89479' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.receiver.state$89486' from module `\ulx3s_packet_top'. +Mapping FSM `$fsm$\bridge.g_packet.asic.packet_core.tx_external_kind$89492' from module `\ulx3s_packet_top'. + +26.13. Executing OPT pass (performing simple optimizations). + +26.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 317 cells. + +26.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88850 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12932_Y, Q = \bridge.utx.shift, rval = 9'111111111). +Adding EN signal on $auto$ff.cc:266:slice$91348 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12932_Y, Q = \bridge.utx.shift). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88849 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12946_Y, Q = \bridge.utx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$91356 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12946_Y, Q = \bridge.utx.bit_cnt). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88848 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12957_Y, Q = \bridge.utx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91364 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12957_Y, Q = \bridge.utx.div_cnt). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88847 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12963_Y, Q = \bridge.utx.tx_serial, rval = 1'1). +Adding EN signal on $auto$ff.cc:266:slice$91368 ($sdff) from module ulx3s_packet_top (D = \bridge.utx.shift [0], Q = \bridge.utx.tx_serial). +Adding SRST signal on $flatten\bridge.\utx.$procdff$88846 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\utx.$procmux$12980_Y, Q = \bridge.utx.tx_ready, rval = 1'1). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89008 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88033_Y, Q = \bridge.urx.wait_idle, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$91375 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88033_Y, Q = \bridge.urx.wait_idle). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89007 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88056_Y, Q = \bridge.urx.receiving, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89006 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$2$lookahead\shift$4385[7:0]$4400, Q = \bridge.urx.shift, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91388 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$or$uart_rx.sv:0$4430_Y, Q = \bridge.urx.shift). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89005 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88079_Y, Q = \bridge.urx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$91394 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88079_Y, Q = \bridge.urx.bit_cnt). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89004 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88093_Y, Q = \bridge.urx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91408 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88093_Y, Q = \bridge.urx.div_cnt). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89003 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$87969_Y, Q = \bridge.urx.framing_err, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89002 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$87987_Y, Q = \bridge.urx.rx_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\urx.$procdff$89001 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\urx.$procmux$88111_Y, Q = \bridge.urx.rx_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91434 ($sdff) from module ulx3s_packet_top (D = \bridge.urx.shift, Q = \bridge.urx.rx_data). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88785 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8861_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$91442 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88784 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8873_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$91448 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88783 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8888_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$91454 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$not$../../asic_core/rtl/lsc1_packet_tx.sv:99$1956_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88782 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8897_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$91460 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.tx_status, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88781 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8903_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91462 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.tx_length, Q = \bridge.g_packet.asic.packet_core.transmitter.saved_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88780 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8915_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$91464 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8915_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.active). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88779 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8924_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91472 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88778 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8942_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$91480 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:100$1992_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.payload_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procdff$88777 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8784_Y, Q = \bridge.g_packet.asic.packet_core.transmitter.done_pulse, rval = 1'0). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88821 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12351_Y, Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88820 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12387_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9109_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9124_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9139_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9154_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9169_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9184_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9199_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9214_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9229_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9244_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9259_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9274_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9289_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9304_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9319_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9334_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9349_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9364_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9379_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9394_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9409_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9424_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9439_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9454_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9469_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9484_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9499_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9514_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9529_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9544_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9559_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9574_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9589_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9604_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9619_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9634_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9649_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9664_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9679_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9694_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9709_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9724_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9739_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9754_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9769_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9784_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9799_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9814_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9829_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9844_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9859_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9874_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9889_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9904_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9919_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9934_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9949_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9964_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9979_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9994_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10009_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10024_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10039_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10054_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10069_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10084_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10099_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10114_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10129_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10144_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10159_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10174_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10189_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10204_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10219_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10234_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10249_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10264_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10279_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10294_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10309_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10324_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10339_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10354_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10369_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10384_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10399_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10414_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10429_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10444_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10459_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10474_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10489_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10504_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10519_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10534_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10549_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10564_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10579_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10594_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10609_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10624_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10639_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10654_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10669_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10684_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10699_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10714_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10729_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10744_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10759_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10774_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10789_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10804_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10819_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10834_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10849_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10864_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10879_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10894_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10909_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10924_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10939_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10954_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10969_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10984_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10999_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11014_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11029_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11044_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11059_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11074_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11089_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11104_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11119_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11134_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11149_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11164_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11179_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11194_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11209_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11224_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11239_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11254_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11269_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11284_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11299_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11314_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11329_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11344_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11359_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11374_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11389_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11404_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11419_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11434_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11449_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11464_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11479_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11494_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11509_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11524_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11539_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11554_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11569_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11584_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11599_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11614_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11629_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11644_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11659_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11674_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11689_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11704_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11719_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11734_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11749_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11764_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11779_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11794_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11809_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11824_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11839_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11854_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11869_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11884_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11899_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11914_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11929_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix, rval = 1520'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11926_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11911_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11896_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [23:16]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11881_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [31:24]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11866_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [39:32]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11851_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [47:40]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11836_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [55:48]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11821_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [63:56]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11806_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [71:64]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11791_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [79:72]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11776_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [87:80]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11761_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:88]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11746_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [103:96]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11731_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [111:104]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11716_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [119:112]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11701_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [127:120]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11686_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [135:128]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11671_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [143:136]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11656_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [151:144]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11641_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [159:152]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11626_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [167:160]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11611_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [175:168]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11596_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [183:176]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11581_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [191:184]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11566_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [199:192]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11551_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [207:200]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11536_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [215:208]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11521_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [223:216]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11506_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [231:224]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11491_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [239:232]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11476_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [247:240]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11461_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [255:248]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11446_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [263:256]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11431_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [271:264]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11416_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [279:272]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11401_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [287:280]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11386_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [295:288]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11371_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [303:296]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11356_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [311:304]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11341_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [319:312]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11326_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [327:320]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11311_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [335:328]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11296_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [343:336]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11281_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [351:344]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11266_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [359:352]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11251_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [367:360]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11236_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [375:368]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11221_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [383:376]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11206_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [391:384]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11191_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [399:392]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11176_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [407:400]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11161_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [415:408]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11146_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [423:416]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11131_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [431:424]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11116_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [439:432]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11101_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [447:440]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11086_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [455:448]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11071_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [463:456]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11056_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [471:464]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11041_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [479:472]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11026_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [487:480]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$11011_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [495:488]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10996_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [503:496]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10981_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [511:504]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10966_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [519:512]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10951_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [527:520]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10936_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [535:528]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10921_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [543:536]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10906_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [551:544]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10891_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [559:552]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10876_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [567:560]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10861_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [575:568]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10846_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [583:576]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10831_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [591:584]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10816_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [599:592]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10801_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [607:600]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10786_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [615:608]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10771_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [623:616]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10756_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [631:624]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10741_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [639:632]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10726_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [647:640]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10711_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [655:648]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10696_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [663:656]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10681_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [671:664]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10666_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [679:672]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10651_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [687:680]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10636_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [695:688]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10621_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [703:696]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10606_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [711:704]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10591_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [719:712]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10576_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [727:720]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10561_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [735:728]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10546_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [743:736]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10531_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [751:744]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10516_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [759:752]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10501_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [767:760]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10486_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [775:768]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10471_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [783:776]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10456_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [791:784]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10441_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [799:792]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10426_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [807:800]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10411_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [815:808]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10396_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [823:816]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10381_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [831:824]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10366_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [839:832]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10351_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [847:840]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10336_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [855:848]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10321_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [863:856]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10306_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [871:864]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10291_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [879:872]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10276_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [887:880]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10261_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [895:888]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10246_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [903:896]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10231_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [911:904]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10216_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [919:912]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10201_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [927:920]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10186_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [935:928]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10171_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [943:936]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10156_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [951:944]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10141_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [959:952]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10126_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [967:960]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10111_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [975:968]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10096_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [983:976]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10081_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [991:984]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10066_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [999:992]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10051_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1007:1000]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10036_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1015:1008]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10021_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1023:1016]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$10006_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1031:1024]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9991_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1039:1032]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9976_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1047:1040]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9961_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1055:1048]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9946_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1063:1056]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9931_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1071:1064]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9916_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1079:1072]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9901_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1087:1080]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9886_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1095:1088]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9871_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1103:1096]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9856_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1111:1104]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9841_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1119:1112]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9826_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1127:1120]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9811_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1135:1128]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9796_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1143:1136]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9781_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1151:1144]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9766_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1159:1152]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9751_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1167:1160]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9736_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1175:1168]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9721_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1183:1176]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9706_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1191:1184]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9691_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1199:1192]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9676_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1207:1200]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9661_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1215:1208]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9646_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1223:1216]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9631_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1231:1224]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9616_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1239:1232]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9601_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1247:1240]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9586_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1255:1248]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9571_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1263:1256]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9556_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1271:1264]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9541_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1279:1272]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9526_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1287:1280]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9511_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1295:1288]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9496_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1303:1296]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9481_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1311:1304]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9466_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1319:1312]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9451_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1327:1320]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9436_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1335:1328]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9421_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1343:1336]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9406_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1351:1344]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9391_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1359:1352]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9376_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1367:1360]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9361_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1375:1368]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9346_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1383:1376]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9331_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1391:1384]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9316_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1399:1392]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9301_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1407:1400]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9286_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1415:1408]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9271_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1423:1416]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9256_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1431:1424]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9241_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1439:1432]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9226_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1447:1440]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9211_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1455:1448]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9196_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1463:1456]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9181_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1471:1464]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9166_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1479:1472]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9151_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1487:1480]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9136_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1495:1488]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9121_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1503:1496]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9106_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1511:1504]). +Adding EN signal on $auto$ff.cc:266:slice$91504 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12384_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1519:1512]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88819 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9043_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9059_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9076_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9094_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9056_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [23:16]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9073_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9091_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$93215 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9040_Y, Q = \bridge.g_packet.asic.packet_core.receiver.received_crc [31:24]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88818 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12404_Y, Q = \bridge.g_packet.asic.packet_core.receiver.crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$93252 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12397_Y, Q = \bridge.g_packet.asic.packet_core.receiver.crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88817 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12419_Y, Q = \bridge.g_packet.asic.packet_core.receiver.flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93262 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.flags). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88816 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12435_Y, Q = \bridge.g_packet.asic.packet_core.receiver.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93266 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.opcode). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88815 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12452_Y, Q = \bridge.g_packet.asic.packet_core.receiver.version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93270 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.version). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88814 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12002_Y $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12016_Y }, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93274 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$93274 ($sdff) from module ulx3s_packet_top (D = \bridge.rx_data_q, Q = \bridge.g_packet.asic.packet_core.receiver.declared_length [7:0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88813 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12480_Y, Q = \bridge.g_packet.asic.packet_core.receiver.body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93281 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12473_Y, Q = \bridge.g_packet.asic.packet_core.receiver.body_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88812 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12494_Y, Q = \bridge.g_packet.asic.packet_core.receiver.header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$93289 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12488_Y, Q = \bridge.g_packet.asic.packet_core.receiver.header_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88810 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12569_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88809 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12603_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93298 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y, Q = \bridge.g_packet.asic.packet_core.receiver.fault_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88808 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12626_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93316 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.declared_length, Q = \bridge.g_packet.asic.packet_core.receiver.frame_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88807 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12649_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93328 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.opcode, Q = \bridge.g_packet.asic.packet_core.receiver.frame_opcode). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procdff$88806 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12674_Y, Q = \bridge.g_packet.asic.packet_core.receiver.frame_valid, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$88838 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93341 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$88837 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93353 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88737 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4441_Y $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4463_Y }, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93365 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4463_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$93365 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4441_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.scratch_byte [7:1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88736 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$93396 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.byte_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procdff$88734 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93422 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88769 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$93432 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88768 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7820_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93448 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.field_encoder.operand_b, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88767 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7836_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93454 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.field_encoder.operand_a, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88766 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7852_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93460 ($sdff) from module ulx3s_packet_top (D = 8'00000010, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.saved_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88764 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93466 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88763 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$93480 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.payload_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88762 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7733_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procdff$88761 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7932_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiplier.fault, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88756 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7408_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.saved_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93504 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.encoder_index, Q = \bridge.g_packet.asic.packet_core.field_encoder.saved_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88755 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423_Y [3:0], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [3:0], rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88755 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7420_Y [4], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [4], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93507 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136_Y [4], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [4]). +Adding EN signal on $auto$ff.cc:266:slice$93506 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423_Y [3:0], Q = \bridge.g_packet.asic.packet_core.field_encoder.bit_index [3:0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88754 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7364_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.multiply_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88753 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7438_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93527 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88752 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [0], rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88752 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93536 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$93535 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_b [0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88751 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7468_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [0], rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88751 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7465_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93556 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:63$2134_Y [127:1], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$93555 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7468_Y [0], Q = \bridge.g_packet.asic.packet_core.field_encoder.operand_a [0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88750 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7374_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88749 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7477_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93580 ($sdff) from module ulx3s_packet_top (D = 1'1, Q = \bridge.g_packet.asic.packet_core.field_encoder.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procdff$88748 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7495_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93586 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7495_Y, Q = \bridge.g_packet.asic.packet_core.field_encoder.busy). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88747 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7226_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93594 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_seq). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88746 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7234_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_service_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93600 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_service_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88745 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7239_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93606 ($sdff) from module ulx3s_packet_top (D = 1'1, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88743 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7265_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93612 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7265_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_result_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88742 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7276_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93620 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_next_fp, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88741 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7284_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93626 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_next_pc, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88740 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7292_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$93632 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.blake_start_txn_id, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.staged_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procdff$88739 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7299_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93638 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$procmux$7299_Y, Q = \bridge.g_packet.asic.packet_core.blake3_lifecycle.result_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procdff$88838 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93646 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12902_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procdff$88837 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93658 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$procmux$12918_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88737 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4441_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4463_Y }, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93670 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4463_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$93670 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4441_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.scratch_byte [7:1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88736 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$93701 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.byte_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procdff$88734 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$93727 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4632_Y, Q = \bridge.g_packet.asic.packet_core.adapter.datapath.fault). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88769 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.adapter.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$93737 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7785_Y, Q = \bridge.g_packet.asic.packet_core.adapter.result_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88768 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7820_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93753 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operand_b, Q = \bridge.g_packet.asic.packet_core.adapter.saved_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88767 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7836_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93759 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operand_a, Q = \bridge.g_packet.asic.packet_core.adapter.saved_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88766 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7852_Y, Q = \bridge.g_packet.asic.packet_core.adapter.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$93765 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.alu_operation, Q = \bridge.g_packet.asic.packet_core.adapter.saved_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88765 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864_Y, Q = \bridge.g_packet.asic.packet_core.adapter.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$93771 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864_Y, Q = \bridge.g_packet.asic.packet_core.adapter.state). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88764 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.adapter.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$93793 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3$lookahead\result$2032[127:0]$2064, Q = \bridge.g_packet.asic.packet_core.adapter.result). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88763 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.adapter.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$93807 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901_Y, Q = \bridge.g_packet.asic.packet_core.adapter.payload_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88762 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7733_Y, Q = \bridge.g_packet.asic.packet_core.adapter.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procdff$88761 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7932_Y, Q = \bridge.g_packet.asic.packet_core.adapter.fault, rval = 1'0). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88945 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1519:1392], Q = \bridge.g_packet.asic.packet_core.staged_out_value[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88944 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1383:1256], Q = \bridge.g_packet.asic.packet_core.staged_out_value[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88943 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1391:1384], Q = \bridge.g_packet.asic.packet_core.staged_out_present[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88942 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [1255:1248], Q = \bridge.g_packet.asic.packet_core.staged_out_present[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88941 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[7]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88940 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[6]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88939 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[5]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88938 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[4]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88937 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[3]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88936 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.cell_alias_check.address_c, Q = \bridge.g_packet.asic.packet_core.staged_access[2]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88935 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227_Y, Q = \bridge.g_packet.asic.packet_core.staged_access[1]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88934 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.cell_alias_check.address_a, Q = \bridge.g_packet.asic.packet_core.staged_access[0]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88933 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83866_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[2], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94211 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83863_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[2]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88932 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83962_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[1], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94267 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83959_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[1]). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88931 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84058_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[0], rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$94323 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84055_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access[0]). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88926 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\write_address[31:0], Q = \bridge.g_packet.asic.packet_core.write_address). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88925 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$9\solved_b[127:0], Q = \bridge.g_packet.asic.packet_core.solved_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88924 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$9\solved_a[127:0], Q = \bridge.g_packet.asic.packet_core.solved_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88923 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\result_value[127:0], Q = \bridge.g_packet.asic.packet_core.result_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88922 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$23\inv_value[127:0], Q = \bridge.g_packet.asic.packet_core.inv_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88921 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\val_c[127:0], Q = \bridge.g_packet.asic.packet_core.val_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88920 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\val_b[127:0], Q = \bridge.g_packet.asic.packet_core.val_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88919 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$21\val_a[127:0], Q = \bridge.g_packet.asic.packet_core.val_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88917 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\pres_c[7:0], Q = \bridge.g_packet.asic.packet_core.pres_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88916 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$22\pres_b[7:0], Q = \bridge.g_packet.asic.packet_core.pres_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88915 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$21\pres_a[7:0], Q = \bridge.g_packet.asic.packet_core.pres_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88914 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [103:96], Q = \bridge.g_packet.asic.packet_core.profile). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88913 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\deferred_local[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_local). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88912 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\deferred_target[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_target). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88911 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$6\next_fp_value[31:0], Q = \bridge.g_packet.asic.packet_core.next_fp_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88910 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$6\next_pc_value[31:0], Q = \bridge.g_packet.asic.packet_core.next_pc_value). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88909 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [687:656], Q = \bridge.g_packet.asic.packet_core.proposed_fp). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88908 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [655:624], Q = \bridge.g_packet.asic.packet_core.proposed_pc). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88906 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_c[31:0], Q = \bridge.g_packet.asic.packet_core.addr_c). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88905 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_b[31:0], Q = \bridge.g_packet.asic.packet_core.addr_b). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88904 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$20\addr_a[31:0], Q = \bridge.g_packet.asic.packet_core.addr_a). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88900 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:64], Q = \bridge.g_packet.asic.packet_core.fp). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88899 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [63:32], Q = \bridge.g_packet.asic.packet_core.pc). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88898 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$17\txn_id[31:0], Q = \bridge.g_packet.asic.packet_core.txn_id). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88896 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\n_deferred[31:0], Q = \bridge.g_packet.asic.packet_core.n_deferred). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88895 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\n_writes[31:0], Q = \bridge.g_packet.asic.packet_core.n_writes). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88894 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$2\staged_write_count[1:0], Q = \bridge.g_packet.asic.packet_core.staged_write_count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$95461 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$25\staged_write_count[1:0], Q = \bridge.g_packet.asic.packet_core.staged_write_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88893 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [6:5] \bridge.g_packet.asic.packet_core.last_fault [3:2] }, rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88893 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [7] \bridge.g_packet.asic.packet_core.last_fault [4] \bridge.g_packet.asic.packet_core.last_fault [1:0] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$95508 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84214_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [7] \bridge.g_packet.asic.packet_core.last_fault [4] \bridge.g_packet.asic.packet_core.last_fault [1:0] }). +Adding EN signal on $auto$ff.cc:266:slice$95503 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84211_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_fault [6:5] \bridge.g_packet.asic.packet_core.last_fault [3:2] }). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88892 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_status [6:5] \bridge.g_packet.asic.packet_core.last_status [3:2] }, rval = 4'0000). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88892 ($dff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_status [7] \bridge.g_packet.asic.packet_core.last_status [4] \bridge.g_packet.asic.packet_core.last_status [1:0] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$95588 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84376_Y [1:0] }, Q = { \bridge.g_packet.asic.packet_core.last_status [7] \bridge.g_packet.asic.packet_core.last_status [4] \bridge.g_packet.asic.packet_core.last_status [1:0] }). +Adding EN signal on $auto$ff.cc:266:slice$95583 ($sdff) from module ulx3s_packet_top (D = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84373_Y [3:2] }, Q = { \bridge.g_packet.asic.packet_core.last_status [6:5] \bridge.g_packet.asic.packet_core.last_status [3:2] }). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88891 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84439_Y, Q = \bridge.g_packet.asic.packet_core.active_profile, rval = 8'00000001). +Adding EN signal on $auto$ff.cc:266:slice$95623 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [23:16], Q = \bridge.g_packet.asic.packet_core.active_profile). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88890 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84505_Y, Q = \bridge.g_packet.asic.packet_core.retire_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95661 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84456_Y, Q = \bridge.g_packet.asic.packet_core.retire_seq). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88889 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84571_Y, Q = \bridge.g_packet.asic.packet_core.committed_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95701 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84522_Y, Q = \bridge.g_packet.asic.packet_core.committed_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88888 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84637_Y, Q = \bridge.g_packet.asic.packet_core.committed_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95741 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84588_Y, Q = \bridge.g_packet.asic.packet_core.committed_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88887 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84703_Y, Q = \bridge.g_packet.asic.packet_core.state_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$95781 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84654_Y, Q = \bridge.g_packet.asic.packet_core.state_valid). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88886 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84799_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_local, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95821 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84796_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_local). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88885 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84895_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_target, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$95877 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84892_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred_target). +Adding EN signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88884 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$3\write_value[127:0], Q = \bridge.g_packet.asic.packet_core.write_value). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88883 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84991_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_value, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$95978 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84988_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_value). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88882 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85087_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_address, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96034 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85084_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_address). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88881 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85183_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access_count, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96090 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_access_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88880 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85279_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$96146 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85276_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_deferred). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88879 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85375_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$96202 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85372_Y, Q = \bridge.g_packet.asic.packet_core.scalar_staged_write_count). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88878 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85473_Y, Q = \bridge.g_packet.asic.packet_core.staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96258 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85470_Y, Q = \bridge.g_packet.asic.packet_core.staged_result_crc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88877 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85569_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96260 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85566_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88876 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85665_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96316 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85662_Y, Q = \bridge.g_packet.asic.packet_core.staged_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88875 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85761_Y, Q = \bridge.g_packet.asic.packet_core.staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96372 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85758_Y, Q = \bridge.g_packet.asic.packet_core.staged_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88872 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85881_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96428 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [95:64], Q = \bridge.g_packet.asic.packet_core.blake_start_next_fp). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88871 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85944_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96466 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_next_pc). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88870 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86007_Y, Q = \bridge.g_packet.asic.packet_core.blake_start_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96504 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [31:0], Q = \bridge.g_packet.asic.packet_core.blake_start_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88869 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82693_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_discard, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88868 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82762_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_accept, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88867 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82833_Y, Q = \bridge.g_packet.asic.packet_core.blake_service_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88866 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86111_Y, Q = \bridge.g_packet.asic.packet_core.result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$96571 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86111_Y, Q = \bridge.g_packet.asic.packet_core.result_pending). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88865 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86204_Y, Q = \bridge.g_packet.asic.packet_core.encoder_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96631 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86201_Y, Q = \bridge.g_packet.asic.packet_core.encoder_index). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88864 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$82976_Y, Q = \bridge.g_packet.asic.packet_core.encoder_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88863 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86318_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96692 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86297_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_b). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88862 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86432_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96754 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86411_Y, Q = \bridge.g_packet.asic.packet_core.alu_operand_a). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88861 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86546_Y, Q = \bridge.g_packet.asic.packet_core.alu_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96816 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y, Q = \bridge.g_packet.asic.packet_core.alu_operation). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88860 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83072_Y, Q = \bridge.g_packet.asic.packet_core.alu_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88858 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86785_Y, Q = \bridge.g_packet.asic.packet_core.capture_result_crc, rval = 1'0). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88857 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86944_Y, Q = \bridge.g_packet.asic.packet_core.short_detail, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96888 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86941_Y, Q = \bridge.g_packet.asic.packet_core.short_detail). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88856 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87095_Y, Q = \bridge.g_packet.asic.packet_core.short_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$96928 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87092_Y, Q = \bridge.g_packet.asic.packet_core.short_txn_id). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88854 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87419_Y, Q = \bridge.g_packet.asic.packet_core.tx_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$96962 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87416_Y, Q = \bridge.g_packet.asic.packet_core.tx_length). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88853 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87581_Y, Q = \bridge.g_packet.asic.packet_core.tx_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$96982 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87578_Y, Q = \bridge.g_packet.asic.packet_core.tx_status). +Adding SRST signal on $flatten\bridge.\g_packet.asic.\packet_core.$procdff$88852 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$procmux$83226_Y, Q = \bridge.g_packet.asic.packet_core.tx_start, rval = 1'0). +Adding SRST signal on $flatten\bridge.$procdff$89000 ($dff) from module ulx3s_packet_top (D = \bridge.por_shift [6:0], Q = \bridge.por_shift [7:1], rval = 7'0000000). +Adding SRST signal on $flatten\bridge.$procdff$88999 ($dff) from module ulx3s_packet_top (D = \bridge.urx.framing_err, Q = \bridge.abort_q, rval = 1'0). +Adding SRST signal on $flatten\bridge.$procdff$88998 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87777_Y, Q = \bridge.rx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$97010 ($sdff) from module ulx3s_packet_top (D = \bridge.urx.rx_data, Q = \bridge.rx_data_q). +Adding SRST signal on $flatten\bridge.$procdff$88997 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87785_Y, Q = \bridge.rx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$97016 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87785_Y, Q = \bridge.rx_full). +Adding SRST signal on $flatten\bridge.$procdff$88995 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87752_Y, Q = \bridge.tx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$97024 ($sdff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.transmitter.tx_data, Q = \bridge.tx_data_q). +Adding SRST signal on $flatten\bridge.$procdff$88994 ($dff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87760_Y, Q = \bridge.tx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$97030 ($sdff) from module ulx3s_packet_top (D = $flatten\bridge.$procmux$87760_Y, Q = \bridge.tx_full). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$93461 ($sdffe) from module ulx3s_packet_top. + +26.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 1539 unused cells and 1727 unused wires. + + +26.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7956. + dead port 2/2 on $mux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7956. + dead port 1/3 on $pmux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7970. + dead port 2/3 on $pmux $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7970. +Removed 4 multiplexer ports. + + +26.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1946 cells. + +26.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 2 unused cells and 1953 unused wires. + + +26.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.13.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.13.20. Executing OPT_DFF pass (perform DFF optimizations). + +26.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.13.23. Finished OPT passes. (There is nothing left to do.) + +26.14. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89023 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89024 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89025 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 1 address bits (of 2) from memory init port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$auto$proc_memwr.cc:45:proc_memwr$89026 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:284$4371 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:284$4372 (bridge.g_packet.asic.packet_core.staged_write_address). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:285$4373 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 31 address bits (of 32) from memory read port ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$memrd$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:285$4374 (bridge.g_packet.asic.packet_core.staged_write_value). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2288 ($div). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mod$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2290 ($mod). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91378 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91380 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96919 ($ne). +Removed top 8 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96913 ($ne). +Removed top 6 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96719 ($ne). +Removed top 6 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96717 ($ne). +Removed top 6 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96715 ($ne). +Removed top 6 bits (of 17) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96713 ($ne). +Removed top 6 bits (of 17) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96711 ($ne). +Removed top 6 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96709 ($ne). +Removed top 6 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96707 ($ne). +Removed top 6 bits (of 23) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96705 ($ne). +Removed top 6 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96703 ($ne). +Removed top 6 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96701 ($ne). +Removed top 6 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96699 ($ne). +Removed top 6 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96697 ($ne). +Removed top 6 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96695 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96674 ($ne). +Removed top 12 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96648 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96646 ($ne). +Removed top 12 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96644 ($ne). +Removed top 12 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96642 ($ne). +Removed top 12 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96640 ($ne). +Removed top 12 bits (of 23) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96638 ($ne). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96636 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$96634 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95668 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95612 ($ne). +Removed top 12 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95610 ($ne). +Removed top 13 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95595 ($ne). +Removed top 13 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95593 ($ne). +Removed top 5 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95576 ($ne). +Removed top 10 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95568 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95564 ($ne). +Removed top 10 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95562 ($ne). +Removed top 9 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95560 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95558 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95556 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95554 ($ne). +Removed top 11 bits (of 21) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95548 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95543 ($ne). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95541 ($ne). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95539 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95537 ($ne). +Removed top 9 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95535 ($ne). +Removed top 11 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95531 ($ne). +Removed top 13 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95529 ($ne). +Removed top 13 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95527 ($ne). +Removed top 11 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95525 ($ne). +Removed top 10 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95523 ($ne). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95521 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95519 ($ne). +Removed top 4 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95517 ($ne). +Removed top 1 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95515 ($ne). +Removed top 1 bits (of 20) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95513 ($ne). +Removed top 12 bits (of 22) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95511 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95015 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95013 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95011 ($ne). +Removed top 4 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95009 ($ne). +Removed top 5 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95007 ($ne). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95005 ($ne). +Removed top 7 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$95001 ($ne). +Removed top 7 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94999 ($ne). +Removed top 7 bits (of 11) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94997 ($ne). +Removed top 8 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94993 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94927 ($ne). +Removed top 9 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94911 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94819 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94817 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94727 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94452 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94450 ($ne). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94446 ($ne). +Removed top 4 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94444 ($ne). +Removed top 4 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94442 ($ne). +Removed top 5 bits (of 10) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94438 ($ne). +Removed top 6 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94434 ($ne). +Removed top 6 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94432 ($ne). +Removed top 6 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94430 ($ne). +Removed top 6 bits (of 15) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94428 ($ne). +Removed top 6 bits (of 16) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94426 ($ne). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94409 ($ne). +Removed top 5 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94405 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94254 ($ne). +Removed top 4 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94252 ($ne). +Removed top 5 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94250 ($ne). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94248 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94246 ($ne). +Removed top 8 bits (of 9) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94244 ($ne). +Removed top 10 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94240 ($ne). +Removed top 10 bits (of 13) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94238 ($ne). +Removed top 10 bits (of 14) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94236 ($ne). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94232 ($ne). +Removed top 12 bits (of 18) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94228 ($ne). +Removed top 12 bits (of 19) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94226 ($ne). +Removed top 9 bits (of 11) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94224 ($ne). +Removed top 9 bits (of 12) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94222 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94220 ($ne). +Removed top 3 bits (of 5) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94218 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94216 ($ne). +Removed top 3 bits (of 6) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$94214 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93788 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93784 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93750 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93730 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93653 ($ne). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93591 ($ne). +Removed top 1 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93521 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93425 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$93362 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90938 ($eq). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90921 ($eq). +Removed top 4 bits (of 6) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90917 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90902 ($eq). +Removed top 2 bits (of 5) from port B of cell ulx3s_packet_top.$auto$fsm_map.cc:77:implement_pattern_cache$90890 ($eq). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91353 ($ne). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91469 ($ne). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177 ($lt). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2184 ($shiftx). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2193 ($shiftx). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:56$2199 ($eq). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 26 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 10 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2216 ($shiftx). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217 ($lt). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 11 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 3 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2227 ($shiftx). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2231 ($shiftx). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2259 ($shiftx). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). +Removed top 12 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2270 ($shiftx). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271 ($eq). +Removed top 27 bits (of 30) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). +Removed top 25 bits (of 30) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280 ($lt). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 3 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 3 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311 ($eq). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2316 ($eq). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 24 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 24 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 11 bits (of 16) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). +Removed top 26 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$shiftx$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2330 ($shiftx). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:200$2336 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:199$2337 ($mux). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5186_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5187_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5188_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5190_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5191_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5194_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5195_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5196_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5198_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5199_CMP0 ($eq). +Removed top 15 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5200_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5293_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5294_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5295_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5296_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5376_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5377_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5378_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5379_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5380_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5381_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5382_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5422_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5423_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5424_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5425_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5426_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5427_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5428_CMP0 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5429_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5506_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5507_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5508_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5509_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5510_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5511_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5512_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5513_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5514_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5515_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5516_CMP0 ($eq). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5517_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5630_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5631_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5632_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$6799_CMP0 ($eq). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$ternary$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:37$2142 ($mux). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131 ($mux). +Removed top 120 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$xor$../../asic_core/rtl/lsc1_field_encoder.sv:27$2132 ($xor). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7423 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7453 ($mux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4593_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4594_CMP0 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4595_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4596_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4597_CMP0 ($eq). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4598_CMP0 ($eq). +Removed top 4 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640 ($pmux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4642_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4643_CMP0 ($eq). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4667 ($mux). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096 ($mux). +Removed top 120 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$xor$../../asic_core/rtl/gf2n_mul_bitstream.sv:65$3097 ($xor). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113 ($eq). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2092 ($eq). +Removed top 24 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Converting cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg) from signed to unsigned. +Removed top 1 bits (of 9) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 25 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2014 ($shiftx). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:83$2859 ($eq). +Removed top 6 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:83$2859 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010 ($eq). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2014 ($shiftx). +Removed top 23 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2019 ($shiftx). +Removed top 23 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2023 ($shiftx). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt). +Removed top 27 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 25 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). +Removed top 22 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$shiftx$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2031 ($shiftx). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:116$2066 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:116$2067 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:117$2069 ($eq). +Removed top 24 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Converting cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg) from signed to unsigned. +Removed top 1 bits (of 9) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2088 ($eq). +Removed top 2 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:142$2089 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$ne$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2091 ($ne). +Removed top 1 bits (of 6) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:143$2092 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:144$2095 ($eq). +Removed top 1 bits (of 5) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:161$2113 ($eq). +Removed top 2 bits (of 3) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7883 ($mux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7943_CMP0 ($eq). +Removed top 120 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096 ($mux). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4667 ($mux). +Removed top 3 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4643_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4642_CMP0 ($eq). +Removed top 4 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640 ($pmux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4598_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4597_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4596_CMP0 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4595_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4594_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4593_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$2922 ($eq). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714 ($ge). +Removed top 29 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717 ($lt). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:52$1720 ($mux). +Removed top 15 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724 ($eq). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725 ($eq). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726 ($eq). +Removed top 29 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818 ($le). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89027 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89029 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89031 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89033 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89035 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89037 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89039 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89041 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89043 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89045 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89047 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89049 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89051 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89053 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89055 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$auto$opt_expr.cc:706:replace_const_cells$89057 ($not). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8950_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$procmux$8949_CMP0 ($eq). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:104$1994 ($eq). +Removed top 24 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89091 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89093 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89095 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89097 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89099 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89101 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89103 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89105 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89107 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89109 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89111 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89113 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89115 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89117 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89119 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89121 ($not). +Removed top 1 bits (of 14) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$auto$opt_expr.cc:706:replace_const_cells$89123 ($not). +Removed top 7 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657 ($gt). +Removed top 189 bits (of 190) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:124$1659 ($mux). +Removed top 15 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700 ($sub). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:153$1703 ($ne). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9052_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$9069_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12013_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12416_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12432_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12512_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732 ($gt). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742 ($gt). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4852 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4942 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5017 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5077 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5122 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5158 ($mux). +Removed top 16 bits (of 32) from FF cell ulx3s_packet_top.$auto$ff.cc:266:slice$95264 ($dffe). +Removed top 16 bits (of 32) from FF cell ulx3s_packet_top.$auto$ff.cc:266:slice$95301 ($dffe). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334 ($mux). +Removed top 12 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316 ($mux). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305 ($mux). +Removed top 11 bits (of 16) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298 ($mux). +Removed top 2 bits (of 4) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91405 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_packet_top.$auto$opt_dff.cc:195:make_patterns_logic$91397 ($ne). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$83259 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$83241 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82124 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$82088 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81410 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$81356 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$80194 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79265 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$79193 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77609 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$77519 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$76106 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75998 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$75588 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$74003 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$73877 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$72062 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71918 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$71676 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69806 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$69644 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67235 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$67055 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64820 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$64523 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61880 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$61664 ($mux). +Removed top 26 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$60678 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57845 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$57611 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54720 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$54468 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51285 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$51150 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47709 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$47421 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$44265 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$43959 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$39171 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38847 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$38170 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37828 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$37057 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36877 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$36010 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35632 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$35179 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$34585 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33907 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$33493 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32998 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32782 ($mux). +Removed top 1 bits (of 2) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32710 ($mux). +Removed top 31 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$23518 ($mux). +Removed top 6 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$16945 ($mux). +Removed top 16 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197 ($mux). +Removed top 28 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$13129 ($mux). +Removed top 28 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$12987 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:372$4367 ($eq). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:1006$4353 ($eq). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:969$4332 ($eq). +Removed top 24 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4314 ($mux). +Removed top 6 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4312 ($eq). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304 ($ge). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303 ($ge). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4301 ($ne). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:903$4287 ($eq). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281 ($gt). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279 ($ge). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:874$4268 ($eq). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:834$4254 ($eq). +Removed top 25 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233 ($gt). +Removed top 4 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:810$4224 ($eq). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222 ($ge). +Removed top 15 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221 ($ge). +Removed top 26 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 16 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 16 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). +Removed top 28 bits (of 32) from port A of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 16 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 16 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). +Removed top 27 bits (of 30) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). +Removed top 25 bits (of 30) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:755$4163 ($mux). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:753$4142 ($ne). +Removed top 10 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084 ($ne). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058 ($eq). +Removed top 30 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:727$4056 ($mux). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:702$4030 ($ne). +Removed top 7 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997 ($ne). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994 ($ge). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993 ($le). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990 ($gt). +Removed top 13 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:676$3989 ($ne). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957 ($eq). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921 ($eq). +Removed top 31 bits (of 32) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:659$3920 ($mux). +Removed top 127 bits (of 128) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:600$3628 ($ne). +Removed top 14 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430 ($add). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:468$3429 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:445$3407 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3200 ($eq). +Removed top 3 bits (of 8) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198 ($eq). +Removed top 1 bits (of 3) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:39$2002 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\utx.$eq$uart_tx.sv:40$4377 ($eq). +Removed top 12 bits (of 16) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$eq$uart_rx.sv:62$4403 ($eq). +Removed top 28 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$le$uart_rx.sv:71$4415 ($le). +Removed top 31 bits (of 32) from port B of cell ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). +Converting cell ulx3s_packet_top.$flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg) from signed to unsigned. +Removed top 1 bits (of 33) from port A of cell ulx3s_packet_top.$flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg). +Removed top 7 bits (of 8) from mux cell ulx3s_packet_top.$flatten\bridge.$procmux$87797 ($mux). +Removed top 3 bits (of 8) from port Y of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 2 bits (of 7) from port B of cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7420 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450 ($mux). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7418 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7448 ($mux). +Removed top 1 bits (of 5) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7415 ($mux). +Removed top 127 bits (of 128) from mux cell ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7445 ($mux). +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.$0\por_shift[7:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3240. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3241. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3246. +Removed top 4 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$0$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3244. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3746. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3752. +Removed top 26 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$10\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3787. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3788. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$11$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3793. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3830. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$12$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3836. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3874. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$13$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3880. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3907. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$14$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3913. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3941. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3947. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$15\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3977. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$16$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3983. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4018. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4024. +Removed top 28 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$17\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4072. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$18$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4078. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4091. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$19$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4097. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3337. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_DATA[31:0]$3338. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3343. +Removed top 10 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$2$memwr$\staged_write_value$../../asic_core/rtl/lsc1_packet_frontend.sv:768$3160_DATA[127:0]$3341. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4109. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$20$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4115. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4127. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$21$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4133. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4148. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$22$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4154. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4175. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4181. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$23\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$4188. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$24$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$4198. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_detail[7:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3390. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$3$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3396. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$30\result_length[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$36\n_writes[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3467. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$4$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3473. +Removed top 26 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$40\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3521. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$5$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3527. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$53\result_length[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$54\result_length[31:0]. +Removed top 28 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$55\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3568. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$6$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3574. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3616. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$7$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3622. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3659. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3665. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$8\result_length[31:0]. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:767$3159_ADDR[1:0]$3704. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$9$memwr$\staged_write_address$../../asic_core/rtl/lsc1_packet_frontend.sv:772$3161_ADDR[1:0]$3710. +Removed top 16 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205_Y. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:921$4300_Y. +Removed top 1 bits (of 2) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$32782_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305_Y. +Removed top 12 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316_Y. +Removed top 11 bits (of 16) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:659$3920_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:727$4056_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:755$4163_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:956$4314_Y. +Removed top 7 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:957$4317_Y. +Removed top 2 bits (of 3) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7883_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028_Y. +Removed top 4 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$2\tx_data[7:0]. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096_Y. +Removed top 1 bits (of 5) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7415_Y. +Removed top 1 bits (of 5) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7418_Y. +Removed top 127 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$procmux$7450_Y. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028_Y. +Removed top 4 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$2858.$result[7:0]$2875. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$2\tx_data[7:0]. +Removed top 120 bits (of 128) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1596_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1600_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1608_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1649_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1595_Y. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_detail[7:0]. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_detail[7:0]. +Removed top 29 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$14\ext_word[31:0]. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$7\ext_word[31:0]. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2215_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2226_Y. +Removed top 27 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:0$2329_Y. +Removed top 24 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279_Y. +Removed top 27 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320_Y. +Removed top 30 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2210_Y. +Removed top 25 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267_Y. +Removed top 3 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305_Y. +Removed top 6 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:199$2337_Y. +Removed top 7 bits (of 8) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$ternary$../../asic_core/rtl/lsc1_response_payload_mux.sv:200$2336_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716_Y. +Removed top 15 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1840_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1844_Y. +Removed top 1 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1864_Y. +Removed top 31 bits (of 32) from wire ulx3s_packet_top.$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$xor$../../asic_core/rtl/lsc1_packet_tx.sv:39$1839_Y. +Removed top 1 bits (of 33) from wire ulx3s_packet_top.$flatten\bridge.\urx.$sub$uart_rx.sv:0$4421_Y. + +26.15. Executing PEEPOPT pass (run peephole optimizers). + +26.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 134 unused wires. + + +26.17. Executing SHARE pass (SAT-based resource sharing). +Found 4 cells in module ulx3s_packet_top that may be considered for resource sharing. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul): + Found 3 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88278 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2405:ReduceOr$88222 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + Found 1 candidates: $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 + Analyzing resource sharing with $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul): + Found 1 activation_patterns using ctrl signal { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending }. + Forbidden control signals for this pair of cells: { $auto$wreduce.cc:461:run$97164 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$xor$../../asic_core/rtl/lsc1_packet_tx.sv:39$1878_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88278 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2405:ReduceOr$88222 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5633_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5632_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5631_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5630_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5629_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5628_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5627_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5626_CMP $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y } + Activation pattern for cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278: { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 } = 12'010000010000 + Activation pattern for cell $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205: { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending } = 21'000000000001001000001 + Size of SAT problem: 0 cells, 3320 variables, 8113 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278: $auto$share.cc:977:make_cell_activation_logic$97166 + New cell: $auto$share.cc:667:make_supercell$97173 ($mul) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$97173 ($mul): + Found 2 activation_patterns using ctrl signal { $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:265$3198_Y \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:560$3353_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:562$3433_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:576$3489_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:588$3538_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:599$3588_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:608$3632_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:616$3678_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:627$3720_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:638$3762_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:649$3805_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:660$3921_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:743$4058_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:745$4084_Y $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:747$4103_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:751$4143_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_or$../../asic_core/rtl/lsc1_packet_frontend.sv:756$4172_Y \bridge.g_packet.asic.packet_core.receiver.fault_valid $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y \bridge.g_packet.asic.packet_core.blake3_lifecycle.service_pending $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 }. + No candidates found. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$div$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2288 ($div): + Found 1 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + No candidates found. + Analyzing resource sharing options for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mod$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2290 ($mod): + Found 1 activation_patterns using ctrl signal { \bridge.g_packet.asic.packet_core.tx_external_kind [4] \bridge.g_packet.asic.packet_core.tx_external_kind [2] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:59$1726_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:58$1725_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:57$1724_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:56$1723_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:55$1722_Y $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717_Y $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88474 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88446 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88412 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$auto$rtlil.cc:2431:And$88372 $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280_Y }. + No candidates found. +Removing 2 cells in module ulx3s_packet_top: + Removing cell $flatten\bridge.\g_packet.asic.\packet_core.$mul$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4205 ($mul). + Removing cell $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$mul$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2278 ($mul). + +26.18. Executing TECHMAP pass (map to technology primitives). + +26.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +26.18.2. Continuing TECHMAP pass. +Using template $paramod$8de9ae31f210b773e84137e37ebdc8a9cec5484d\_90_lut_cmp_ for cells of type $le. +No more expansions possible. + + +26.19. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.20. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 6 unused wires. + + +26.21. Executing TECHMAP pass (map to technology primitives). + +26.21.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/usr/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +26.21.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/dsp_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL18X18'. +Successfully finished Verilog frontend. + +26.21.3. Continuing TECHMAP pass. +Using template $paramod$6b45b5ab16ff1f3173b7cf3a190b9b2e0bbf2838\_80_mul for cells of type $mul. +Using template $paramod$1dafd33bc1a8aa1686876f77247edd05aadd21e4\_80_mul for cells of type $mul. +Using template $paramod$ebf35d89a536bf64810c60aaed904912ddcf22dd\$__MUL18X18 for cells of type $__MUL18X18. +No more expansions possible. + + +26.22. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module ulx3s_packet_top: + creating $macc model for $add$ulx3s_packet_top.sv:21$159 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078 ($neg). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817 ($add). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719 ($sub). + creating $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730 ($sub). + creating $macc model for $flatten\bridge.\urx.$add$uart_rx.sv:69$4414 ($add). + creating $macc model for $flatten\bridge.\urx.$add$uart_rx.sv:86$4433 ($add). + creating $macc model for $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422 ($neg). + creating $macc model for $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420 ($sub). + creating $macc model for $flatten\bridge.\utx.$add$uart_tx.sv:55$4379 ($add). + creating $macc model for $flatten\bridge.\utx.$add$uart_tx.sv:58$4380 ($add). + merging $macc model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2320 into $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321. + merging $macc model for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4206 into $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207. + creating $alu model for $macc $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420. + creating $alu model for $macc $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422. + creating $alu model for $macc $flatten\bridge.\urx.$add$uart_rx.sv:86$4433. + creating $alu model for $macc $flatten\bridge.\urx.$add$uart_rx.sv:69$4414. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190. + creating $alu model for $macc $flatten\bridge.\utx.$add$uart_tx.sv:55$4379. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350. + creating $alu model for $macc $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430. + creating $alu model for $macc $flatten\bridge.\utx.$add$uart_tx.sv:58$4380. + creating $alu model for $macc $add$ulx3s_packet_top.sv:21$159. + creating $macc cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:84$2321: $auto$alumacc.cc:365:replace_macc$97182 + creating $macc cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:429$4207: $auto$alumacc.cc:365:replace_macc$97183 + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:820$4232 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:829$4249 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:830$4252 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4238 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:826$4240 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:827$4243 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:828$4246 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4277 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993 ($le): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742 ($gt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714 ($ge): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818 ($le): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717 ($lt): new $alu + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997 ($ne): merged with $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177. + creating $alu model for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912 ($eq): merged with $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818. + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$lt$../../asic_core/rtl/lsc1_packet_tx.sv:51$1717: $auto$alumacc.cc:485:replace_alu$97233 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$le$../../asic_core/rtl/lsc1_packet_tx.sv:94$1818, $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$eq$../../asic_core/rtl/lsc1_packet_tx.sv:98$1912: $auto$alumacc.cc:485:replace_alu$97238 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ge$../../asic_core/rtl/lsc1_packet_tx.sv:51$1714: $auto$alumacc.cc:485:replace_alu$97247 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:75$2291: $auto$alumacc.cc:485:replace_alu$97256 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2280, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:79$2311: $auto$alumacc.cc:485:replace_alu$97267 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:70$2260, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:72$2271: $auto$alumacc.cc:485:replace_alu$97278 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:60$2217: $auto$alumacc.cc:485:replace_alu$97289 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:57$2204: $auto$alumacc.cc:485:replace_alu$97300 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:53$2185, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$eq$../../asic_core/rtl/lsc1_response_payload_mux.sv:55$2194: $auto$alumacc.cc:485:replace_alu$97311 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$lt$../../asic_core/rtl/lsc1_response_payload_mux.sv:51$2177, $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$procmux$5197_CMP0: $auto$alumacc.cc:485:replace_alu$97322 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2742: $auto$alumacc.cc:485:replace_alu$97333 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2732: $auto$alumacc.cc:485:replace_alu$97338 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2722: $auto$alumacc.cc:485:replace_alu$97343 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2702: $auto$alumacc.cc:485:replace_alu$97348 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2692: $auto$alumacc.cc:485:replace_alu$97353 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2682: $auto$alumacc.cc:485:replace_alu$97358 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2672: $auto$alumacc.cc:485:replace_alu$97363 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2662: $auto$alumacc.cc:485:replace_alu$97368 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2652: $auto$alumacc.cc:485:replace_alu$97373 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2642: $auto$alumacc.cc:485:replace_alu$97378 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2632: $auto$alumacc.cc:485:replace_alu$97383 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2622: $auto$alumacc.cc:485:replace_alu$97388 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2612: $auto$alumacc.cc:485:replace_alu$97393 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2602: $auto$alumacc.cc:485:replace_alu$97398 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:97$2592: $auto$alumacc.cc:485:replace_alu$97403 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:152$2571: $auto$alumacc.cc:485:replace_alu$97408 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$gt$../../asic_core/rtl/lsc1_request_validator.sv:145$2559: $auto$alumacc.cc:485:replace_alu$97413 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$lt$../../asic_core/rtl/lsc1_packet_rx.sv:134$1661: $auto$alumacc.cc:485:replace_alu$97418 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$gt$../../asic_core/rtl/lsc1_packet_rx.sv:120$1657: $auto$alumacc.cc:485:replace_alu$97429 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024: $auto$alumacc.cc:485:replace_alu$97434 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$lt$../../asic_core/rtl/lsc1_stream_adapter.sv:74$2024: $auto$alumacc.cc:485:replace_alu$97445 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$le$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3993: $auto$alumacc.cc:485:replace_alu$97456 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:888$4281: $auto$alumacc.cc:485:replace_alu$97469 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4277: $auto$alumacc.cc:485:replace_alu$97474 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:828$4246: $auto$alumacc.cc:485:replace_alu$97485 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:827$4243: $auto$alumacc.cc:485:replace_alu$97496 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:826$4240: $auto$alumacc.cc:485:replace_alu$97507 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4238: $auto$alumacc.cc:485:replace_alu$97518 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:822$4233: $auto$alumacc.cc:485:replace_alu$97529 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$gt$../../asic_core/rtl/lsc1_packet_frontend.sv:678$3990, $flatten\bridge.\g_packet.asic.\packet_core.$ne$../../asic_core/rtl/lsc1_packet_frontend.sv:686$3997: $auto$alumacc.cc:485:replace_alu$97534 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:926$4304: $auto$alumacc.cc:485:replace_alu$97543 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:925$4303: $auto$alumacc.cc:485:replace_alu$97552 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:887$4279: $auto$alumacc.cc:485:replace_alu$97561 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:830$4252: $auto$alumacc.cc:485:replace_alu$97570 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:829$4249: $auto$alumacc.cc:485:replace_alu$97583 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:820$4232: $auto$alumacc.cc:485:replace_alu$97596 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4222: $auto$alumacc.cc:485:replace_alu$97609 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:806$4221: $auto$alumacc.cc:485:replace_alu$97618 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$ge$../../asic_core/rtl/lsc1_packet_frontend.sv:684$3994: $auto$alumacc.cc:485:replace_alu$97627 + creating $alu cell for $add$ulx3s_packet_top.sv:21$159: $auto$alumacc.cc:485:replace_alu$97636 + creating $alu cell for $flatten\bridge.\utx.$add$uart_tx.sv:58$4380: $auto$alumacc.cc:485:replace_alu$97639 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:469$3430: $auto$alumacc.cc:485:replace_alu$97642 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:556$3350: $auto$alumacc.cc:485:replace_alu$97645 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:557$3351: $auto$alumacc.cc:485:replace_alu$97648 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:712$4045: $auto$alumacc.cc:485:replace_alu$97651 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:774$4204: $auto$alumacc.cc:485:replace_alu$97654 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:799$4215: $auto$alumacc.cc:485:replace_alu$97657 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:814$4226: $auto$alumacc.cc:485:replace_alu$97660 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:815$4227: $auto$alumacc.cc:485:replace_alu$97663 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:816$4228: $auto$alumacc.cc:485:replace_alu$97666 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:817$4229: $auto$alumacc.cc:485:replace_alu$97669 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:818$4230: $auto$alumacc.cc:485:replace_alu$97672 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:819$4231: $auto$alumacc.cc:485:replace_alu$97675 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$add$../../asic_core/rtl/lsc1_packet_frontend.sv:892$4285: $auto$alumacc.cc:485:replace_alu$97678 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:825$4237: $auto$alumacc.cc:485:replace_alu$97681 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.$sub$../../asic_core/rtl/lsc1_packet_frontend.sv:885$4276: $auto$alumacc.cc:485:replace_alu$97684 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087: $auto$alumacc.cc:485:replace_alu$97687 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096: $auto$alumacc.cc:485:replace_alu$97690 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078: $auto$alumacc.cc:485:replace_alu$97693 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028: $auto$alumacc.cc:485:replace_alu$97696 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908: $auto$alumacc.cc:485:replace_alu$97699 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:28$2483: $auto$alumacc.cc:485:replace_alu$97702 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_alias_check.$add$../../asic_core/rtl/lsc1_blake3_alias_check.sv:30$2484: $auto$alumacc.cc:485:replace_alu$97705 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\blake3_lifecycle.$add$../../asic_core/rtl/lsc1_blake3_lifecycle.sv:62$2145: $auto$alumacc.cc:485:replace_alu$97708 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$sub$../../asic_core/rtl/lsc1_field_encoder.sv:76$2136: $auto$alumacc.cc:485:replace_alu$97711 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:139$2087: $auto$alumacc.cc:485:replace_alu$97714 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$add$../../asic_core/rtl/lsc1_stream_adapter.sv:154$2096: $auto$alumacc.cc:485:replace_alu$97717 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$neg$../../asic_core/rtl/lsc1_stream_adapter.sv:0$2078: $auto$alumacc.cc:485:replace_alu$97720 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$sub$../../asic_core/rtl/lsc1_stream_adapter.sv:77$2028: $auto$alumacc.cc:485:replace_alu$97723 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$2908: $auto$alumacc.cc:485:replace_alu$97726 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:131$1660: $auto$alumacc.cc:485:replace_alu$97729 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$add$../../asic_core/rtl/lsc1_packet_rx.sv:166$1705: $auto$alumacc.cc:485:replace_alu$97732 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$sub$../../asic_core/rtl/lsc1_packet_rx.sv:145$1700: $auto$alumacc.cc:485:replace_alu$97735 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:73$2279: $auto$alumacc.cc:485:replace_alu$97738 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$add$../../asic_core/rtl/lsc1_response_payload_mux.sv:81$2315: $auto$alumacc.cc:485:replace_alu$97741 + creating $alu cell for $flatten\bridge.\utx.$add$uart_tx.sv:55$4379: $auto$alumacc.cc:485:replace_alu$97744 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:54$2190: $auto$alumacc.cc:485:replace_alu$97747 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:58$2209: $auto$alumacc.cc:485:replace_alu$97750 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:61$2220: $auto$alumacc.cc:485:replace_alu$97753 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:64$2228: $auto$alumacc.cc:485:replace_alu$97756 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:71$2267: $auto$alumacc.cc:485:replace_alu$97759 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:74$2287: $auto$alumacc.cc:485:replace_alu$97762 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\response_payload_mux.$sub$../../asic_core/rtl/lsc1_response_payload_mux.sv:78$2305: $auto$alumacc.cc:485:replace_alu$97765 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:104$1993: $auto$alumacc.cc:485:replace_alu$97768 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:108$1995: $auto$alumacc.cc:485:replace_alu$97771 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:51$1716: $auto$alumacc.cc:485:replace_alu$97774 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$add$../../asic_core/rtl/lsc1_packet_tx.sv:94$1817: $auto$alumacc.cc:485:replace_alu$97777 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:52$1719: $auto$alumacc.cc:485:replace_alu$97780 + creating $alu cell for $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$sub$../../asic_core/rtl/lsc1_packet_tx.sv:63$1730: $auto$alumacc.cc:485:replace_alu$97783 + creating $alu cell for $flatten\bridge.\urx.$add$uart_rx.sv:69$4414: $auto$alumacc.cc:485:replace_alu$97786 + creating $alu cell for $flatten\bridge.\urx.$add$uart_rx.sv:86$4433: $auto$alumacc.cc:485:replace_alu$97789 + creating $alu cell for $flatten\bridge.\urx.$neg$uart_rx.sv:0$4422: $auto$alumacc.cc:485:replace_alu$97792 + creating $alu cell for $flatten\bridge.\urx.$sub$uart_rx.sv:72$4420: $auto$alumacc.cc:485:replace_alu$97795 + created 103 $alu and 2 $macc cells. + +26.23. Executing OPT pass (performing simple optimizations). + +26.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$95660: { $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:656$3852_Y $flatten\bridge.\g_packet.asic.\packet_core.$eq$../../asic_core/rtl/lsc1_packet_frontend.sv:675$3957_Y $flatten\bridge.\g_packet.asic.\packet_core.$logic_and$../../asic_core/rtl/lsc1_packet_frontend.sv:683$3995_Y $auto$alumacc.cc:501:replace_alu$97535 $auto$alumacc.cc:502:replace_alu$97536 [7] $auto$rtlil.cc:2401:Not$93451 $auto$rtlil.cc:2401:Not$93833 $auto$rtlil.cc:2401:Not$93839 $auto$rtlil.cc:2401:Not$93841 $auto$rtlil.cc:2401:Not$93843 $auto$rtlil.cc:2401:Not$93845 $auto$rtlil.cc:2401:Not$93847 $auto$rtlil.cc:2401:Not$93849 $auto$rtlil.cc:2401:Not$93851 $auto$rtlil.cc:2401:Not$93853 $auto$rtlil.cc:2401:Not$93855 $auto$rtlil.cc:2401:Not$93857 $auto$rtlil.cc:2401:Not$93859 $auto$rtlil.cc:2401:Not$95628 $auto$rtlil.cc:2401:Not$95634 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$91485: { $auto$alumacc.cc:501:replace_alu$97239 $auto$rtlil.cc:2401:Not$91483 $auto$rtlil.cc:2405:ReduceOr$97246 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$logic_and$../../asic_core/rtl/lsc1_packet_tx.sv:93$1796_Y } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$91459: { $auto$alumacc.cc:501:replace_alu$97239 $auto$rtlil.cc:2405:ReduceOr$97246 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$logic_and$../../asic_core/rtl/lsc1_packet_tx.sv:93$1796_Y } + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 3 changes. + +26.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.23.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 9 unused cells and 80 unused wires. + + +26.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.23.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.23.16. Finished OPT passes. (There is nothing left to do.) + +26.24. Executing MEMORY pass. + +26.24.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +26.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 2 transformations. + +26.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address write port 0. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address write port 1. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value write port 0. + Analyzing ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value write port 1. + +26.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +26.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_address'[0] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_address'[1] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_value'[0] in module `\ulx3s_packet_top': no output FF found. +Checking read port `\bridge.g_packet.asic.packet_core.staged_write_value'[1] in module `\ulx3s_packet_top': no output FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_address'[0] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_address'[1] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_value'[0] in module `\ulx3s_packet_top': no address FF found. +Checking read port address `\bridge.g_packet.asic.packet_core.staged_write_value'[1] in module `\ulx3s_packet_top': no address FF found. + +26.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address by address: + Merging ports 0, 1 (address 1'1). +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address by address: +Consolidating read ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value by address: + Merging ports 0, 1 (address 1'1). +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value by address: +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address using sat-based resource sharing: + Checking group clocked with posedge \bridge.clk, width 32: ports 0, 1. + Common input cone for all EN signals: 88 cells. + Size of unconstrained SAT problem: 2798 variables, 6514 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating write ports of memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value using sat-based resource sharing: + Checking group clocked with posedge \bridge.clk, width 128: ports 0, 1. + Common input cone for all EN signals: 88 cells. + Size of unconstrained SAT problem: 2798 variables, 6514 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. + +26.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +26.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +26.25. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). +using FF mapping for memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_address +using FF mapping for memory ulx3s_packet_top.bridge.g_packet.asic.packet_core.staged_write_value + + +26.27. Executing TECHMAP pass (map to technology primitives). + +26.27.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/lutrams_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +26.27.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/brams_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ECP5_DP16KD_'. +Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. +Successfully finished Verilog frontend. + +26.27.3. Continuing TECHMAP pass. +No more expansions possible. + + +26.28. Executing OPT pass (performing simple optimizations). + +26.28.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.28.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 209 cells. + +26.28.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$95371 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\n_deferred[31:0], Q = \bridge.g_packet.asic.packet_core.n_deferred, rval = 0). +Adding SRST signal on $auto$ff.cc:266:slice$94940 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\deferred_target[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_target, rval = 0). +Adding SRST signal on $auto$ff.cc:266:slice$94895 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.$4\deferred_local[31:0], Q = \bridge.g_packet.asic.packet_core.deferred_local, rval = 0). + +26.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 41 unused cells and 1950 unused wires. + + +26.28.5. Rerunning OPT passes. (Removed registers in this run.) + +26.28.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.28.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.28.8. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$91491 ($dffe) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [188:0], Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [189:1], rval = 189'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $auto$ff.cc:266:slice$91491 ($dffe) from module ulx3s_packet_top (D = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ne$../../asic_core/rtl/lsc1_packet_rx.sv:124$1658_Y, Q = \bridge.g_packet.asic.packet_core.receiver.payload_write_enable [0], rval = 1'0). + +26.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 1 unused cells and 6 unused wires. + + +26.28.10. Rerunning OPT passes. (Removed registers in this run.) + +26.28.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.28.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.28.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.28.15. Finished fast OPT passes. + +26.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \bridge.g_packet.asic.packet_core.staged_write_address in module \ulx3s_packet_top: + created 2 $dff cells and 0 static cells of width 32. + read interface: 0 $dff and 0 $mux cells. + write interface: 4 write mux blocks. +Mapping memory \bridge.g_packet.asic.packet_core.staged_write_value in module \ulx3s_packet_top: + created 2 $dff cells and 0 static cells of width 128. + read interface: 0 $dff and 0 $mux cells. + write interface: 4 write mux blocks. + +26.30. Executing OPT pass (performing simple optimizations). + +26.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 2 cells. + +26.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$12987: + Old ports: A=4'0011, B=4'1011, Y=$auto$wreduce.cc:461:run$97095 [3:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97095 [3] + New connections: $auto$wreduce.cc:461:run$97095 [2:0] = 3'011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13129: + Old ports: A=4'0111, B=4'1111, Y=$auto$wreduce.cc:461:run$97094 [3:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97094 [3] + New connections: $auto$wreduce.cc:461:run$97094 [2:0] = 3'111 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 12'000000000001 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 12'000000000010 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [15:0] + New ports: A={ 2'01 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 2'10 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [5:0] + New connections: $auto$wreduce.cc:461:run$97093 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$16945: + Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:461:run$97083 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97083 [1] + New connections: $auto$wreduce.cc:461:run$97083 [0] = 1'0 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17206: + Old ports: A={ 6'000000 $auto$wreduce.cc:461:run$97083 [1:0] }, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] + New ports: A=$auto$wreduce.cc:461:run$97083 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24082: + Old ports: A={ 31'0000000000000000000000000000000 $auto$wreduce.cc:461:run$97087 [0] }, B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] + New ports: A=$auto$wreduce.cc:461:run$97087 [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29049: + Old ports: A=8'00000000, B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71676: + Old ports: A=6'010011, B=6'100011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0] + New ports: A=2'01, B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:4] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [3:0] = 4'0011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739: + Old ports: A={ 10'0000000000 $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0] }, B=16'0000000000100111, Y=$auto$wreduce.cc:461:run$97086 [15:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0], B=6'100111, Y=$auto$wreduce.cc:461:run$97086 [5:0] + New connections: $auto$wreduce.cc:461:run$97086 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75588: + Old ports: A=6'011011, B=6'100011, Y=$auto$wreduce.cc:461:run$97063 [5:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] } + New connections: { $auto$wreduce.cc:461:run$97063 [4] $auto$wreduce.cc:461:run$97063 [2:0] } = { $auto$wreduce.cc:461:run$97063 [3] 3'011 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97063 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97080 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97080 [5:0] + New connections: $auto$wreduce.cc:461:run$97080 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97063 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97058 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97058 [5:0] + New connections: $auto$wreduce.cc:461:run$97058 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80194: + Old ports: A=6'011011, B=6'100011, Y=$auto$wreduce.cc:461:run$97046 [5:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97046 [5] $auto$wreduce.cc:461:run$97046 [3] } + New connections: { $auto$wreduce.cc:461:run$97046 [4] $auto$wreduce.cc:461:run$97046 [2:0] } = { $auto$wreduce.cc:461:run$97046 [3] 3'011 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97046 [5:0] }, B=16'0000000000101111, Y=$auto$wreduce.cc:461:run$97102 [15:0] + New ports: A=$auto$wreduce.cc:461:run$97046 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97102 [5:0] + New connections: $auto$wreduce.cc:461:run$97102 [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078: + Old ports: A=8'10001100, B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [1] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096: + Old ports: A=8'10000111, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y + New ports: A=2'01, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [3:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114: + Old ports: A=8'10000001, B=8'10000110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y + New ports: A=2'01, B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143: + Old ports: A=8'10001100, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [2:1] } = { 5'10001 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176: + Old ports: A=8'10001010, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [2:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84176_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194: + Old ports: A=8'10001100, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y + New ports: A=2'10, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [2:1] } = { 5'10001 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84194_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204: + Old ports: A=8'10001101, B=8'10010000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y + New ports: A=2'01, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [3:1] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255: + Old ports: A=8'00000010, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [3:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] 6'000010 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262: + Old ports: A=8'10010010, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [3:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] 6'000010 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273: + Old ports: A=8'10000110, B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [7:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291: + Old ports: A=8'00000011, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [7] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [6:0] = 7'0000011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323: + Old ports: A=8'00000000, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84323_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335: + Old ports: A=8'00000000, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [7:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353: + Old ports: A=8'00000000, B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [1:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363: + Old ports: A=8'00000000, B=8'10001101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126: + Old ports: A={ 6'000000 $auto$wreduce.cc:461:run$97114 [1:0] }, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y + New ports: A=$auto$wreduce.cc:461:run$97114 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447: + Old ports: A=8'00000010, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y + New ports: A=2'10, B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808: + Old ports: A=8'00000000, B={ 6'000000 $auto$wreduce.cc:461:run$97117 [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y + New ports: A=2'00, B=$auto$wreduce.cc:461:run$97117 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826: + Old ports: A=8'00000000, B={ 6'000000 $auto$wreduce.cc:461:run$97116 [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y + New ports: A=2'00, B=$auto$wreduce.cc:461:run$97116 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873: + Old ports: A=8'00000000, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [7:1] = { 6'000000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86873_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906: + Old ports: A=8'00000000, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [7:1] = { 6'000000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86906_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87298: + Old ports: A=5'10000, B=5'00101, Y=$auto$wreduce.cc:461:run$97110 [4:0] + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97110 [4] $auto$wreduce.cc:461:run$97110 [0] } + New connections: $auto$wreduce.cc:461:run$97110 [3:1] = { 1'0 $auto$wreduce.cc:461:run$97110 [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301: + Old ports: A=16'0000000000000101, B={ 11'00000000000 $auto$wreduce.cc:461:run$97110 [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y + New ports: A=5'00101, B=$auto$wreduce.cc:461:run$97110 [4:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87305: + Old ports: A=5'00101, B=5'10000, Y=$auto$wreduce.cc:461:run$97111 [4:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$97111 [4] $auto$wreduce.cc:461:run$97111 [0] } + New connections: $auto$wreduce.cc:461:run$97111 [3:1] = { 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87316: + Old ports: A=4'0101, B=4'1110, Y=$auto$wreduce.cc:461:run$97112 [3:0] + New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:461:run$97112 [1:0] + New connections: $auto$wreduce.cc:461:run$97112 [3:2] = { $auto$wreduce.cc:461:run$97112 [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319: + Old ports: A=16'0000000000000101, B={ 12'000000000000 $auto$wreduce.cc:461:run$97112 [3:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y + New ports: A=4'0101, B=$auto$wreduce.cc:461:run$97112 [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87334: + Old ports: A=5'10100, B=5'00101, Y=$auto$wreduce.cc:461:run$97113 [4:0] + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97113 [4] $auto$wreduce.cc:461:run$97113 [0] } + New connections: $auto$wreduce.cc:461:run$97113 [3:1] = 3'010 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345: + Old ports: A={ 10'0000000000 $auto$wreduce.cc:461:run$97090 [5:0] }, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y + New ports: A=$auto$wreduce.cc:461:run$97090 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$ternary$../../asic_core/rtl/lsc1_packet_frontend.sv:1020$4365: + Old ports: A=2'11, B=2'01, Y=$auto$wreduce.cc:461:run$97114 [1:0] + New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$97114 [1] + New connections: $auto$wreduce.cc:461:run$97114 [0] = 1'1 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7864: { $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7609_CMP $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:57$2009_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$eq$../../asic_core/rtl/lsc1_stream_adapter.sv:60$2010_Y $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3\core_rx_valid[0:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868: + Old ports: A=3'000, B=3'100, Y=$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y [2] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7868_Y [1:0] = 2'00 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$procmux$7901: $flatten\bridge.\g_packet.asic.\packet_core.\adapter.$3\core_rx_valid[0:0] + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4491: { $auto$opt_reduce.cc:134:opt_pmux$98364 $auto$opt_reduce.cc:134:opt_pmux$98362 } + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.$procmux$4640: + Old ports: A=4'0000, B=12'000111111000, Y=$auto$wreduce.cc:461:run$97122 [3:0] + New ports: A=3'000, B=9'001111100, Y={ $auto$wreduce.cc:461:run$97122 [3] $auto$wreduce.cc:461:run$97122 [1:0] } + New connections: $auto$wreduce.cc:461:run$97122 [2] = $auto$wreduce.cc:461:run$97122 [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\adapter.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97124 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98156 [120] + New connections: $auto$wreduce.cc:461:run$97124 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] $auto$opt_expr.cc:205:group_cell_inputs$98156 [120] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.$ternary$../../asic_core/rtl/lsc1_field_encoder.sv:28$2131: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97128 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98150 [120] + New connections: $auto$wreduce.cc:461:run$97128 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] $auto$opt_expr.cc:205:group_cell_inputs$98150 [120] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7901: \bridge.g_packet.asic.packet_core.field_encoder.multiplier.state [4] + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4491: { $auto$opt_reduce.cc:134:opt_pmux$98368 $auto$opt_reduce.cc:134:opt_pmux$98366 } + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.$procmux$4640: + Old ports: A=4'0000, B=12'000111111000, Y=$auto$wreduce.cc:461:run$97130 [3:0] + New ports: A=3'000, B=9'001111100, Y={ $auto$wreduce.cc:461:run$97130 [3] $auto$wreduce.cc:461:run$97130 [1:0] } + New connections: $auto$wreduce.cc:461:run$97130 [2] = $auto$wreduce.cc:461:run$97130 [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.\datapath.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$3096: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:461:run$97132 [7:1] $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:205:group_cell_inputs$98153 [120] + New connections: $auto$wreduce.cc:461:run$97132 [7:1] = { $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] 4'0000 $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] $auto$opt_expr.cc:205:group_cell_inputs$98153 [120] } + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12397: $auto$opt_reduce.cc:134:opt_pmux$98370 + New ctrl vector for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12473: \bridge.g_packet.asic.packet_core.receiver.state [1] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580: + Old ports: A=8'10000101, B=8'10000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y + New ports: A=1'1, B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [2] + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [1:0] } = 7'1000001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1595: + Old ports: A={ 25'0111111111111111111111111 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7:1] }, B={ 25'1001001001000111011111001 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] $auto$opt_expr.cc:205:group_cell_inputs$98231 [0] $auto$opt_expr.cc:205:group_cell_inputs$98227 [5:1] }, Y={ $auto$wreduce.cc:461:run$97133 [30:0] $auto$wreduce.cc:461:run$97137 [0] } + New ports: A={ 2'01 $auto$opt_expr.cc:205:group_cell_inputs$98227 [6] }, B={ 2'10 $auto$opt_expr.cc:205:group_cell_inputs$98231 [0] }, Y={ $auto$wreduce.cc:461:run$97133 [30] $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [4] } + New connections: { $auto$wreduce.cc:461:run$97133 [29:8] $auto$wreduce.cc:461:run$97133 [6:5] $auto$wreduce.cc:461:run$97133 [3:0] $auto$wreduce.cc:461:run$97137 [0] } = { $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] $auto$wreduce.cc:461:run$97133 [7] 3'111 $auto$wreduce.cc:461:run$97133 [7] 5'11111 $auto$wreduce.cc:461:run$97133 [7] 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] $auto$opt_expr.cc:205:group_cell_inputs$98227 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 [12:11] $auto$wreduce.cc:461:run$97133 [28] $auto$opt_expr.cc:205:group_cell_inputs$98235 [10:9] $auto$wreduce.cc:461:run$97133 [25] $auto$opt_expr.cc:205:group_cell_inputs$98235 [8:7] $auto$wreduce.cc:461:run$97133 [22] $auto$opt_expr.cc:205:group_cell_inputs$98235 [6:4] $auto$wreduce.cc:461:run$97133 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98235 [3] $auto$wreduce.cc:461:run$97133 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98235 [2:1] $auto$wreduce.cc:461:run$97133 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98235 [0] $auto$wreduce.cc:461:run$97133 [4:0] }, Y={ $auto$wreduce.cc:461:run$97134 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:29] $auto$wreduce.cc:461:run$97133 [27:26] $auto$wreduce.cc:461:run$97133 [24:23] $auto$wreduce.cc:461:run$97133 [21:19] $auto$wreduce.cc:461:run$97133 [15] $auto$wreduce.cc:461:run$97133 [9:8] $auto$wreduce.cc:461:run$97133 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 }, Y={ $auto$wreduce.cc:461:run$97134 [30:28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New connections: { $auto$wreduce.cc:461:run$97134 [27] $auto$wreduce.cc:461:run$97134 [24] $auto$wreduce.cc:461:run$97134 [21] $auto$wreduce.cc:461:run$97134 [17:15] $auto$wreduce.cc:461:run$97134 [13:9] $auto$wreduce.cc:461:run$97134 [6:5] $auto$wreduce.cc:461:run$97134 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599_Y [0] } = { $auto$wreduce.cc:461:run$97133 [28] $auto$wreduce.cc:461:run$97133 [25] $auto$wreduce.cc:461:run$97133 [22] $auto$wreduce.cc:461:run$97133 [18:16] $auto$wreduce.cc:461:run$97133 [14:10] $auto$wreduce.cc:461:run$97133 [7:6] $auto$wreduce.cc:461:run$97133 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 [12:11] $auto$wreduce.cc:461:run$97134 [28] $auto$opt_expr.cc:205:group_cell_inputs$98239 [10:9] $auto$wreduce.cc:461:run$97134 [25] $auto$opt_expr.cc:205:group_cell_inputs$98239 [8:7] $auto$wreduce.cc:461:run$97134 [22] $auto$opt_expr.cc:205:group_cell_inputs$98239 [6:4] $auto$wreduce.cc:461:run$97134 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98239 [3] $auto$wreduce.cc:461:run$97134 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98239 [2:1] $auto$wreduce.cc:461:run$97134 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98239 [0] $auto$wreduce.cc:461:run$97134 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [27:26] $auto$wreduce.cc:461:run$97134 [24:23] $auto$wreduce.cc:461:run$97134 [21:19] $auto$wreduce.cc:461:run$97134 [15] $auto$wreduce.cc:461:run$97134 [9:8] $auto$wreduce.cc:461:run$97134 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603_Y [0] } = { $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [25] $auto$wreduce.cc:461:run$97134 [22] $auto$wreduce.cc:461:run$97134 [18:16] $auto$wreduce.cc:461:run$97134 [14:10] $auto$wreduce.cc:461:run$97134 [7:6] $auto$wreduce.cc:461:run$97134 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98243 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98243 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98243 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98243 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98243 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98243 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97135 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: { $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $auto$wreduce.cc:461:run$97135 [17:15] $auto$wreduce.cc:461:run$97135 [13:9] $auto$wreduce.cc:461:run$97135 [6:5] $auto$wreduce.cc:461:run$97135 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 [12:11] $auto$wreduce.cc:461:run$97135 [28] $auto$opt_expr.cc:205:group_cell_inputs$98247 [10:9] $auto$wreduce.cc:461:run$97135 [25] $auto$opt_expr.cc:205:group_cell_inputs$98247 [8:7] $auto$wreduce.cc:461:run$97135 [22] $auto$opt_expr.cc:205:group_cell_inputs$98247 [6:4] $auto$wreduce.cc:461:run$97135 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98247 [3] $auto$wreduce.cc:461:run$97135 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98247 [2:1] $auto$wreduce.cc:461:run$97135 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98247 [0] $auto$wreduce.cc:461:run$97135 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27:26] $auto$wreduce.cc:461:run$97135 [24:23] $auto$wreduce.cc:461:run$97135 [21:19] $auto$wreduce.cc:461:run$97135 [15] $auto$wreduce.cc:461:run$97135 [9:8] $auto$wreduce.cc:461:run$97135 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611_Y [0] } = { $auto$wreduce.cc:461:run$97135 [28] $auto$wreduce.cc:461:run$97135 [25] $auto$wreduce.cc:461:run$97135 [22] $auto$wreduce.cc:461:run$97135 [18:16] $auto$wreduce.cc:461:run$97135 [14:10] $auto$wreduce.cc:461:run$97135 [7:6] $auto$wreduce.cc:461:run$97135 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98251 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98251 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98251 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98251 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98251 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98251 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98255 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98255 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98255 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98255 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98255 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98255 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1623: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98259 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98259 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98259 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98259 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98259 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98259 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.receiver.crc [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98266 [12:11] \bridge.g_packet.asic.packet_core.receiver.crc [29] $auto$opt_expr.cc:205:group_cell_inputs$98266 [10:9] \bridge.g_packet.asic.packet_core.receiver.crc [26] $auto$opt_expr.cc:205:group_cell_inputs$98266 [8:7] \bridge.g_packet.asic.packet_core.receiver.crc [23] $auto$opt_expr.cc:205:group_cell_inputs$98266 [6:4] \bridge.g_packet.asic.packet_core.receiver.crc [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98266 [3] \bridge.g_packet.asic.packet_core.receiver.crc [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98266 [2:1] \bridge.g_packet.asic.packet_core.receiver.crc [8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7] $auto$opt_expr.cc:205:group_cell_inputs$98266 [0] $auto$opt_expr.cc:205:group_cell_inputs$98263 [5:1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.receiver.crc [31:30] \bridge.g_packet.asic.packet_core.receiver.crc [28:27] \bridge.g_packet.asic.packet_core.receiver.crc [25:24] \bridge.g_packet.asic.packet_core.receiver.crc [22:20] \bridge.g_packet.asic.packet_core.receiver.crc [16] \bridge.g_packet.asic.packet_core.receiver.crc [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98263 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98266 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1628_Y [0] } = { \bridge.g_packet.asic.packet_core.receiver.crc [29] \bridge.g_packet.asic.packet_core.receiver.crc [26] \bridge.g_packet.asic.packet_core.receiver.crc [23] \bridge.g_packet.asic.packet_core.receiver.crc [19:17] \bridge.g_packet.asic.packet_core.receiver.crc [15:11] \bridge.g_packet.asic.packet_core.receiver.crc [8] $auto$opt_expr.cc:205:group_cell_inputs$98263 [7] $auto$opt_expr.cc:205:group_cell_inputs$98263 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98270 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98270 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98270 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98270 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98270 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98270 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98270 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98270 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1632_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1629_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98274 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98274 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98274 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98274 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98274 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98274 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98274 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98274 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1636_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1633_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98278 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98278 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98278 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98278 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98278 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98278 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98278 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98278 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1640_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1637_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98282 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98282 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98282 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98282 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98282 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98282 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98282 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98282 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1644_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1641_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98286 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98286 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98286 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98286 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98286 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98286 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98286 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97136 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98286 }, Y={ $auto$wreduce.cc:461:run$97136 [30:28] $auto$wreduce.cc:461:run$97136 [26:25] $auto$wreduce.cc:461:run$97136 [23:22] $auto$wreduce.cc:461:run$97136 [20:18] $auto$wreduce.cc:461:run$97136 [14] $auto$wreduce.cc:461:run$97136 [8:7] $auto$wreduce.cc:461:run$97136 [4] } + New connections: { $auto$wreduce.cc:461:run$97136 [27] $auto$wreduce.cc:461:run$97136 [24] $auto$wreduce.cc:461:run$97136 [21] $auto$wreduce.cc:461:run$97136 [17:15] $auto$wreduce.cc:461:run$97136 [13:9] $auto$wreduce.cc:461:run$97136 [6:5] $auto$wreduce.cc:461:run$97136 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1648_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1645_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97136 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98290 [12:11] $auto$wreduce.cc:461:run$97136 [28] $auto$opt_expr.cc:205:group_cell_inputs$98290 [10:9] $auto$wreduce.cc:461:run$97136 [25] $auto$opt_expr.cc:205:group_cell_inputs$98290 [8:7] $auto$wreduce.cc:461:run$97136 [22] $auto$opt_expr.cc:205:group_cell_inputs$98290 [6:4] $auto$wreduce.cc:461:run$97136 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98290 [3] $auto$wreduce.cc:461:run$97136 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98290 [2:1] $auto$wreduce.cc:461:run$97136 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98290 [0] $auto$wreduce.cc:461:run$97136 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97136 [30:29] $auto$wreduce.cc:461:run$97136 [27:26] $auto$wreduce.cc:461:run$97136 [24:23] $auto$wreduce.cc:461:run$97136 [21:19] $auto$wreduce.cc:461:run$97136 [15] $auto$wreduce.cc:461:run$97136 [9:8] $auto$wreduce.cc:461:run$97136 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98290 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1652_Y [0] } = { $auto$wreduce.cc:461:run$97136 [28] $auto$wreduce.cc:461:run$97136 [25] $auto$wreduce.cc:461:run$97136 [22] $auto$wreduce.cc:461:run$97136 [18:16] $auto$wreduce.cc:461:run$97136 [14:10] $auto$wreduce.cc:461:run$97136 [7:6] $auto$wreduce.cc:461:run$97136 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1656: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98294 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98294 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98294 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98294 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98294 [3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98294 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98294 [0] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98294 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12395_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1653_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4789: + Old ports: A=8'00000000, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] + New ports: A=1'0, B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [7:1] = { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4852: + Old ports: A=2'00, B=2'11, Y=$auto$wreduce.cc:461:run$97142 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$97142 [0] + New connections: $auto$wreduce.cc:461:run$97142 [1] = $auto$wreduce.cc:461:run$97142 [0] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98160 [12:11] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [29] $auto$opt_expr.cc:205:group_cell_inputs$98160 [10:9] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [26] $auto$opt_expr.cc:205:group_cell_inputs$98160 [8:7] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [23] $auto$opt_expr.cc:205:group_cell_inputs$98160 [6:4] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98160 [3] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98160 [2:1] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7] $auto$opt_expr.cc:205:group_cell_inputs$98160 [0] $auto$opt_expr.cc:205:group_cell_inputs$98157 [5:1] }, Y={ $auto$wreduce.cc:461:run$97162 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [31:30] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [28:27] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [25:24] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [22:20] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [16] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98157 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98160 }, Y={ $auto$wreduce.cc:461:run$97162 [30:28] $auto$wreduce.cc:461:run$97162 [26:25] $auto$wreduce.cc:461:run$97162 [23:22] $auto$wreduce.cc:461:run$97162 [20:18] $auto$wreduce.cc:461:run$97162 [14] $auto$wreduce.cc:461:run$97162 [8:7] $auto$wreduce.cc:461:run$97162 [4] } + New connections: { $auto$wreduce.cc:461:run$97162 [27] $auto$wreduce.cc:461:run$97162 [24] $auto$wreduce.cc:461:run$97162 [21] $auto$wreduce.cc:461:run$97162 [17:15] $auto$wreduce.cc:461:run$97162 [13:9] $auto$wreduce.cc:461:run$97162 [6:5] $auto$wreduce.cc:461:run$97162 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1843_Y [0] } = { \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [29] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [26] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [23] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [19:17] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [15:11] \bridge.g_packet.asic.packet_core.transmitter.envelope_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98157 [7] $auto$opt_expr.cc:205:group_cell_inputs$98157 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97162 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98164 [12:11] $auto$wreduce.cc:461:run$97162 [28] $auto$opt_expr.cc:205:group_cell_inputs$98164 [10:9] $auto$wreduce.cc:461:run$97162 [25] $auto$opt_expr.cc:205:group_cell_inputs$98164 [8:7] $auto$wreduce.cc:461:run$97162 [22] $auto$opt_expr.cc:205:group_cell_inputs$98164 [6:4] $auto$wreduce.cc:461:run$97162 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98164 [3] $auto$wreduce.cc:461:run$97162 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98164 [2:1] $auto$wreduce.cc:461:run$97162 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98164 [0] $auto$wreduce.cc:461:run$97162 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97162 [30:29] $auto$wreduce.cc:461:run$97162 [27:26] $auto$wreduce.cc:461:run$97162 [24:23] $auto$wreduce.cc:461:run$97162 [21:19] $auto$wreduce.cc:461:run$97162 [15] $auto$wreduce.cc:461:run$97162 [9:8] $auto$wreduce.cc:461:run$97162 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98164 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1847_Y [0] } = { $auto$wreduce.cc:461:run$97162 [28] $auto$wreduce.cc:461:run$97162 [25] $auto$wreduce.cc:461:run$97162 [22] $auto$wreduce.cc:461:run$97162 [18:16] $auto$wreduce.cc:461:run$97162 [14:10] $auto$wreduce.cc:461:run$97162 [7:6] $auto$wreduce.cc:461:run$97162 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98168 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98168 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98168 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98168 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98168 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98168 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98168 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98168 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1851_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1848_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98172 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98172 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98172 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98172 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98172 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98172 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98172 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98172 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1855_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1852_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98176 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98176 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98176 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98176 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98176 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98176 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98176 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98176 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1859_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1856_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98180 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98180 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98180 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98180 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98180 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98180 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98180 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4:0] }, Y={ $auto$wreduce.cc:461:run$97163 [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98180 }, Y={ $auto$wreduce.cc:461:run$97163 [30:28] $auto$wreduce.cc:461:run$97163 [26:25] $auto$wreduce.cc:461:run$97163 [23:22] $auto$wreduce.cc:461:run$97163 [20:18] $auto$wreduce.cc:461:run$97163 [14] $auto$wreduce.cc:461:run$97163 [8:7] $auto$wreduce.cc:461:run$97163 [4] } + New connections: { $auto$wreduce.cc:461:run$97163 [27] $auto$wreduce.cc:461:run$97163 [24] $auto$wreduce.cc:461:run$97163 [21] $auto$wreduce.cc:461:run$97163 [17:15] $auto$wreduce.cc:461:run$97163 [13:9] $auto$wreduce.cc:461:run$97163 [6:5] $auto$wreduce.cc:461:run$97163 [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1863_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1860_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97163 [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98184 [12:11] $auto$wreduce.cc:461:run$97163 [28] $auto$opt_expr.cc:205:group_cell_inputs$98184 [10:9] $auto$wreduce.cc:461:run$97163 [25] $auto$opt_expr.cc:205:group_cell_inputs$98184 [8:7] $auto$wreduce.cc:461:run$97163 [22] $auto$opt_expr.cc:205:group_cell_inputs$98184 [6:4] $auto$wreduce.cc:461:run$97163 [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98184 [3] $auto$wreduce.cc:461:run$97163 [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98184 [2:1] $auto$wreduce.cc:461:run$97163 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98184 [0] $auto$wreduce.cc:461:run$97163 [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97163 [30:29] $auto$wreduce.cc:461:run$97163 [27:26] $auto$wreduce.cc:461:run$97163 [24:23] $auto$wreduce.cc:461:run$97163 [21:19] $auto$wreduce.cc:461:run$97163 [15] $auto$wreduce.cc:461:run$97163 [9:8] $auto$wreduce.cc:461:run$97163 [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98184 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1867_Y [0] } = { $auto$wreduce.cc:461:run$97163 [28] $auto$wreduce.cc:461:run$97163 [25] $auto$wreduce.cc:461:run$97163 [22] $auto$wreduce.cc:461:run$97163 [18:16] $auto$wreduce.cc:461:run$97163 [14:10] $auto$wreduce.cc:461:run$97163 [7:6] $auto$wreduce.cc:461:run$97163 [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98188 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98188 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98188 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98188 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98188 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98188 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98188 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98188 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1871_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1868_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882: + Old ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [31:8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7:1] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98195 [12:11] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [29] $auto$opt_expr.cc:205:group_cell_inputs$98195 [10:9] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [26] $auto$opt_expr.cc:205:group_cell_inputs$98195 [8:7] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [23] $auto$opt_expr.cc:205:group_cell_inputs$98195 [6:4] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [19:17] $auto$opt_expr.cc:205:group_cell_inputs$98195 [3] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [15:11] $auto$opt_expr.cc:205:group_cell_inputs$98195 [2:1] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7] $auto$opt_expr.cc:205:group_cell_inputs$98195 [0] $auto$opt_expr.cc:205:group_cell_inputs$98192 [5:1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] } + New ports: A={ 1'0 \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [31:30] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [28:27] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [25:24] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [22:20] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [16] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [10:9] $auto$opt_expr.cc:205:group_cell_inputs$98192 [6] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98195 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1882_Y [0] } = { \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [29] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [26] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [23] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [19:17] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [15:11] \bridge.g_packet.asic.packet_core.transmitter.payload_crc_work [8] $auto$opt_expr.cc:205:group_cell_inputs$98192 [7] $auto$opt_expr.cc:205:group_cell_inputs$98192 [5:1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98199 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98199 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98199 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98199 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98199 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98199 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98199 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98199 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1886_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1883_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98203 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98203 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98203 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98203 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98203 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98203 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98203 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98203 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1890_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1887_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98207 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98207 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98207 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98207 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98207 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98207 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98207 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98207 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1894_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1891_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98211 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98211 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98211 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98211 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98211 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98211 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98211 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98211 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1898_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1895_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98215 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98215 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98215 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98215 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98215 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98215 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98215 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98215 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1902_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1899_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98219 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98219 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98219 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98219 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98219 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98219 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98219 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98219 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [20:18] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [27] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [21] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [17:15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [13:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [3:0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1906_Y [0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1903_Y [4:0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:0] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98223 [12:11] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [28] $auto$opt_expr.cc:205:group_cell_inputs$98223 [10:9] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [25] $auto$opt_expr.cc:205:group_cell_inputs$98223 [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [22] $auto$opt_expr.cc:205:group_cell_inputs$98223 [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [18:16] $auto$opt_expr.cc:205:group_cell_inputs$98223 [3] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14:10] $auto$opt_expr.cc:205:group_cell_inputs$98223 [2:1] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98223 [0] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [5] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98223 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [5] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$ternary$../../asic_core/rtl/lsc1_packet_tx.sv:41$1910_Y [4:0] } = { $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [18:16] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [14:10] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [7:6] $flatten\bridge.\g_packet.asic.\packet_core.\transmitter.$shr$../../asic_core/rtl/lsc1_packet_tx.sv:41$1907_Y [4:0] } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$98361: { \bridge.g_packet.asic.packet_core.adapter.datapath.state [9] \bridge.g_packet.asic.packet_core.adapter.datapath.state [7] \bridge.g_packet.asic.packet_core.adapter.datapath.state [3:1] } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$98365: { \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [9] \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [7] \bridge.g_packet.asic.packet_core.field_encoder.multiplier.datapath.state [3:1] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 2'01 $auto$wreduce.cc:461:run$97095 [3:0] }, B={ 2'10 $auto$wreduce.cc:461:run$97094 [3:0] }, Y=$auto$wreduce.cc:461:run$97093 [5:0] + New ports: A={ 1'1 $auto$wreduce.cc:461:run$97095 [3] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$97094 [3] 1'1 }, Y=$auto$wreduce.cc:461:run$97093 [4:2] + New connections: { $auto$wreduce.cc:461:run$97093 [5] $auto$wreduce.cc:461:run$97093 [1:0] } = { $auto$wreduce.cc:461:run$97093 [2] 2'11 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18214: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24484: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$35\n_writes[31:0] [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29181: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0], B=8'10010100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_fault[7:0] [0] }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [7:3] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$60678: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97090 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97090 [5:2] + New connections: $auto$wreduce.cc:461:run$97090 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$71739: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:0], B=6'100111, Y=$auto$wreduce.cc:461:run$97086 [5:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$32\result_length[31:0] [5:4] 1'0 }, B=3'101, Y={ $auto$wreduce.cc:461:run$97086 [5:4] $auto$wreduce.cc:461:run$97086 [2] } + New connections: { $auto$wreduce.cc:461:run$97086 [3] $auto$wreduce.cc:461:run$97086 [1:0] } = 3'011 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$75645: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97080 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97080 [5:2] + New connections: $auto$wreduce.cc:461:run$97080 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$78834: + Old ports: A=$auto$wreduce.cc:461:run$97063 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97058 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97063 [5] $auto$wreduce.cc:461:run$97063 [3] $auto$wreduce.cc:461:run$97063 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97058 [5:2] + New connections: $auto$wreduce.cc:461:run$97058 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$80245: + Old ports: A=$auto$wreduce.cc:461:run$97046 [5:0], B=6'101111, Y=$auto$wreduce.cc:461:run$97102 [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97046 [5] $auto$wreduce.cc:461:run$97046 [3] $auto$wreduce.cc:461:run$97046 [3] 1'0 }, B=4'1011, Y=$auto$wreduce.cc:461:run$97102 [5:2] + New connections: $auto$wreduce.cc:461:run$97102 [1:0] = 2'11 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y + New ports: A=5'00111, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84078_Y [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y, B=8'10010010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84096_Y [0] }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [3:1] } = { 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84114_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84204_Y [0] }, B=4'0110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [4:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [2] } = { 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84209_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y, B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84237_Y [2] 1'0 }, B=3'101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [6:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [1] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y + New ports: A=3'101, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84255_Y [4] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [3:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276: + Old ports: A=8'10000001, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y + New ports: A=3'101, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84273_Y [1] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84302_Y [2] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84335_Y [1] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [2] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [1] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84338_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84353_Y [2] 1'0 }, B=3'011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [3:2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [7:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [1] } = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [2] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84356_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y, B=8'10010000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84363_Y [0] }, B=3'110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [3:1] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126: + Old ports: A=$auto$wreduce.cc:461:run$97114 [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0] + New ports: A=$auto$wreduce.cc:461:run$97114 [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86447_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811: + Old ports: A=8'00000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y + New ports: A=2'00, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86808_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y, B={ 6'000000 \bridge.g_packet.asic.packet_core.blake_retire_mismatch_detail [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86826_Y [1:0], B=\bridge.g_packet.asic.packet_core.blake_retire_mismatch_detail [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270: + Old ports: A=16'0000000000000101, B=$auto$wreduce.cc:461:run$97093 [15:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y + New ports: A=6'000101, B=$auto$wreduce.cc:461:run$97093 [5:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301: + Old ports: A=5'00101, B=$auto$wreduce.cc:461:run$97110 [4:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0] + New ports: A=2'01, B={ $auto$wreduce.cc:461:run$97110 [4] $auto$wreduce.cc:461:run$97110 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y, B={ 11'00000000000 $auto$wreduce.cc:461:run$97111 [4:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0], B={ $auto$wreduce.cc:461:run$97111 [4] 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 $auto$wreduce.cc:461:run$97111 [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319: + Old ports: A=4'0101, B=$auto$wreduce.cc:461:run$97112 [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0] + New ports: A=2'01, B=$auto$wreduce.cc:461:run$97112 [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366: + Old ports: A=$auto$wreduce.cc:461:run$97086 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y + New ports: A=$auto$wreduce.cc:461:run$97086 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378: + Old ports: A=$auto$wreduce.cc:461:run$97080 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y + New ports: A=$auto$wreduce.cc:461:run$97080 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396: + Old ports: A=$auto$wreduce.cc:461:run$97058 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y + New ports: A=$auto$wreduce.cc:461:run$97058 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406: + Old ports: A=$auto$wreduce.cc:461:run$97102 [15:0], B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y + New ports: A=$auto$wreduce.cc:461:run$97102 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y, B=8'10000100, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12580_Y [2] 1'1 }, B=2'10, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [7:3] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [1] } = 6'100000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4888: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$7\fault_status[7:0] [0] }, B=2'11, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [7:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [2:1] } = { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4942: + Old ports: A=$auto$wreduce.cc:461:run$97142 [1:0], B=2'00, Y=$auto$wreduce.cc:461:run$97141 [1:0] + New ports: A=$auto$wreduce.cc:461:run$97142 [0], B=1'0, Y=$auto$wreduce.cc:461:run$97141 [0] + New connections: $auto$wreduce.cc:461:run$97141 [1] = $auto$wreduce.cc:461:run$97141 [0] + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18295: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0], B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_detail[7:0] [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24993: + Old ports: A=0, B=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] + New ports: A=1'0, B=$flatten\bridge.\g_packet.asic.\packet_core.$34\n_writes[31:0] [0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$29307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0], B=8'10000110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_fault[7:0] [0] }, B=4'0110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y, B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84081_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84102_Y [0] }, B=3'001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [1] } = 5'10001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y + New ports: A=2'10, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84117_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [7:2] = { 5'10000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243: + Old ports: A=8'10000111, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y + New ports: A=6'100111, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84240_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84258_Y [0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84262_Y [4] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [3:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y, B=8'10000111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84276_Y [1:0] }, B=3'111, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y, B=8'10001010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84366_Y [0] }, B=5'10110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [4:3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [2] } = { 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84371_Y [0] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85126_Y [1], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86452_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86811_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86832_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270: + Old ports: A=6'000101, B=$auto$wreduce.cc:461:run$97093 [5:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] + New ports: A=5'00010, B={ $auto$wreduce.cc:461:run$97093 [2] $auto$wreduce.cc:461:run$97093 [4:2] 1'1 }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y, B=16'0000000001111010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87270_Y [5:0] }, B=7'1111010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [6:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [15:7] = 9'000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4:0], B={ $auto$wreduce.cc:461:run$97111 [4] 1'0 $auto$wreduce.cc:461:run$97111 [0] 1'0 $auto$wreduce.cc:461:run$97111 [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87301_Y [0] }, B={ $auto$wreduce.cc:461:run$97111 [4] $auto$wreduce.cc:461:run$97111 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [15:5] = 11'00000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87319_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325: + Old ports: A=16'0000000000000101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y + New ports: A=4'0101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345: + Old ports: A=$auto$wreduce.cc:461:run$97090 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97090 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366: + Old ports: A=$auto$wreduce.cc:461:run$97086 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97086 [5:4] $auto$wreduce.cc:461:run$97086 [2] 1'1 }, B=4'0010, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [5:4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [2:1] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87366_Y [0] } = 2'01 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378: + Old ports: A=$auto$wreduce.cc:461:run$97080 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97080 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396: + Old ports: A=$auto$wreduce.cc:461:run$97058 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97058 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406: + Old ports: A=$auto$wreduce.cc:461:run$97102 [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0] + New ports: A={ $auto$wreduce.cc:461:run$97102 [5:2] 1'1 }, B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $pmux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590: + Old ports: A=8'10000000, B={ 8'10000011 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y + New ports: A=3'000, B={ 3'011 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [2] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12583_Y [0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y [2:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12590_Y [7:3] = 5'10000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$4972: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0], B=8'10001000, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$6\fault_status[7:0] [0] }, B=3'110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [2:1] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15046: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=4'1110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17032: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=5'01111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [7:5] = { $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17459: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18832: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$23806: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10001100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=5'01100, Y=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [7:5] = { $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [2] 2'00 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26380: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B=4'1101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$28929: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0], B=0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$33\n_writes[31:0] [0], B=1'0, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] [0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\n_writes[31:0] [31:1] = 31'0000000000000000000000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84084_Y [4:0], B=5'00011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [4:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [7:5] = 3'100 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84120_Y [1:0] }, B=3'011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [2:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [7:3] = 5'10000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y, B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84243_Y [4:0] }, B=6'100101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84264_Y [0] }, B=4'1001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [2] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [6:5] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [1] } = 4'0001 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y + New ports: A=3'110, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84279_Y [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [6:2] = { 4'0000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85141_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86455_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86814_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87273_Y [6:0], B=7'0000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y [6:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87276_Y [15:7] = 9'000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4:0], B=5'00101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87307_Y [0] }, B=2'01, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [4] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [3:1] = { 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87310_Y [0] 1'0 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325: + Old ports: A=4'0101, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [3:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0] + New ports: A=2'01, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87322_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [15:4] = 12'000000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87345_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87348_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87378_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87381_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87396_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87399_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87406_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y, B=16'0000000000000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [15:6] = 10'0000000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5041: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0], B=8'10000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$5\fault_status[7:0] [0] }, B=4'1001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [1:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [6:4] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [2] } = { 3'000 $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [0] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15202: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17290: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$44\decision_fault[7:0] [4:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$17720: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$42\decision_fault[7:0] [4:0] }, B=6'110101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19123: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$21154: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0], B=8'10010101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$35\decision_fault[7:0] [2:0] }, B=4'1101, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24220: + Old ports: A=8'10001001, B=$flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] + New ports: A=6'101001, B={ $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$31\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26530: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$28\decision_fault[7:0] [2:0] }, B=4'1110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [4] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2:0] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [7:5] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [3] } = { $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2] 3'000 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84246_Y [4:0] }, B=6'100011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84282_Y [1:0] }, B=4'1011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [2:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [6:3] = 4'0000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85153_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y, B=8'00000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86478_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [3:0], B=4'0101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87325_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [3:2] = { $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87328_Y [1] 1'1 } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:0], B=6'000101, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87409_Y [5:1], B=5'00010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [5:1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$87414_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5095: + Old ports: A=8'10000110, B=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] + New ports: A=5'10110, B={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [3] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [0] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$4\fault_status[7:0] [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [3:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14093: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], B=8'10001011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, B=6'101011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18133: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$43\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$41\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19548: + Old ports: A=8'00000000, B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] + New ports: A=2'00, B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_detail[7:0] [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$21586: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$34\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26674: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$27\decision_fault[7:0] [2:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1:0], B=2'11, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85165_Y [1], B=1'1, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [1] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$85180_Y [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86490_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5134: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0], B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$3\fault_status[7:0] [3:0] }, B=5'10011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [3:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14345: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0], B=8'10001110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$51\decision_fault[7:0] [4:0] }, B=6'101110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18373: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0], B=8'10001111, Y=$flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$40\decision_fault[7:0] [4:0] }, B=6'101111, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$22989: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26812: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0], B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$26\decision_fault[7:0] [4:0] }, B=6'110001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y, B=8'00000010, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86516_Y [1:0], B=2'10, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$procmux$5164: + Old ports: A=8'10000010, B=$flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0], Y=\bridge.g_packet.asic.packet_core.request_fault_status + New ports: A=5'10010, B={ $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.\request_validator.$2\fault_status[7:0] [3:0] }, Y={ \bridge.g_packet.asic.packet_core.request_fault_status [7] \bridge.g_packet.asic.packet_core.request_fault_status [3:0] } + New connections: \bridge.g_packet.asic.packet_core.request_fault_status [6:4] = 3'000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14744: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$50\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18607: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0], B=8'10010110, Y=$flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$39\decision_fault[7:0] [4:0] }, B=6'110110, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$25434: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$22\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [7:2] = 6'000000 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$26944: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0], B=8'10010001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$25\decision_fault[7:0] [4:0] }, B=6'110001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86522_Y [1:0], B=2'01, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86525_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$14971: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$46\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$49\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$18907: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0], B=8'10001001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$38\decision_fault[7:0] [4:0] }, B=6'101001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$27609: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$21\decision_detail[7:0] [1:0], B=2'00, Y=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$15720: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2] $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$20\decision_fault[7:0] [2:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$48\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0], B={ 6'000000 \bridge.g_packet.asic.packet_core.request_fault_detail [1:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$20\decision_detail[7:0] [1:0], B=\bridge.g_packet.asic.packet_core.request_fault_detail [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$19617: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$45\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$37\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86801_Y [1:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86817_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$22131: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$36\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$33\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y + New ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86819_Y [1:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86835_Y [1:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y [1:0] + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$86837_Y [7:2] = 6'000000 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$24867: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$32\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$30\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$27189: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0], B=$flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0], Y=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$29\decision_fault[7:0] [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$24\decision_fault[7:0] [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0], B=\bridge.g_packet.asic.packet_core.request_fault_status, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] }, B={ \bridge.g_packet.asic.packet_core.request_fault_status [7] 1'0 \bridge.g_packet.asic.packet_core.request_fault_status [3:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0], B=8'00000000, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [7] $flatten\bridge.\g_packet.asic.\packet_core.$23\decision_fault[7:0] [4:0] }, B=6'000000, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84071_Y [4:0] }, B={ 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84087_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y, B=8'00000001, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84227_Y [4:0] }, B=6'000001, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84089_Y [4:0] }, B={ 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [2] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84105_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y, B=\bridge.g_packet.asic.packet_core.request_fault_status, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84230_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.request_fault_status [7] 1'0 \bridge.g_packet.asic.packet_core.request_fault_status [3:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84107_Y [4:0] }, B={ 3'100 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84123_Y [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84233_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84249_Y [4:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y, B=8'10000011, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84125_Y [4:0] }, B=6'100011, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84251_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [4] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [2] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84267_Y [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84269_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84285_Y [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y, B=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84287_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84291_Y [7] 5'00011 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 247 changes. + +26.30.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 3 cells. + +26.30.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 49 unused wires. + + +26.30.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$13197: + Old ports: A={ 1'1 $auto$wreduce.cc:461:run$97094 [3] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$97094 [3] 1'1 }, Y={ $auto$wreduce.cc:461:run$97093 [4:3] $auto$wreduce.cc:461:run$97093 [5] } + New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$97093 [4] $auto$wreduce.cc:461:run$97093 [5] } + New connections: $auto$wreduce.cc:461:run$97093 [3] = $auto$wreduce.cc:461:run$97094 [3] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1599: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30:29] 1'1 $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97133 [29] 2'11 $auto$wreduce.cc:461:run$97133 [29] $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98235 }, Y={ $auto$wreduce.cc:461:run$97134 [30:28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97133 [30] 1'1 $auto$wreduce.cc:461:run$97133 [29] $auto$opt_expr.cc:205:group_cell_inputs$98227 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98374 [1] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98374 [0] $auto$opt_expr.cc:205:group_cell_inputs$98374 [2] }, Y={ $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [4] } + New connections: { $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26:25] $auto$wreduce.cc:461:run$97134 [23:22] $auto$wreduce.cc:461:run$97134 [20:18] $auto$wreduce.cc:461:run$97134 [14] } = { $auto$wreduce.cc:461:run$97134 [7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [8:7] $auto$wreduce.cc:461:run$97134 [7] $auto$wreduce.cc:461:run$97134 [8] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [23] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [20:19] 2'11 $auto$wreduce.cc:461:run$97134 [8] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97135 [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [3] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [23] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [20:19] $auto$wreduce.cc:461:run$97134 [8] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98378 [6:3] $auto$opt_expr.cc:205:group_cell_inputs$98378 [7] $auto$opt_expr.cc:205:group_cell_inputs$98378 [2:0] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [3] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97135 [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20] $auto$wreduce.cc:461:run$97135 [3] $auto$wreduce.cc:461:run$97135 [3] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97134 [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] 2'11 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [23] $auto$wreduce.cc:461:run$97134 [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [20:19] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [8] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98382 [6:5] $auto$opt_expr.cc:205:group_cell_inputs$98382 [9] $auto$opt_expr.cc:205:group_cell_inputs$98382 [4] $auto$opt_expr.cc:205:group_cell_inputs$98382 [8] $auto$opt_expr.cc:205:group_cell_inputs$98382 [3] $auto$opt_expr.cc:205:group_cell_inputs$98382 [7] $auto$opt_expr.cc:205:group_cell_inputs$98382 [2:1] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98382 [0] $auto$opt_expr.cc:205:group_cell_inputs$98382 [10] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [8:7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: $auto$wreduce.cc:461:run$97135 [14] = $auto$wreduce.cc:461:run$97135 [8] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 4 changes. + +26.30.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.30.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_value[1]$98343 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.receiver.frame_payload_prefix [335:208], Q = \bridge.g_packet.asic.packet_core.staged_write_value[1]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_value[0]$98341 ($dff) from module ulx3s_packet_top (D = $memory\bridge.g_packet.asic.packet_core.staged_write_value$wrmux[0][1][0]$y$98352, Q = \bridge.g_packet.asic.packet_core.staged_write_value[0]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_address[1]$98315 ($dff) from module ulx3s_packet_top (D = \bridge.g_packet.asic.packet_core.staged_access[7], Q = \bridge.g_packet.asic.packet_core.staged_write_address[1]). +Adding EN signal on $memory\bridge.g_packet.asic.packet_core.staged_write_address[0]$98313 ($dff) from module ulx3s_packet_top (D = $memory\bridge.g_packet.asic.packet_core.staged_write_address$wrmux[0][1][0]$y$98328, Q = \bridge.g_packet.asic.packet_core.staged_write_address[0]). +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93299 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$96091 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$96817 ($sdffe) from module ulx3s_packet_top. + +26.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 2 unused cells and 22 unused wires. + + +26.30.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.16. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134: + Old ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 4'0000 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84131_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 2'00 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296: + Old ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] 2'00 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 4'0000 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84293_Y [4:0] }, B={ \bridge.g_packet.asic.packet_core.receiver.fault_status [7] 2'00 \bridge.g_packet.asic.packet_core.receiver.fault_status [2:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1603: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [26] $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98239 [12:11] $auto$opt_expr.cc:205:group_cell_inputs$98239 [9] $auto$opt_expr.cc:205:group_cell_inputs$98239 [7] $auto$opt_expr.cc:205:group_cell_inputs$98239 [10] $auto$opt_expr.cc:205:group_cell_inputs$98239 [5:4] $auto$opt_expr.cc:205:group_cell_inputs$98239 [1] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [13] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97134 [30:29] $auto$wreduce.cc:461:run$97133 [29] $auto$wreduce.cc:461:run$97134 [28] $auto$wreduce.cc:461:run$97134 [26] 1'1 }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98411 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98411 [4] $auto$opt_expr.cc:205:group_cell_inputs$98411 [1:0] 1'0 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97135 [27] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [13] } + New connections: { $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [21] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] } = { $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [6] $auto$wreduce.cc:461:run$97135 [6] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1607: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] 1'1 $auto$wreduce.cc:461:run$97135 [13] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98243 [12:4] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98243 [1:0] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [7] $auto$wreduce.cc:461:run$97135 [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [30:29] $auto$wreduce.cc:461:run$97134 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1604_Y [19] 1'1 $auto$wreduce.cc:461:run$97135 [13] $auto$wreduce.cc:461:run$97133 [29] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98413 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98413 [5] $auto$opt_expr.cc:205:group_cell_inputs$98413 [1:0] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98413 [4] $auto$opt_expr.cc:205:group_cell_inputs$98413 [6] }, Y={ $auto$wreduce.cc:461:run$97135 [30:28] $auto$wreduce.cc:461:run$97135 [20:18] $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97135 [7] $auto$wreduce.cc:461:run$97135 [4] } + New connections: { $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97135 [23:22] } = { $auto$wreduce.cc:461:run$97135 [20:19] $auto$wreduce.cc:461:run$97135 [20:19] } + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y, B={ 4'1000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84134_Y [4:0] }, B={ 2'10 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [3] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84143_Y [1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84145_Y [6:5] = 2'00 + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307: + Old ports: A=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] 3'000 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] }, Y=$flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y + New ports: A={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84296_Y [4:0] }, B={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] 1'0 $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [3] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84305_Y [1] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [4:0] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.$procmux$84307_Y [6:5] = 2'00 + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 6 changes. + +26.30.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 1 cells. + +26.30.20. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$93766 ($sdffe) from module ulx3s_packet_top. + +26.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 3 unused wires. + + +26.30.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.23. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1611: + Old ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27:26] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97134 [28] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98247 [12:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98247 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [12] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [2] } + New ports: A={ 1'0 $auto$wreduce.cc:461:run$97135 [30:29] $auto$wreduce.cc:461:run$97135 [27] $auto$wreduce.cc:461:run$97135 [24] $auto$wreduce.cc:461:run$97135 [26:25] $auto$wreduce.cc:461:run$97133 [29] 1'1 $auto$wreduce.cc:461:run$97135 [14] $auto$wreduce.cc:461:run$97134 [28] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98416 [6:4] $auto$opt_expr.cc:205:group_cell_inputs$98416 [1] $auto$opt_expr.cc:205:group_cell_inputs$98416 [3:2] $auto$opt_expr.cc:205:group_cell_inputs$98416 [8] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98416 [0] $auto$opt_expr.cc:205:group_cell_inputs$98416 [7] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [16] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [12] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8:7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [2] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23:22] } = { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] } + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98251 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23:22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [20:19] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98418 [6:5] $auto$opt_expr.cc:205:group_cell_inputs$98418 [9] $auto$opt_expr.cc:205:group_cell_inputs$98418 [4:3] $auto$opt_expr.cc:205:group_cell_inputs$98418 [8] $auto$opt_expr.cc:205:group_cell_inputs$98418 [2:1] $auto$opt_expr.cc:205:group_cell_inputs$98418 [10] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98418 [0] $auto$opt_expr.cc:205:group_cell_inputs$98418 [7] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [20] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 2 changes. + +26.30.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.27. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.30.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.30. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1615: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98251 [12:9] $auto$opt_expr.cc:205:group_cell_inputs$98251 [7] $auto$opt_expr.cc:205:group_cell_inputs$98251 [8] $auto$opt_expr.cc:205:group_cell_inputs$98251 [5:3] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98251 [1:0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [30:29] $auto$wreduce.cc:461:run$97135 [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [26] $auto$wreduce.cc:461:run$97135 [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $auto$wreduce.cc:461:run$97134 [28] 1'1 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [8] $auto$wreduce.cc:461:run$97135 [24] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98420 [5:4] $auto$opt_expr.cc:205:group_cell_inputs$98420 [8] $auto$opt_expr.cc:205:group_cell_inputs$98420 [3] $auto$opt_expr.cc:205:group_cell_inputs$98420 [7] $auto$opt_expr.cc:205:group_cell_inputs$98420 [1] $auto$opt_expr.cc:205:group_cell_inputs$98420 [2] $auto$opt_expr.cc:205:group_cell_inputs$98420 [9] 1'0 $auto$opt_expr.cc:205:group_cell_inputs$98420 [0] $auto$opt_expr.cc:205:group_cell_inputs$98420 [6] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26:25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [17] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [13] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [6] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [3] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1619: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97133 [29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $auto$wreduce.cc:461:run$97135 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98255 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [19] $auto$wreduce.cc:461:run$97135 [17] $auto$wreduce.cc:461:run$97133 [29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [8] $auto$wreduce.cc:461:run$97135 [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98422 [7:6] $auto$opt_expr.cc:205:group_cell_inputs$98422 [1] $auto$opt_expr.cc:205:group_cell_inputs$98422 [5] $auto$opt_expr.cc:205:group_cell_inputs$98422 [0] $auto$opt_expr.cc:205:group_cell_inputs$98422 [4:3] $auto$opt_expr.cc:205:group_cell_inputs$98422 [9] $auto$opt_expr.cc:205:group_cell_inputs$98422 [10] $auto$opt_expr.cc:205:group_cell_inputs$98422 [2] $auto$opt_expr.cc:205:group_cell_inputs$98422 [8] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [18] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [14] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [7] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [4] } + New connections: { $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] } = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [20:19] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 2 changes. + +26.30.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.34. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 2 unused wires. + + +26.30.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.30.37. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. + Consolidated identical input bits for $mux cell $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$ternary$../../asic_core/rtl/lsc1_packet_rx.sv:53$1623: + Old ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $auto$wreduce.cc:461:run$97135 [18] $auto$wreduce.cc:461:run$97134 [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98259 }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24:23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New ports: A={ 1'0 $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [30:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [28] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [25] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1616_Y [22] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [23] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [22] $auto$wreduce.cc:461:run$97135 [18] $auto$wreduce.cc:461:run$97134 [26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1620_Y [8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$shr$../../asic_core/rtl/lsc1_packet_rx.sv:53$1612_Y [7] }, B={ 1'1 $auto$opt_expr.cc:205:group_cell_inputs$98424 [8:7] $auto$opt_expr.cc:205:group_cell_inputs$98424 [3] $auto$opt_expr.cc:205:group_cell_inputs$98424 [6] $auto$opt_expr.cc:205:group_cell_inputs$98424 [2:1] $auto$opt_expr.cc:205:group_cell_inputs$98424 [5] $auto$opt_expr.cc:205:group_cell_inputs$98424 [9] $auto$opt_expr.cc:205:group_cell_inputs$98424 [10] $auto$opt_expr.cc:205:group_cell_inputs$98424 [11] $auto$opt_expr.cc:205:group_cell_inputs$98424 [4] $auto$opt_expr.cc:205:group_cell_inputs$98424 [0] }, Y={ $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [31:29] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [27:26] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [24] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [21:19] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [15] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [9:8] $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [5] } + New connections: $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [23] = $flatten\bridge.\g_packet.asic.\packet_core.\receiver.$procmux$12401_Y [20] + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 1 changes. + +26.30.40. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.41. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 1 unused wires. + + +26.30.43. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.30.44. Rerunning OPT passes. (Maybe there is more to do..) + +26.30.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +26.30.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.30.47. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.30.48. Executing OPT_DFF pass (perform DFF optimizations). + +26.30.49. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.30.50. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.30.51. Finished OPT passes. (There is nothing left to do.) + +26.31. Executing TECHMAP pass (map to technology primitives). + +26.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/arith_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ecp5_alu'. +Successfully finished Verilog frontend. + +26.31.3. Continuing TECHMAP pass. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ecp5_alu for cells of type $alu. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $lut. +Using extmapper simplemap for cells of type $sdff. +Using template $paramod$3e6013394447b9f5655f40d9b082bb75de6c7f0c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d66a711d7e97d14a7c7a9fd9e900c39b1fc36cfa\_80_ecp5_alu for cells of type $alu. +Using extmapper maccmap for cells of type $macc. + add \bridge.g_packet.asic.packet_core.response_payload_mux.payload_index [4:0] (5 bits, unsigned) + sub { $techmap97179$auto$share.cc:667:make_supercell$97173.Y [2:0] 2'00 } (5 bits, unsigned) + add 5'10001 (5 bits, unsigned) +Using extmapper simplemap for cells of type $mux. +Using template $paramod$constmap:f00043fc55daea38aef72d8e6295cbc9727d4528$paramod$b434c177fd0ba7b727bcf52e63869b1f5cb81d5c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$8b1a36ab2238111d2a0f4cb4ef2e14f2a55fc1f9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e20dd69394642b602af944fa966e099d5a6789a2\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:3d770d3f0e63622fe3434edb9a878b97222d5e2a$paramod$5d2a8dabb79f284440e8a72a1afb5894aff4d0d1\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$a460ba4831a5c553df03ee15bf45a690343e194f\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9a7f8f842c7d15a8f6b6820db3daba71c00239a1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f956edc9fe4df758d9fdb10bfc518a364c99e75e\_90_alu for cells of type $alu. +Using template $paramod$e95b69d3115bf069a0763f3951e78119084acbbc\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:b932cf6f5b744e7a22fe56014111479eed600561$paramod$6b401fce98938c3da90dba3992a2381126d14c86\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$f5ef69b350eb4888d7fd5599e5525777232de9ee\_80_ecp5_alu for cells of type $alu. +Using template $paramod$c78beacbbce872b25786db84eb9f11fc34f75ce1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9984296a4bb6718f9a1d83dbdd617d11d154c2d7\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:d3cca817093d0befd4513a92cfe48f9b2294495b$paramod$a33f210e9dfd7445c53aacb0e77dd047a12d9b6f\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$bee761d331fdedbd8626647f29f2ee65d35196da\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\_90_mod for cells of type $mod. +Using template $paramod$d90c3448203144d55644b597072d6cf1b3e54430\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\_90_div for cells of type $div. +Using template $paramod$fb7f6c42d84fe8fae89a359df55310f1e494c563\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3feadc943c245786557f92f999c9b43f572b6b8b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:da283fa03f54264b1ac64045e6b92c72b69afff5$paramod$3c22fa67685c4ece6d7a71e8c65fa1c930a7b26e\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$106402fc14ba87a4d8643cf9e9a3de5e7eff24e1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:dbc0e80e8b30c37248cdc71088745cad46c205c8$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. + add { $techmap97179$auto$share.cc:667:make_supercell$97173.Y 2'00 } (7 bits, unsigned) + add 16'0000000000101111 (16 bits, unsigned) +Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$29dcfde687ab76cd03c4ee062fb9520b20dbe845\_90_pmux for cells of type $pmux. +Using template $paramod$38e8498ccdc425801fe5312e427e3cf0d9089c58\_80_ecp5_alu for cells of type $alu. +Using template $paramod$72f7795a18b8bd21d2def9f98cbb7d0e4ff65a7f\_90_pmux for cells of type $pmux. +Using template $paramod$0f9ef3943735053e2437cb2dfebddb8617beb01b\_90_pmux for cells of type $pmux. +Using template $paramod$f42569e367821ad1b7d52f2d157a44ce80c766dc\_90_pmux for cells of type $pmux. +Using template $paramod$4f9ddb8bcc47f1c63c5307c488aaf2e8cb141a6c\_90_pmux for cells of type $pmux. +Using template $paramod$b8765a8123741d1543ecc993bbc61eeed6ca73ea\_90_pmux for cells of type $pmux. +Using template $paramod$0612aa82a8bdb3c60f7a2e5f068aa820e0b30027\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ecp5_alu for cells of type $alu. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$constmap:2609a5722a69691cd18f1ae36c23d1d8a273e785$paramod$ef0ec05b6682614df4f877d3cc76a5f45a4b7300\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using template $paramod$231afaec00e6fad0c71d9f677e0405124d548ad2\_90_pmux for cells of type $pmux. +Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. +Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. +Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. +Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. +Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. +Using template $paramod$e830d104b5de63a966ae948f6aff012e63986700\_90_pmux for cells of type $pmux. +Using template $paramod$70d30c21ff772b34d0d1da2801fbd781dc3c70e4\_90_pmux for cells of type $pmux. +Using template $paramod$b8a7a49af93c9972e4faced050a7ddb2a5968b70\_80_ecp5_alu for cells of type $alu. +Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:d3a9dbfbcdb01b8f2b0053b3a234a39cfa4a68b0$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 +Creating constmapped module `$paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx'. + +26.31.136. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$122515. + dead port 2/2 on $mux $procmux$122509. + dead port 2/2 on $mux $procmux$122503. + dead port 2/2 on $mux $procmux$122497. + dead port 2/2 on $mux $procmux$122491. + dead port 2/2 on $mux $procmux$122485. + dead port 2/2 on $mux $procmux$122479. + dead port 2/2 on $mux $procmux$122473. +Removed 8 multiplexer ports. + + +26.31.137. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx. + +Removed 0 unused cells and 13 unused wires. +Using template $paramod$constmap:0a5066471a34f60e973d392b0f8a69ac616f6e53$paramod$725c87e39d9cfa8e3f87960d3d9518e9172132b3\_90_shift_shiftx for cells of type $shift. +Using template $paramod$7b16819b516a037d220ff7463dffc76498bbb23b\_90_alu for cells of type $alu. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Bit 10 of port B and bit 9 of port B are connected. + Bit 11 of port B and bit 9 of port B are connected. + Bit 12 of port B and bit 9 of port B are connected. + Bit 13 of port B and bit 9 of port B are connected. + Bit 14 of port B and bit 9 of port B are connected. + Bit 15 of port B and bit 9 of port B are connected. + Bit 16 of port B and bit 9 of port B are connected. + Bit 17 of port B and bit 9 of port B are connected. + Bit 18 of port B and bit 9 of port B are connected. + Bit 19 of port B and bit 9 of port B are connected. + Bit 20 of port B and bit 9 of port B are connected. + Bit 21 of port B and bit 9 of port B are connected. + Bit 22 of port B and bit 9 of port B are connected. + Bit 23 of port B and bit 9 of port B are connected. + Bit 24 of port B and bit 9 of port B are connected. + Bit 25 of port B and bit 9 of port B are connected. + Bit 26 of port B and bit 9 of port B are connected. + Bit 27 of port B and bit 9 of port B are connected. + Bit 28 of port B and bit 9 of port B are connected. + Bit 29 of port B and bit 9 of port B are connected. + Bit 30 of port B and bit 9 of port B are connected. + Bit 31 of port B and bit 9 of port B are connected. +Creating constmapped module `$paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx'. + +26.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$116161. + dead port 1/2 on $mux $procmux$116158. + dead port 2/2 on $mux $procmux$116158. + dead port 1/2 on $mux $procmux$116155. + dead port 1/2 on $mux $procmux$116152. + dead port 2/2 on $mux $procmux$116152. + dead port 1/2 on $mux $procmux$116149. + dead port 1/2 on $mux $procmux$116146. + dead port 2/2 on $mux $procmux$116146. + dead port 2/2 on $mux $procmux$116140. + dead port 2/2 on $mux $procmux$116134. + dead port 2/2 on $mux $procmux$116128. + dead port 2/2 on $mux $procmux$116122. + dead port 2/2 on $mux $procmux$116116. +Removed 14 multiplexer ports. + + +26.31.142. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx. + +Removed 45 unused cells and 62 unused wires. +Using template $paramod$constmap:d29377bf92c6b5e3d3913df779fe7cd351ff1639$paramod$ec3a5fe9d090f707e227c8899faaed3e3740e17c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:6c39e690103f07a79a9a7bc3048d8f2f5e5d9d3c$paramod$f612e35060ae7fb18272569c570296f68e4cce8a\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:09a194da8e942924b0a9ba3642691e46c42a5672$paramod$ca10b04578db81bdaee95c919a49f80d9e62ba64\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:779758473956024271d76e132066ad805458a885$paramod$31bea9f4cbe46260fd6192157109a9aa617193fa\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. +Using template $paramod$fc16b9f758000d363d24f130038bd99b46b4fa1b\_90_pmux for cells of type $pmux. +Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$076c9a7a3f037230073fe14dd4865d470cb48917\_80_ecp5_alu for cells of type $alu. +Using template $paramod$bc5b76409c189dae1304578314e9d1ddd73fedb5\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9fd1289fe94899e73ba1836aa1d18f7f186f44e4\_80_ecp5_alu for cells of type $alu. +Using template $paramod$a34f5a54451e27e96d7c38bcd96183b90a0e2cf0\_80_ecp5_alu for cells of type $alu. +Using template $paramod$74ae009756a053357cf6867c0f5ef34bbd93f8bc\_80_ecp5_alu for cells of type $alu. +Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. +Using template $paramod$9dd2c168c92ea5e7211728a4dd85e9d07319b5c9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$081ba1a4a7201ecdb44563d3c3bd7013d1ebf4eb\_80_ecp5_alu for cells of type $alu. +Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fb2ccc7567b9f572f99303d62bd705e69acf8cd5\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $sdffce. +Using template $paramod$dd7e7d5c03aea134912316b6b5bb7a107010ead9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. +Using template $paramod$ebf89ea36a793f0f77858f212141d47c833068ad\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fdd20cfde6eff5e426e814d02912ca76c51febc9\_80_ecp5_alu for cells of type $alu. +Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. +Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f634e570cbc550b94014122ad284ced3e6dbf131\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ecp5_alu for cells of type $alu. +Using template $paramod$dde52db7035cb02b3cc5e73865788532339e3bcb\_80_ecp5_alu for cells of type $alu. +Using template $paramod$99501223b6f7e5af250351eeb57edb5403a5ad0b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$constmap:51fb3526f3621c6ba109a6fa670766d42e57f474$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx'. + +26.31.214. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$164768. + dead port 2/2 on $mux $procmux$164762. + dead port 2/2 on $mux $procmux$164756. + dead port 2/2 on $mux $procmux$164750. +Removed 4 multiplexer ports. + + +26.31.215. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:92b06b5a8b86d5cecb92c0600747e371f589a4a3$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000101 for cells of type $fa. +Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ecp5_alu for cells of type $alu. +Using template $paramod$88c684be3b0c454edf76bb30cb93069ee379ec5b\$__div_mod_trunc for cells of type $__div_mod_trunc. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Running "alumacc" on wrapper $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:Y_WIDTH=32:A_WIDTH=32:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $paramod\$__div_mod_u\WIDTH=32'00000000000000000000000000100000 for cells of type $__div_mod_u. +Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=63:B_WIDTH=63:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=62:B_WIDTH=62:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=61:B_WIDTH=61:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=60:B_WIDTH=60:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=59:B_WIDTH=59:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=58:B_WIDTH=58:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=57:B_WIDTH=57:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=56:B_WIDTH=56:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=55:B_WIDTH=55:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=54:B_WIDTH=54:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=53:B_WIDTH=53:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=52:B_WIDTH=52:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=51:B_WIDTH=51:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=50:B_WIDTH=50:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=49:B_WIDTH=49:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=48:B_WIDTH=48:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=47:B_WIDTH=47:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=46:B_WIDTH=46:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=45:B_WIDTH=45:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=44:B_WIDTH=44:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=43:B_WIDTH=43:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=42:B_WIDTH=42:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=41:B_WIDTH=41:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=40:B_WIDTH=40:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=39:B_WIDTH=39:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=38:B_WIDTH=38:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=37:B_WIDTH=37:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=36:B_WIDTH=36:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=35:B_WIDTH=35:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=34:B_WIDTH=34:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=33:B_WIDTH=33:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $paramod$789c344356a154d2afc7b832b41d1067dbc946ba\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e39069e3f4ee35c1eea86993bd74689959babaab\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d7aca3dc44b07ff19908fb1a3b606577588c15f1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f9e3a3c4b84f99cb56fad07743ec44ad55b11c8b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$dd5ba471f7dcf35707f23b88cfd15b9582f97277\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b7531bc0616f8d4cdd8159edd2237c9ddbb2ce01\_80_ecp5_alu for cells of type $alu. +Using template $paramod$ff8ba121d2f8e85b775c9f35ef677a1a276e7e1b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$9a66d4bebbc4fab84566caffef9f094a1a467389\_80_ecp5_alu for cells of type $alu. +Using template $paramod$57bc309a5d8a948cec8981d26d896ee1cbf54d58\_80_ecp5_alu for cells of type $alu. +Using template $paramod$f94cfdb8ad389f4fc4515bcb65bccd7e2d189e95\_80_ecp5_alu for cells of type $alu. +Using template $paramod$2a25669ccd39fe7c0fbfb2a4d17416fc78667f00\_80_ecp5_alu for cells of type $alu. +Using template $paramod$d9397dfdf5f7cf5715aebc9527845402880218a0\_80_ecp5_alu for cells of type $alu. +Using template $paramod$acc477ace2583cc2ee0cf651c72a385d2bbbe9f1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$415abdcadc251df4f0f033b62b8f3296b8461b4e\_80_ecp5_alu for cells of type $alu. +Using template $paramod$6573c1c269218f299badf6e04ca86aa37fdb352c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$6a21b72c9c0b32e81b169c7e08a4d8b9c462448f\_80_ecp5_alu for cells of type $alu. +Using template $paramod$324e0706ebb77f1915b22f4a136962ec3fd1d7ff\_80_ecp5_alu for cells of type $alu. +Using template $paramod$461fc931d630cb01bec1fea87f37fbcc53f6f6a4\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fe074227b1c5fbaa1ea56076182c29dbcf3a782a\_80_ecp5_alu for cells of type $alu. +Using template $paramod$85502450775e62e9c6a2fe29020b3433d4335647\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e32c921f95fe0e2350204f4ecefc9e296355521b\_80_ecp5_alu for cells of type $alu. +Using template $paramod$05d913fba320393c7e943e625bef3af776153b60\_80_ecp5_alu for cells of type $alu. +Using template $paramod$8e07e2c0a3efc148d2f3714f3901076678774ed1\_80_ecp5_alu for cells of type $alu. +Using template $paramod$5b7e592b3c2951af6800b7fd597f66a79b72b91c\_80_ecp5_alu for cells of type $alu. +Using template $paramod$90182783100594e2dd636a282c4723cfc9adaedd\_80_ecp5_alu for cells of type $alu. +Using template $paramod$851c5c9b30913ea2deae68e3ca9e9c4e649723bc\_80_ecp5_alu for cells of type $alu. +Using template $paramod$1445aacdb5f2a1ef9fedf1373097ffa45438211d\_80_ecp5_alu for cells of type $alu. +Using template $paramod$7add42b712fe5bbbba521e93062103d6bf78a453\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b6f86f6a0c43c26b22ee55f51e05d5951f0e6562\_80_ecp5_alu for cells of type $alu. +Using template $paramod$044fdceace8c449ec99f900b42120ac005ff4065\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b6b58933bcf3c8b9e3e5de18c2637bd0e12c7c47\_80_ecp5_alu for cells of type $alu. +No more expansions possible. + + +26.32. Executing OPT pass (performing simple optimizations). + +26.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 9955 cells. + +26.32.3. Executing OPT_DFF pass (perform DFF optimizations). + +26.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 19639 unused cells and 32416 unused wires. + + +26.32.5. Finished fast OPT passes. + +26.33. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +26.35. Executing TECHMAP pass (map to technology primitives). + +26.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +26.35.2. Continuing TECHMAP pass. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. +Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +26.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +26.38. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in ulx3s_packet_top. + +26.39. Executing ATTRMVCP pass (move or copy attributes). + +26.40. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 6 unused cells and 33530 unused wires. + + +26.41. Executing TECHMAP pass (map to technology primitives). + +26.41.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/latches_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +26.41.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42. Executing ABC9 pass. + +26.42.1. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.2. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.3. Executing SCC pass (detecting logic loops). +Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$103721 $auto$ff.cc:266:slice$144591 $auto$simplemap.cc:126:simplemap_reduce$100400 $auto$simplemap.cc:126:simplemap_reduce$100396 $auto$simplemap.cc:126:simplemap_reduce$100390 $auto$simplemap.cc:126:simplemap_reduce$100379 $auto$simplemap.cc:267:simplemap_mux$151506 $auto$ff.cc:266:slice$119395 $auto$simplemap.cc:126:simplemap_reduce$103723 $auto$simplemap.cc:126:simplemap_reduce$103720 $auto$ff.cc:266:slice$144201 $auto$simplemap.cc:126:simplemap_reduce$100402 +Found an SCC: $auto$ff.cc:266:slice$119266 $auto$simplemap.cc:126:simplemap_reduce$103714 $auto$simplemap.cc:126:simplemap_reduce$103712 $auto$simplemap.cc:225:simplemap_logbin$119201 $auto$simplemap.cc:225:simplemap_logbin$164196 +Found 2 SCCs in module ulx3s_packet_top. +Found 2 SCCs. + +26.42.4. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.5. Executing PROC pass (convert processes to netlists). + +26.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +26.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +26.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +26.42.5.4. Executing PROC_INIT pass (extract init attributes). + +26.42.5.5. Executing PROC_ARST pass (detect async resets in processes). + +26.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +26.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +26.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +26.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +26.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +26.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +26.42.5.12. Executing OPT_EXPR pass (perform const folding). + +26.42.6. Executing TECHMAP pass (map to technology primitives). + +26.42.6.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.42.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42.7. Executing OPT pass (performing simple optimizations). + +26.42.7.1. Executing OPT_EXPR pass (perform const folding). + +26.42.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +26.42.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +26.42.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +26.42.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +26.42.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +26.42.7.8. Executing OPT_EXPR pass (perform const folding). + +26.42.7.9. Finished OPT passes. (There is nothing left to do.) + +26.42.8. Executing TECHMAP pass (map to technology primitives). + +26.42.8.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +26.42.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +26.42.9. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +26.42.10. Executing ABC9_OPS pass (helper functions for ABC9). + + +26.42.11. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.12. Executing ABC9_OPS pass (helper functions for ABC9). + + +26.42.13. Executing TECHMAP pass (map to technology primitives). + +26.42.13.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +26.42.13.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $or. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +26.42.14. Executing OPT pass (performing simple optimizations). + +26.42.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + + +26.42.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. + +Removed a total of 2 cells. + +26.42.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +26.42.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.42.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.42.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. +Removed 0 unused cells and 55 unused wires. + + +26.42.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.42.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +26.42.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_packet_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +26.42.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_packet_top. +Performed a total of 0 changes. + +26.42.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_packet_top'. +Removed a total of 0 cells. + +26.42.14.13. Executing OPT_DFF pass (perform DFF optimizations). + +26.42.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_packet_top.. + +26.42.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_packet_top. + +26.42.14.16. Finished OPT passes. (There is nothing left to do.) + +26.42.15. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_packet_top: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 2 $_OR_ + 2 $_XOR_ + 14 $_MUX_ + not replaced 3 cell types: + 31 $specify2 + 4 $_NOT_ + 4 $_AND_ + +26.42.16. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_packet_top: replaced 49747 cells with 308809 new cells, skipped 21329 cells. + replaced 3 cell types: + 13140 $_OR_ + 7422 $_XOR_ + 29185 $_MUX_ + not replaced 7 cell types: + 5022 $_NOT_ + 5733 $_AND_ + 1 MULT18X18D + 1 EHXPLLL + 7221 TRELLIS_FF + 3350 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + 1 $__ABC9_SCC_BREAKER + +26.42.16.1. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.16.2. Executing ABC9_OPS pass (helper functions for ABC9). + +26.42.16.3. Executing XAIGER backend. + +Extracted 128694 AND gates and 346594 wires from module `ulx3s_packet_top' to a netlist network with 7233 inputs and 8853 outputs. + +26.42.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +26.42.16.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 7233/ 8853 and = 114508 lev = 311 (17.77) mem = 2.17 MB box = 3350 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 7233/ 8853 and = 148895 lev = 63 (8.30) mem = 2.10 MB ch =20031 box = 806 bb = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no +ABC: Node = 148895. Ch = 17039. Total mem = 25.98 MB. Peak cut mem = 1.22 MB. +ABC: P: Del = 22659.00. Ar = 135334.0. Edge = 149273. Cut = 1640461. T = 0.45 sec +ABC: P: Del = 22532.00. Ar = 133587.0. Edge = 144083. Cut = 1600620. T = 0.44 sec +ABC: P: Del = 22532.00. Ar = 30136.0. Edge = 94304. Cut = 3442399. T = 0.82 sec +ABC: F: Del = 22532.00. Ar = 28710.0. Edge = 92343. Cut = 3310419. T = 0.84 sec +ABC: A: Del = 22532.00. Ar = 27598.0. Edge = 88719. Cut = 3338144. T = 2.28 sec +ABC: A: Del = 22532.00. Ar = 27529.0. Edge = 88679. Cut = 3324904. T = 2.38 sec +ABC: Total time = 7.22 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 7233/ 8853 and = 88404 lev = 59 (9.52) mem = 1.40 MB box = 785 bb = 0 +ABC: Mapping (K=7) : lut = 23076 edge = 86702 lev = 29 (5.21) levB = 89 mem = 0.94 MB +ABC: LUT = 23076 : 2=1054 4.6 % 3=7181 31.1 % 4=11359 49.2 % 5=3342 14.5 % 6=75 0.3 % 7=65 0.3 % Ave = 3.76 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 71.32 seconds, total: 71.32 seconds + +26.42.16.6. Executing AIGER frontend. + +Removed 132395 unused cells and 156371 unused wires. + +26.42.16.7. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 23150 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 785 +ABC RESULTS: input signals: 189 +ABC RESULTS: output signals: 8780 +Removing temp directory. + +26.42.17. Executing TECHMAP pass (map to technology primitives). + +26.42.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/usr/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +26.42.17.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000010 for cells of type $__ABC9_SCC_BREAKER. +No more expansions possible. + +Removed 1642 unused cells and 345388 unused wires. + +26.43. Executing TECHMAP pass (map to technology primitives). + +26.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +26.43.2. Continuing TECHMAP pass. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. +Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. +Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. +Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. +Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. +Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. +Using template $paramod$fedcddf7a4357754b8c2c1b3c873f3560b924a39\$lut for cells of type $lut. +Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$b9f1cc075fd5e1dc13f6aa9fc152bf79a0f71ef7\$lut for cells of type $lut. +Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157\$lut for cells of type $lut. +Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut. +Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1\$lut for cells of type $lut. +Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. +Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. +Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. +Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut. +Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. +Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut. +Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. +Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut. +Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. +Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. +Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. +Using template $paramod$000bb7a035b5a5c1934ca0e20d202ab94a0e06c9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. +Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut. +Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. +Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. +Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a\$lut for cells of type $lut. +Using template $paramod$52d96bfa17866bab828b9f1286c638d27fce0ef0\$lut for cells of type $lut. +Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. +Using template $paramod$6a0faddbb1877e236e8eb8130711942937277f4e\$lut for cells of type $lut. +Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. +Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. +Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578\$lut for cells of type $lut. +Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. +Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. +Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut. +Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. +Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. +Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut. +Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. +Using template $paramod$1769b870d47911d7a8ec3b7224a7974dbc5fe069\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut. +Using template $paramod$549a24c0b77071744eefd28bf11342e15d6bc181\$lut for cells of type $lut. +Using template $paramod$c388bdf5bc34e848632d723db494e9a79bee28dd\$lut for cells of type $lut. +Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut. +Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. +Using template $paramod$adb3580ae7f1e000bff662054d4f52a48cec1e58\$lut for cells of type $lut. +Using template $paramod$c0b24172d263163a8e6b59024cdb9dfb57b52d61\$lut for cells of type $lut. +Using template $paramod$f056b3cf42701dfc7f540d463578d46c622fe830\$lut for cells of type $lut. +Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut. +Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut. +Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut. +Using template $paramod$0383ea234f9fd03480ea2f8696098da806b349de\$lut for cells of type $lut. +Using template $paramod$233b70872b0d11ad6386b65bc4d8864ac02395bb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut. +Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. +Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut. +Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut. +Using template $paramod$86d1a361297b330f6575bda7e44a0fcda00635d1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut. +Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. +Using template $paramod$a067ca065a0e8fdac308d6893e69914865d54ec4\$lut for cells of type $lut. +Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut. +Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. +Using template $paramod$bbb10333e84a7e80f65e1494ebbfbf3f28568fcd\$lut for cells of type $lut. +Using template $paramod$ffa1224fa26b3074d5175286833c5c7f95f6fb8b\$lut for cells of type $lut. +Using template $paramod$fe70bb3280659663b8fa2b45f42fda9ccf4ccfaa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. +Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. +Using template $paramod$7776c9f5ae2211fea85581af31384e8ba1fa501e\$lut for cells of type $lut. +Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. +Using template $paramod$8d41622da0aa87c171e3ad24745637a8e540bedc\$lut for cells of type $lut. +Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut. +Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut. +Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. +Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039\$lut for cells of type $lut. +Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394\$lut for cells of type $lut. +Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395\$lut for cells of type $lut. +Using template $paramod$96bf8e3dce66ee15df06137d7b93bf7e34b26863\$lut for cells of type $lut. +Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. +Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848\$lut for cells of type $lut. +Using template $paramod$53085fa3385a29b95b991d58be8f55774e1a4d92\$lut for cells of type $lut. +Using template $paramod$2a533b2b9ed36df203d5fca44a14d68feeb67362\$lut for cells of type $lut. +Using template $paramod$70e649cff31ac39ffa7544751d17e54df9788341\$lut for cells of type $lut. +Using template $paramod$a5810b3064bbc05b2c453025774af99926f05666\$lut for cells of type $lut. +Using template $paramod$5f3abb125a0361a143f12eec230ed33f6f988a00\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100001 for cells of type $lut. +Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e\$lut for cells of type $lut. +Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. +Using template $paramod$a2078492a93db2b736e3f44dc8f19641566d846d\$lut for cells of type $lut. +Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b\$lut for cells of type $lut. +Using template $paramod$810e0f22d547104f8208898922f6ac2444aeece7\$lut for cells of type $lut. +Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut. +Using template $paramod$29f1cd2a09b892eea21b26ecd16aa99574b3d6c4\$lut for cells of type $lut. +Using template $paramod$3b383aa74b05b60cb9cabc0ba0eca4dea92c2b33\$lut for cells of type $lut. +Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b\$lut for cells of type $lut. +Using template $paramod$9c8231ab3b30fd231c3be4df663c91e1a5781fa7\$lut for cells of type $lut. +Using template $paramod$c7b20ecfdd4b0c41f8ccf7e4154a4ad7dca4807c\$lut for cells of type $lut. +Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. +Using template $paramod$842028a23ac07055161965e8aace63da0714578f\$lut for cells of type $lut. +Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. +Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. +Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut. +Using template $paramod$f377b83bfd4274750d2cc48e6e3fa52263d09667\$lut for cells of type $lut. +Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e\$lut for cells of type $lut. +Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut. +Using template $paramod$2af3e003254181d08baef124757f4cecfb778e26\$lut for cells of type $lut. +Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut. +Using template $paramod$74a12c4d30e035eeda2d34c53b77373f2b2df37a\$lut for cells of type $lut. +Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut. +Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab\$lut for cells of type $lut. +Using template $paramod$9640380942618015231dc80e07fe9e6281ac216a\$lut for cells of type $lut. +Using template $paramod$c50bf79556f7c35c37bbd3d892f752a0609f21ca\$lut for cells of type $lut. +Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut. +Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99\$lut for cells of type $lut. +Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821\$lut for cells of type $lut. +Using template $paramod$90edad2b6a4dec5adef9ce6a532f7a1edb48db32\$lut for cells of type $lut. +Using template $paramod$011b9cadb5a2b1bb00b102aedec4f2cce186949e\$lut for cells of type $lut. +Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. +Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. +Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. +Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut. +Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. +Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut. +Using template $paramod$3070c1773f3a1b28a0a0b5f34a4a299b8a02055e\$lut for cells of type $lut. +Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut. +Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. +Using template $paramod$5a490b0e00aeb3aa961ff44c01138435d4948c4d\$lut for cells of type $lut. +Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut. +Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut. +Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c\$lut for cells of type $lut. +Using template $paramod$7a4cd79e1c19466b5946403ebacd15021cb8b814\$lut for cells of type $lut. +Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99\$lut for cells of type $lut. +Using template $paramod$3f0badb1a6257830a007d1166225fb9999e2000c\$lut for cells of type $lut. +Using template $paramod$61c4cbf8581170b67138b98e32863cf2de767f72\$lut for cells of type $lut. +Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. +Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut. +Using template $paramod$cfe658add7b49bc6805d629e0a88423d427de396\$lut for cells of type $lut. +Using template $paramod$32fb8371bd734b78a418ea9de39d47de7a9266da\$lut for cells of type $lut. +Using template $paramod$2b757c49dce94706e41b149d1a63f58eface8af9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011010 for cells of type $lut. +Using template $paramod$a59b6c8d81194b59764286a4118e90f9abac65dc\$lut for cells of type $lut. +Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. +Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$fbb57d8211f7406edbcbc7da6109c62aa6dcf0c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$5f99aa1a31b4f0c356281a67e16706e1e689d29f\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001010 for cells of type $lut. +Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. +Using template $paramod$43526719abd92ef1dcf092f5ae5632bfd65b96d8\$lut for cells of type $lut. +Using template $paramod$aa007bf717dd7ed8e7e12b31bda3917c395525ce\$lut for cells of type $lut. +Using template $paramod$b6508574947c9efbad5feaa6ee5d3e467e528885\$lut for cells of type $lut. +Using template $paramod$edcf01b6b14b71de1ef174d0767058217359b674\$lut for cells of type $lut. +Using template $paramod$f054a7d7ab239e8c6ce022005b59678182897bfe\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. +Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. +Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. +Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. +Using template $paramod$b80e608920ce9cfa1f5c7d21df7a72954e9b0a70\$lut for cells of type $lut. +Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut. +Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. +Using template $paramod$ef2d70b738add7194c07433b79aa092a92f6f1ea\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut. +Using template $paramod$ab802f374fd5db87cad46a1e7b287d7bfdd01aa7\$lut for cells of type $lut. +Using template $paramod$97da510a48140d987a9d50d2cc471e443af59783\$lut for cells of type $lut. +Using template $paramod$5107935b445e7ae7ab686f113b224ad25949eb1b\$lut for cells of type $lut. +Using template $paramod$90687826ecc50762f08b06e0c2f0be8f8b42044c\$lut for cells of type $lut. +Using template $paramod$eeed37ce45abdda29d3e180f2d1dfc0c4c376530\$lut for cells of type $lut. +Using template $paramod$63353a9cd99b0c49001cfade269881ffdd3905ee\$lut for cells of type $lut. +Using template $paramod$20eb354dbce30b5cbcf95731162faf3d60aac496\$lut for cells of type $lut. +Using template $paramod$a5e7a6e7aedf5438d458c5134b7c80da31bdbad3\$lut for cells of type $lut. +Using template $paramod$126a2bf227a5e24e40d623d3ec32202e0557c612\$lut for cells of type $lut. +Using template $paramod$0003932bde6e5d83aa0e3ebadf2bc95f80ff5c46\$lut for cells of type $lut. +Using template $paramod$02eefd9b74acf66558bff242fcbe62a514559f6a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$2f43819c0455a6eb10ff545f8331e5d7d67cb6a2\$lut for cells of type $lut. +Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. +Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. +Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut. +Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. +Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4\$lut for cells of type $lut. +Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. +Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. +Using template $paramod$e56967e4a5743f6ef12dfe7b1009bf8e0aa2fe0d\$lut for cells of type $lut. +Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. +Using template $paramod$a6ef2a845efd4ff0d96bc4fd2f06cc3516fa63ff\$lut for cells of type $lut. +Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. +Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. +Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut. +Using template $paramod$3be30a5a9f993377f0c44a54aadf0fabaaafa2c9\$lut for cells of type $lut. +Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut. +Using template $paramod$76af301ebe268bf10bfd5137e11ac427e045abf5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. +Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. +Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. +Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. +Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. +Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut. +Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. +Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. +Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. +Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. +Using template $paramod$2c95149d0c6ec8cb015c816ff2bb05269df37d88\$lut for cells of type $lut. +Using template $paramod$dbd6bfc0079f30bdbd8251243755394b48ae1fbb\$lut for cells of type $lut. +Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut. +Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut. +Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. +Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut. +Using template $paramod$37fffb60c4ed9143f4207129d4a64018994d852d\$lut for cells of type $lut. +Using template $paramod$dc80e74b9623b8a802ef4b5162559616e5ac1cef\$lut for cells of type $lut. +Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut. +Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut. +Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut. +Using template $paramod$723eb79ef8d5d376f3f196f4acfa8e347145a0fa\$lut for cells of type $lut. +Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. +Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e\$lut for cells of type $lut. +Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. +Using template $paramod$1de39b75a080bd0f6489e0fbdbfc12d8187bcf6f\$lut for cells of type $lut. +Using template $paramod$d47075a53ff1dff553bbe454ba83286b2e9de7dd\$lut for cells of type $lut. +Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut. +Using template $paramod$cba6b89907e1a68cc011c9a30e7e6cfab421f1a1\$lut for cells of type $lut. +Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. +Using template $paramod$a56a39c0f6a5a7dc6beed165205ecc9aaf916f10\$lut for cells of type $lut. +Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. +Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut. +Using template $paramod$b76eeafe3553c6220aebff28fb37e7d4bf1fb01a\$lut for cells of type $lut. +Using template $paramod$9c32fd119457e69e03a24d4d2698f238bf59d9d3\$lut for cells of type $lut. +Using template $paramod$37203517188e0e81c6d1574dd1c274ed56646adf\$lut for cells of type $lut. +Using template $paramod$a3077fa2cf8e48a37d410abdac8a7cce2583fbf3\$lut for cells of type $lut. +Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. +Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. +Using template $paramod$b28b4ecbaa07efdcc51c93348ccdc2395f8b41c1\$lut for cells of type $lut. +Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. +Using template $paramod$f096cbf7810c657d1faa5ebcdd247974deedeea6\$lut for cells of type $lut. +Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut. +Using template $paramod$fd20386aee979bc7d1fe84e4b6d9cb788fcf6275\$lut for cells of type $lut. +Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut. +Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. +Using template $paramod$64591bf347debff55b06eb75d4492bcbee74fc6b\$lut for cells of type $lut. +Using template $paramod$8e01928b484e04dfe17fd3fb8751c9b4f4d6b28e\$lut for cells of type $lut. +Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut. +Using template $paramod$f5c5f595015aee4de78d8a59fd7b7003b8956fde\$lut for cells of type $lut. +Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut. +Using template $paramod$a8cb2c06e172ce1c41ab3f6b96725153b1bfcd6a\$lut for cells of type $lut. +Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut. +Using template $paramod$3b3518232ab43bce2b5905ad42c85b24b1dbc08b\$lut for cells of type $lut. +Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. +Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut. +Using template $paramod$9c6fa709082a3074237b74172629c9b5608bfcac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$d98f7cae393e2fb5f134f7da3a0376cfdd41f123\$lut for cells of type $lut. +Using template $paramod$b4006828b803a36d06401e5093668a1907e825ca\$lut for cells of type $lut. +Using template $paramod$e5cad3f70ef8abd514139dd032da350013fc446a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. +Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. +Using template $paramod$7991e43c533565df3969b82a304afcde859daeba\$lut for cells of type $lut. +Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. +Using template $paramod$15b1be980a14edac79713e171a9494e1b4bd5060\$lut for cells of type $lut. +Using template $paramod$95994721d3c832b251cca338772f7ec207995711\$lut for cells of type $lut. +Using template $paramod$46a3c0240e7a0e1ba60e351b8dd1863f2b554f8b\$lut for cells of type $lut. +Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. +Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$430d9aae42a88b878b2a6ceac307a334dfa959c7\$lut for cells of type $lut. +Using template $paramod$7afde302ddf552f0fb7d1a62db4a89eaf7d351f0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. +Using template $paramod$378674974b3807d742e27f000a928a69cc15ff78\$lut for cells of type $lut. +Using template $paramod$ef23bc364ceee2a8dc5800c611734cfdf1fda657\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. +Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut. +Using template $paramod$175fdba264784436cc7fddca63446b9ae0bf4881\$lut for cells of type $lut. +Using template $paramod$812955f328f06a04a937e86a4a65f93c71c9dd61\$lut for cells of type $lut. +Using template $paramod$0aae27145afd1348566af63c85046495acb0e0d8\$lut for cells of type $lut. +Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. +Using template $paramod$dfdaea48b7611eab326be448302a98c04e3e259b\$lut for cells of type $lut. +Using template $paramod$edf0f1ca1d51bddab33b022d26d3da5ca2294e0d\$lut for cells of type $lut. +Using template $paramod$c1d19d26fc76dcae92dcb8d4cb83a61d66690ab8\$lut for cells of type $lut. +Using template $paramod$0331a4a399782662e6707b65e29e002ee5c3c2ad\$lut for cells of type $lut. +Using template $paramod$9b97a0ad7480907fc31589a8d320d2c7b5988f46\$lut for cells of type $lut. +Using template $paramod$ca2532991f2c847ac990e1deeca1e91108bc2da0\$lut for cells of type $lut. +Using template $paramod$859290076eb0ab5533d03769d9103e68d9252019\$lut for cells of type $lut. +Using template $paramod$16d276ea5dd24ebdbea76e6b5e97f981d6f732d4\$lut for cells of type $lut. +Using template $paramod$cced35221b5252719c37669ece663f2282e06857\$lut for cells of type $lut. +Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. +Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut. +Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc\$lut for cells of type $lut. +Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. +Using template $paramod$049f24bb0a60e88df65dcd16ca4d803000f3ec33\$lut for cells of type $lut. +Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut. +Using template $paramod$e2abc3b706ab86fd7c0d14a17f66f1e597465517\$lut for cells of type $lut. +Using template $paramod$0d94766b8f50ae8b32739d9cec096f2c5d44402a\$lut for cells of type $lut. +Using template $paramod$d61dc5ff3a9102f3e1b420770cb57c48730b6a64\$lut for cells of type $lut. +Using template $paramod$999f605d750567959edab1f1540f58f5f587176d\$lut for cells of type $lut. +Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. +Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000001 for cells of type $lut. +Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. +Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. +Using template $paramod$d2714c8e745a1556f41422d88e68656f7be2eb51\$lut for cells of type $lut. +Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. +Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376\$lut for cells of type $lut. +Using template $paramod$6b6ddc5b21698d9ced7db10b7c11cd0e0bbe1724\$lut for cells of type $lut. +Using template $paramod$93eb7afdb7ba444e94bb8ab99bb6e437294e72c5\$lut for cells of type $lut. +Using template $paramod$59e08c1819e5983704830c894d51357a44766911\$lut for cells of type $lut. +Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut. +Using template $paramod$8f8f3ed0dfbd822273417c0b66ef033f29ee6b95\$lut for cells of type $lut. +Using template $paramod$09452af5ff446506ce6933e409a1fd44c0b602cf\$lut for cells of type $lut. +Using template $paramod$f48bfbefa45c13216169eb3f6bfd33f86a743af6\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. +Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. +Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut. +Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. +Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. +Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. +Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. +Using template $paramod$35369ee2661bc6f22afa7fd33e082ebba93672ba\$lut for cells of type $lut. +Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. +Using template $paramod$8bb130805bdc6693bee1a55c66f5eb884b1589c8\$lut for cells of type $lut. +Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut. +Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut. +Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. +Using template $paramod$ececc55fe721b2d80098bfc00a6005f1af14b6e5\$lut for cells of type $lut. +Using template $paramod$3eb8805ccd6f91bad96dcbf190c2fb4f72f4634f\$lut for cells of type $lut. +Using template $paramod$04979dc4ef7042e984db9bc945cb489ee7f78f7a\$lut for cells of type $lut. +Using template $paramod$68b70f4e14df413658bd31cabb75ae13fe669a27\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. +Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut. +Using template $paramod$314f3c3dec7cf6ef51df1856bd63e6c4433257ff\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. +Using template $paramod$c53aa6fdec082f49347d41c5f71d8229b851ab6e\$lut for cells of type $lut. +Using template $paramod$81e1f78eaf1f9871e7a0d69382986cf21d267346\$lut for cells of type $lut. +Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. +Using template $paramod$5d3a75742a49186e20388443881a0a0917f692ec\$lut for cells of type $lut. +Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. +Using template $paramod$6c5ce7d614693d944f80092742f538498fb7dffc\$lut for cells of type $lut. +Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. +Using template $paramod$e5fa67e3abf5feee06fdd503a1d449e36f4bc6de\$lut for cells of type $lut. +Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. +Using template $paramod$5e15ae04a76125f3b517c457f68d762add482c29\$lut for cells of type $lut. +Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. +Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut. +Using template $paramod$05f73913e867143bcd43eab9e44b992e09d91590\$lut for cells of type $lut. +Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. +Using template $paramod$046677a75b0582b9c306f74453325906cb0a2362\$lut for cells of type $lut. +Using template $paramod$f66976b7a2c3a813b681ce6945edb10a3d232304\$lut for cells of type $lut. +Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. +Using template $paramod$755a25b60136c9f99207cadea9d10868cf2976eb\$lut for cells of type $lut. +Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. +Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut. +Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. +Using template $paramod$9d86735a665af3c1da46d993ca9fb8a1a8b4a873\$lut for cells of type $lut. +Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. +Using template $paramod$64977556c846e4e7f9ced3a7b7fe9d317e7a6b98\$lut for cells of type $lut. +Using template $paramod$43af8829d7b6b99a1d878f6f70b47d603b01581b\$lut for cells of type $lut. +Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. +Using template $paramod$d4aeb23fcfb2d027ae9345ab12ffffa58ef955b9\$lut for cells of type $lut. +Using template $paramod$0c60ec4482aeb729b020b7c47556a79f3cd19781\$lut for cells of type $lut. +Using template $paramod$d97c3b09adecfac2ca8a551bbe295665d430c156\$lut for cells of type $lut. +Using template $paramod$d8021370f0670d331038a0473505efae4dff2706\$lut for cells of type $lut. +Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae\$lut for cells of type $lut. +Using template $paramod$dc41e9665158f6caac97365e95c1c2f88dcb2656\$lut for cells of type $lut. +Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut. +Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut. +Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut. +Using template $paramod$d5b81050f4dde17d887b41d5503081be421dbab6\$lut for cells of type $lut. +Using template $paramod$b90d0bd825ef9aa143f3f391212f99bcd2d228dc\$lut for cells of type $lut. +Using template $paramod$8a6467e94c91f2ff2d68f9e1e4ae64482bde0370\$lut for cells of type $lut. +Using template $paramod$7227ea4800fccfe8973caa4fde61c413cc991170\$lut for cells of type $lut. +Using template $paramod$255b5b55b70a9f31c54d169ac13bc0391040bb53\$lut for cells of type $lut. +Using template $paramod$d2ef43814113ff73f9ebc73be6b7b228fcced45d\$lut for cells of type $lut. +Using template $paramod$81406f9d5ea793037b12f1f0a56a402afa7fbc64\$lut for cells of type $lut. +Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. +Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. +Using template $paramod$5c9402ac1f9624bebb844c6f1a2fa39fceb58fa6\$lut for cells of type $lut. +Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. +Using template $paramod$67ec9a31a0e23cc9bc3ec8cdbf560a93252ed7b7\$lut for cells of type $lut. +Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. +Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b\$lut for cells of type $lut. +Using template $paramod$6bbb754f7471a2fa1afcc5de924e8223eb328dca\$lut for cells of type $lut. +Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. +Using template $paramod$d894ffa1ba7cf53c4b1e0d5fd84aff28dfe71e96\$lut for cells of type $lut. +Using template $paramod$eaca67fb3817360f00958a66ab21b64eef766c33\$lut for cells of type $lut. +Using template $paramod$05bdebefca68d0e34a810cad2de0d2e5e9f7e5f6\$lut for cells of type $lut. +Using template $paramod$e9da3de86f237bcb085ba1689fb89690cf1237d9\$lut for cells of type $lut. +Using template $paramod$b2d762b3bb51b18915702c16c434bdbec4a25a4a\$lut for cells of type $lut. +Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. +Using template $paramod$65fb1d96ed353a5487bb4df51139b6105a246601\$lut for cells of type $lut. +Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut. +Using template $paramod$8f8dc162b887d52b83e5151ac53aec77083a5f6b\$lut for cells of type $lut. +Using template $paramod$a875f8d2599ac50ad4512ef7895d43899873516f\$lut for cells of type $lut. +Using template $paramod$dec948165935e60a7c91daec6fba305409bbb893\$lut for cells of type $lut. +Using template $paramod$241249d1d4c3f5d365d48855d52a4050c66b5508\$lut for cells of type $lut. +Using template $paramod$154d92943fca0a03a3c1537763a41af3e08c4957\$lut for cells of type $lut. +Using template $paramod$778cfa89a311116b4664a0be7522bd19e4c50232\$lut for cells of type $lut. +Using template $paramod$cf3d59690e35586ab717eef77fac309ee05c62c0\$lut for cells of type $lut. +Using template $paramod$e197e162644f13ba3d6def1b385f7543969ee569\$lut for cells of type $lut. +Using template $paramod$15deee21bfb7f6f9f3963bae01e1abc87728ceb1\$lut for cells of type $lut. +Using template $paramod$61cdb7b3beca9f8f70061c399b61d688c3f31426\$lut for cells of type $lut. +Using template $paramod$f4c73d849f7d47805ca1aefb950c4e26e4eae9d0\$lut for cells of type $lut. +Using template $paramod$b3443607fc1ff22fec48eb4559c7f22149c73850\$lut for cells of type $lut. +Using template $paramod$8eef681bdc083ca203a9548d7f7f1d9f218fed21\$lut for cells of type $lut. +Using template $paramod$2ed66c070898e6f5d3963fa62c6aed3c198b27ba\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut. +Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut. +Using template $paramod$2aae3f707bbf5bef51f256ca9ea2cff34ba32805\$lut for cells of type $lut. +Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut. +Using template $paramod$a73e5affe093cbfcf0d2b43eb8fbeac4ea474b24\$lut for cells of type $lut. +Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. +Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. +Using template $paramod$2413346fa47cf8a80719d09e44e1141a42fc9c2e\$lut for cells of type $lut. +Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut. +Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut. +Using template $paramod$16b79a5eba6e0c11d0283a95b16674705257a0eb\$lut for cells of type $lut. +Using template $paramod$437f3216c8a8575307ce60e7fe92b253b67b329d\$lut for cells of type $lut. +Using template $paramod$a53f5ca73ba0589d00065fc440f90f301dc78994\$lut for cells of type $lut. +Using template $paramod$158bf41561e34f496d0afe28c4ac547a36925821\$lut for cells of type $lut. +Using template $paramod$384e64758675daaf5330f45461f59a669167b732\$lut for cells of type $lut. +Using template $paramod$5708ac7a777fae8f9c9daa5e9a52c3f2588c942e\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. +Using template $paramod$157079f0ae4b31275bd0fd04027309ce6c2bb03d\$lut for cells of type $lut. +Using template $paramod$8701b6ee4399940a285292efbe9cceb7b706f778\$lut for cells of type $lut. +Using template $paramod$27f6c8873fe0bdf83df63bf8f11e3e13c46924b1\$lut for cells of type $lut. +Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut. +Using template $paramod$583578005113b28fdc769049949029c37251036c\$lut for cells of type $lut. +Using template $paramod$abac68f66a0af6ba506e4e6ed0564789f19d3056\$lut for cells of type $lut. +Using template $paramod$db1f16b3540819f8331a11890309aca8220a6666\$lut for cells of type $lut. +Using template $paramod$ab50f6fb413073986e8fac916d43b5751b6500aa\$lut for cells of type $lut. +Using template $paramod$4bb876346cbc5d13aef9f873277f12d388c5d51a\$lut for cells of type $lut. +Using template $paramod$640f0b255c4baeb1d5ed3ee07d5b4acf52609838\$lut for cells of type $lut. +Using template $paramod$6da36b00000992020b7b7eba5fbe42bbd326035f\$lut for cells of type $lut. +Using template $paramod$af12fcdb6d4167b15843baf81994cca157a7081f\$lut for cells of type $lut. +Using template $paramod$7fc326a07e1ca3332e6c50518f95d4ba681a1c4f\$lut for cells of type $lut. +Using template $paramod$8df3d57693e1fe1eb8939740ef44b31f69a48327\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod$3ec83cc0e0ec241030d7c40596e80d62c44c0f57\$lut for cells of type $lut. +Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\$lut for cells of type $lut. +Using template $paramod$36400b42aaf9adb061f1992c31e0ecb97c8d592b\$lut for cells of type $lut. +Using template $paramod$541493f767dfdad47f5523f3df4c2b5d41f262fa\$lut for cells of type $lut. +Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3\$lut for cells of type $lut. +Using template $paramod$76be5a5900f80a135961ac09b0cf70ec8308af2c\$lut for cells of type $lut. +Using template $paramod$e87f431398fe61dc3cef677df705fdf1c11aa0f7\$lut for cells of type $lut. +Using template $paramod$191987e4132f69ca46dd53dfa3f15f72d990cc0a\$lut for cells of type $lut. +Using template $paramod$0babebe51def8f4db6daaf70fa957a9414a7eb6e\$lut for cells of type $lut. +Using template $paramod$78b7f61776f7b3e82414706b5df5da710258defb\$lut for cells of type $lut. +Using template $paramod$d584fea2360dda8151932e9c7650815d06026aad\$lut for cells of type $lut. +Using template $paramod$da763b8130a28e1b216739f1a8785f84cdad4cc8\$lut for cells of type $lut. +Using template $paramod$da591023dfd122102746056e60cbd4335dee2967\$lut for cells of type $lut. +Using template $paramod$fecd70a3c12842afedfe0991d741483f4333befc\$lut for cells of type $lut. +Using template $paramod$48ccd01538754f822c4e0d1b7072b646dfab838e\$lut for cells of type $lut. +Using template $paramod$bd9bf3da00bf7305b997889fd74bf71914fe3b76\$lut for cells of type $lut. +Using template $paramod$a36df8cc99428717d44c2342ab2159150ec5d5d5\$lut for cells of type $lut. +Using template $paramod$01c954f3ccfb35914a3a738c89d5bf2cb57b50f6\$lut for cells of type $lut. +Using template $paramod$83f89089d8d50aea6704278132bab8dff4ae4634\$lut for cells of type $lut. +Using template $paramod$762dcdf49521c1aa2145fa6746ab6d57dd5df22e\$lut for cells of type $lut. +Using template $paramod$73d48bb02406b4c5f2ce0cd0a01e47009788eea6\$lut for cells of type $lut. +Using template $paramod$659a07cb052b531f6a26959304b909a63e9b19d9\$lut for cells of type $lut. +Using template $paramod$ed029e6c1e87a70cff2c1ea2f266e7c04d3c3742\$lut for cells of type $lut. +Using template $paramod$37988d71f70f8b382e293f926b32f5a20cfeb976\$lut for cells of type $lut. +Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. +Using template $paramod$d0e4f0cb614d58f16d39673a463165f3a53e05d1\$lut for cells of type $lut. +Using template $paramod$f85c9b2d5ed035cbe08436c409030da7e7effb9b\$lut for cells of type $lut. +Using template $paramod$8c469afba5eb89d974fdc046eae3ff1079e10df4\$lut for cells of type $lut. +Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut. +Using template $paramod$e84e4a245515000cd6930e0f4535753ed485f71e\$lut for cells of type $lut. +Using template $paramod$7593ee757eddab004dbe16f2eed5d381e66ab3f1\$lut for cells of type $lut. +Using template $paramod$360505de37fa7f3b097fcbc42bceab80083d3453\$lut for cells of type $lut. +Using template $paramod$dd55d80dc488f5a4ac45b94e2affc1a910c2c3e4\$lut for cells of type $lut. +Using template $paramod$4ac7f780adaaa22c08c8293c1e5f87245df90c92\$lut for cells of type $lut. +Using template $paramod$e582eabb72f618e7f43a74f48f19b24904765833\$lut for cells of type $lut. +Using template $paramod$08d200a0ce8385a41744a4f3b58fc12712eba5aa\$lut for cells of type $lut. +Using template $paramod$6353e02154629763bb936385ec889903cce366ba\$lut for cells of type $lut. +Using template $paramod$b42c71661456ab1f51df3cf9b706c5bfaf5033b4\$lut for cells of type $lut. +Using template $paramod$2314742bee32bcbcec3260491c4b270a378de401\$lut for cells of type $lut. +Using template $paramod$994df4878b93229fd396eb4dcca07bd1eadd5560\$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. +Using template $paramod$c7da182350c463dac9341b9202c767a484f2d529\$lut for cells of type $lut. +Using template $paramod$54ef21ccddfa27629768f219f304bb4163ac6894\$lut for cells of type $lut. +Using template $paramod$243fb93e736df5581df7bafa378886f2bdf5bea9\$lut for cells of type $lut. +Using template $paramod$a50983bc2d916c31a7d4beac5feb90028d16502d\$lut for cells of type $lut. +Using template $paramod$2af7fd5c408581c2b6e80048f54948ce05a232f8\$lut for cells of type $lut. +Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut. +Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut. +Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut. +Using template $paramod$f0773b2e1ec54f4b5730a332b99958a07b433091\$lut for cells of type $lut. +Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut. +Using template $paramod$e00d03686849cf5e50e9f0c13f0f78958ff5e7ae\$lut for cells of type $lut. +Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. +Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut. +Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. +Using template $paramod$f71cd4e12d252829a6db80287a07ec7f20c3e099\$lut for cells of type $lut. +Using template $paramod$dae8f9b502bd1460fd180a1c0b20d573cb3bdfaa\$lut for cells of type $lut. +Using template $paramod$60e0a526d5120cb853aa823aea6dcb02645a9f39\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010010 for cells of type $lut. +Using template $paramod$348e2e3c2386524c4c07656cb22e89d0405fecdc\$lut for cells of type $lut. +Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005\$lut for cells of type $lut. +Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut. +Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. +Using template $paramod$9c7a967a5dd69d8b7070c7493295b0c7b420660f\$lut for cells of type $lut. +Using template $paramod$792289623e28f7bc3d64dc7e2dfa26bc7f05ab4b\$lut for cells of type $lut. +Using template $paramod$026ce654ad9d4d9bd0be5200be74a4e269c217d5\$lut for cells of type $lut. +Using template $paramod$24ca0390b3c7866a19922039474de91afb9e77c2\$lut for cells of type $lut. +Using template $paramod$066c8b79539c6cc144c5af6a60f411ebf4e1a8d9\$lut for cells of type $lut. +Using template $paramod$2a53f1f183bcacb7879917d65d33616d9ae625bd\$lut for cells of type $lut. +Using template $paramod$64e53fd3a6f1160fc572afc2acdd7c1e160cb372\$lut for cells of type $lut. +Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut. +Using template $paramod$8749993695cb7da49450e673823d6cab088c25d0\$lut for cells of type $lut. +Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. +Using template $paramod$3d7aaf571d14e064fbd16f4b1c68734d6cf34112\$lut for cells of type $lut. +Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. +Using template $paramod$0f321fbc35ab60cc9b1f13bcbf4423cb3e15af29\$lut for cells of type $lut. +Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. +Using template $paramod$e7aa2f1c351872cafc7a537c79b7ddbfb688eb74\$lut for cells of type $lut. +Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4\$lut for cells of type $lut. +Using template $paramod$6dbbd23ebc1f6c14e7875f941d268d34f7f03613\$lut for cells of type $lut. +Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut. +Using template $paramod$250e9ed6c15020113b6b30a5ef7c8f11f208ca8e\$lut for cells of type $lut. +Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut. +Using template $paramod$b4d49db958e100f96eebdc703313cdb7c6da2d30\$lut for cells of type $lut. +Using template $paramod$f5c118b1371bfc24986fe89a9f3e936c05edfbc3\$lut for cells of type $lut. +Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut. +Using template $paramod$12801c6c97a78eae361d6725b3f112db891faf26\$lut for cells of type $lut. +Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. +Using template $paramod$edfdd002d369b276282ba114ad80081aeb01c009\$lut for cells of type $lut. +Using template $paramod$6f20c26c0721e8b3757ca7b9a77b6e1d35f0f91c\$lut for cells of type $lut. +Using template $paramod$48ed08ac863093cb81be5bfb1a860b60659d37e0\$lut for cells of type $lut. +Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. +Using template $paramod$f045317e24613b3327ba32c229fc29aecd46a578\$lut for cells of type $lut. +Using template $paramod$afb8959a93937986ded51b1cddcab9e31c6ea2ed\$lut for cells of type $lut. +Using template $paramod$b8c12e9f20286ec99dd92b2fd58c920f7e7cec0f\$lut for cells of type $lut. +Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut. +Using template $paramod$f8276d8043930bc37fe6e7aece4838ca8cbbed88\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011110 for cells of type $lut. +Using template $paramod$5d9bdb7f5954011ff004758709112a4f3d3263f1\$lut for cells of type $lut. +Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. +Using template $paramod$39b3ba6c949a044323f4c3d176cbbb241f762ca2\$lut for cells of type $lut. +Using template $paramod$2ffdd48c31fd3abb3756c8ed29b2777c7dc5fa83\$lut for cells of type $lut. +Using template $paramod$cba63f0d3ee9d49c25aa31a3006491d02c8ce45c\$lut for cells of type $lut. +Using template $paramod$16709c7277a90cf041bff64ab2ca758c41bc27be\$lut for cells of type $lut. +Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. +Using template $paramod$15884c19b49d782a8abfd3de481c24e2addb4014\$lut for cells of type $lut. +Using template $paramod$31355df6e553d8cd6fcd0bf57a837c84b61d1970\$lut for cells of type $lut. +Using template $paramod$8ff12d04a511f1681452a4f5ee3c51dba9cfce88\$lut for cells of type $lut. +Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. +Using template $paramod$5a3c42a1f10797f72f7dc04a8b3d2a4bed295e15\$lut for cells of type $lut. +Using template $paramod$c980dd261d6fb09bc841af11d4475dbcab25c466\$lut for cells of type $lut. +Using template $paramod$eecb66b63ca1b933f7cd7fb6f0e7840fa51bb9cd\$lut for cells of type $lut. +Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. +Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. +Using template $paramod$cd39481dd3aba995896cce486ea250f3438a3533\$lut for cells of type $lut. +Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut. +Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70\$lut for cells of type $lut. +Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593\$lut for cells of type $lut. +Using template $paramod$45d35c067ded9854bad436d064758afc38659286\$lut for cells of type $lut. +Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd\$lut for cells of type $lut. +Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. +Using template $paramod$fae6ca420eabd44e6c9fdca31474d250778770c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. +Using template $paramod$92dc953d4569c20cd5765a3ce5567d53a74e7bab\$lut for cells of type $lut. +Using template $paramod$498a44c299976466f23c7e4de76f60e6cc568478\$lut for cells of type $lut. +Using template $paramod$f1c808a575959b8e5fe662725b574608671d76e5\$lut for cells of type $lut. +Using template $paramod$83f8a77a82b30303d0d950f0eb545c79a45eece4\$lut for cells of type $lut. +Using template $paramod$7b0d2a2ffb3b8f28d614fe2eb48a97cfa46f63f9\$lut for cells of type $lut. +Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut. +Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. +Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018\$lut for cells of type $lut. +Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. +Using template $paramod$246ec991bdd99746c8a8bc3d7793b764df6ed8d7\$lut for cells of type $lut. +Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. +Using template $paramod$a70047793dbc7d59dc2bc31d6c4f156b9e13dcbd\$lut for cells of type $lut. +Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. +Using template $paramod$f1e658ef767025439b6a062b79969dc402e1d2ab\$lut for cells of type $lut. +Using template $paramod$0ff46acca3c504a56e28cebb7c80b4cf6727f8cb\$lut for cells of type $lut. +Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. +Using template $paramod$a1eb35ff1d6419b0fc78314211740ca314e2d3e1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. +Using template $paramod$ef2e713cf94754a85372c7c4eece657b7521f115\$lut for cells of type $lut. +Using template $paramod$342895d61650d958a2336ec313ba396bdba7b36d\$lut for cells of type $lut. +Using template $paramod$ee454ad2383885733a4273245816698f8443c10b\$lut for cells of type $lut. +Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut. +Using template $paramod$afdefd64f115cbb578c1cd4bf8426ecfef85ae91\$lut for cells of type $lut. +Using template $paramod$ce57c8604805f80ab07a0434d106bb987e82ae6c\$lut for cells of type $lut. +Using template $paramod$7dc80f6db7113f8d3efb3affd3151d83c6b5c052\$lut for cells of type $lut. +Using template $paramod$c4e4e438f53deb14c1ad728c967e8024f686836f\$lut for cells of type $lut. +Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut. +Using template $paramod$f919e2eb4f0ec7b3a3ece075b1a81cd1886359a9\$lut for cells of type $lut. +Using template $paramod$28c1b4eb2d2d71f05d2260a615cda612ac87485b\$lut for cells of type $lut. +Using template $paramod$b1ad3aa394426898eee56afdd1a015c08b8ec3ca\$lut for cells of type $lut. +Using template $paramod$44adbaeba8aebac00b5b76c0c821287bd76a54f4\$lut for cells of type $lut. +Using template $paramod$8cd5a5f75f43fffe243164dff2e5d4f1454af19a\$lut for cells of type $lut. +Using template $paramod$242599a6dd1ccb968650e97e72150d00ebb8ccfc\$lut for cells of type $lut. +Using template $paramod$8ee9afdaea0539b1dd0f1adf915c5c609a483c46\$lut for cells of type $lut. +Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut. +Using template $paramod$849eede967b3c8935808391f1a9ce50503aa897a\$lut for cells of type $lut. +Using template $paramod$a511f425a16be7369933baa8c17a62ec61a7d7bf\$lut for cells of type $lut. +Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. +Using template $paramod$52fff9e56e72ea7ba0438be276221256c87f3756\$lut for cells of type $lut. +Using template $paramod$68fe50ee5a60a0bed36b1b1843c805d7bc807f41\$lut for cells of type $lut. +Using template $paramod$949912d41b6703327b37a3cbe8a7a7bc923219b7\$lut for cells of type $lut. +Using template $paramod$20ac3f9f2cd752a746ad32213f9c4f07fd5930ff\$lut for cells of type $lut. +Using template $paramod$d96938b933811903763c8fc48238ba3a4fe3fe61\$lut for cells of type $lut. +Using template $paramod$0f31dbbdcf77bf9799eaa7f2770f351711caa9d7\$lut for cells of type $lut. +Using template $paramod$a34a1094e2d314048608fde4d3073e1293d36b6f\$lut for cells of type $lut. +Using template $paramod$4cef79c5dcf504d402cc91e8e17ad287350b8594\$lut for cells of type $lut. +Using template $paramod$98c396e6f215a5928f903721dfd7ad31ae8269ff\$lut for cells of type $lut. +Using template $paramod$085ac6daadd555b0f8cf8f603c7849f876be6cbc\$lut for cells of type $lut. +Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut. +Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut. +Using template $paramod$67f667c8a3d1d844698cdb7b2f5a5deab3d9409a\$lut for cells of type $lut. +Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut. +Using template $paramod$7a09c632ebd39a203628a04507a2df81de3ade57\$lut for cells of type $lut. +Using template $paramod$04037df916e752dc482342577e8299341aae51a4\$lut for cells of type $lut. +Using template $paramod$cd6ddbad0e2d34a9a4c4738962cbc71837b95c56\$lut for cells of type $lut. +Using template $paramod$d80a3e34243dd01a86cdf267e33e3f33845e0abb\$lut for cells of type $lut. +Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. +Using template $paramod$ec0df19840033c8b18208b7471309a53c2b25de8\$lut for cells of type $lut. +Using template $paramod$106a0e61e3103f1a5ff0d32c1eb749cff02adb43\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. +Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut. +Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut. +Using template $paramod$d8f3c716f81512daaf4db8814134a1981792e8a8\$lut for cells of type $lut. +Using template $paramod$948f2992d65cd45de16107a58830a18abac36467\$lut for cells of type $lut. +Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut. +Using template $paramod$f6499a512b57be5fed724a1220dd8b76f9cb276b\$lut for cells of type $lut. +Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. +Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut. +Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut. +Using template $paramod$14480a541c7accf2d8a8c2b8f162e571e737174d\$lut for cells of type $lut. +Using template $paramod$b63d17d6a4aca2801204553b213c0505b1dcfa61\$lut for cells of type $lut. +Using template $paramod$67be80acf92b4861aed3d8085a5bb296f128f875\$lut for cells of type $lut. +Using template $paramod$028e503861792ef2faa7a49f86896b8c441bfd8d\$lut for cells of type $lut. +Using template $paramod$9eed22699c2653b52e395b92910215456ca209e1\$lut for cells of type $lut. +Using template $paramod$79432275bae6ba3c8cd1f392a278d15c8c6d8c77\$lut for cells of type $lut. +Using template $paramod$ea474c71a7a9bb027676021008daefb4ecbb4eb1\$lut for cells of type $lut. +Using template $paramod$b49c34751da1b37066c4dedc23af15b0caf21eff\$lut for cells of type $lut. +Using template $paramod$15d3dd50cc31557057274aea687fe2a8296cd155\$lut for cells of type $lut. +Using template $paramod$d7c634c964a868577f926c0690c937ab5b147f6e\$lut for cells of type $lut. +Using template $paramod$af0c0e3aea5daa768aac0697b02a2a49301800b1\$lut for cells of type $lut. +Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. +Using template $paramod$d9f23974f72a3ab437d1a63d2f34fd3483a6f58d\$lut for cells of type $lut. +Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut. +Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut. +Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076\$lut for cells of type $lut. +Using template $paramod$d62fc140c26bd45d16de3ebed6da0aa258adf691\$lut for cells of type $lut. +Using template $paramod$823cc3693c093331e82006c402f318cfda9e9960\$lut for cells of type $lut. +Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut. +Using template $paramod$889dc7b17c448030eaa05f5eb6c645a7ac00212c\$lut for cells of type $lut. +Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. +Using template $paramod$0d5e420ccfc2dddc13533c0817d1e17e68a2c136\$lut for cells of type $lut. +Using template $paramod$61e71a6b219041f218388451735d309581e08c5a\$lut for cells of type $lut. +Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut. +Using template $paramod$e13515ff50e27c9008f50b05a66e5bcc5bfc830a\$lut for cells of type $lut. +Using template $paramod$9bc8328e11fe3fccdf86fc34790ac24d79f83988\$lut for cells of type $lut. +Using template $paramod$03f612cf47cd227bbcfebe52575115af80c7c16c\$lut for cells of type $lut. +Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. +Using template $paramod$70d7bf515ac9884ee9b23e71bf77b47f76d185ef\$lut for cells of type $lut. +Using template $paramod$5fc7b8a2c522f6d2673f42cd967352990b6c7262\$lut for cells of type $lut. +Using template $paramod$9e3dc3fff64456e2f7592466fa8d9168932a933b\$lut for cells of type $lut. +Using template $paramod$89c0f9d0c35e6d27b98a949543dd6ffb685c8494\$lut for cells of type $lut. +Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut. +Using template $paramod$3c014941563a279228df79e25630751fec86819c\$lut for cells of type $lut. +Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. +Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut. +Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut. +Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut. +Using template $paramod$de4e6a7b8a15f6a5473e5f664954e687cc29a030\$lut for cells of type $lut. +Using template $paramod$f0f848e7cfbbc6be3de026782b732eac78406dea\$lut for cells of type $lut. +Using template $paramod$d96e26d600b7afaf2bc32e15f141020b276413e7\$lut for cells of type $lut. +Using template $paramod$368d87bdae2d7c7edd4471a7544662ae1a87a1e6\$lut for cells of type $lut. +Using template $paramod$5084523aff77b31b8ebe7370c66eee056a7dfa8d\$lut for cells of type $lut. +Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. +Using template $paramod$0425f46a1444788a7d60572c26dbde5e7cb29de0\$lut for cells of type $lut. +Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut. +Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut. +Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. +Using template $paramod$ea74080f8ebc8f3ea8275fd61051fa8e4bd0300d\$lut for cells of type $lut. +Using template $paramod$bccd6a49db7603b1feab5a542c51ed065a930da8\$lut for cells of type $lut. +Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. +Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. +Using template $paramod$b31dd1d80549ddba3254da46cdcb07cc4ccccfbe\$lut for cells of type $lut. +Using template $paramod$daf647bf6403143068eea8188cee93c3147be893\$lut for cells of type $lut. +Using template $paramod$8c23cdf2a4f29c3245c8b87835fc4980076df069\$lut for cells of type $lut. +Using template $paramod$35039c9689735d0b61f44caa3553cfd5a2fbb4b7\$lut for cells of type $lut. +Using template $paramod$eb762d00edf4fa32a2d134b034b0b70d5545798c\$lut for cells of type $lut. +Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut. +Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. +Using template $paramod$8a98d1c91d920b5f0ab2d9972c6d6a50d9b3c6a0\$lut for cells of type $lut. +Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. +Using template $paramod$d1d6b5f05bbc9409db63d690a4e859de80aaf468\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod$66e741791413519a466d4f44240bc83d3a191818\$lut for cells of type $lut. +Using template $paramod$2615c96857d1544911b5f413e145132efdb858f4\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. +Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$91cf3b8946a6c260321b0156c1a86ce6a2bf132f\$lut for cells of type $lut. +Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. +Using template $paramod$ba318f6d3458908ac57d56e5fa81a962ff2ab52b\$lut for cells of type $lut. +Using template $paramod$8543f2365289954cda2d9c99ae041aa434eda106\$lut for cells of type $lut. +Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut. +Using template $paramod$4bf055ca8a75a6b2e0a7cc21f3141b6576bbc879\$lut for cells of type $lut. +Using template $paramod$07138df23ef575563a02de1d610b812cf677ab4c\$lut for cells of type $lut. +Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut. +Using template $paramod$26582a7543f385ddf0816d466b3062a20d272771\$lut for cells of type $lut. +Using template $paramod$dd82bdb82a639de3374fa55b64e3421389be06aa\$lut for cells of type $lut. +Using template $paramod$e0592112fe4ea0fcfc3950f3065219da5f87f992\$lut for cells of type $lut. +Using template $paramod$21f957a7073b1ba634cad0df400394ca323de2fc\$lut for cells of type $lut. +Using template $paramod$1380a7bce1312c754eede24e3ccb152531be4f52\$lut for cells of type $lut. +Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83\$lut for cells of type $lut. +Using template $paramod$414fd3c1d97526aa52c17e578c5aaa0e6063335b\$lut for cells of type $lut. +Using template $paramod$482996866aebe48dc155049098c96180706e5d91\$lut for cells of type $lut. +Using template $paramod$5cbc08fcae16eb4ba45340fd09ba55fbeee8fd1b\$lut for cells of type $lut. +Using template $paramod$88433ebfb4d698fe0a845fd0a518078e0471ea2e\$lut for cells of type $lut. +Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. +Using template $paramod$464c0ecb5e74ffed195f4d7c313e6e3ea55be670\$lut for cells of type $lut. +Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. +Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut. +Using template $paramod$351521e8b01efeb144a39a20c4d973eb0b1643fa\$lut for cells of type $lut. +Using template $paramod$1607ccad58d340fc93ee9777e1a8e09981196091\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. +Using template $paramod$2bbec90035bea8ace991b30dd6d61930d1c61b49\$lut for cells of type $lut. +Using template $paramod$b01a883499671a5425bc39f21c1d1e0278d16ad5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. +Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. +Using template $paramod$ab5aa5e59731bfdc24344a9d76ddb6d9330c36d8\$lut for cells of type $lut. +Using template $paramod$cab646641d68cefe20d4670d8440ba9c72e8a81d\$lut for cells of type $lut. +Using template $paramod$02b64df0c401f8e2ba178158bc5ce7175355234e\$lut for cells of type $lut. +Using template $paramod$08ae2f8c57e504d818c187980b1ee5d5ef6b1a53\$lut for cells of type $lut. +Using template $paramod$d2e99342926657515eaf7de0e0d6e0ab51c92111\$lut for cells of type $lut. +Using template $paramod$dc2c6712e2363e0ec4d02acb1b3c7aca5011dab3\$lut for cells of type $lut. +Using template $paramod$b738327f68fe6bf1555d8b2ce106aa85e35a6229\$lut for cells of type $lut. +Using template $paramod$6477682786f5d5e7389f71b44247ccc2d8ce5e8a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000010 for cells of type $lut. +Using template $paramod$3cbede9dc45aa7c93c185b8b3fb81d9b642a0901\$lut for cells of type $lut. +Using template $paramod$5e3c6f6e85a59d8f346a84209f5467e2836bf075\$lut for cells of type $lut. +Using template $paramod$8d5f7407b13422c8618a39f6e856e3fba0266b3e\$lut for cells of type $lut. +Using template $paramod$756411e77af623de7df7b1d1a9d7ff92c0454cde\$lut for cells of type $lut. +Using template $paramod$c5dfd15977aff7866c1f09b915c247bca50db8d6\$lut for cells of type $lut. +Using template $paramod$63e7f8842b2dc57884e28c60d852ac2425249fe5\$lut for cells of type $lut. +Using template $paramod$36a4c79e9812e72b3f6507c9dad3f12c6810002b\$lut for cells of type $lut. +Using template $paramod$3a394e8383b9e427703b747b908e336d98ac94af\$lut for cells of type $lut. +Using template $paramod$c5d52721a6fa5fa0cd6921002a3db881c9ac6b2d\$lut for cells of type $lut. +Using template $paramod$c44e11032e98972888a9936a4d39d6c205c8401e\$lut for cells of type $lut. +Using template $paramod$4af6c2eac05ebe3ee05e3a43b6cf864989a9a4d3\$lut for cells of type $lut. +Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut. +Using template $paramod$be65c6dd49b2d5e0cfc5bbae2439c0c6399f66e9\$lut for cells of type $lut. +Using template $paramod$d7af698a9225f22318e3e0624744afe3ade563d2\$lut for cells of type $lut. +Using template $paramod$4ff816b87f3f349eb9fc7f927f77fe55d27f31db\$lut for cells of type $lut. +Using template $paramod$cb3b4bc8731dc6a330664b5559c44ae895962c70\$lut for cells of type $lut. +Using template $paramod$73c16989abb0b6227357c782c6da9786372b6d01\$lut for cells of type $lut. +Using template $paramod$694260564f5128262db3caa34951c3359318f936\$lut for cells of type $lut. +Using template $paramod$2adae487a6026f8719510df993658c524e9de1a6\$lut for cells of type $lut. +Using template $paramod$c6e922301decb6dd7dc97e85b89e30d1e96329e6\$lut for cells of type $lut. +Using template $paramod$20664e4f19b19b225c7d14483ea396530f4bb055\$lut for cells of type $lut. +Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999\$lut for cells of type $lut. +Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. +Using template $paramod$b71fae56e3eab939c22ce153c13d4d14b5267148\$lut for cells of type $lut. +Using template $paramod$59441c2b025f9a3bc4e5c2f53a4be4bc145aef49\$lut for cells of type $lut. +Using template $paramod$01d346930d9890fc7de6387e6db51bcc29b39c35\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. +Using template $paramod$b956a90e2f7ebac67c9d1d9c6aeb80f6d973e2e4\$lut for cells of type $lut. +No more expansions possible. + + +26.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in ulx3s_packet_top. + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$94980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$86011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$80011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$59984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$59168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$58946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35271.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35019.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$35007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$34605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$34528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276770.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$10965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$10965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$11009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$11027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$11970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$12986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$13931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$14992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$15947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$16808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$17861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$18827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$19886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$20716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$21785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$22707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$23935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$24982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$25946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$26968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$27950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$28963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$29240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$29247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$30210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$30232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$31060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$31940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$31988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$32137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$32150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$33712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$35403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$37888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$37951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$37989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$37999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$38773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$38822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$38956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$38996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$39799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$39888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$39910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$39986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$40322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$40763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$40859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$40981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$41650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$41737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$41963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$41974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$42851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$42999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$42999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$43401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$43726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$43988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$43997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$44214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$44253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$44336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$44879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$45966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$46432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$46471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$47576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$47633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$47843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$48540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$48767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$48926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$49956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$49956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$49969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$50978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$51452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$51752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$52569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$52758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$52890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$53887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$54988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$55987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$56825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$57478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$58721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$63009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63407.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$63981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$64002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$66322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$66557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$66575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$275068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$63724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$69883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$70527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$75268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$75442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$78625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$78629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$78647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$78658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$78675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$79389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$79984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$80980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$81339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$82429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$82461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$83451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$83465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$83560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84445.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$84506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$84536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$85547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$85876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$85984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$86339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$89566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$90764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$94984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$95018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$95026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$9744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$97834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$97891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$9991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$auto$abc9_ops.cc:595:break_scc$297311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$63710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$60672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$68771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$275068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$276642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$36005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$flatten\bridge.\g_packet.asic.\packet_core.\field_encoder.\multiplier.$procmux$7932_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$915302$lut$aiger915301$58148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$58634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$279676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$47514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$280162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$281998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$283512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$282928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$284998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$285238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$286602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$69869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70205.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$70093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$287240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$71381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$70793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$71017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$81493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$83035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$82475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$288914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$auto$rtlil.cc:2609:MuxGate$289966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$92000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$91948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$84329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$915829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$78690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$915302$lut$aiger915301$75627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$915302$lut$aiger915301$75482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$915302$lut$aiger915301$32974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$916947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) +Removed 0 unused cells and 53858 unused wires. + +26.45. Executing AUTONAME pass. +Renamed 4810507 objects in module ulx3s_packet_top (720 iterations). + + +26.46. Executing HIERARCHY pass (managing design hierarchy). + +26.46.1. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top + +26.46.2. Analyzing design hierarchy.. +Top module: \ulx3s_packet_top +Removed 0 unused modules. + +26.47. Printing statistics. + +=== ulx3s_packet_top === + + Number of wires: 26458 + Number of wire bits: 78079 + Number of public wires: 26458 + Number of public wire bits: 78079 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 39206 + CCU2C 785 + EHXPLLL 1 + L6MUX21 270 + LUT4 27175 + MULT18X18D 1 + PFUMX 3753 + TRELLIS_FF 7221 + +26.48. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_packet_top... +Found and reported 0 problems. + +27. Executing JSON backend. + +Warnings: 4 unique messages, 8 total +End of script. Logfile hash: 90f553ec51, CPU: user 272.59s system 4.03s, MEM: 1873.06 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 21% 1x abc9_exe (76 sec), 17% 1x autoname (63 sec), ... diff --git a/evidence/lsc1-09-cleanroom/reproduction-receipt.json b/evidence/lsc1-09-cleanroom/reproduction-receipt.json index 52c911e8..d2dee55f 100644 --- a/evidence/lsc1-09-cleanroom/reproduction-receipt.json +++ b/evidence/lsc1-09-cleanroom/reproduction-receipt.json @@ -1,10 +1,10 @@ { - "schema": "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v1", + "schema": "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v2", "scoper": "99f65947-0cdb-4d83-a569-d3bf3d1458ae", "base_commit": "5610ea221dd82b5749690043e8c3665b2be9ced8", "build_source": { - "commit": "fde1b885a56b98391833f4632676f14d1e3e2f9c", - "tree": "87462c2c698c43318df8b9a4db78c0c6ca9de251", + "commit": "adc3e2c5b86fb08e1b0225573486ae08af4ac194", + "tree": "cec1a2ede2202e7889dfec4165d658f8d3e415d5", "inputs_match_revision": true }, "scope": { @@ -20,8 +20,8 @@ "executable_model": "not exercised by the reproduction builds", "lean": "validated separately; does not prove the bitstream", "authored_rtl": "build input only", - "netlist": "generated intermediate only", - "place_and_route": "two host executions with archived timing receipts", + "netlist": "generated logical intermediate only", + "place_and_route": "two preserved host executions with timing receipts", "physical_hardware": "no board attached, programmed, or observed" }, "toolchain": { @@ -35,50 +35,44 @@ "runs": [ { "id": "clean-build-1", - "checkout": "independent detached worktree", + "checkout": "separate clean clone detached at build_source", "pre_build_tracked_clean": true, "exit_code": 0, - "source_manifest_sha256": "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", - "artifact_manifest_complete": true, - "program_finished_normally": true, - "core_clock_pass": true, - "achieved_core_clock_mhz": 15.32, - "raw_receipt_sha256": { + "evidence_sha256": { "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", - "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", - "yosys.log": "54813f13acb695472ce71450f9f94d5a6118274c47332866cea1ed9b4271149f", - "nextpnr.log": "8a161adaf61e8d97c25a7bacadcbcb82144ed8c0392e31445c0d8cec754c8fb0", - "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba" - }, - "artifacts": { + "SOURCE_MANIFEST.txt": "0bc16e2f0a9ac2898397b294ee8598bab14d2e3e365b639ed14e3a2d3406dab8", + "build.stderr": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "build.stdout": "6f7d74f3be9705e033495da9fb32f471f94f96dea3aba12186e9439840155e18", + "ecppack.log": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "nextpnr.log": "07b91105557953e74ad07c1abcd79b644580301eddb470bbfa1a9c2f3a9fcf17", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", + "tool_versions.txt": "e026fa9460991757e1d8f6a077ae81a6e36607c93887d8b17979b3e0edf38f26", "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", - "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee" + "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee", + "yosys.log": "bbfbb242f6bc0f3b02f1b105c1b3f7c981cab7be08deb71a995e69fe09acfdd7" } }, { "id": "clean-build-2", - "checkout": "independent detached worktree", + "checkout": "separate clean clone detached at build_source", "pre_build_tracked_clean": true, "exit_code": 0, - "source_manifest_sha256": "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", - "artifact_manifest_complete": true, - "program_finished_normally": true, - "core_clock_pass": true, - "achieved_core_clock_mhz": 15.32, - "raw_receipt_sha256": { + "evidence_sha256": { "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", - "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", - "yosys.log": "a6ad59bf36b5acd48fe7448132d687730118a33c5181ff9185d7358d8e840028", - "nextpnr.log": "2d01813e70101a4dfc7a376f8234c4a3d92007e6c97e0ea1b428fbaf579f65c2", - "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba" - }, - "artifacts": { + "SOURCE_MANIFEST.txt": "0bc16e2f0a9ac2898397b294ee8598bab14d2e3e365b639ed14e3a2d3406dab8", + "build.stderr": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "build.stdout": "667c264f5ceb3a207c1e0b8deda6020d700963c2d60f7f50385acb8c2d5db38b", + "ecppack.log": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "nextpnr.log": "3dc26a9f8dca3b968e034728fd453eb5234b148b8f039792f844d0395d4f6139", + "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", + "tool_versions.txt": "e026fa9460991757e1d8f6a077ae81a6e36607c93887d8b17979b3e0edf38f26", "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", - "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee" + "ulx3s_lsc1_packet.svf": "0ad6510adeb1afbc3b20bdbc96528211a2d2e38ebcee398fdeb82acb3b1ad0ee", + "yosys.log": "189e5d6c46bacdc04b208684042a95ce8f4f8887daece94e58bfdf7f71148b10" } } ], - "conclusion": "two clean host builds reproduced the archived packet bitstream artifacts byte-for-byte" + "conclusion": "two isolated clean host builds reproduced the archived packet bitstream artifacts byte-for-byte" } diff --git a/test/test_lsc1_fpga_packet_evidence.py b/test/test_lsc1_fpga_packet_evidence.py index 552484d0..a548c4ea 100644 --- a/test/test_lsc1_fpga_packet_evidence.py +++ b/test/test_lsc1_fpga_packet_evidence.py @@ -9,6 +9,7 @@ from tools.verify_lsc1_fpga_packet_evidence import ( ROOT, PACKET_BUILD_INPUTS, PINNED_BITSTREAM, PINNED_BUILD_FILES, + PINNED_BUILD_SOURCE, PINNED_BUILD_TREE, PINNED_SOURCE_ANCHOR, SUPPORTED_CAD_VERSIONS, pinned_build_bytes, verify, EvidenceError, ) import lsc1_transaction as p @@ -38,11 +39,11 @@ def fixture(self, directory: Path) -> None: capture = {"transport": "ULX3S UART to existing 8-bit ready/valid pins", "reset": "fresh hardware reset before first byte", "exchanges": exchanges} (directory / "capture.json").write_text(json.dumps(capture, sort_keys=True) + "\n") - head = "fde1b885a56b98391833f4632676f14d1e3e2f9c" - tree = subprocess.check_output(["git", "rev-parse", f"{head}^{{tree}}"], cwd=ROOT, text=True).strip() + head = PINNED_BUILD_SOURCE + tree = PINNED_BUILD_TREE entries = [] for source_rel in sorted(PACKET_BUILD_INPUTS): - source = subprocess.check_output(["git", "show", f"{head}:{source_rel}"], cwd=ROOT) + source = subprocess.check_output(["git", "show", f"{PINNED_SOURCE_ANCHOR}:{source_rel}"], cwd=ROOT) entries.append(f"{hashlib.sha256(source).hexdigest()} {source_rel}\n") manifest = (f"=== SOURCE PROVENANCE ===\nrevision: {head}\n" "inputs-match-revision: yes\n" + "".join(entries)) diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index f61c3690..d92556e1 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -1,50 +1,98 @@ from __future__ import annotations import copy +import hashlib import json import tempfile import unittest from pathlib import Path -from tools.verify_lsc1_ulx3s_reproduction import RECEIPT, verify +from tools.verify_lsc1_ulx3s_reproduction import EVIDENCE, RECEIPT, verify class ReproductionReceiptTest(unittest.TestCase): def receipt(self) -> dict: return json.loads(RECEIPT.read_text()) - def rejected(self, mutate, message: str) -> None: + def evidence_links(self, root: Path) -> None: + for run_id in ("clean-build-1", "clean-build-2"): + target = root / run_id + target.mkdir() + for source in (EVIDENCE / run_id).iterdir(): + (target / source.name).symlink_to(source) + + @staticmethod + def replace(path: Path, payload: bytes) -> None: + path.unlink() + path.write_bytes(payload) + + def rejected(self, mutate_receipt=lambda _r: None, mutate_evidence=lambda _e, _r: None, + message: str = "") -> None: receipt = copy.deepcopy(self.receipt()) - mutate(receipt) + mutate_receipt(receipt) with tempfile.TemporaryDirectory() as td: - path = Path(td) / "receipt.json" + root = Path(td) + evidence = root / "evidence" + evidence.mkdir() + self.evidence_links(evidence) + mutate_evidence(evidence, receipt) + path = root / "receipt.json" path.write_text(json.dumps(receipt)) with self.assertRaisesRegex(ValueError, message): - verify(path) + verify(path, evidence) def test_receipt_accepts(self): verify() - def test_missing_second_run_rejected(self): - self.rejected(lambda r: r["runs"].pop(), "exactly two runs") + def test_missing_second_run_receipt_rejected(self): + self.rejected(mutate_receipt=lambda r: r["runs"].pop(), message="exactly two runs") - def test_nonzero_exit_rejected(self): - self.rejected(lambda r: r["runs"][1].update(exit_code=1), "normal exit") + def test_missing_preserved_run_file_rejected(self): + def remove(evidence: Path, _receipt: dict) -> None: + (evidence / "clean-build-2" / "nextpnr.log").unlink() + self.rejected(mutate_evidence=remove, message="complete run evidence clean-build-2") - def test_timing_failure_rejected(self): - self.rejected(lambda r: r["runs"][0].update(core_clock_pass=False), "10 MHz timing") + def test_substituted_run_file_rejected(self): + def substitute(evidence: Path, _receipt: dict) -> None: + payload = (EVIDENCE / "clean-build-1" / "nextpnr.log").read_bytes() + self.replace(evidence / "clean-build-2" / "nextpnr.log", payload) + self.rejected(mutate_evidence=substitute, message="preserved evidence hashes clean-build-2") - def test_artifact_divergence_rejected(self): - self.rejected(lambda r: r["runs"][1]["artifacts"].update(ulx3s_lsc1_packet={}), "run artifact hashes") + def test_rehashed_inconsistent_timing_receipt_rejected(self): + def inconsistent(evidence: Path, receipt: dict) -> None: + path = evidence / "clean-build-1" / "timing.txt" + payload = b"Info: Max frequency for clock 'core_clk': 99 MHz (PASS at 10.00 MHz)\n" + self.replace(path, payload) + receipt["runs"][0]["evidence_sha256"]["timing.txt"] = hashlib.sha256(payload).hexdigest() + self.rejected(mutate_evidence=inconsistent, message="timing receipt consistency clean-build-1") - def test_raw_log_digest_mutation_rejected(self): - self.rejected(lambda r: r["runs"][0]["raw_receipt_sha256"].update({"nextpnr.log": "0" * 64}), "raw receipt hashes") + def test_rehashed_self_authored_cad_log_rejected(self): + def forged(evidence: Path, receipt: dict) -> None: + path = evidence / "clean-build-1" / "nextpnr.log" + payload = (b"Info: Derived frequency constraint of 10.0 MHz for net core_clk\n" + b"Info: Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz)\n") + self.replace(path, payload) + receipt["runs"][0]["evidence_sha256"]["nextpnr.log"] = hashlib.sha256(payload).hexdigest() + self.rejected(mutate_evidence=forged, message="nextpnr completion clean-build-1") + + def test_rehashed_source_substitution_rejected(self): + def substitute(evidence: Path, receipt: dict) -> None: + path = evidence / "clean-build-1" / "SOURCE_MANIFEST.txt" + payload = path.read_bytes().replace(b"revision: adc3e2c5", b"revision: fde1b885") + self.replace(path, payload) + receipt["runs"][0]["evidence_sha256"]["SOURCE_MANIFEST.txt"] = hashlib.sha256(payload).hexdigest() + self.rejected(mutate_evidence=substitute, message="source manifest identity") + + def test_nonzero_exit_rejected(self): + self.rejected(mutate_receipt=lambda r: r["runs"][1].update(exit_code=1), message="normal exit") def test_scope_expansion_rejected(self): - self.rejected(lambda r: r["scope"].update(physical_hardware=True), "scope boundary physical_hardware") + self.rejected(mutate_receipt=lambda r: r["scope"].update(physical_hardware=True), + message="scope boundary physical_hardware") def test_unpinned_option_rejected(self): - self.rejected(lambda r: r["nextpnr_options"].remove("--no-tmdriv"), "nextpnr options") + self.rejected(mutate_receipt=lambda r: r["nextpnr_options"].remove("--no-tmdriv"), + message="nextpnr options") if __name__ == "__main__": diff --git a/tools/verify_lsc1_fpga_packet_evidence.py b/tools/verify_lsc1_fpga_packet_evidence.py index 957ae944..d9c27a1e 100644 --- a/tools/verify_lsc1_fpga_packet_evidence.py +++ b/tools/verify_lsc1_fpga_packet_evidence.py @@ -66,6 +66,13 @@ class EvidenceError(RuntimeError): # verifier therefore anchors generated outputs and raw CAD receipts to this # Git-tracked bundle, whose SOURCE_MANIFEST names the exact clean input commit. PINNED_BUILD_DIR = "results/ulx3s-lsc1-packet-20260726" +PINNED_BUILD_SOURCE = "fde1b885a56b98391833f4632676f14d1e3e2f9c" +PINNED_BUILD_TREE = "87462c2c698c43318df8b9a4db78c0c6ca9de251" +# The historical clean checkout above was detached and its commit object was +# never made reachable. adc3e2c is on this branch and has byte-identical +# packet-build inputs, so standalone verification reads those inputs here. +PINNED_SOURCE_ANCHOR = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" +PINNED_SOURCE_ANCHOR_TREE = "cec1a2ede2202e7889dfec4165d658f8d3e415d5" PINNED_BUILD_FILES = frozenset({ "tool_versions.txt", "timing.txt", @@ -104,6 +111,8 @@ def verify_pinned_build(directory: Path, source_head: str, bit_name: str) -> Non build_revision, _ = parse_source_manifest(Path(manifest_file.name)) require(source_head == build_revision, "provenance", "source HEAD is not the pinned build input revision") + require(build_revision == PINNED_BUILD_SOURCE, "provenance", + "pinned build manifest has an unexpected historical revision") require(bit_name == PINNED_BITSTREAM, "provenance", "bitstream name is not the pinned build output") require((directory / bit_name).read_bytes() == pinned_build_bytes(PINNED_BITSTREAM), @@ -211,7 +220,10 @@ def verify(directory: Path) -> None: require(receipt.get("physical_capture") is True, "provenance", "receipt does not claim a physical capture") source_head = receipt.get("source_head", "") require(len(source_head) == 40, "provenance", "source HEAD is not a full object ID") - require(receipt.get("source_tree") == git("rev-parse", f"{source_head}^{{tree}}"), "provenance", "source tree differs from pinned source commit") + require(receipt.get("source_tree") == PINNED_BUILD_TREE, "provenance", + "source tree differs from recorded clean build tree") + require(git("rev-parse", f"{PINNED_SOURCE_ANCHOR}^{{tree}}") == PINNED_SOURCE_ANCHOR_TREE, + "provenance", "reachable source anchor tree mismatch") require(receipt.get("source_clean") is True and receipt.get("source_status_porcelain") == "" and receipt.get("build_inputs_clean") is True, "provenance", "source/build cleanliness is not affirmed") require(receipt.get("board_revision") == "v3.1.8", "provenance", "board revision is not v3.1.8") @@ -257,7 +269,7 @@ def verify(directory: Path) -> None: for rel, expected in sources.items(): candidate = (ROOT / rel).resolve() require(candidate.is_relative_to(ROOT), "provenance", f"manifest path escapes repository: {rel}") - require(hashlib.sha256(git_bytes("show", f"{revision}:{rel}")).hexdigest() == expected, + require(hashlib.sha256(git_bytes("show", f"{PINNED_SOURCE_ANCHOR}:{rel}")).hexdigest() == expected, "provenance", f"source digest mismatch: {rel}") artifacts = receipt.get("artifacts", {}) require(artifacts.get("capture.json") == digest(capture_path), "provenance", "capture digest mismatch") diff --git a/tools/verify_lsc1_ulx3s_reproduction.py b/tools/verify_lsc1_ulx3s_reproduction.py index 7cddfbe5..e17819c2 100644 --- a/tools/verify_lsc1_ulx3s_reproduction.py +++ b/tools/verify_lsc1_ulx3s_reproduction.py @@ -1,17 +1,20 @@ #!/usr/bin/env python3 -"""Fail-closed verification of the two-run host-build reproduction receipt.""" +"""Fail-closed verification of two preserved clean ULX3S host builds.""" from __future__ import annotations import hashlib import json +import re import subprocess import sys from pathlib import Path ROOT = Path(__file__).resolve().parents[1] RECEIPT = ROOT / "evidence/lsc1-09-cleanroom/reproduction-receipt.json" +EVIDENCE = ROOT / "evidence/lsc1-09-cleanroom" ARCHIVE = ROOT / "results/ulx3s-lsc1-packet-20260726" -SOURCE = "fde1b885a56b98391833f4632676f14d1e3e2f9c" +SOURCE = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" +SOURCE_TREE = "cec1a2ede2202e7889dfec4165d658f8d3e415d5" BASE = "5610ea221dd82b5749690043e8c3665b2be9ced8" ARTIFACTS = { "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", @@ -24,21 +27,10 @@ "ecppack": "Project Trellis ecppack Version 1.4-2build4", } OPTIONS = ["--85k", "--package", "CABGA381", "--seed", "2", "--placer", "static", "--no-tmdriv", "--router", "router1"] -RAW_RECEIPTS = { - "clean-build-1": { - "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", - "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", - "yosys.log": "54813f13acb695472ce71450f9f94d5a6118274c47332866cea1ed9b4271149f", - "nextpnr.log": "8a161adaf61e8d97c25a7bacadcbcb82144ed8c0392e31445c0d8cec754c8fb0", - "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", - }, - "clean-build-2": { - "SHA256SUMS": "cfe3dd6c384c54aedef2221263aa7b401ccf677e874e320b567a0359aaa515cf", - "tool_versions.txt": "2e986e53019b3d9e7b8229739010f1cf7e7140184f0026bb3cbfb99116a8f1fe", - "yosys.log": "a6ad59bf36b5acd48fe7448132d687730118a33c5181ff9185d7358d8e840028", - "nextpnr.log": "2d01813e70101a4dfc7a376f8234c4a3d92007e6c97e0ea1b428fbaf579f65c2", - "timing.txt": "47341676d69dd768b09e816679652101ec997dca651dfacdb90a3da8cad2c9ba", - }, +RUN_FILES = { + "SHA256SUMS", "SOURCE_MANIFEST.txt", "build.stderr", "build.stdout", + "ecppack.log", "nextpnr.log", "timing.txt", "tool_versions.txt", + *ARTIFACTS, "yosys.log", } @@ -51,15 +43,92 @@ def sha(path: Path) -> str: return hashlib.sha256(path.read_bytes()).hexdigest() -def verify(path: Path = RECEIPT) -> None: +def git(*args: str) -> str: + return subprocess.check_output(["git", *args], cwd=ROOT, text=True).strip() + + +def parse_hash_manifest(path: Path) -> dict[str, str]: + result: dict[str, str] = {} + for line in path.read_text(encoding="utf-8").splitlines(): + fields = line.split() + require(len(fields) == 2 and re.fullmatch(r"[0-9a-f]{64}", fields[0]) is not None, + f"malformed hash manifest {path.name}") + require(fields[1] not in result, f"duplicate hash manifest entry {fields[1]}") + result[fields[1]] = fields[0] + return result + + +def verify_source_manifest(path: Path) -> None: + lines = path.read_text(encoding="utf-8").splitlines() + require(lines[:3] == ["=== SOURCE PROVENANCE ===", f"revision: {SOURCE}", + "inputs-match-revision: yes"], "source manifest identity") + entries: dict[str, str] = {} + for line in lines[3:]: + fields = line.split() + require(len(fields) == 2 and re.fullmatch(r"[0-9a-f]{64}", fields[0]) is not None, + "malformed source manifest") + require(fields[1] not in entries, f"duplicate source input {fields[1]}") + entries[fields[1]] = fields[0] + require(len(entries) == 25, "complete source manifest") + for name, expected in entries.items(): + try: + payload = subprocess.check_output(["git", "show", f"{SOURCE}:{name}"], cwd=ROOT) + except subprocess.CalledProcessError as error: + raise ValueError(f"source input absent at pinned commit: {name}") from error + require(hashlib.sha256(payload).hexdigest() == expected, + f"source input differs from pinned commit: {name}") + + +def verify_run(run: dict, evidence_root: Path) -> dict[str, str]: + run_id = run.get("id", "") + require(run_id in {"clean-build-1", "clean-build-2"}, "independent run identities") + require(run.get("checkout") == "separate clean clone detached at build_source", "isolated checkout") + require(run.get("pre_build_tracked_clean") is True, "clean checkout") + require(run.get("exit_code") == 0, "normal exit") + directory = evidence_root / run_id + require(directory.is_dir(), f"missing run evidence {run_id}") + actual_names = {item.name for item in directory.iterdir() if item.is_file()} + require(actual_names == RUN_FILES, f"complete run evidence {run_id}") + expected_hashes = run.get("evidence_sha256") + require(isinstance(expected_hashes, dict) and set(expected_hashes) == RUN_FILES, + f"complete evidence hash set {run_id}") + actual_hashes = {name: sha(directory / name) for name in RUN_FILES} + require(actual_hashes == expected_hashes, f"preserved evidence hashes {run_id}") + + verify_source_manifest(directory / "SOURCE_MANIFEST.txt") + require(parse_hash_manifest(directory / "SHA256SUMS") == ARTIFACTS, + f"artifact manifest {run_id}") + for name, expected in ARTIFACTS.items(): + require(actual_hashes[name] == expected, f"generated artifact {run_id} {name}") + versions = (directory / "tool_versions.txt").read_text(encoding="utf-8") + require(all(value in versions for value in TOOLS.values()), f"tool versions {run_id}") + require((directory / "build.stderr").read_bytes() == b"", f"build stderr {run_id}") + stdout = (directory / "build.stdout").read_text(encoding="utf-8") + require("inputs-match-revision: yes" in stdout and "PASS at 10.00 MHz" in stdout + and f"sha256: {ARTIFACTS['ulx3s_lsc1_packet.bit']}" in stdout, + f"build command receipt {run_id}") + nextpnr = (directory / "nextpnr.log").read_text(encoding="utf-8") + require("Info: Program finished normally." in nextpnr, f"nextpnr completion {run_id}") + require("Derived frequency constraint of 10.0 MHz for net core_clk" in nextpnr + and "Max frequency for clock '$glbnet$core_clk': 15.32 MHz (PASS at 10.00 MHz)" in nextpnr, + f"10 MHz timing {run_id}") + timing_lines = [line for line in nextpnr.splitlines() + if re.search(r"Input frequency of PLL|Derived frequency constraint|Max frequency|Slack", line)][-8:] + require((directory / "timing.txt").read_text(encoding="utf-8").splitlines() == timing_lines, + f"timing receipt consistency {run_id}") + require("Number of cells: 39206" in (directory / "yosys.log").read_text(encoding="utf-8"), + f"yosys completion {run_id}") + return actual_hashes + + +def verify(path: Path = RECEIPT, evidence_root: Path = EVIDENCE) -> None: r = json.loads(path.read_text(encoding="utf-8")) - require(r.get("schema") == "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v1", "schema") + require(r.get("schema") == "lean-silicon.lsc1-ulx3s-cleanroom-reproduction.v2", "schema") require(r.get("scoper") == "99f65947-0cdb-4d83-a569-d3bf3d1458ae", "scoper") require(r.get("base_commit") == BASE, "base commit") source = r.get("build_source", {}) - require(source == {"commit": SOURCE, "tree": "87462c2c698c43318df8b9a4db78c0c6ca9de251", "inputs_match_revision": True}, "source identity") - tree = subprocess.check_output(["git", "rev-parse", f"{SOURCE}^{{tree}}"], cwd=ROOT, text=True).strip() - require(tree == source["tree"], "source tree object") + require(source == {"commit": SOURCE, "tree": SOURCE_TREE, "inputs_match_revision": True}, "source identity") + require(git("rev-parse", f"{SOURCE}^{{tree}}") == SOURCE_TREE, "source tree object") scope = r.get("scope", {}) require(scope.get("design") == "full LSC-1 host-prepared packet UART endpoint", "full LSC-1 scope") for key in ("host_fetch", "memory_expansion", "physical_hardware", "end_to_end", "universal_or_unbounded", "later_roadmap_work"): @@ -70,30 +139,23 @@ def verify(path: Path = RECEIPT) -> None: require(r.get("command") == ["./fpga/ulx3s/build_packet_uart.sh"], "command") require(r.get("nextpnr_options") == OPTIONS, "nextpnr options") require(r.get("required_core_clock_mhz") == 10.0, "clock requirement") - manifest = {line.split()[1]: line.split()[0] for line in (ARCHIVE / "SHA256SUMS").read_text().splitlines()} - require(manifest == ARTIFACTS, "archived artifact manifest") + require(parse_hash_manifest(ARCHIVE / "SHA256SUMS") == ARTIFACTS, "archived artifact manifest") for name, expected in ARTIFACTS.items(): require(sha(ARCHIVE / name) == expected, f"archived hash {name}") runs = r.get("runs") require(isinstance(runs, list) and len(runs) == 2, "exactly two runs") - require({x.get("id") for x in runs} == {"clean-build-1", "clean-build-2"}, "independent run identities") - for run in runs: - require(run.get("checkout") == "independent detached worktree", "isolated checkout") - require(run.get("pre_build_tracked_clean") is True, "clean checkout") - require(run.get("exit_code") == 0, "normal exit") - require(run.get("source_manifest_sha256") == "bd86d1c1b265d4ee34d4aa152b7a86cba6cea36b2fde3d29bc48e3852e5f8f81", "complete source manifest") - require(run.get("artifact_manifest_complete") is True, "complete artifact manifest") - require(run.get("program_finished_normally") is True, "nextpnr completion") - require(run.get("core_clock_pass") is True and run.get("achieved_core_clock_mhz", 0) >= 10.0, "10 MHz timing") - require(run.get("raw_receipt_sha256") == RAW_RECEIPTS[run["id"]], "raw receipt hashes") - require(run.get("artifacts") == ARTIFACTS, "run artifact hashes") - require(r.get("conclusion") == "two clean host builds reproduced the archived packet bitstream artifacts byte-for-byte", "conclusion") + require({x.get("id") for x in runs if isinstance(x, dict)} == {"clean-build-1", "clean-build-2"}, "independent run identities") + hashes = {run["id"]: verify_run(run, evidence_root) for run in runs} + require(hashes["clean-build-1"]["nextpnr.log"] != hashes["clean-build-2"]["nextpnr.log"] + and hashes["clean-build-1"]["yosys.log"] != hashes["clean-build-2"]["yosys.log"], + "independent run receipts") + require(r.get("conclusion") == "two isolated clean host builds reproduced the archived packet bitstream artifacts byte-for-byte", "conclusion") def main() -> int: try: verify() - except (ValueError, KeyError, json.JSONDecodeError, OSError, subprocess.CalledProcessError) as error: + except (ValueError, KeyError, TypeError, json.JSONDecodeError, OSError, subprocess.CalledProcessError) as error: print(f"FAIL reproduction receipt: {error}", file=sys.stderr) return 1 print("PASS two-run clean-room ULX3S LSC-1 host-build reproduction") From ebf087429ad01cb89d604996a67a76ac565f598d Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 04:07:56 +0200 Subject: [PATCH 04/10] fix: keep ULX3S evidence valid after squash --- SHA256SUMS | 6 ++-- test/test_lsc1_ulx3s_reproduction.py | 42 +++++++++++++++++++++++ tools/verify_lsc1_fpga_packet_evidence.py | 8 ++--- tools/verify_lsc1_ulx3s_reproduction.py | 9 ++--- 4 files changed, 54 insertions(+), 11 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index 590fd199..239d0f9e 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -2fa8f3fb0eb7bd1a9c6ae69b6aecac7c6a5978e5ca22bfacbc1d2586ff1e93ef ./test/test_lsc1_ulx3s_reproduction.py +89bf755b3c41f7992a7d487f600dbc94ffe2b7764f716d2549507051f3134180 ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py @@ -627,8 +627,8 @@ d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b ./tools/rtl_st a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py 6f6d2f97d96aeddd39e3bae8c4ea9193bec8a5a4237d5a17a93057e1d2c38f26 ./tools/verify_fabrication_bundle.py -39798bd016682b3ab57644a8eca7fedf46d5369d3c54230fdf8c4645c673536f ./tools/verify_lsc1_fpga_packet_evidence.py -e914ee72891c4a49a50e698a425e1d822501c0ad8408f31faf25e7a265d821ea ./tools/verify_lsc1_ulx3s_reproduction.py +28bb061b2dee67ca8768a54a7d216762b601fc700606f52c076e894939dd12ba ./tools/verify_lsc1_fpga_packet_evidence.py +a89cefd8ff81aef14586746339c6d4a214d1bbc35619e31e48c39fe67247a701 ./tools/verify_lsc1_ulx3s_reproduction.py 650919f4b3f0d2a94022d4de230f16afca36fc5c3eee45b77571cb0ec5c52994 ./tools/verify_lsc1u_release_equivalence.py 4af566c345d8108c6b409f0c622fe132bdfc3b3a2b3eddee28f778e378d71254 ./tools/workload_validation.py d930b3a00795450bad3cfa1941fcc3028e03b5cf9724dab32c7f07d0678f38b4 ./workloads/blake3_stack.program.json diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index d92556e1..935c9e26 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -3,6 +3,9 @@ import copy import hashlib import json +import os +import subprocess +import sys import tempfile import unittest from pathlib import Path @@ -94,6 +97,45 @@ def test_unpinned_option_rejected(self): self.rejected(mutate_receipt=lambda r: r["nextpnr_options"].remove("--no-tmdriv"), message="nextpnr options") + def test_post_squash_single_branch_checkout_accepts(self): + """P1 family: verification cannot depend on an intermediate PR commit.""" + source = RECEIPT.parents[2] + intermediate = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" + base = "5610ea221dd82b5749690043e8c3665b2be9ced8" + with tempfile.TemporaryDirectory() as td: + root = Path(td) + staging = root / "staging.git" + checkout = root / "checkout" + subprocess.run(["git", "clone", "--bare", "--shared", str(source), str(staging)], + check=True, stdout=subprocess.DEVNULL) + tree = subprocess.check_output(["git", "-C", str(source), "rev-parse", "HEAD^{tree}"], + text=True).strip() + env = os.environ | { + "GIT_AUTHOR_NAME": "post-squash regression", + "GIT_AUTHOR_EMAIL": "regression@example.invalid", + "GIT_COMMITTER_NAME": "post-squash regression", + "GIT_COMMITTER_EMAIL": "regression@example.invalid", + } + squash = subprocess.check_output( + ["git", f"--git-dir={staging}", "commit-tree", tree, "-p", base, "-m", "squash"], + env=env, text=True).strip() + refs = subprocess.check_output( + ["git", f"--git-dir={staging}", "for-each-ref", "--format=%(refname)"], + text=True).splitlines() + for ref in refs: + subprocess.run(["git", f"--git-dir={staging}", "update-ref", "-d", ref], check=True) + subprocess.run(["git", f"--git-dir={staging}", "update-ref", "refs/heads/squash", squash], + check=True) + subprocess.run(["git", "clone", "--no-local", "--single-branch", "--branch", "squash", + str(staging), str(checkout)], check=True, stdout=subprocess.DEVNULL) + missing = subprocess.run(["git", "-C", str(checkout), "cat-file", "-e", intermediate], + stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) + self.assertNotEqual(missing.returncode, 0) + subprocess.run([sys.executable, "tools/verify_lsc1_ulx3s_reproduction.py"], + cwd=checkout, check=True) + subprocess.run([sys.executable, "test/test_lsc1_fpga_packet_evidence.py", "-v"], + cwd=checkout, env=os.environ | {"PYTHONPATH": "."}, check=True) + if __name__ == "__main__": unittest.main() diff --git a/tools/verify_lsc1_fpga_packet_evidence.py b/tools/verify_lsc1_fpga_packet_evidence.py index d9c27a1e..e03de594 100644 --- a/tools/verify_lsc1_fpga_packet_evidence.py +++ b/tools/verify_lsc1_fpga_packet_evidence.py @@ -69,10 +69,10 @@ class EvidenceError(RuntimeError): PINNED_BUILD_SOURCE = "fde1b885a56b98391833f4632676f14d1e3e2f9c" PINNED_BUILD_TREE = "87462c2c698c43318df8b9a4db78c0c6ca9de251" # The historical clean checkout above was detached and its commit object was -# never made reachable. adc3e2c is on this branch and has byte-identical -# packet-build inputs, so standalone verification reads those inputs here. -PINNED_SOURCE_ANCHOR = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" -PINNED_SOURCE_ANCHOR_TREE = "cec1a2ede2202e7889dfec4165d658f8d3e415d5" +# never made reachable. The exact base of this evidence change has +# byte-identical packet-build inputs and remains reachable after squash merge. +PINNED_SOURCE_ANCHOR = "5610ea221dd82b5749690043e8c3665b2be9ced8" +PINNED_SOURCE_ANCHOR_TREE = "50a1741b7377a1649540af6431056b3da53320e8" PINNED_BUILD_FILES = frozenset({ "tool_versions.txt", "timing.txt", diff --git a/tools/verify_lsc1_ulx3s_reproduction.py b/tools/verify_lsc1_ulx3s_reproduction.py index e17819c2..c0c7d62e 100644 --- a/tools/verify_lsc1_ulx3s_reproduction.py +++ b/tools/verify_lsc1_ulx3s_reproduction.py @@ -16,6 +16,7 @@ SOURCE = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" SOURCE_TREE = "cec1a2ede2202e7889dfec4165d658f8d3e415d5" BASE = "5610ea221dd82b5749690043e8c3665b2be9ced8" +BASE_TREE = "50a1741b7377a1649540af6431056b3da53320e8" ARTIFACTS = { "ulx3s_lsc1_packet.bit": "226514183384b875821426b8c4d338508d8cff08cd12cb8e39c9162db37e3b9e", "ulx3s_lsc1_packet.config": "0737bbafae6704139ad9de2669a4e43f64d02644ce7cb9fc7bef336b28b7bf6b", @@ -72,11 +73,11 @@ def verify_source_manifest(path: Path) -> None: require(len(entries) == 25, "complete source manifest") for name, expected in entries.items(): try: - payload = subprocess.check_output(["git", "show", f"{SOURCE}:{name}"], cwd=ROOT) + payload = subprocess.check_output(["git", "show", f"{BASE}:{name}"], cwd=ROOT) except subprocess.CalledProcessError as error: - raise ValueError(f"source input absent at pinned commit: {name}") from error + raise ValueError(f"source input absent at durable base anchor: {name}") from error require(hashlib.sha256(payload).hexdigest() == expected, - f"source input differs from pinned commit: {name}") + f"source input differs from durable base anchor: {name}") def verify_run(run: dict, evidence_root: Path) -> dict[str, str]: @@ -128,7 +129,7 @@ def verify(path: Path = RECEIPT, evidence_root: Path = EVIDENCE) -> None: require(r.get("base_commit") == BASE, "base commit") source = r.get("build_source", {}) require(source == {"commit": SOURCE, "tree": SOURCE_TREE, "inputs_match_revision": True}, "source identity") - require(git("rev-parse", f"{SOURCE}^{{tree}}") == SOURCE_TREE, "source tree object") + require(git("rev-parse", f"{BASE}^{{tree}}") == BASE_TREE, "durable base anchor tree") scope = r.get("scope", {}) require(scope.get("design") == "full LSC-1 host-prepared packet UART endpoint", "full LSC-1 scope") for key in ("host_fetch", "memory_expansion", "physical_hardware", "end_to_end", "universal_or_unbounded", "later_roadmap_work"): From d5ca3d83e0fce0eaffa8c3d8bc4db0e583715595 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 04:30:30 +0200 Subject: [PATCH 05/10] fix: close ULX3S manifest verification gaps --- SHA256SUMS | 4 +- test/test_lsc1_ulx3s_reproduction.py | 62 ++++++++++++++++++++++--- tools/verify_lsc1_ulx3s_reproduction.py | 29 +++++++++++- 3 files changed, 85 insertions(+), 10 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index 239d0f9e..b6204009 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -89bf755b3c41f7992a7d487f600dbc94ffe2b7764f716d2549507051f3134180 ./test/test_lsc1_ulx3s_reproduction.py +dbfa5a0be90ac60c109a23cb9e57674f983cd206941a610dad89bd26a161929a ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py @@ -628,7 +628,7 @@ a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py 6f6d2f97d96aeddd39e3bae8c4ea9193bec8a5a4237d5a17a93057e1d2c38f26 ./tools/verify_fabrication_bundle.py 28bb061b2dee67ca8768a54a7d216762b601fc700606f52c076e894939dd12ba ./tools/verify_lsc1_fpga_packet_evidence.py -a89cefd8ff81aef14586746339c6d4a214d1bbc35619e31e48c39fe67247a701 ./tools/verify_lsc1_ulx3s_reproduction.py +f6be19c16f86edda9d1248f5d1cab6a487a369b5106fa621fac40ba2c010e293 ./tools/verify_lsc1_ulx3s_reproduction.py 650919f4b3f0d2a94022d4de230f16afca36fc5c3eee45b77571cb0ec5c52994 ./tools/verify_lsc1u_release_equivalence.py 4af566c345d8108c6b409f0c622fe132bdfc3b3a2b3eddee28f778e378d71254 ./tools/workload_validation.py d930b3a00795450bad3cfa1941fcc3028e03b5cf9724dab32c7f07d0678f38b4 ./workloads/blake3_stack.program.json diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index 935c9e26..b2a783c5 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -10,7 +10,7 @@ import unittest from pathlib import Path -from tools.verify_lsc1_ulx3s_reproduction import EVIDENCE, RECEIPT, verify +from tools.verify_lsc1_ulx3s_reproduction import BASE, EVIDENCE, RECEIPT, verify class ReproductionReceiptTest(unittest.TestCase): @@ -86,6 +86,20 @@ def substitute(evidence: Path, receipt: dict) -> None: receipt["runs"][0]["evidence_sha256"]["SOURCE_MANIFEST.txt"] = hashlib.sha256(payload).hexdigest() self.rejected(mutate_evidence=substitute, message="source manifest identity") + def test_rehashed_source_input_name_substitution_rejected(self): + def substitute(evidence: Path, receipt: dict) -> None: + path = evidence / "clean-build-1" / "SOURCE_MANIFEST.txt" + lines = path.read_text().splitlines() + removed = next(i for i, line in enumerate(lines) + if line.endswith(" asic_core/rtl/gf128_mul_bitstream.sv")) + del lines[removed] + readme = subprocess.check_output(["git", "show", f"{BASE}:README.md"], cwd=RECEIPT.parents[2]) + lines.append(f"{hashlib.sha256(readme).hexdigest()} README.md") + payload = ("\n".join(lines) + "\n").encode() + self.replace(path, payload) + receipt["runs"][0]["evidence_sha256"]["SOURCE_MANIFEST.txt"] = hashlib.sha256(payload).hexdigest() + self.rejected(mutate_evidence=substitute, message="complete source manifest") + def test_nonzero_exit_rejected(self): self.rejected(mutate_receipt=lambda r: r["runs"][1].update(exit_code=1), message="normal exit") @@ -97,16 +111,24 @@ def test_unpinned_option_rejected(self): self.rejected(mutate_receipt=lambda r: r["nextpnr_options"].remove("--no-tmdriv"), message="nextpnr options") - def test_post_squash_single_branch_checkout_accepts(self): - """P1 family: verification cannot depend on an intermediate PR commit.""" - source = RECEIPT.parents[2] + def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> None: intermediate = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" - base = "5610ea221dd82b5749690043e8c3665b2be9ced8" with tempfile.TemporaryDirectory() as td: root = Path(td) staging = root / "staging.git" checkout = root / "checkout" - subprocess.run(["git", "clone", "--bare", "--shared", str(source), str(staging)], + # upload-pack deliberately disables lazy fetching while serving a + # partial clone. Materialize its promised blobs in one fetch + # before asking it to create an independent bare repository; do + # not borrow the source's incomplete object store. + promisor = subprocess.run( + ["git", "-C", str(source), "config", "--get", "remote.origin.promisor"], + text=True, stdout=subprocess.PIPE) + if promisor.returncode == 0 and promisor.stdout.strip() == "true": + subprocess.run( + ["git", "-C", str(source), "fetch", "--refetch", "--no-filter", "origin"], + check=True, stdout=subprocess.DEVNULL) + subprocess.run(["git", "clone", "--bare", "--no-local", str(source), str(staging)], check=True, stdout=subprocess.DEVNULL) tree = subprocess.check_output(["git", "-C", str(source), "rev-parse", "HEAD^{tree}"], text=True).strip() @@ -117,7 +139,7 @@ def test_post_squash_single_branch_checkout_accepts(self): "GIT_COMMITTER_EMAIL": "regression@example.invalid", } squash = subprocess.check_output( - ["git", f"--git-dir={staging}", "commit-tree", tree, "-p", base, "-m", "squash"], + ["git", f"--git-dir={staging}", "commit-tree", tree, "-p", BASE, "-m", "squash"], env=env, text=True).strip() refs = subprocess.check_output( ["git", f"--git-dir={staging}", "for-each-ref", "--format=%(refname)"], @@ -136,6 +158,32 @@ def test_post_squash_single_branch_checkout_accepts(self): subprocess.run([sys.executable, "test/test_lsc1_fpga_packet_evidence.py", "-v"], cwd=checkout, env=os.environ | {"PYTHONPATH": "."}, check=True) + def test_post_squash_single_branch_checkout_accepts(self): + """P1 family: verification cannot depend on an intermediate PR commit.""" + self.assert_post_squash_single_branch_checkout_accepts(RECEIPT.parents[2]) + + def test_post_squash_checkout_accepts_from_blob_filtered_source(self): + """The squash fixture must copy/fetch objects from a partial checkout.""" + source = RECEIPT.parents[2] + with tempfile.TemporaryDirectory() as td: + root = Path(td) + upstream = root / "upstream.git" + partial = root / "partial" + subprocess.run(["git", "clone", "--bare", "--no-local", str(source), str(upstream)], + check=True, stdout=subprocess.DEVNULL) + subprocess.run(["git", f"--git-dir={upstream}", "config", "uploadpack.allowFilter", "true"], + check=True) + subprocess.run(["git", "clone", "--no-local", "--filter=blob:none", str(upstream), + str(partial)], check=True, stdout=subprocess.DEVNULL) + self.assertEqual(subprocess.check_output( + ["git", "-C", str(partial), "config", "--bool", "remote.origin.promisor"], + text=True).strip(), "true") + missing = subprocess.check_output( + ["git", "-C", str(partial), "rev-list", "--objects", "--missing=print", + BASE], text=True).splitlines() + self.assertTrue(any(line.startswith("?") for line in missing)) + self.assert_post_squash_single_branch_checkout_accepts(partial) + if __name__ == "__main__": unittest.main() diff --git a/tools/verify_lsc1_ulx3s_reproduction.py b/tools/verify_lsc1_ulx3s_reproduction.py index c0c7d62e..7bdb94b6 100644 --- a/tools/verify_lsc1_ulx3s_reproduction.py +++ b/tools/verify_lsc1_ulx3s_reproduction.py @@ -28,6 +28,33 @@ "ecppack": "Project Trellis ecppack Version 1.4-2build4", } OPTIONS = ["--85k", "--package", "CABGA381", "--seed", "2", "--placer", "static", "--no-tmdriv", "--router", "router1"] +PACKET_BUILD_INPUTS = frozenset({ + "asic_core/rtl/gf128_mul_bitstream.sv", + "asic_core/rtl/gf2n_mul_bitstream.sv", + "asic_core/rtl/lean_silicon_lsc1.sv", + "asic_core/rtl/lean_silicon_lsc1_mincore.sv", + "asic_core/rtl/leanvm_b_stream_alu.sv", + "asic_core/rtl/lsc1_blake3_alias_check.sv", + "asic_core/rtl/lsc1_blake3_lifecycle.sv", + "asic_core/rtl/lsc1_cell_alias_check.sv", + "asic_core/rtl/lsc1_field_encoder.sv", + "asic_core/rtl/lsc1_packet_frontend.sv", + "asic_core/rtl/lsc1_packet_rx.sv", + "asic_core/rtl/lsc1_packet_tx.sv", + "asic_core/rtl/lsc1_request_validator.sv", + "asic_core/rtl/lsc1_response_payload_mux.sv", + "asic_core/rtl/lsc1_stream_adapter.sv", + "fpga/ulx3s/build_packet_uart.sh", + "fpga/ulx3s/uart_bridge.sv", + "fpga/ulx3s/uart_rx.sv", + "fpga/ulx3s/uart_tx.sv", + "fpga/ulx3s/ulx3s_core_pll.sv", + "fpga/ulx3s/ulx3s_packet_top.sv", + "fpga/ulx3s/ulx3s_v318_smoke.lpf", + "tools/atomic_publish.py", + "tools/portable_build_support.py", + "tools/source_provenance.py", +}) RUN_FILES = { "SHA256SUMS", "SOURCE_MANIFEST.txt", "build.stderr", "build.stdout", "ecppack.log", "nextpnr.log", "timing.txt", "tool_versions.txt", @@ -70,7 +97,7 @@ def verify_source_manifest(path: Path) -> None: "malformed source manifest") require(fields[1] not in entries, f"duplicate source input {fields[1]}") entries[fields[1]] = fields[0] - require(len(entries) == 25, "complete source manifest") + require(set(entries) == PACKET_BUILD_INPUTS, "complete source manifest") for name, expected in entries.items(): try: payload = subprocess.check_output(["git", "show", f"{BASE}:{name}"], cwd=ROOT) From a15dab2022ac6e93786058d815851c35cb3b5038 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Sun, 6 Sep 2026 08:25:39 +0200 Subject: [PATCH 06/10] test: materialize partial clone fixtures --- SHA256SUMS | 2 +- test/test_lsc1_ulx3s_reproduction.py | 23 ++++++++++++++++------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index b6204009..2b28e26d 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -dbfa5a0be90ac60c109a23cb9e57674f983cd206941a610dad89bd26a161929a ./test/test_lsc1_ulx3s_reproduction.py +dface3255b3c37f9316a2e319463ed549cb17e0a54db89d40fcf01829e10cdb7 ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index b2a783c5..2f1726e8 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -111,6 +111,17 @@ def test_unpinned_option_rejected(self): self.rejected(mutate_receipt=lambda r: r["nextpnr_options"].remove("--no-tmdriv"), message="nextpnr options") + @staticmethod + def materialize_promised_objects(source: Path) -> None: + """Make an independent clone safe to serve without lazy fetching.""" + promisor = subprocess.run( + ["git", "-C", str(source), "config", "--get", "remote.origin.promisor"], + text=True, stdout=subprocess.PIPE) + if promisor.returncode == 0 and promisor.stdout.strip() == "true": + subprocess.run( + ["git", "-C", str(source), "fetch", "--refetch", "--no-filter", "origin"], + check=True, stdout=subprocess.DEVNULL) + def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> None: intermediate = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" with tempfile.TemporaryDirectory() as td: @@ -121,13 +132,7 @@ def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> Non # partial clone. Materialize its promised blobs in one fetch # before asking it to create an independent bare repository; do # not borrow the source's incomplete object store. - promisor = subprocess.run( - ["git", "-C", str(source), "config", "--get", "remote.origin.promisor"], - text=True, stdout=subprocess.PIPE) - if promisor.returncode == 0 and promisor.stdout.strip() == "true": - subprocess.run( - ["git", "-C", str(source), "fetch", "--refetch", "--no-filter", "origin"], - check=True, stdout=subprocess.DEVNULL) + self.materialize_promised_objects(source) subprocess.run(["git", "clone", "--bare", "--no-local", str(source), str(staging)], check=True, stdout=subprocess.DEVNULL) tree = subprocess.check_output(["git", "-C", str(source), "rev-parse", "HEAD^{tree}"], @@ -169,6 +174,10 @@ def test_post_squash_checkout_accepts_from_blob_filtered_source(self): root = Path(td) upstream = root / "upstream.git" partial = root / "partial" + # This test itself may be running from a genuine blob-filtered + # checkout. Materialize that source before the first independent + # bare clone, just as the nested squash helper does below. + self.materialize_promised_objects(source) subprocess.run(["git", "clone", "--bare", "--no-local", str(source), str(upstream)], check=True, stdout=subprocess.DEVNULL) subprocess.run(["git", f"--git-dir={upstream}", "config", "uploadpack.allowFilter", "true"], From 9d7032338a44a229203de78703532f25c3c1aa93 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Mon, 7 Sep 2026 04:57:05 +0200 Subject: [PATCH 07/10] test: serialize partial-clone materialization --- SHA256SUMS | 2 +- test/test_lsc1_ulx3s_reproduction.py | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index 2b28e26d..18861aa8 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -dface3255b3c37f9316a2e319463ed549cb17e0a54db89d40fcf01829e10cdb7 ./test/test_lsc1_ulx3s_reproduction.py +f3a23cd51dbc86e2b3427319e766b4538a45b66629bf1840c0441305966d94c8 ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index 2f1726e8..abbd1c24 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -9,6 +9,7 @@ import tempfile import unittest from pathlib import Path +from unittest import mock from tools.verify_lsc1_ulx3s_reproduction import BASE, EVIDENCE, RECEIPT, verify @@ -119,7 +120,8 @@ def materialize_promised_objects(source: Path) -> None: text=True, stdout=subprocess.PIPE) if promisor.returncode == 0 and promisor.stdout.strip() == "true": subprocess.run( - ["git", "-C", str(source), "fetch", "--refetch", "--no-filter", "origin"], + ["git", "-C", str(source), "fetch", "--no-auto-maintenance", "--refetch", + "--no-filter", "origin"], check=True, stdout=subprocess.DEVNULL) def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> None: @@ -167,6 +169,14 @@ def test_post_squash_single_branch_checkout_accepts(self): """P1 family: verification cannot depend on an intermediate PR commit.""" self.assert_post_squash_single_branch_checkout_accepts(RECEIPT.parents[2]) + def test_promised_object_fetch_cannot_start_background_maintenance(self): + """A serving clone must not race an auto-repack of fetched objects.""" + completed = subprocess.CompletedProcess([], 0, stdout="true\n") + with mock.patch("subprocess.run", return_value=completed) as run: + self.materialize_promised_objects(Path("partial")) + fetch = run.call_args_list[1].args[0] + self.assertIn("--no-auto-maintenance", fetch) + def test_post_squash_checkout_accepts_from_blob_filtered_source(self): """The squash fixture must copy/fetch objects from a partial checkout.""" source = RECEIPT.parents[2] @@ -191,7 +201,11 @@ def test_post_squash_checkout_accepts_from_blob_filtered_source(self): ["git", "-C", str(partial), "rev-list", "--objects", "--missing=print", BASE], text=True).splitlines() self.assertTrue(any(line.startswith("?") for line in missing)) - self.assert_post_squash_single_branch_checkout_accepts(partial) + # Match hermetic runners: explicit fetches remain allowed, but Git + # may not hide an incomplete source by fetching lazily while it is + # serving the nested independent clone. + with mock.patch.dict(os.environ, {"GIT_NO_LAZY_FETCH": "1"}): + self.assert_post_squash_single_branch_checkout_accepts(partial) if __name__ == "__main__": From 8d6eec26d8cbfe00561e8940ddcc09e74a3f90cb Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Mon, 7 Sep 2026 05:31:47 +0200 Subject: [PATCH 08/10] fix: harden ULX3S reproduction certification --- SHA256SUMS | 4 +- test/test_lsc1_ulx3s_reproduction.py | 61 ++++++++++++++++++++----- tools/verify_lsc1_ulx3s_reproduction.py | 25 +++++++--- 3 files changed, 70 insertions(+), 20 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index 18861aa8..b98dcae8 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -f3a23cd51dbc86e2b3427319e766b4538a45b66629bf1840c0441305966d94c8 ./test/test_lsc1_ulx3s_reproduction.py +e0bd89e19ffae189a4a458fc9368a9f5eaa0ce7c44cfabf53a706d933e731178 ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py @@ -628,7 +628,7 @@ a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py 6f6d2f97d96aeddd39e3bae8c4ea9193bec8a5a4237d5a17a93057e1d2c38f26 ./tools/verify_fabrication_bundle.py 28bb061b2dee67ca8768a54a7d216762b601fc700606f52c076e894939dd12ba ./tools/verify_lsc1_fpga_packet_evidence.py -f6be19c16f86edda9d1248f5d1cab6a487a369b5106fa621fac40ba2c010e293 ./tools/verify_lsc1_ulx3s_reproduction.py +11496eff27eae96804bfcc30351a92fe950f9e0d6f0e92b1877672deb4162ac9 ./tools/verify_lsc1_ulx3s_reproduction.py 650919f4b3f0d2a94022d4de230f16afca36fc5c3eee45b77571cb0ec5c52994 ./tools/verify_lsc1u_release_equivalence.py 4af566c345d8108c6b409f0c622fe132bdfc3b3a2b3eddee28f778e378d71254 ./tools/workload_validation.py d930b3a00795450bad3cfa1941fcc3028e03b5cf9724dab32c7f07d0678f38b4 ./workloads/blake3_stack.program.json diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index abbd1c24..0e7dc491 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -11,7 +11,9 @@ from pathlib import Path from unittest import mock -from tools.verify_lsc1_ulx3s_reproduction import BASE, EVIDENCE, RECEIPT, verify +from tools.verify_lsc1_ulx3s_reproduction import ( + BASE, EVIDENCE, EVIDENCE_LAYERS, RECEIPT, SCOPE, verify, +) class ReproductionReceiptTest(unittest.TestCase): @@ -104,9 +106,33 @@ def substitute(evidence: Path, receipt: dict) -> None: def test_nonzero_exit_rejected(self): self.rejected(mutate_receipt=lambda r: r["runs"][1].update(exit_code=1), message="normal exit") - def test_scope_expansion_rejected(self): - self.rejected(mutate_receipt=lambda r: r["scope"].update(physical_hardware=True), - message="scope boundary physical_hardware") + def test_scope_claim_family_rejected(self): + mutations = { + "physical hardware": lambda scope: scope.update(physical_hardware=True), + "unbounded correspondence": lambda scope: scope.update(universal_or_unbounded=True), + "unknown physical board claim": + lambda scope: scope.update(physical_board_validated=True), + } + for name, mutation in mutations.items(): + with self.subTest(name=name): + self.rejected(mutate_receipt=lambda r, m=mutation: m(r["scope"]), + message="scope boundaries") + + def test_evidence_layer_claim_family_rejected(self): + mutations = { + "physical board validation": ("physical_hardware", "validated on a physical board"), + "false place and route status": ("place_and_route", "not run"), + "unbounded Lean to RTL": ("lean", "unbounded Lean-to-RTL correspondence proved"), + } + for name, (layer, claim) in mutations.items(): + with self.subTest(name=name): + self.rejected( + mutate_receipt=lambda r, key=layer, value=claim: + r["evidence_layers"].update({key: value}), + message="evidence layer claims") + + self.assertEqual(self.receipt()["scope"], SCOPE) + self.assertEqual(self.receipt()["evidence_layers"], EVIDENCE_LAYERS) def test_unpinned_option_rejected(self): self.rejected(mutate_receipt=lambda r: r["nextpnr_options"].remove("--no-tmdriv"), @@ -115,13 +141,20 @@ def test_unpinned_option_rejected(self): @staticmethod def materialize_promised_objects(source: Path) -> None: """Make an independent clone safe to serve without lazy fetching.""" - promisor = subprocess.run( - ["git", "-C", str(source), "config", "--get", "remote.origin.promisor"], + configured = subprocess.run( + ["git", "-C", str(source), "config", "--get-regexp", + r"^remote\..*\.promisor$"], text=True, stdout=subprocess.PIPE) - if promisor.returncode == 0 and promisor.stdout.strip() == "true": + if configured.returncode not in (0, 1): + configured.check_returncode() + for line in configured.stdout.splitlines(): + key, separator, value = line.rpartition(" ") + if not separator or value.strip().lower() != "true": + continue + remote = key.removeprefix("remote.").removesuffix(".promisor") subprocess.run( ["git", "-C", str(source), "fetch", "--no-auto-maintenance", "--refetch", - "--no-filter", "origin"], + "--no-filter", remote], check=True, stdout=subprocess.DEVNULL) def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> None: @@ -171,11 +204,13 @@ def test_post_squash_single_branch_checkout_accepts(self): def test_promised_object_fetch_cannot_start_background_maintenance(self): """A serving clone must not race an auto-repack of fetched objects.""" - completed = subprocess.CompletedProcess([], 0, stdout="true\n") + completed = subprocess.CompletedProcess( + [], 0, stdout="remote.evidence-upstream.promisor true\n") with mock.patch("subprocess.run", return_value=completed) as run: self.materialize_promised_objects(Path("partial")) fetch = run.call_args_list[1].args[0] self.assertIn("--no-auto-maintenance", fetch) + self.assertEqual(fetch[-1], "evidence-upstream") def test_post_squash_checkout_accepts_from_blob_filtered_source(self): """The squash fixture must copy/fetch objects from a partial checkout.""" @@ -192,10 +227,12 @@ def test_post_squash_checkout_accepts_from_blob_filtered_source(self): check=True, stdout=subprocess.DEVNULL) subprocess.run(["git", f"--git-dir={upstream}", "config", "uploadpack.allowFilter", "true"], check=True) - subprocess.run(["git", "clone", "--no-local", "--filter=blob:none", str(upstream), - str(partial)], check=True, stdout=subprocess.DEVNULL) + subprocess.run(["git", "clone", "--no-local", "--filter=blob:none", "--origin", + "evidence-upstream", str(upstream), str(partial)], check=True, + stdout=subprocess.DEVNULL) self.assertEqual(subprocess.check_output( - ["git", "-C", str(partial), "config", "--bool", "remote.origin.promisor"], + ["git", "-C", str(partial), "config", "--bool", + "remote.evidence-upstream.promisor"], text=True).strip(), "true") missing = subprocess.check_output( ["git", "-C", str(partial), "rev-list", "--objects", "--missing=print", diff --git a/tools/verify_lsc1_ulx3s_reproduction.py b/tools/verify_lsc1_ulx3s_reproduction.py index 7bdb94b6..13865c35 100644 --- a/tools/verify_lsc1_ulx3s_reproduction.py +++ b/tools/verify_lsc1_ulx3s_reproduction.py @@ -28,6 +28,23 @@ "ecppack": "Project Trellis ecppack Version 1.4-2build4", } OPTIONS = ["--85k", "--package", "CABGA381", "--seed", "2", "--placer", "static", "--no-tmdriv", "--router", "router1"] +SCOPE = { + "design": "full LSC-1 host-prepared packet UART endpoint", + "host_fetch": False, + "memory_expansion": False, + "physical_hardware": False, + "end_to_end": False, + "universal_or_unbounded": False, + "later_roadmap_work": False, +} +EVIDENCE_LAYERS = { + "executable_model": "not exercised by the reproduction builds", + "lean": "validated separately; does not prove the bitstream", + "authored_rtl": "build input only", + "netlist": "generated logical intermediate only", + "place_and_route": "two preserved host executions with timing receipts", + "physical_hardware": "no board attached, programmed, or observed", +} PACKET_BUILD_INPUTS = frozenset({ "asic_core/rtl/gf128_mul_bitstream.sv", "asic_core/rtl/gf2n_mul_bitstream.sv", @@ -157,12 +174,8 @@ def verify(path: Path = RECEIPT, evidence_root: Path = EVIDENCE) -> None: source = r.get("build_source", {}) require(source == {"commit": SOURCE, "tree": SOURCE_TREE, "inputs_match_revision": True}, "source identity") require(git("rev-parse", f"{BASE}^{{tree}}") == BASE_TREE, "durable base anchor tree") - scope = r.get("scope", {}) - require(scope.get("design") == "full LSC-1 host-prepared packet UART endpoint", "full LSC-1 scope") - for key in ("host_fetch", "memory_expansion", "physical_hardware", "end_to_end", "universal_or_unbounded", "later_roadmap_work"): - require(scope.get(key) is False, f"scope boundary {key}") - layers = r.get("evidence_layers", {}) - require(set(layers) == {"executable_model", "lean", "authored_rtl", "netlist", "place_and_route", "physical_hardware"}, "evidence layer separation") + require(r.get("scope") == SCOPE, "scope boundaries") + require(r.get("evidence_layers") == EVIDENCE_LAYERS, "evidence layer claims") require(r.get("toolchain") == TOOLS, "toolchain") require(r.get("command") == ["./fpga/ulx3s/build_packet_uart.sh"], "command") require(r.get("nextpnr_options") == OPTIONS, "nextpnr options") From 3a8c0e5aac7dcc56c5950af40f1fd2b998623692 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Mon, 7 Sep 2026 06:10:35 +0200 Subject: [PATCH 09/10] test: materialize historical promised blobs --- test/test_lsc1_ulx3s_reproduction.py | 35 ++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/test/test_lsc1_ulx3s_reproduction.py b/test/test_lsc1_ulx3s_reproduction.py index 0e7dc491..42157781 100644 --- a/test/test_lsc1_ulx3s_reproduction.py +++ b/test/test_lsc1_ulx3s_reproduction.py @@ -17,6 +17,8 @@ class ReproductionReceiptTest(unittest.TestCase): + HISTORICAL_PROMISED_BLOB = "18861aa826de9eb97f0b6db62538507f501788cd" + def receipt(self) -> dict: return json.loads(RECEIPT.read_text()) @@ -156,6 +158,16 @@ def materialize_promised_objects(source: Path) -> None: ["git", "-C", str(source), "fetch", "--no-auto-maintenance", "--refetch", "--no-filter", remote], check=True, stdout=subprocess.DEVNULL) + objects = subprocess.check_output( + ["git", "-C", str(source), "rev-list", "--objects", "--all", + "--missing=print"], text=True) + missing = [line[1:] for line in objects.splitlines() if line.startswith("?")] + if missing: + subprocess.run( + ["git", "-C", str(source), "fetch", "--no-auto-maintenance", + "--no-tags", "--no-write-fetch-head", "--stdin", remote], + input="\n".join(missing) + "\n", check=True, text=True, + stdout=subprocess.DEVNULL) def assert_post_squash_single_branch_checkout_accepts(self, source: Path) -> None: intermediate = "adc3e2c5b86fb08e1b0225573486ae08af4ac194" @@ -206,11 +218,16 @@ def test_promised_object_fetch_cannot_start_background_maintenance(self): """A serving clone must not race an auto-repack of fetched objects.""" completed = subprocess.CompletedProcess( [], 0, stdout="remote.evidence-upstream.promisor true\n") - with mock.patch("subprocess.run", return_value=completed) as run: + with (mock.patch("subprocess.run", return_value=completed) as run, + mock.patch("subprocess.check_output", + return_value=f"?{self.HISTORICAL_PROMISED_BLOB}\n")): self.materialize_promised_objects(Path("partial")) - fetch = run.call_args_list[1].args[0] - self.assertIn("--no-auto-maintenance", fetch) - self.assertEqual(fetch[-1], "evidence-upstream") + fetches = [call.args[0] for call in run.call_args_list[1:]] + self.assertEqual(len(fetches), 2) + for fetch in fetches: + self.assertIn("--no-auto-maintenance", fetch) + self.assertEqual(fetch[-1], "evidence-upstream") + self.assertIn("--stdin", fetches[1]) def test_post_squash_checkout_accepts_from_blob_filtered_source(self): """The squash fixture must copy/fetch objects from a partial checkout.""" @@ -242,6 +259,16 @@ def test_post_squash_checkout_accepts_from_blob_filtered_source(self): # may not hide an incomplete source by fetching lazily while it is # serving the nested independent clone. with mock.patch.dict(os.environ, {"GIT_NO_LAZY_FETCH": "1"}): + promised = subprocess.run( + ["git", "-C", str(partial), "cat-file", "-e", + self.HISTORICAL_PROMISED_BLOB], + stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) + self.assertNotEqual(promised.returncode, 0) + self.materialize_promised_objects(partial) + subprocess.run( + ["git", "-C", str(partial), "cat-file", "-e", + self.HISTORICAL_PROMISED_BLOB], + check=True, stdout=subprocess.DEVNULL) self.assert_post_squash_single_branch_checkout_accepts(partial) From 65890eb6e1e86ceba38dea7e0dac4ddfee3c0da8 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Mon, 7 Sep 2026 06:24:29 +0200 Subject: [PATCH 10/10] chore: refresh reproduction test checksum --- SHA256SUMS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SHA256SUMS b/SHA256SUMS index b98dcae8..16b325cc 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -586,7 +586,7 @@ d8346b848aa30f16f29eb236f502c61aa356b44d3a43cb274606e16821d4bb7d ./test/test_ls d6c7dd33771eb5386c9fc00e1003edce1d90b4a25625400eb8f0eccc57efc7e9 ./test/test_lsc1_fpga_packet_evidence.py 2dd4a7cbfcb2cf765e3068526fd1f68c5ab738d752ff6b60c0fa4260cab87219 ./test/test_lsc1_host_authored_rtl_boundary.py e482475415e3a56c90db896fac31f7faff94a4a36f344fe6630222da88bcf07c ./test/test_lsc1_scalar_status_workflow.py -e0bd89e19ffae189a4a458fc9368a9f5eaa0ce7c44cfabf53a706d933e731178 ./test/test_lsc1_ulx3s_reproduction.py +16417a203b31e19b4c4d3c84a75a26c6ac271c15c1b48ceb13e016ab254296a1 ./test/test_lsc1_ulx3s_reproduction.py 7220320ea36a1436e5f982e6af56444dbf21768be2b38ad3f01e90fde2820cc6 ./test/test_oss_cad_suite_workflow.py 1a047bd2d21b30021b0f958b913f0a67a8740fc0732f4e1efaf3d56bc6de2ad5 ./test/test_select_exact_gds_run.py d32b66a8f2b5961f686b478f19f1b1a14bb638e2031c23cafb86575b68d5c8ea ./test/test_tt.py